Memory control method, control circuit, and memory

Abstract

The application provides a memory control method, a control circuit and a memory. The memory comprises a storage unit connected with a bit line. The control method comprises the following steps: obtaining a working temperature of the memory; and adjusting a voltage of the storage unit in the memory according to the working temperature of the memory. The voltage of the storage unit comprises one or more of a voltage of an upper plate of a capacitor when the storage unit stores first data, a voltage on the bit line before a transistor in the storage unit is turned on, and a gate-on voltage of the transistor. The voltage of the upper plate of the capacitor when the storage unit stores the first data is greater than a voltage of a lower plate of the capacitor.

Description

Technical Field

[0001] The present application relates to, but is not limited to, a memory control method, a control circuit, and a memory. Background Art

[0002] With the development of memory technology, memory has been widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] Therefore, the performance of the memory includes but is not limited to various timing parameters, data readout accuracy, and power consumption. This application aims to improve the performance of the memory. Summary of the Invention

[0004] The present application provides a method for controlling a memory, wherein the memory includes a memory cell connected to a bit line. The method includes:

[0005] Get the operating temperature of the memory;

[0006] adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory;

[0007] Among them, the voltage of the storage cell includes one or more of the voltage of the upper plate of the capacitor when the storage cell stores the first data, the voltage on the bit line before the transistor in the storage cell is turned on, and the gate turn-on voltage of the transistor. When the storage cell stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0008] In some embodiments, adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following:

[0009] When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage of the upper plate of the capacitor to be greater than the upper plate reference voltage when the storage unit stores the first data;

[0010] When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be greater than a bit line reference voltage; and

[0011] When the operating temperature of the memory is less than or equal to the first temperature threshold, the gate turn-on voltage of the control transistor is the gate reference voltage.

[0012] In some embodiments, adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following:

[0013] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the first data is stored in the storage unit;

[0014] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage; and

[0015] When the operating temperature of the memory is greater than a second temperature threshold, the gate turn-on voltage of the control transistor is less than the gate reference voltage;

[0016] The second temperature threshold is greater than the first temperature threshold.

[0017] In some embodiments, adjusting the voltage of a storage unit in a memory according to an operating temperature of the memory specifically includes:

[0018] When the operating temperature of the memory is greater than a first temperature threshold and less than or equal to a second temperature threshold, the voltage of the storage unit in the memory is adjusted according to the model of the memory, wherein the second temperature threshold is greater than the first temperature threshold.

[0019] In some embodiments, when the operating temperature of the memory is greater than the first temperature threshold and the operating temperature of the memory is less than or equal to the second temperature threshold, the following steps are performed depending on the model of the memory:

[0020] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage of the upper plate of the capacitor to be an upper plate reference voltage when the storage unit stores the first data; and

[0021] When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is low power consumption, the voltage on the bit line before the transistor in the memory cell is turned on is controlled to be the bit line reference voltage.

[0022] In some embodiments, adjusting the voltage of a storage unit in the memory according to the memory model and the operating temperature of the memory specifically includes at least one of the following:

[0023] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold; and the type of the memory is not low power consumption, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data; and

[0024] When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption, the voltage on the bit line before the transistor in the memory cell is turned on is controlled to be less than the bit line reference voltage.

[0025] In some embodiments, when the first condition is satisfied, the voltage on the upper plate of the capacitor when the memory cell stores the first data is greater than the voltage on the upper plate of the capacitor when the memory cell stores the first data when the second condition is satisfied;

[0026] Among them, satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0027] In some embodiments, the voltage on the bit line before the transistor in the memory cell is turned on when the first condition is satisfied is greater than the voltage on the bit line before the transistor in the memory cell is turned on when the second condition is satisfied;

[0028] Satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0029] Some embodiments of the present application provide a control circuit of a memory, the memory including a memory cell connected to a bit line, the control circuit including: a temperature monitoring circuit and a voltage control circuit;

[0030] The temperature monitoring circuit monitors the operating temperature of the memory;

[0031] The voltage control circuit is connected to the temperature monitoring circuit, and the voltage control circuit adjusts the voltage of the storage unit in the memory according to the operating temperature of the memory;

[0032] Among them, the voltage of the storage cell includes one or more of the voltage of the upper plate of the capacitor when the storage cell stores the first data, the voltage on the bit line before the transistor in the storage cell is turned on, and the gate turn-on voltage of the transistor. When the storage cell stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0033] Some embodiments of the present application provide a memory, including: a memory unit and the control circuit involved in the above embodiments, where the memory unit is connected to a bit line.

[0034] The memory control method, control circuit and memory provided in the present application include obtaining the operating temperature data of the memory and adjusting one or more of the voltage of the upper plate of the capacitor, the bit line precharge voltage and the gate turn-on voltage of the transistor when the memory cell stores the first data according to the temperature data. This can adjust the performance of the tail memory cell, thereby improving the overall performance of the memory and improving the pass rate of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 This is an example diagram of a memory architecture;

[0037] Figure 2 This is a diagram illustrating an example structure of a storage unit according to an embodiment;

[0038] Figure 3 for Figure 2 A circuit schematic diagram of the memory cell shown;

[0039] Figure 4 A schematic diagram of the structure of a storage unit;

[0040] Figures 5 to 8 A flowchart of a memory control method provided in some embodiments of the present application;

[0041] Figure 9A A schematic diagram of the relationship between the core voltage of a memory cell and the bit line precharge voltage;

[0042] Figure 9B A schematic diagram of the distribution of dVBL provided in some embodiments of the present application;

[0043] Figures 10 to 12 A flowchart of a memory control method provided in some embodiments of the present application.

[0044] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0046] At present, memory technology is developing rapidly, taking DRAM as an example, the main applications are Synchronous Dynamic Random-Access Memory (SDRAM), various generations of Double Data Rate (DDR) SDRAM, various generations of Low Power Double Data Rate (LPDDR) SDRAM and other types.

[0047] Figure 1 As an example of the architecture of a memory, as shown in Figure 1 Taking DRAM as an example, it includes address processing circuit 210, command decoding circuit 220, data input / output circuit 230, row decoder 240, column decoder 250, sense amplifier (SA) 260 and storage area. Among them, address processing circuit 210, command decoding circuit 220 and data input / output circuit 230 belong to peripheral area circuit, row decoder 240, column decoder 250, sense amplifier 260 and storage area belong to array area circuit. The storage area is mainly composed of storage unit 270, bit line BL and word line WL. The word line WL in the storage area extends along the row direction, the bit line BL in the storage area extends along the column direction, and the intersection of the word line WL and the bit line BL is the storage unit 270 of the storage area.

[0048] Among them, each storage unit 270 is used to store one bit of data. As shown in Figure 2 Figure 2 As an example of the structure of the storage unit shown in an embodiment, the storage unit 270 includes a switch transistor M and a capacitor Cs, any one of the source or drain of the switch transistor M is connected with the upper plate of the capacitor, the other of the source or drain of the switch transistor M is connected with the bit line BL, and the lower plate of the capacitor Cs is connected with the power supply line. The gate of the switch transistor M is connected with the word line WL, and the gate-on voltage of the switch transistor M is called Vwlp. The gate-on voltage is the voltage of the enable signal used to turn on the transistor before the transistor is turned on. Among them, the capacitor Cs is used to store data, and the switch transistor M is used to turn off or turn on according to the selected state. The voltage of the lower plate of the capacitor Cs is called Vap2, and the pre-charge voltage before the charge sharing on the bit line is called Vad2.

[0049] ​The word line WL of the row where the memory cell is located can be selected by the row decoder 240, and the corresponding switching transistor M in the figure is turned on. By setting the logic level of the bit line to 1, the upper plate of the capacitor Cs is charged, and the data "1" is written to the memory cell. Conversely, if a 0 is to be written, the logic level of the bit line is set to 0, causing the upper plate of the capacitor Cs to discharge, and the data "0" is written to the memory cell.

[0050] Figure 3 for Figure 2 The circuit schematic diagram of the storage unit is shown in FIG. Figure 3 As shown, the resistance between transistor M and bit line BL is called bit line contact resistance RBLC, the contact resistance between transistor M and capacitor Cs is called transistor contact resistance RNC, and the resistance on capacitor Cs is called capacitor resistance RCH. The capacitor top plate voltage when the memory cell stores data "1" is called core voltage Vblh.

[0051] As chip integration increases and transistor feature sizes continue to shrink, issues such as threshold voltage fluctuations in MOS transistors (MOS transistors) in sense amplifiers (SAMPs) and the susceptibility of small voltage signals to noise interference are becoming increasingly prominent, seriously impacting the accuracy of the sense amplifier's sensing of data in memory cells. Sensing margin (SM) is a key performance metric for sense amplifiers. The formula for calculating SM is: SM = Supply dVBL - Required dVBL, where Supply dVBL refers to the voltage difference between the bit line and the complementary bit line at the end of the charge sharing phase (also known as the supply of the sensing margin). Required dVBL refers to the voltage difference required for accurate SAMP amplification (also known as the loss of the sensing margin). Sensing margin loss is primarily caused by offset voltage and coupling noise caused by MOS transistor threshold voltage mismatch.

[0052] Figure 4 A schematic diagram of the structure of a storage unit is shown in FIG. Figure 4 As shown, a first doped region and a second doped region are formed on the substrate. A word line is embedded between the first and second doped regions, and a channel is formed around the word line. Leakage current within a memory cell includes gate-induced drain leakage (GIDL), junction leakage, and subthreshold leakage.

[0053] Wherein, the GIDL current refers to a leakage mechanism of the transistor in the off state, and for an N-type transistor, it occurs in the state of high voltage at the drain and zero or negative voltage at the gate. In this case, the N-type transistor should be in the off state, and the off current Ioff should be small. However, due to the existence of the GIDL current, the off current Ioff is large, and becomes more obvious with the increase of the negative voltage at the gate.

[0054] Generally, according to the data retention time or the size of the sensing margin, the storage unit is divided into a main unit and a tail storage unit.

[0055] The bit line contact resistance RBLC, the transistor contact resistance RNC and the capacitor resistance RCH of the main unit are small, and the gate-induced drain leakage current and the P-N junction leakage current are small, which results in a large voltage difference dVBL between the bit line BL and the complementary bit line BLB. The retention time and the refresh time tREF are related to the voltage difference dVBL between the bit line BL and the complementary bit line BLB, and the sensing margin is related to the refresh time tREF and the voltage difference dVBL between the bit line BL and the complementary bit line BLB. The sensing margin and the data retention time of the main storage unit are good.

[0056] The bit line contact resistance RBLC, the transistor contact resistance RNC and the capacitor resistance RCH of the tail storage unit are large, and the gate-induced drain leakage current and the P-N junction leakage current are large, which results in a small voltage difference dVBL between the bit line BL and the complementary bit line BLB. The sensing margin and the data retention time of the tail storage unit are poor.

[0057] In addition, there is a data preference problem in the memory. The sensing margin when reading data from the memory by setting a test condition that is not conducive to reading out data "1" is referred to as the sensing margin D1 SM of data "1", and the sensing margin when reading data from the memory by setting a test condition that is not conducive to reading out data "0" is referred to as the sensing margin D0 SM of data "0". There may be a case where D1 SM and D0 SM are not equal. That is, the case where D1 SM is greater than D0 SM, or the case where D0 SM is greater than D1 SM.

[0058] For the tail storage unit, the leakage current, resistance and data preference in the storage unit are more obvious, and will be further deteriorated with the change of the working temperature of the memory. Therefore, improving the performance and yield of the tail storage unit is the key to improving the overall performance and yield of the memory chip.

[0059] Some aspects of embodiments of the present disclosure relate to the above considerations. The following describes the solutions in conjunction with some embodiments of the present disclosure. For ease of description, the data "1" is referred to as the first data, and the data "0" is referred to as the second data.

[0060] Figure 5 This is a flow chart of a memory control method provided in some embodiments of the present application. Figure 5 As shown, some embodiments of the present application provide a memory control method comprising the following steps:

[0061] S101: Obtain the operating temperature of the memory.

[0062] In this step, a sensor may be used to detect the operating temperature of the memory.

[0063] S102: Regulate the voltage of the storage unit in the memory according to the operating temperature of the memory.

[0064] In this step, the voltage of the memory cell includes one or more of the voltage Vblh of the capacitor top plate when the memory cell stores the first data, the voltage Vad2 on the bit line before the transistor in the memory cell is turned on, and the gate turn-on voltage Vwlp of the transistor. When the memory cell stores the first data, the voltage of the capacitor top plate is greater than the voltage of the capacitor bottom plate.

[0065] For the convenience of subsequent description, the voltage Vblh on the upper plate of the capacitor when the memory cell stores the first data is referred to as the core voltage Vblh of the memory cell, and the voltage Vad2 on the bit line before the transistor in the memory cell is turned on is referred to as the bit line precharge voltage Vad2.

[0066] Adjusting the core voltage Vblh of a memory cell based on the memory's operating temperature data can reduce the voltage at the drain and / or source of the transistor, thereby reducing GIDL current, minimizing charge loss on the capacitor, improving sensing margin, and reducing the probability of sensing errors by the sense amplifier, thereby improving the memory's data readout accuracy. Furthermore, by adjusting the core voltage Vblh of a memory cell based on the memory's operating temperature data, the gate-to-source voltage difference Vgs of the transistor and the current Ids between the transistor's source and drain can be adjusted to accommodate a shorter write recovery time tWR and a shorter refresh time tREF.

[0067] By adjusting the bit line precharge voltage Vad2 according to the operating temperature data of the memory, the sensing margin of the first data or the sensing margin of the second data can be adjusted, thereby adjusting the data preference of the memory.

[0068] At different operating temperatures of the memory, it is necessary to set different gate turn-on voltages Vwlp of the transistors.

[0069] In the above technical solution, the working temperature data of the memory is acquired, and one or more of the voltage Vblh of the upper plate of the capacitor when the storage unit stores the first data, the bit line pre-charge voltage Vad2, and the gate opening voltage Vwlp of the transistor are adjusted according to the temperature data, so that the performance of the tail storage unit can be adjusted, and the overall performance of the memory is improved, and the yield of the memory is improved.

[0070] More specifically, the first temperature threshold Th1 and the second temperature threshold Th2 are set to determine the high-temperature range, the normal-temperature range, and the low-temperature range of the memory. The first temperature threshold Th1 is less than the second temperature threshold Th2. When the working temperature of the memory is less than or equal to the first temperature threshold Th1, the memory works in the low-temperature range. When the working temperature of the memory is greater than the first temperature threshold Th1 and less than or equal to the second temperature threshold Th2, the memory works in the normal-temperature range. When the working temperature of the memory is greater than the second temperature threshold Th2, the memory works in the high-temperature range.

[0071] The first temperature threshold Th1 and the second temperature threshold Th2 can be set according to actual needs, which are only used as examples here. For example, the first temperature threshold can be between 15°C and 20°C. If the first temperature threshold Th1 is 20°C and the second temperature threshold Th2 is 45°C, when the working temperature of the memory Tc≤20°C, the memory works in the low-temperature range. When the working temperature of the memory 20°C

[0072] In addition, the third temperature threshold Th3 and the fourth temperature threshold Th4 can also be set, the third temperature threshold Th3 is less than the first temperature threshold Th1, and the fourth temperature threshold Th4 is greater than the second temperature threshold Th2. When the working temperature of the memory is less than or equal to the first temperature threshold Th1 and greater than the third temperature threshold Th3, the memory works in the low-temperature range. When the working temperature of the memory is greater than the second temperature threshold Th2 and less than or equal to the fourth temperature threshold Th4, the memory works in the high-temperature range.

[0073] The third temperature threshold Th3 and the fourth temperature threshold Th4 can be set according to actual needs, which are only used as examples here. For example, the third temperature threshold Th3 is -40°C, and the fourth temperature threshold Th4 is 95°C. When the working temperature of the memory -40°C

[0074] Figure 6 The flowchart of the control method of the memory provided by some embodiments of the present application is shown. As shown in FIG. 1, the control method of the memory includes the following steps. Figure 6 As shown, the core voltage Vblh of the storage unit is adjusted according to the working temperature Tc of the memory, specifically including:

[0075] S201, when the working temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the core voltage Vblh of the storage unit is controlled to be greater than the upper plate reference voltage Vref1.

[0076] Wherein, when the working temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the memory works in a low temperature range.

[0077] The frequency response of the capacitor Cs in each storage unit is slower, and the effective capacitance value of the capacitor Cs is smaller in the low temperature range, which will cause the voltage difference dVBL between the bit line and the complementary bit line to be smaller during charge sharing. So that the sensing margin of the main storage unit and the tail storage unit is relatively small, and the refresh time is relatively long. That is, the performance of the main storage unit and the tail storage unit is much worse. Therefore, the main adjustment target is the main storage unit when working in the low temperature range.

[0078] When the memory works in the low temperature range, the core voltage Vblh of the storage unit is increased to increase the voltage difference between the bit line and the complementary bit line corresponding to the main storage unit, and then to increase the sensing margin of the sensitive amplifier corresponding to the main storage unit.

[0079] For example: the upper plate reference voltage Vref1 is 1V, when the memory works in the low temperature range, the core voltage Vblh of the storage unit is adjusted to be greater than 1V, more specifically, the value of the core voltage Vblh of the storage unit is in the range of [1.02V~1.06V]. In this way, the sensing margin of the sensitive amplifier corresponding to the main storage unit is increased.

[0080] S202, when the working temperature Tc of the memory is greater than the first temperature threshold Th1 and the working temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the core voltage Vblh of the storage unit is adjusted according to the type of the memory.

[0081] Wherein, when the working temperature Tc of the memory is greater than the first temperature threshold Th1 and the working temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the memory works in a normal temperature range.

[0082] When the memory works in the normal temperature range, the power consumption of the memory is a factor that needs to be considered, especially for the memory applied to mobile electronic devices. When adjusting the core voltage Vblh of the storage unit, it is necessary to avoid increasing the circuit power consumption.

[0083] The type of the memory is obtained when the memory operates in a normal temperature range. The memory includes SDRAM, double data rate SDRAM of each generation, and low power double data rate SDRAM of each generation.

[0084] The double data rate SDRAM of each generation includes double data rate SDRAM of the first generation, double data rate SDRAM of the second generation, …, and double data rate SDRAM of the xth generation.

[0085] The low power double data rate SDRAM of each generation includes low power double data rate SDRAM of the first generation, low power double data rate SDRAM of the second generation, …, and low power double data rate SDRAM of the yth generation.

[0086] The SDRAM and the double data rate SDRAM of each generation are non-low power type memories, and the low power double data rate SDRAM of each generation is a low power type memory.

[0087] Different adjustment strategies of the core voltage Vblh of the memory cell are set according to the type of the memory when the memory operates in the normal temperature range.

[0088] In some embodiments, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power, the core voltage Vblh of the memory cell is controlled to be the upper plate reference voltage Vref1. That is, when the memory operates in the normal temperature range and the memory is a low power memory, the core voltage Vblh of the memory cell is not adjusted, so as to avoid increasing the loss of the memory due to the adjustment of the core voltage Vblh of the memory cell.

[0089] In some embodiments, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is non-low power, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage Vref1. That is, when the memory operates in the normal temperature range and the memory is a non-low power memory, the core voltage Vblh of the memory cell is adjusted to be less than the upper plate reference voltage Vref1, so as to reduce the leakage current of the transistor in the memory, improve the voltage difference dVBL between the bit line and the complementary bit line corresponding to the memory cell, and improve the sensing margin of the tail memory cell. In addition, reducing the core voltage Vblh of the memory cell improves the gate-to-source voltage difference Vgs of the adjustment transistor, increases the current Ids between the source and the drain of the transistor, so as to adapt to smaller write recovery time tWR and shorter refresh time tREF, thereby improving the overall performance of the memory.

[0090] For example, if the plate reference voltage Vref1 is 1V, when the memory operates at room temperature and is a low-power memory, the core voltage Vblh of the memory cell is maintained constant at the upper plate reference voltage of 1V. When the memory operates at room temperature and is not a low-power memory, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage. More specifically, the core voltage Vblh of the memory cell ranges from 0.99V to 1.0V.

[0091] S203 : When the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , controlling the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1 .

[0092] Among them, when the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the memory operates in a high temperature range. When the memory operates in a high temperature range, the reliability of the transistors in the memory decreases and the leakage current is large. Adjusting the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1 can reduce the leakage current of the transistors in the memory, increase the voltage difference dVBL between the bit line corresponding to the memory cell and the complementary bit line, and improve the sensing margin of the tail memory cell. In addition, reducing the core voltage Vblh of the memory cell, increasing the voltage difference Vgs from the gate to the source of the adjustment transistor, and increasing the current Ids between the source and drain of the transistor can adapt to a shorter write recovery time tWR and a shorter refresh time tREF, thereby improving the overall performance of the memory.

[0093] For example, if the plate reference voltage Vref1 is 1V, when the memory operates in a high temperature range, the core voltage Vblh of the memory cell is controlled to be lower than the upper plate reference voltage. More specifically, the core voltage Vblh of the memory cell has a value range of [0.9V~1.0V].

[0094] When the memory operates in a high temperature range and when the memory operates in a normal temperature range and the memory is not a low-power memory, the core voltage Vblh of the memory unit is controlled to be lower than the upper plate reference voltage Vref1. Since the leakage of the transistor when the memory operates in a normal temperature range is lower than the leakage of the transistor when the memory operates in a high temperature range, the core voltage Vblh of the memory unit when the memory operates in a normal temperature range and the memory is not a low-power memory is higher than the core voltage Vblh of the memory unit when the memory is controlled to operate in a high temperature range.

[0095] That is, when the first condition is met, the core voltage Vblh of the memory cell is greater than the core voltage Vblh of the memory cell when the second condition is met. The first condition being met specifically includes the memory's operating temperature Tc being greater than a first temperature threshold Th1, the memory's operating temperature Tc being less than or equal to a second temperature threshold Th2, and the memory being of a non-low power type. The second condition being met specifically includes the memory's operating temperature Tc being greater than a second temperature threshold Th2.

[0096] In the above technical solution, the core voltage Vblh of the memory cell is adjusted according to the operating temperature Tc of the memory, which can improve the overall performance of the memory. When the memory operates in a normal temperature range, the core voltage Vblh of the memory cell is adjusted according to the type of memory, which can meet the low power consumption requirements of the memory for mobile electronic devices.

[0097] Figure 7 This is a flow chart of a memory control method provided in some embodiments of the present application. Figure 7 As shown, the bit line precharge voltage Vad2 is adjusted according to the operating temperature Tc of the memory, specifically including:

[0098] S301 : When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , control the bit line precharge voltage Vad2 to be greater than the bit line reference voltage Vref2 .

[0099] When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , the memory operates in a low temperature range.

[0100] When the memory operates in a low-temperature range, the sensing margin D0 SM of the second data is smaller than the sensing margin D1 SM of the first data. By adjusting the bitline precharge voltage Vad2 to be greater than the bitline reference voltage Vref2, the sensing margin D1 SM of the first data can be reduced, thereby narrowing the difference between the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data, thereby balancing the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data.

[0101] For example, if the bit line reference voltage Vref2 is 0.5V, when the memory operates in a low temperature range, the bit line precharge voltage Vad2 is controlled to be greater than the bit line reference voltage Vref2. More specifically, the value range of the bit line precharge voltage Vad2 is [0.51V-0.55V].

[0102] S302 : When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and is less than or equal to the second temperature threshold Th2 , adjust the bit line precharge voltage Vad2 according to the type of the memory.

[0103] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and is less than or equal to the second temperature threshold Th2, the memory operates in a normal temperature range.

[0104] When the memory operates at room temperature, the power consumption of the memory is a key factor to be considered, especially for the memory used in mobile electronic devices. Therefore, when adjusting the bit line precharge voltage Vad2, it is necessary to avoid increasing the circuit power consumption.

[0105] When the memory operates in a normal temperature range, different adjustment strategies for the bit line precharge voltage Vad2 are set according to the type of the memory to adjust the data preference of the memory.

[0106] When the memory operates in a normal temperature range, the sensing margin D1 SM of the first data is smaller than the sensing margin D0 SM of the second data.

[0107] In some embodiments, when the operating temperature Tc of the memory is greater than a first temperature threshold Th1, less than or equal to a second temperature threshold Th2, and the memory is of low power consumption type, the bitline precharge voltage Vad2 is controlled to be the bitline reference voltage Vref2. That is, when the memory operates within a normal temperature range and is of low power consumption type, the bitline precharge voltage Vad2 is not adjusted, thereby avoiding increasing memory wear due to adjustment of the bitline precharge voltage Vad2.

[0108] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the memory is not of a low-power type, the bitline precharge voltage Vad2 is controlled to be less than the bitline reference voltage Vref2. That is, when the memory operates within a normal temperature range and is not of a low-power type, adjusting the bitline precharge voltage Vad2 to be less than the bitline reference voltage Vref2 can reduce the sensing margin D0 SM of the second data, narrow the difference between the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data, and balance the sensing margin D1 SM of the first data with the sensing margin D0 SM of the second data.

[0109] For example, if the bitline reference voltage Vref2 is 0.5V, when the memory operates at room temperature and is a low-power memory, the bitline precharge voltage Vad2 is maintained constant at 0.5V. When the memory operates at room temperature and is not a low-power memory, the bitline precharge voltage Vad2 is controlled to be lower than the bitline reference voltage Vref2. More specifically, the value range of the bitline precharge voltage Vad2 is [0.49V-0.5V].

[0110] S303, when the working temperature Tc of the memory is greater than the second temperature threshold Th2, the bit line pre-charge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2.

[0111] When the working temperature Tc of the memory is greater than the second temperature threshold Th2, the memory works in a high temperature range. When the memory works in the high temperature range, the transistor reliability in the memory decreases, and the leakage current is large.

[0112] When the memory works in the high temperature range, the sensing margin D1 SM of the first data is less than the sensing margin D0 SM of the second data. By adjusting the bit line pre-charge voltage Vad2 to be less than the bit line reference voltage Vref2, the sensing margin D0 SM of the second data can be reduced, the difference between the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data can be reduced, and the sensing margin D1 SM of the first data and the sensing margin D0 SM of the second data can be balanced.

[0113] For example, when the bit line reference voltage Vref2 is 0.5V, the bit line pre-charge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2 when the memory works in the high temperature range. More specifically, the bit line pre-charge voltage Vad2 is in the range of [0.45V~0.5V].

[0114] The bit line pre-charge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2 when the memory works in the high temperature range and when the memory works in the normal temperature range and the memory is a non-low-power memory. Since the leakage amount of the transistor when the memory works in the normal temperature range is less than the leakage amount of the transistor when the memory works in the high temperature range, the bit line pre-charge voltage Vad2 when the memory works in the normal temperature range and the memory is a non-low-power memory is greater than the bit line pre-charge voltage Vad2 when the memory works in the high temperature range.

[0115] That is, the bit line pre-charge voltage Vad2 when the first condition is met is greater than the bit line pre-charge voltage Vad2 in the memory when the second condition is met. The first condition specifically includes that the working temperature of the memory is greater than the first temperature threshold, the working temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low-power. The second condition specifically includes that the working temperature of the memory is greater than the second temperature threshold.

[0116] In the above technical solution, the bit line pre-charge voltage Vad2 is adjusted according to the working temperature Tc of the memory, which can improve the overall performance of the memory, and the bit line pre-charge voltage Vad2 is adjusted according to the type of the memory when the memory works in the normal temperature range, which can adapt to the low-power demand of the memory for mobile electronic devices.

[0117] In some embodiments, adjusting the gate turn-on voltage Vwlp of the transistor according to the operating temperature Tc of the memory specifically includes:

[0118] S401 : When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , the gate turn-on voltage Vwlp of the control transistor is controlled to be the gate reference voltage Vref3 .

[0119] S402 : When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2 , the gate turn-on voltage Vwlp of the control transistor is set to the gate reference voltage Vref3 .

[0120] S403 : When the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , the gate turn-on voltage Vwlp of the control transistor is controlled to be less than the gate reference voltage Vref3 .

[0121] When the memory's operating temperature Tc is greater than the second temperature threshold Th2, the memory operates in a high-temperature range. When the memory operates in this high-temperature range, the reliability of the transistors within the memory decreases, and leakage current increases. The gate threshold voltage Vwlp of the control transistor is adjusted to be lower than the gate reference voltage Vref3, that is, a lower gate threshold voltage is used. However, a lower gate threshold voltage causes the sensing margin D1 SM of the first data to be smaller than the sensing margin D0 SM of the second data. Therefore, the bitline precharge voltage Vad2 can be controlled to be lower than the bitline reference voltage Vref2 to reduce the sensing margin D0 SM of the second data.

[0122] In the above technical solution, the gate reference voltage Vref3 is adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0123] Figure 8 This is a flow chart of a memory control method provided in some embodiments of the present application. Figure 8 As shown, some embodiments of the present application further provide a memory control method, the control method comprising:

[0124] S501 , when the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , controlling the core voltage Vblh of the memory cell to be greater than the upper plate reference voltage Vref1 , and controlling the bit line precharge voltage Vad2 to be greater than the bit line reference voltage Vref2 .

[0125] S502 , when the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and is less than or equal to the second temperature threshold Th2 , adjusting the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell according to the type of the memory.

[0126] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the memory cell is controlled to be the upper plate reference voltage Vref1, and the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Ref2.

[0127] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, and the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Ref2.

[0128] S503 , when the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , controlling the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1 , and controlling the bit line precharge voltage Vad2 to be less than the bit line reference voltage Vref2 .

[0129] In the above technical solution, the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell are adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0130] Here, the memory operates in a high temperature range, and the core voltage Vblh of the memory cell is controlled to be lower than the upper plate reference voltage Vref1 , and the bit line precharge voltage Vad2 is controlled to be lower than the bit line reference voltage Vref2 .

[0131] Figure 9A Schematic diagram of the relationship between the core voltage of the memory cell and the bit line precharge voltage. Figure 9A As shown, when the memory operates in a high temperature range, if the core voltage Vblh of the memory cell is still maintained at 1V, the bit line precharge voltage Vad2 is 0.5V, the voltage difference between the main memory cell and the bit line is 1.0V-0.5V=0.5V, and the voltage difference between the tail main memory cell and the bit line is 0.6V-0.5V=0.1V.

[0132] When the memory operates in a high-temperature range, if the core voltage Vblh of the control memory cells is reduced to 0.95V and the bitline precharge voltage Vad2 is reduced to 0.475V, the voltage difference between the main memory cells and the bitline is 0.95V-0.475V = 0.475V, and the voltage difference between the tail memory cells and the bitline is 0.58V-0.475V = 0.105V. This means that by simultaneously reducing the core voltage Vblh and the bitline precharge voltage Vad2 of the memory cells, the performance of the main memory cells is reduced, but the performance of the tail memory cells is improved. While the reduction in the performance of the main memory cells does not affect the memory's yield, the improved performance of the tail memory cells does improve the memory's yield.

[0133] Figure 9B This is a schematic diagram of the distribution of dVBL provided in some embodiments of the present application. Figure 9B As shown, the horizontal axis dVBL represents the voltage difference between the bit line BL and the complementary bit line BLB after the memory cell and the bit line BL share charge. A larger dVBL indicates a higher accuracy rate in reading and writing data. The dashed line represents the dVbl distribution before lowering the memory cell's core voltage Vblh and the bit line precharge voltage Vad2, while the solid line represents the dVbl distribution after lowering the memory cell's core voltage Vblh and the bit line precharge voltage Vad2. Lowering the memory cell's core voltage Vblh reduces the dVBL of the main memory cell, but increases the dVBL of the tail memory cell. While the performance degradation of the main memory cell does not affect the memory's yield, the increased dVBL of the tail memory cell helps save the tail memory cells that otherwise would not be correctly sensed, thereby improving the memory cell yield.

[0134] Figure 10 This is a flow chart of a memory control method provided in some embodiments of the present application. Figure 10 As shown, some embodiments of the present application further provide a memory control method, the control method comprising:

[0135] S601. When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1, the core voltage Vblh of the memory cell is controlled to be greater than the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be greater than the bit line reference voltage Vref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0136] S602. When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the core voltage Vblh and the bit line precharge voltage Vad2 of the memory cell are adjusted according to the type of the memory, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0137] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the storage unit is controlled to be the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0138] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0139] S603. When the operating temperature Tc of the memory is greater than the second temperature threshold Th2, the core voltage Vblh of the memory cell is controlled to be less than the upper plate reference voltage Vref1, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Vref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be less than the gate reference voltage Vref3.

[0140] In the above technical solution, the core voltage Vblh of the memory cell, the bit line precharge voltage Vad2 and the gate turn-on voltage Vwlp of the transistor are adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0141] Figure 11 This is a flow chart of a memory control method provided in some embodiments of the present application. Figure 11 As shown, some embodiments of the present application further provide a memory control method, the control method comprising:

[0142] S701 , when the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , controlling the core voltage Vblh of the memory cell to be greater than the upper plate reference voltage Vref1 , and controlling the gate turn-on voltage Vwlp of the transistor to be the gate reference voltage Vref3 .

[0143] S702. When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, adjust the core voltage Vblh of the memory cell according to the type of the memory, and control the gate turn-on voltage Vwlp of the transistor to be the gate reference voltage Vref3.

[0144] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the core voltage Vblh of the storage unit is controlled to be the upper plate reference voltage Vref1, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0145] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power, the core voltage Vblh of the storage unit is controlled to be less than the upper plate reference voltage Vref1, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0146] S703 , when the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , controlling the core voltage Vblh of the memory cell to be less than the upper plate reference voltage Vref1 , and controlling the gate turn-on voltage Vwlp of the transistor to be less than the gate reference voltage Vref3 .

[0147] In the above technical solution, the core voltage Vblh of the memory cell and the gate turn-on voltage Vwlp of the transistor are adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0148] Figure 12 This is a flow chart of a memory control method provided in some embodiments of the present application. Figure 12 As shown, some embodiments of the present application further provide a memory control method, the control method comprising:

[0149] S801 . When the operating temperature Tc of the memory is less than or equal to the first temperature threshold Th1 , control the bit line precharge voltage Vad2 to be greater than the bit line reference voltage Vref2 , and control the gate turn-on voltage Vwlp of the transistor to be the gate reference voltage Vref3 .

[0150] S802. When the operating temperature Tc of the memory is greater than the first temperature threshold Th1 and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, the bit line precharge voltage Vad2 is adjusted according to the type of the memory, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0151] More specifically, when the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is low power consumption, the bit line precharge voltage Vad2 is controlled to be the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0152] When the operating temperature Tc of the memory is greater than the first temperature threshold Th1, and the operating temperature Tc of the memory is less than or equal to the second temperature threshold Th2, and the type of the memory is not low power, the bit line precharge voltage Vad2 is controlled to be less than the bit line reference voltage Ref2, and the gate turn-on voltage Vwlp of the transistor is controlled to be the gate reference voltage Vref3.

[0153] S803 , when the operating temperature Tc of the memory is greater than the second temperature threshold Th2 , control the bit line precharge voltage Vad2 to be less than the bit line reference voltage Vref2 , and control the gate turn-on voltage Vwlp of the transistor to be less than the gate reference voltage Vref3 .

[0154] In the above technical solution, the bit line precharge voltage Vad2 and the gate turn-on voltage Vwlp of the transistor are adjusted according to the operating temperature Tc of the memory, so as to improve the overall performance of the memory.

[0155] Some embodiments of the present application further provide a control circuit of a memory, the memory including a memory cell connected to a bit line, the control circuit including: a temperature monitoring circuit and a voltage control circuit;

[0156] The temperature monitoring circuit monitors the operating temperature of the memory;

[0157] The voltage control circuit is connected to the temperature monitoring circuit, and the voltage control circuit adjusts the voltage of the storage unit in the memory according to the operating temperature of the memory;

[0158] Among them, the voltage of the storage cell includes one or more of the voltage of the upper plate of the capacitor when the storage cell stores the first data, the voltage on the bit line before the transistor in the storage cell is turned on, and the gate turn-on voltage of the transistor. When the storage cell stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor.

[0159] In some embodiments, the voltage control circuit is further configured to:

[0160] When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage of the upper plate of the capacitor to be greater than the upper plate reference voltage when the storage unit stores the first data;

[0161] When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be greater than a bit line reference voltage; and

[0162] When the operating temperature of the memory is less than or equal to the first temperature threshold, the gate turn-on voltage of the control transistor is the gate reference voltage.

[0163] In some embodiments, the voltage control circuit is further configured to:

[0164] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the first data is stored in the storage unit;

[0165] When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage;

[0166] When the operating temperature of the memory is greater than a second temperature threshold, the gate turn-on voltage of the control transistor is less than the gate reference voltage; and

[0167] The second temperature threshold is greater than the first temperature threshold.

[0168] In some embodiments, the voltage control circuit is further configured to:

[0169] When the operating temperature of the memory is greater than a first temperature threshold and the operating temperature of the memory is less than or equal to a second temperature threshold, the voltage of the storage unit in the memory is adjusted according to the model of the memory.

[0170] In some embodiments, the voltage control circuit is further configured to:

[0171] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage of the upper plate of the capacitor to be an upper plate reference voltage when the storage unit stores the first data; and

[0172] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be a bit line reference voltage;

[0173] The second temperature threshold is greater than the first temperature threshold.

[0174] In some embodiments, the voltage control circuit is further configured to:

[0175] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold; and the type of the memory is not low power consumption, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the storage unit stores the first data; and

[0176] When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is not low power consumption, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage;

[0177] The second temperature threshold is greater than the first temperature threshold.

[0178] In some embodiments, when the first condition is satisfied, the voltage on the upper plate of the capacitor when the memory cell stores the first data is greater than the voltage on the upper plate of the capacitor when the memory cell stores the first data when the second condition is satisfied;

[0179] Among them, satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0180] In some embodiments, the voltage on the bit line before the transistor in the memory cell is turned on when the first condition is satisfied is greater than the voltage on the bit line before the transistor in the memory cell is turned on when the second condition is satisfied;

[0181] Satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

[0182] Some embodiments of the present application further provide a memory, comprising: a memory unit and the control circuit involved in the above embodiments, wherein the memory unit is connected to a bit line.

[0183] It should be noted that the terms "high level" and "low level" in the above embodiments are relative concepts (i.e., the voltage value of the high level is higher than the voltage value of the corresponding low level). They do not limit the specific voltage values ​​of the high level or the low level. Furthermore, in this specific embodiment, the high levels applied to different signal lines are not necessarily equal. For example, the high level of the bit line and the high level of the word line can be different voltages. Nor is it necessarily true that the high levels of a particular signal line are equal at different stages. For example, the high level applied to the bit line during a write-1 operation and during a read operation can be different voltages. Those skilled in the art will appreciate that the corresponding high and low level values ​​can be set based on the process node, speed requirements, reliability requirements, and the like.

[0184] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0185] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A memory control method, characterized in that: The memory includes a memory cell connected to a bit line, and the method includes: Obtaining an operating temperature of the memory; Setting a first temperature threshold and a second temperature threshold to determine a high temperature range, a normal temperature range, and a low temperature range of the memory, wherein the second temperature threshold is greater than the first temperature threshold; adjusting the voltage of a storage unit in the memory according to the operating temperature range of the memory; In which, the voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor. When the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor; the gate turn-on voltage is the voltage of the enable signal used to turn on the transistor preset before the transistor is turned on.

2. The control method according to claim 1, characterized in that: Adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following: When the operating temperature of the memory is less than or equal to a first temperature threshold, controlling the voltage of the upper plate of the capacitor to be greater than an upper plate reference voltage when the first data is stored in the storage unit; When the operating temperature of the memory is less than or equal to the first temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be greater than a bit line reference voltage; as well as When the operating temperature of the memory is less than or equal to the first temperature threshold, the gate turn-on voltage of the transistor is controlled to be a gate reference voltage.

3. The control method according to claim 1, wherein: Adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes at least one of the following: When the operating temperature of the memory is greater than a second temperature threshold, controlling the voltage of the upper plate of the capacitor to be less than an upper plate reference voltage when the first data is stored in the storage unit; When the operating temperature of the memory is greater than the second temperature threshold, controlling the voltage on the bit line before the transistor in the memory cell is turned on to be less than a bit line reference voltage; as well as When the operating temperature of the memory is greater than a second temperature threshold, controlling the gate turn-on voltage of the transistor to be less than a gate reference voltage; The second temperature threshold is greater than the first temperature threshold.

4. The control method according to claim 1, wherein: Adjusting the voltage of a storage unit in the memory according to the operating temperature of the memory specifically includes: When the operating temperature of the memory is greater than a first temperature threshold and the operating temperature of the memory is less than or equal to a second temperature threshold, the voltage of the storage unit in the memory is adjusted according to the model of the memory; wherein the second temperature threshold is greater than the first temperature threshold.

5. The control method according to claim 4, wherein: When the operating temperature of the memory is greater than a first temperature threshold and the operating temperature of the memory is less than or equal to a second temperature threshold, the following steps are performed according to the model of the memory: When the operating temperature of the memory is greater than a first temperature threshold, the operating temperature of the memory is less than or equal to a second temperature threshold, and the type of the memory is low power consumption, controlling the voltage of the upper plate of the capacitor to be an upper plate reference voltage when the first data is stored in the storage unit; and When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is low power consumption, the voltage on the bit line before the transistor in the storage unit is turned on is controlled to be the bit line reference voltage.

6. The control method according to claim 4, wherein: Adjusting the voltage of a storage unit in the memory according to the model of the memory and the operating temperature of the memory specifically includes at least one of the following: When the operating temperature of the memory is greater than a first temperature threshold and the operating temperature of the memory is less than or equal to a second temperature threshold; and when the type of the memory is not low power consumption, controlling the voltage of the upper plate of the capacitor to be less than the upper plate reference voltage when the first data is stored in the storage unit; as well as When the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is not low power consumption, the voltage on the bit line is controlled to be less than the bit line reference voltage before the transistor in the storage unit is turned on.

7. The control method according to claim 6, characterized in that: When the first condition is met, the voltage of the upper plate of the capacitor when the storage unit stores the first data is greater than the voltage of the upper plate of the capacitor when the storage unit stores the first data when the second condition is met; Among them, satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

8. The control method according to claim 6, characterized in that: When the first condition is met, the voltage on the bit line before the transistor in the memory cell is turned on is greater than the voltage on the bit line before the transistor in the memory cell is turned on when the second condition is met; Satisfying the first condition specifically includes: the operating temperature of the memory is greater than the first temperature threshold, the operating temperature of the memory is less than or equal to the second temperature threshold, and the type of the memory is non-low power consumption; satisfying the second condition specifically includes: the operating temperature of the memory is greater than the second temperature threshold.

9. A memory control circuit, characterized in that: The memory includes a storage unit connected to a bit line, and the control circuit includes: a temperature monitoring circuit and a voltage control circuit; The temperature monitoring circuit monitors the operating temperature of the memory; The voltage control circuit is connected to the temperature monitoring circuit, and the voltage control circuit adjusts the voltage of the storage unit in the memory according to the operating temperature range of the memory; wherein the operating temperature range includes a high temperature range, a normal temperature range, and a low temperature range, and is set by a first temperature threshold and a second temperature threshold, and the second temperature threshold is greater than the first temperature threshold; The voltage of the storage unit includes one or more of the voltage of the upper plate of the capacitor when the storage unit stores the first data, the voltage on the bit line before the transistor in the storage unit is turned on, and the gate turn-on voltage of the transistor, and when the storage unit stores the first data, the voltage of the upper plate of the capacitor is greater than the voltage of the lower plate of the capacitor; The gate-on voltage is a voltage of an enable signal that is preset before the transistor is turned on and is used to turn on the transistor.

10. A memory, characterized in that: include: A memory cell and a control circuit as claimed in claim 9, wherein the memory cell is connected to a bit line.

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