Power simulation and estimation

Abstract

The invention relates to power simulation and estimation. An example method for power simulation and estimation includes estimating a functional power consumption value associated with a memory system by determining: a scan-based power estimation; a power measurement based on the scan; a calibration factor from correlating the scan-based power estimate with the scan-based power measurement; and related functional power using the calibration factor. The calibration factor may be applied to functional power estimation in order to achieve higher accuracy.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to memory power simulation and estimation. Background Art

[0002] Memory systems may include digital logic and associated power supply, voltage control, and clock control. In general, the power supply, voltage control, and / or clock control may change the voltage or frequency during operation of the digital logic. Summary of the invention

[0003] On the one hand, the present application provides a method for power simulation and estimation, which includes: estimating functional power consumption values ​​associated with a memory system by determining: a scan-based power estimate; a scan-based power measurement; a calibration factor from correlating the scan-based power estimate with the scan-based power measurement; and a correlated functional power using the calibration factor.

[0004] On the other hand, the present application provides a method for power simulation and estimation, which includes: estimating functional power consumption values ​​associated with a memory system by: using a tester to determine a scan-based power measurement to apply an automatic test pattern generator (ATPG) pattern to a silicon die; using a simulation vector to determine a scan-based power estimate; correlating the scan-based power measurement with the scan-based power estimate to generate a calibration factor; and using the calibration factor to determine a final functional power estimate.

[0005] On the other hand, the present application provides an apparatus for power simulation and estimation, comprising: a memory; and a processing device coupled to the memory, the processing device being configured to: estimate a functional power consumption value associated with a memory system by determining: a function switching activity vector using register transfer level (RTL) data and function verification data; a gate-level function power estimation, wherein the gate-level function power estimation uses a plurality of function vectors; a scan-based power estimation, wherein the scan-based power estimation uses a scan vector from a scan mode simulation, wherein the scan mode simulation is generated using a final netlist; a scan-based power measurement, wherein the scan-based power measurement uses the final netlist to determine a layout of a silicon die and tests the silicon die to determine the scan-based power measurement; and a calibration factor based on a comparison of the scan-based power estimation with the scan-based power measurement, wherein the calibration factor is used together with the gate-level function power estimation to adjust the gate-level function power estimation, the RTL-based function power estimation, or both. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example memory subsystem for power simulation and estimation according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example system for power simulation and estimation according to some embodiments of the present disclosure is described.

[0009] Figure 3A FIG. 1 shows an example of a power simulation and estimation method according to some embodiments of the present disclosure.

[0010] Figure 4 An example diagram illustrating a power simulation and estimation method according to some embodiments of the present disclosure.

[0011] Figure 5 Example methods for power simulation and estimation according to some embodiments of the present disclosure are described.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure relate to power simulation and estimation. It may be beneficial to reduce power consumption in digital logic circuits. Memory systems may increasingly occupy more area in a system on chip (SoC). Power estimation may determine whether a memory device will meet a target power specification. In today's world, electronic devices may have high transistor densities. Therefore, more interconnects between these elements may be used and therefore the share of power consumed in the interconnects may increase compared to the total power consumption. Therefore, additional cooling loops may be employed and / or component (e.g., battery) life may be shortened. Power estimation may mitigate or avoid problems associated with additional cooling and reliability. For example, power estimation may thereby determine the extent to which additional cooling may be required to mitigate any reliability issues, etc. Therefore, it may be desirable to obtain accurate power estimates.

[0014] Power consumption may depend on both the physical structure and the operating mode on the chip. For today's multi-mode SoCs, it is increasingly challenging to determine the correct stimulus to verify the average power and peak power across multiple modes. In order to estimate power more accurately, switching activity data can be obtained by simulating test cases using real system stimulus. Typically, this simulation is not available until the late stage of the design cycle. If switching activity data cannot be obtained from the simulation, the switching activity on the main input of the chip can be estimated and the estimation can be applied in the power analysis tool. For example, transient switching power can be estimated based on the number of flip-flops, combinational gates, and clock speeds. Power simulation can use power sensors and corresponding power models to extend hardware simulation technology to collect estimated power analysis data of the tested design. Power estimation may also be referred to as early power analysis or power simulation and may be based on modeling. In some instances, it is possible to obtain activity vectors from power simulation and apply them to power analysis. In other instances, power can be measured physically. Power estimation can be performed with or without switching activity input, but it may not be accurate when there is no vector. In either case, the specific switching activity profiles of all nodes can play a key role in the final accuracy of power estimation. The simulation can be performed using a field programmable gate array (FPGA) or other discrete components or a specific machine. It is possible to obtain activity vectors from power simulation and apply them to power analysis. In other cases, power can be measured physically. Either way, the exact switching activity profile of all nodes will affect the final accuracy.

[0015] In some previous methods, power consumption can be estimated only by real or pseudo gate-level simulation power analysis. In some previous methods, power consumption can be estimated by functional mode automatic test equipment (ATE) power measurement. In some previous methods, power consumption can be a direct or indirect power measurement. However, previous methods may be inaccurate due to the difficulty in generating switching activities. In addition, it may be difficult to align different parts of the design so that peak activities are simultaneously present. Early netlists may be significantly different from the final netlist. The model itself may have inaccuracies, etc. In simulation, the devices simulating ASIC structures may be physically different. They may use different architectures, structures, processes and / or may have completely different power characteristics. Therefore, measuring the power simulated by them may be quite off target. For example, these previous methods may have limitations when trying to analyze or simulate only part of the design.

[0016] To address the above and other deficiencies, the method herein estimates functional power consumption values ​​associated with a system by calibrating pre-silicon (Si) and post-silicon power values. The calibration may use multiple vectors from a scan mode simulation. A scan-based power estimate may use a scan vector from a scan mode simulation. As an example, a functional power estimate may be determined and a calibration factor may be used to modify the functional power estimate without using a full physical design to do so, and still produce an accurate estimate. In this way, estimates based on functional vectors from simulations may be modified using a calibration factor and be more accurate without using a full physical design. The following description demonstrates in more detail how this calibration factor is determined.

[0017] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0021] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0022] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] The memory devices 130, 140 may include various combinations of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include non-and (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130, 140 may include one or more arrays of memory cells. One type of memory cell (e.g., a single level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells (e.g., SLC, MLC, TLC, QLC, PLC, or any combination thereof). In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of a memory cell. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory devices 130, 140 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or provided by a processor or controller separate from the memory subsystem).

[0030] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130 and / or the memory device 140, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.). The memory subsystem controller 115 may further include a host interface circuit system for communicating with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0031] Memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0032] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] The memory subsystem 110 includes a power component 113, which may be configured to coordinate and / or perform operations related to power simulation and estimation and may use various components, data paths, and / or interfaces of the memory subsystem 110 to achieve the above operations. The power component 113 may include various circuit systems to facilitate power simulation and estimation and control the scanning and transfer of data from and to the memory cells of the memory devices 130, 140. For example, the power component 113 may include dedicated circuit systems in the form of ASICs, FPGAs, state machines, and / or other logic circuit systems or software and / or firmware, which may allow the power component 113 to coordinate and / or perform data storage operations related to programming memory cells in order to simulate and / or estimate power and communicate with various components, data paths, and / or interfaces of the memory subsystem 110.

[0034] Power component 113 may be communicatively coupled to memory devices 130 , 140 and may access memory devices 130 , 140 , internal data paths of memory subsystem 110 , and / or interfaces of memory subsystem 110 to perform the operations described herein and / or transfer storage data to additional elements of memory subsystem 110 .

[0035] In some embodiments, the memory subsystem controller 115 includes at least a portion of the power component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the power component 113 is part of a host system 120 (not illustrated), an application, or an operating system.

[0036] According to some embodiments of the present disclosure, Figure 1 The memory devices 130, 140 in the embodiment may include several physical blocks. For example, the memory devices 130, 140 may include a NAND flash memory array including the several physical blocks. However, the embodiments of the present disclosure are not limited to a specific type of memory or memory array. For example, the memory array may be a DRAM array, an RRAM array, or a PCRAM array, as well as other types of memory arrays. In addition, the memory array may be located on a specific semiconductor die together with various peripheral circuit systems associated with its operation.

[0037] The memory cells of the memory array may be mixed mode cells that may operate as SLC and / or XLC (e.g., may refer to additional level cells that may operate at a level greater than SLC, also referred to as non-SLC mode cells, where three-level cells (TLC) and four-level cells (QLC) are non-SLC mode cells). The number of physical blocks in the memory array may be 128 blocks, 512 blocks, or 1,024 blocks, but embodiments are not limited to a particular multiple of 128 or any particular number of physical blocks in the memory array. In addition, different portions of the memory may act as a dynamic SLC cache for media management operations such as garbage collection. For example, as the demand for memory increases and / or decreases, the size of different portions of the memory may be dynamically increased and / or decreased to allow garbage collection to more efficiently meet these demands.

[0038] Each physical block of the memory array may contain several physical rows of memory cells coupled to access lines (e.g., word lines). The number of rows (e.g., word lines) in each physical block may be 32, but embodiments are not limited to a particular number of rows per physical block. In addition, the memory cells may be coupled to sense lines (e.g., data lines and / or digit lines).

[0039] Each row may include several memory cell pages (e.g., physical pages). A physical page refers to a unit of programming and / or sensing (e.g., several memory cells that are programmed and / or sensed together as a functional group). Each row may include one memory cell physical page. However, the embodiments of the present disclosure are not limited thereto. For example, in several embodiments, each row may include multiple memory cell physical pages (e.g., one or more memory cell even pages coupled to even bit lines, and one or more memory cell odd pages coupled to odd bit lines). In addition, for embodiments including XLC, a memory cell physical page may store multiple data pages (e.g., logical pages), such as an upper data page and a lower data page, wherein each cell in the physical page stores one or more bits toward the upper data page and one or more bits toward the lower data page.

[0040] In a non-limiting example, a device (e.g., computing system 100) may include a memory subsystem power component 113 (referred to as a "power component" for short). The memory subsystem power component 113 may reside on the memory subsystem 110. As used herein, the term "residing on" refers to something that is physically located on a particular component. For example, the memory subsystem power component 113 "residing on the memory subsystem 110" refers to a condition in which the hardware circuitry including the memory subsystem power component 113 is physically located on the memory subsystem 110. The term "residing on" may be used interchangeably with other terms ("deployed on" or "located on") as mentioned herein.

[0041] Figure 2 An example system 202 for power simulation and estimation according to some embodiments of the present disclosure is illustrated. The system 202 may include an automatic test equipment (ATE) component 220 and a power component 213 (e.g., Figure 1 In some examples, the power component 213 may be a system on a chip (SoC). Components such as the ATE component 220 described herein may include components to facilitate operations associated with the component (e.g., testing a memory system (e.g., Figure 1 ATE component 220 may include various circuit systems (part of the memory subsystem 110 in the memory subsystem). For example, ATE component 220 may include dedicated circuit systems in the form of ASICs, FPGAs, state machines and / or other logic circuits or software and / or firmware, which may allow ATE component 220 to test other components and / or parameters of the memory subsystem. As an example, ATE component 220 may be a simple computer-controlled digital multimeter, or a complex system containing dozens or more complex test instruments (real or simulated electronic test equipment) capable of automatically testing and diagnosing faults in complex electronic package components or performing on-wafer testing, including systems on chips and / or integrated circuits. Although similar to Figure 2 The associated examples can be used for power estimation, but it may be more difficult to estimate power using effective clock and voltage control that can change power values. In some examples, the model of the intermediate voltage may not even be available.

[0042] In addition, in some examples, the power component 213 may be an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc. The power component 213 includes a design unit 222 and a power management controller 224. The power management controller 224 may apply dynamic and adjustable parameters in order to control performance and power consumption. The design unit 222 includes a circuit system that may include one or more cores (e.g., "intellectual property (IP) core"). As used herein, a "core" or "IP core" generally refers to one or more data and / or logic blocks that form a constituent component of an application specific integrated circuit or a field programmable gate array. In some examples, the power management controller 224 may be a power management integrated circuit (or PMIC) for managing the power of the system 202. Although a PMIC may refer to a wide range of chips (or modules in a system on chip (SoC) device), most include several DC / DC converters. A DC / DC converter is an electronic circuit or electromechanical device that converts a direct current (DC) source from one voltage level to another voltage level. It is a type of power converter. PMICs are typically included in battery-powered devices (such as mobile phones and portable media players) to reduce the amount of space required.

[0043] ATE component 220 communicates with design unit 222 by MBIST (" memory built-in self test ") controller 212 and / or scan controller 214 (such as AC scan controller, DC scan controller and other types of scan controller). Although MBIST controller 212 is described herein, embodiments are not limited thereto. For example, MBIST is only an example self-test and any number of self-test circuits can be used. Scan controller 214 can refer to the circuit system and / or control logic that are used to control and manage scans (such as, AC scan, DC scan, etc.), as will be further described below. MBIST can refer to the industry standard method of testing embedded memory. MBIST is operated by performing read and write sequences to memory according to a test algorithm. There are many industry standard test algorithms. MBIST controller produces correct read and write sequences to all positions of memory (for example, such as random access memory (RAM)) to ensure that the unit operates correctly. When doing so, some additional test coverage is realized in the address and data path used by MBIST. Additionally, the design unit 222 may communicate with a power management controller 224 through a clock ("CLK") control component 228 and a voltage control component 229, and the voltage control component 229 communicates with a power supply 226. The voltage control component 229 may control the voltage of the power supply 226 according to instructions received from the power management controller 224. In some examples, the power management controller 224 may be a power management integrated circuit system (PMIC).

[0044] The clock control component 228 may include various circuit systems and / or logic inserted on the power component 213 for controlling the clock. The clock control component 228 may scale the clock timing according to instructions received from the power management controller 224. In addition, since AC (full speed) testing generally requires two or more clock pulses in a capture mode at a frequency equal to or substantially close to the functional clock frequency, it may be necessary to pass the system (e.g., Figure 110) provides full speed pulses associated with the ATE component 220 using input / output (I / O) pads of the memory subsystem 110 in the power management controller 224. However, these I / O pads may have limitations in the maximum frequency they can support. On the other hand, in some instances, the clock control component 228 may use an internal phase-locked loop (PLL) clock to generate clock pulses for testing, and / or use an internal delay-locked loop (DLL) clock in other instances to generate clock pulses for testing. Although the clock control component 228 is described as providing clock timing for the ATE component 220 and clock timing according to instructions received from the power management controller 224, the embodiments are not limited thereto. For example, the clock control component 228 may be used to scale the frequency according to instructions from the power management controller 224 to dynamically adjust the frequency for matching voltages (dynamic or adaptive voltage-frequency scaling), and a different clock control component (not illustrated) may be used only for the clock timing of the ATE component 220 and the ATE test itself. Furthermore, the clock control component 228 may be used to operate in a functional mode (as will be further described below), and some elements of the clock control component 228 or other such structures may be reused in conjunction with testing of the ATE component 220 .

[0045] In some examples, a PLL clock may refer to a circuit system and / or logic that generates an output signal whose phase is related to the phase of an input signal. Although there are several different types of PLL clock circuits, the simplest is an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, thereby adjusting the oscillator to keep the phase matching. Keeping the input and output phases in step also implies keeping the input and output frequencies the same. Therefore, in addition to synchronizing the signal, the phase-locked loop can also track the input frequency, or it can generate a frequency that is a multiple of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis.

[0046] In other examples, a delay locked loop (DLL) may be a digital circuit similar to a phase locked loop (PLL), the main difference being that there is no internal voltage controlled oscillator, which is replaced by a delay line. A DLL may be used to change the phase of a clock signal (a signal having a periodic waveform), and is typically used to enhance the clock rise to data output valid timing characteristics of an integrated circuit (e.g., a DRAM device). A DLL may also be used for clock recovery (CDR). From an external perspective, a DLL may be viewed as a negative delay gate wired in the clock path of a digital circuit. The main component of a DLL may be a delay chain consisting of many delay gates with outputs connected to inputs. The input of the chain (and therefore the DLL) is connected to the clock to be negatively delayed. A multiplexer may be connected to each stage of the delay chain and the selector of this multiplexer may be automatically updated by a control circuit to produce a negative delay effect. The output of the DLL may be the resulting negatively delayed clock signal.

[0047] Phase-locked loops can be widely used in radio, telecommunications, computers and other electronic applications. They can be used to demodulate signals, recover signals from noisy communication channels, generate stable frequencies that are several times the input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits (such as microprocessors). Since a single integrated circuit can now provide a complete phase-locked loop building block, the technology can be widely used in modern electronic devices, where the output frequency ranges from a few tenths of a hertz to several gigahertz. In addition, although a phase-locked loop (PLL) and a delay locked loop (DLL) are provided in these examples, the embodiments are not limited thereto. For example, any circuit capable of generating a clock or frequency change can be used.

[0048] In some embodiments, system 202 may be deployed on or otherwise included in a memory system (e.g., a storage device, a memory module, or a hybrid of a storage device and a memory module). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0049] In other embodiments, the system 202 may be deployed on or otherwise included in a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile computing device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such computing device including a memory and a processing device. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or tablet form factor. In general, a tablet form factor may include a display screen of between approximately 3 inches and 5.2 inches (measured diagonally), while a tablet form factor may include a display screen of between approximately 5.2 inches and 7 inches (measured diagonally). However, examples of a "mobile computing device" are not limited thereto, and in some embodiments, a "mobile computing device" may refer to an IoT device as well as other types of edge computing devices.

[0050] Such a computing device may include a host system coupled to a memory system (e.g., one or more storage devices, memory modules, or a hybrid of storage devices and memory modules). The host system may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system uses the storage devices, memory modules, or a hybrid of storage devices and memory modules, for example, to write data to and read data from the storage devices, memory modules, or a hybrid of storage devices and memory modules.

[0051] In these examples, the host system may include a processing unit, such as a central processing unit (CPU), configured to execute an operating system. In some embodiments, the processing unit may execute a complex instruction set computer architecture, such as x86 or other architecture suitable for use as a CPU for the host system.

[0052] The host system may be coupled to the memory system via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system and the memory system. When the memory system is coupled to the host system via a PCIe interface, the host system may further utilize an NVM Express (NVMe) interface to access the component. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory system and the host system. Typically, the host system may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0053] The memory system may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0054] Some examples of non-volatile memory devices include non-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0055] Although nonvolatile memory components such as three-dimensional cross-point arrays of nonvolatile memory cells and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0056] The memory system may also include additional circuitry or components. In some embodiments, the memory system may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from a memory system controller and decode the addresses to access (several) memory devices. In some embodiments, the memory device may include a local media controller that operates in conjunction with the memory system controller to perform operations on one or more memory cells of the memory device. For example, an external controller may manage the memory device externally (e.g., perform media management operations on the memory device). In some embodiments, the memory device is a managed memory device, which is a raw memory device combined with a local controller for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. Although the non-limiting examples herein are generally described in terms of applicability to memory subsystems and / or memory devices, the embodiments are not limited thereto, and aspects of the present disclosure may also be applied to systems on chip, computing subsystems, data collection and processing, storage, networking, communications, power, artificial intelligence, control, telemetry, sensing and monitoring, digital entertainment, and other types of systems / subsystems and / or devices. Thus, aspects of the present disclosure may be applied to these components to provide power simulation and estimation, as described herein.

[0057] Figure 3A B illustrates an example of a power simulation and estimation method according to some embodiments of the present disclosure. For ease of description, since the entire figure is larger than the figure that can be described on a single page, Figures 3A to 3B Each of is a part of the figure and letters A to E indicate connections to other corresponding figures. For example, Figure 3A The "A" in Figure 303-1 is connected to Figure 3B303-2, and so on. In addition, as will be further described below, square boxes (such as the square box labeled "Functional Verification" 331) illustrate inputs (such as code) or objects used in power estimation and simulation. Trapezoidal (or inverted trapezoidal) shapes (such as the trapezoidal-shaped "Simulation" 333) illustrate tools and / or processes used during the estimation and simulation steps. Circles (such as the circle "RTL-based Power Estimation" 339, such as RTL-based functional power estimation) illustrate results or reports generated using the previously mentioned inputs and tools.

[0058] Figure 3A The following description of A to B describes a process for determining a calibration factor 357. The calibration factor 357 may be applied to a gate-level functional power estimate 353 (e.g., a gate-level functional power estimate) to produce a more accurate gate-level functional power estimate 353 and thus a more accurate related functional power 359 (e.g., a final functional power estimate). Related functional power 359 refers to the power consumption of a digital logic circuit when performing a specific function or operation. Related functional power 359 represents the dynamic power consumed by the circuit when the circuit switches between logic states (e.g., from 0 to 1 or from 1 to 0) during a specific operation or functional mode. In addition, the calibration factor 357 may be applied to an RTL-based functional power estimate 339 to produce a more accurate RTL-based functional power estimate 339. Subsequent executions of the system may use the calibration factor 357 and the RTL-based functional power estimate 339 to be more accurate than using only the RTL-based functional power estimate 339. Likewise, using the calibration factor 357 together with the gate-level functional power estimate 353 may be more accurate than using only the gate-level functional power estimate 353.

[0059] Example of power simulation and estimation method diagram 303-1 may include inputs from functional verification 331 and a design abstraction called register transfer level (RTL) 332. Functional verification 331 may refer to the task of verifying that a logic design meets specifications. In other words, functional verification 331 attempts to answer the question "Does this proposed design achieve the expected results?" Functional verification may be part of what is called design verification, which considers non-functional aspects such as timing, placement, and power in addition to functional verification.

[0060] Functional verification 331 may include methods of logic simulation, simulation acceleration, emulation, formal verification, smart verification, and / or HDL-specific versions of lint and other heuristics. Simulation acceleration refers to applying dedicated hardware to a logic simulation problem. Emulation refers to building a version of a memory system using programmable logic. Formal verification may refer to mathematically proving that certain requirements (also formally expressed) are met, or that certain undesirable behaviors (such as deadlocks) cannot occur. Smart verification may use automation to adapt the test platform to changes in register transfer level code. HDL-specific versions of lint and other heuristics may be used to discover common problems. Functional verification 331 includes inputs (such as code) that can be used to guide function switching activity vectors during simulation 333, as described in the following document. These vectors may be in any format that can be read by a power estimation tool, such as a value change dump (VCD), a fast signal database (FSDB), and the like.

[0061] RTL 332 may refer to a design abstraction that models synchronous digital circuits based on digital signal (data) flows between hardware registers and logical operations performed on those signals. Power estimation based on RTL 332 may be a first method and may be run using both RTL 332 and active vectors. RTL 332 may also be used by synthesis and scanning 334 tools, as will be described below, where RTL 332 may be mapped into gates and inserted into scan chains. RTL 332 may be used in hardware description languages ​​(HDLs) such as Verilog and VHDL to create high-level representations of circuits, from which lower-level representations and final actual wiring may be derived. Design at the RTL level is a typical practice of modern digital design. Unlike software compiler design (where register transfer level (RTL) is an intermediate representation and is at the lowest level), the RTL level may be an input used by digital designers to operate. In addition, in synthesis, an intermediate language between the input RTL representation and the target netlist may be used (as will be described below). Unlike netlists, structures such as cells, functions, macros, and multi-bit registers are available.

[0062] As an example, synchronous circuits may include two types of standard cell elements: registers (sequential logic) and combinational logic. Registers (usually implemented as D flip-flops) synchronize the operation of the circuit with the edge of the clock signal and are some of the sequential elements (such as flip-flops, latches, register files, etc.) in the circuit that have memory properties. Combinatorial logic can perform all logical functions in the circuit and may include logic gates, buffers, shifters, isolation units, and many other elements. When designing digital integrated circuits using hardware description languages ​​(HDLs), the design can be done at a higher level of abstraction than the transistor level (logic series) or logic gate level. In HDL, designers can determine registers (which may correspond to variables in a computer programming language) and can describe combinational logic by using familiar structures in programming languages ​​(such as if-then-else and arithmetic operations). This level is called register transfer level (RTL). The term refers to the fact that RTL focuses on describing the signal flow between registers.

[0063] Outputs from functional verification 331 and RTL 332 may be used as inputs to simulation 333. Simulation (e.g., logic simulation) 333 may refer to the use of simulation software to predict the behavior of digital circuits and hardware description languages. Simulation 333 may be performed at different levels of physical abstraction (e.g., at transistor level, gate level, RTL 332, electronic system level (ESL), or behavioral level). Simulation 333 may be used as part of the verification process in designing hardware. Simulation has the advantage of providing a familiar look and feel to the user because it is constructed from the same language and symbols used in the design. By allowing the user to interact directly with the design, simulation 333 is a natural way for designers to get feedback on their designs. Simulation 333 may provide switching activities that are used as inputs to RTL power estimation 335. For use with gate-level functional power estimation, switching activities may be annotated, such as shown as switching activity annotation 341. The resulting annotated switching activities may be used as the basis for netlist power estimation 347. As an example, switching activity from simulation 333 is first annotated (or in other words, translated) from the RTL design structure to be usable with the gate-level (netlist) structure for use in netlist power estimation 347. Netlist power estimation 347 may ultimately be used to determine power estimation 353. Additionally, RTL power estimation 335 may be used to determine a final RTL-based functional power estimation 339.

[0064] The synthesis and scan 334 tool or process may include mapping the inputs of the RTL 332 to gates and inserting scan chains. The output of the synthesis and scan 334 may include a synthesis netlist 336. The synthesis netlist 336 is an object produced by the process of synthesis and scan 334 (where the process is represented by a trapezoidal shape). A netlist refers to a description of the connectivity of an electronic circuit. In its simplest form, a netlist contains a list of electronic components in a circuit and a list of nodes to which the electronic components are connected. A net is a collection of two or more interconnected components. The structure, complexity, and representation of a netlist may vary, but at least one purpose of a netlist is to convey connectivity information. A netlist may provide examples, nodes, and some properties of the components that may be involved. In some instances, if they express much more than this, they are typically considered to be hardware description languages ​​(such as Verilog or VHDL), or one of several languages ​​that are specifically designed for input to a simulator or hardware compiler (such as a SPICE simulation netlist). Although the synthesis netlist 336 includes gates and scans, the synthesis netlist 336 does not have all routing, wire, or clock buffer infrastructure.

[0065] Synthesized netlist 336 may provide information about the inputs and outputs of the circuit, thereby providing a description of the digital logic circuit that specifies the connections of the digital logic circuit and the logical functions of the components of the digital logic circuit. Synthesized netlist 336 may be an intermediate step in the process of designing a digital circuit, where a high-level description of the circuit is first transformed into a lower-level netlist that can be used to implement the design in hardware. Synthesized netlist 336 includes information about the inputs and outputs of the circuit, as well as the logical functions performed by each of its components, such as gates, flip-flops, and other digital logic elements. Synthesized netlist 336 may also include other details, such as annotations indicating timing constraints, power optimization, and area constraints.

[0066] The physical design 338 process involves mapping the logical elements and connections of the circuit to specific components and connections on a chip or board. During physical design 338, the synthesized netlist 336 is transformed into a final (e.g., physical) netlist representing the actual interconnections between the components of the digital circuit. This involves routing and routing (e.g., referred to as "P&R" or routing and routing) the components on the chip or board, taking into account factors such as physical size constraints, signal integrity, power consumption, design rules, reliability, and / or other factors. Although the synthesized netlist 336 does not typically assign specific coordinates to gates (because it uses abstract wires without exact lengths and / or traces), the P&R process places gates (i.e., assigns exact coordinates to assigned gates) and inserts clock trees (through buffered clock structures) and handles all physical wire connections (e.g., "routing"). After routing and routing, the physical netlist is then physical rather than abstract. Each of the corresponding cells has exact coordinates and is connected to the power grid by wires corresponding to exact widths, lengths, pathways, and traces, etc. The physical netlist is then used to generate manufacturing masks used in the manufacturing process of the chip or board. These masks define the exact location and shape of the components on the chip and the interconnections between them.

[0067] The synthesized netlist 336 may be used as an input to an automatic test pattern generator (ATPG) 337. ATPG 337 may generate vectors used by testers to test manufactured products. ATPG 337 may refer to an electronic design automation method or technique used to find input (or test) sequences that, when applied to a circuit, enable automatic test equipment to distinguish correct circuit behavior from faulty circuit behavior caused by a defect. Generated patterns (e.g., high or low power patterns) are used to test semiconductor devices after manufacturing, or to assist in determining the cause of a failure (e.g., failure analysis). The effectiveness of ATPG 337 may be measured by the number of modeled defects or fault models that can be detected, the number of generated patterns, and / or the test coverage that can reach a certain threshold (e.g., approximately 99%). These metrics generally indicate test quality (the more fault detections, the higher the test quality) and test application time (the more patterns, the longer the test application time). ATPG efficiency is another important consideration that is affected by the fault models considered, the type of circuit under test (full scan, synchronous sequential, or asynchronous sequential), the level of abstraction used to represent the circuit under test (gates, register transfers, switches), and the quality of test required.

[0068] The ATPG 337 tool may read the synthesized netlist 336 and generate scan patterns. As an example, this stage involving the ATPG 337 tool may be highly customizable. For example, patterns may be generated to create high or low power modes, number of modes per chain, number of chains per mode, modes based on clock criteria (e.g., clock value, clock speed, clock domain), number of power domains, modes based on power domains, or any combination thereof. The ATPG 337 may provide a series of scan patterns to be used by the simulation 343. The simulation 343 may also use inputs from the synthesized netlist 336 and the final netlist with parasitics 345. The results of the simulation 343 may be used as the basis for the netlist power estimate 349. The netlist power estimate 349 may be used to determine a scan-based power estimate 361, which is based on the power consumed by the device when scanned because the consumed power is based on the final netlist with parasitics 345 and the simulated switching activity. The physical design 338 may generate an output of a final netlist 345 with parasitic effects, which includes appropriate parasitic extraction corresponding to a specific netlist-level power estimate. The final netlist is a netlist based on the complete physical design 338 of the circuit, including all details of its components, connections, and timing characteristics in addition to the PLL and / or PHY and other components. In contrast to the synthetic netlist 336, which is a logical representation of the circuit, the final netlist is a physical representation of the circuit. After the physical design 338 of the circuit has been completed, the final netlist is generated by analysis and optimization tools that verify the correctness and performance of the design. These tools perform various checks on the netlist to ensure that it meets the design specifications, such as functional correctness, timing requirements, power consumption, and area constraints. The final netlist typically includes information about components used in the circuit (such as gates, flip-flops, input / output buffers, and other elements). It also includes information about the interconnections between components, such as wire routing and component positioning on a chip or board. The final netlist can serve as the basis for generating manufacturing masks used when manufacturing chips or boards. It represents the complete physical implementation of a circuit, and it is used to ensure that the final product meets the original design specifications in terms of performance, power consumption, and area requirements.

[0069] Parasitics in a circuit refer to any unexpected or unwanted elements or effects that are due to the physical properties of the circuit components or layout. For example, unexpected or unwanted elements may include parasitic capacitance in addition to other such elements including resistance, inductance, crosstalk, etc. Parasitics can have a significant impact on the performance of the circuit, causing signal quality degradation, increased power consumption, and even circuit failure. Therefore, it is critical that parasitics are included in the final netlist to ensure that the physical implementation of the circuit meets the design specifications. The final netlist is generated after performing several post-layout analysis steps, including extracting parasitic elements. Parasitic extraction refers to the process of analyzing the electrical behavior of a circuit to determine the effects of parasitic elements.

[0070] The final netlist 345 with parasitics can be used to analyze the actual die 351. That is, as used herein, parasitics such as parasitics 345 can refer to undesirable and / or non-ideal effects due to physical components and interconnections within a circuit. As is well known, parasitics can affect or determine the final capacitance, inductance and / or resistance and other inherent properties of a circuit such as a digital logic circuit. The structure created by the final netlist 345 with parasitics of the die 351 can be tested by performing a tester power measurement 355 using the ATPG 337 mode. First, the standby power can be measured. Next, the mode can be enabled and the power increase associated with the mode can be captured. The mode can target the entire intellectual property ("IP") core or a portion thereof; for example, a partition, a specific IP within an IP core, some power or clock domains, etc. Other IP cores can remain static and may not interfere with the measurement. The tester power measurement 355 can generate a scan-based power measurement 363.

[0071] At this point, a particularly accurate power value can be obtained. In order to provide a final functional power estimate, the scan-based power measurement 363 is used as a reference and is correlated with the scan-based power estimate 361. The correlation 365 between the scan-based power estimate 361 and the scan-based power measurement 363 provides a calibration factor 357 that can be used to fine-tune other power estimates. As an example, the calibration factor 357 is a ratio between the scan-based power measurement 363 (which is measured) and the scan-based power estimate 361 (which is estimated). This calibration factor 357 can be applied to the gate-level functional power estimate 353, thereby generating a correlated functional power 359. The calibration factor 357 can mitigate or reduce errors in the gate-level functional power estimate and subsequent gate-level functional power estimates. In addition, the calibration factor 357 can be applied to the RTL power estimate 335, thereby generating a more accurate RTL-based functional power estimate 339. Subsequent execution of the system can use the calibration factor 357 and the RTL-based functional power estimate 339 to be more accurate than using only the RTL-based functional power estimate 339. Likewise, using calibration factor 357 together with gate-level functional power estimate 353 may be more accurate than using gate-level functional power estimate 353 alone. Although described herein as individual calibration factors 357, in some embodiments, there may be multiple calibration factors. For example, there may be multiple calibration factors associated with respective portions or partitions of an IP core. For example, some IP or partitioned IP cores may have significantly higher operating frequencies and / or a higher percentage of LVT cells, or be more cell power dominant (vs. interconnect power), or have higher cell density, etc. In this example, higher accuracy may be achieved by applying different calibration factors to different portions or partitions. Thus, some IP or partitioned IP may have different (e.g., higher or lower) performance characteristics and therefore have different calibration factors associated therewith.

[0072] Figure 4 An example diagram 404 illustrates a power simulation and estimation method according to some embodiments of the present disclosure. Figure 3B 363) and estimated (e.g., Figure 3B Correlation can be performed for the entire IP or a portion of the IP (e.g., clock domain, power domain, hierarchical module, etc. (each of which can be mode-dependent)) when both scan-based power values ​​of the scan-based power estimate 361 in the . Correlation can be performed for different process inflection points (e.g., slow, typical, etc.). This feature can allow efficient process shift planning and implementation for yield as well as performance and power optimization. Calibration factors obtained from the correlation (e.g., Figure 3B The calibration factor 357 in ( ) can be applied to both RTL-based and gate-level-based estimates. Since the scan-based switching profile is brought close to the functional profile, the estimate corrected by the factor will represent the closest possible approximation to the true functional power. For example, due to adjustable control of ATPG parameters, patterns of higher or lower switching activity can be generated. In addition, current ATPG tools and scan controllers may allow a wide variety of patterns. However, in addition to this, different DFT patterns can also be used to create detailed profiles per IP asset.

[0073] like Figure 4 As described in Figure 3A331 in ) can be used as an input to a functional mode 475, which in turn is used as an input to an automatic test equipment (ATE) functional mode 493. Thus, the method herein is flexible and relatively computationally inexpensive, compared to previous methods in which planning and / or executing ATE functional modes is time consuming, computationally intensive, and / or may consume a significant amount of ATE time (and thus increase production costs). In addition, the functional mode of the ATE may include debugging and / or manual work to properly tune. As specific examples thereof, ATPG and built-in self-test (BIST) 473 may include scan shift 477, full speed scan 479, single domain scan 481, and / or memory BIST 483, respectively, which are part of a superset of ATPG and BIST 473. In one example in which there is no shift, the ATE stable core power 485 refers to the static (leakage) power. The scan shifter 477 may also be used to generate and / or adjust the intensity of switching activity in both flip-flops (FFs) and logic domains. Full-speed scan 479 may refer to power measurement under ATE peak core power mode 487. As an example, multi-capture AC scans may allow peak power measurements that are particularly close to functional scenarios. Single-domain scan 481 may refer to power measurement that occurs during ATE single-domain power mode 489. Single-domain scans may include scans that target only FFs and logics in a specific clock domain, power domain, or specific IP partition. Typically, FFs and logics are isolated from memory and mixed-signal IPs. It should be clear that embedded memory is usually not scanned, nor is it a memory affected by the scan. However, in some embodiments, for example, when using BIST 483 to measure power, additional modes may be deployed to determine the amount of power consumed by the controller of memory BIST 483 itself. Memory BIST 483 may refer to memory power measurement that occurs during MBIST power mode 491. Similar techniques applied to MBIST may help to make the power of other arrays (such as register files, latch arrays, CAMs, etc.) relevant. In at least some cases, once associated with a particular technology node and a particular IP, the factors can be applied to all subsequent projects completed at the same node and IP version with increased accuracy.

[0074] Figure 5 An example method 506 for power simulation and estimation according to some embodiments of the present disclosure is described. The method 506 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 506 is performed by Figure 1 One or more components of computing system 100 and / or Figure 2The processes of the system 202 may be performed by one or more components of the system 202. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood to be merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] At operation 562, a functional power consumption value associated with the memory system may be estimated based on operations including 564, 566, 568, and 570 described further below. For example, the functional power consumption value may be determined based on the results of each of the operations at 564, 566, 568, and 570 as described below.

[0076] At operation 564, a scan-based power estimate may be determined. The scan-based power estimate may be determined using input from a simulation.

[0077] At operation 566, a scan-based power measurement may be determined. The scan-based power measurement may be determined using measurements from a tester testing silicon of a test die. The silicon of the die may be generated based on a final netlist, as described herein. The final netlist may be created based on a synthesized netlist, as described herein.

[0078] At operation 568, a calibration factor may be determined. The calibration factor may be based on a difference between an estimate of power and an actual measurement of power that indicates or demonstrates power using the same parameters. In this manner, the calibration factor may adjust the function power estimate to be closer to the measured actual value without requiring measurement of the function actual power value. At operation 570, the function power consumption value may be estimated by determining the relevant function power using the calibration factor. The relevant function power may be a more accurate estimate than an estimate determined without using the calibration factor.

[0079] In some examples, the functional power consumption value may include determining the function switching activity vector using register transfer level (RTL) data and functional verification data or a netlist and functional verification data. In an embodiment using a netlist and functional verification data, the netlist may be a synthesized netlist or a final netlist. For example, the function switching activity vector may be determined using register transfer level (RTL) data and functional verification data. Using RTL data may include estimating the power consumption value by using a synthesis operation to map the RTL data into a gate and inserting a scan chain. In some examples, estimating power consumption includes measuring sample power. The sample power may be measured using a tester. The tester may use various test modes generated by an automatic test pattern generator (ATPG) or other pattern generators. For example, other pattern generators may include MBIST or other such pattern generator sources. In some examples, the measurement of sample power includes measuring standby power. In some examples, the measurement of sample power includes starting a mode after measuring the standby power. The mode may be one of an ATPG mode, an MBIST mode, and / or another type of dynamic mode. In some examples, the mode targets at least a portion of an intellectual property (IP) circuit.

[0080] Figure 6 is a block diagram of an example computer system 671 in which embodiments of the present disclosure may operate. For example, Figure 6 An example machine illustrating a computer system 671 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 671 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0081] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0082] The example computer system 671 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 618, which communicate with each other via a bus 603.

[0083] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 671 may further include a network interface device 608 for communicating over a network 611.

[0084] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functionality described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 671, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0085] In one embodiment, the instructions 626 include instructions for implementing the instructions corresponding to the power component 613 ( Figure 1113) of the power component 113). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more methodologies of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0086] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0087] It should be remembered, however, that all of these and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0088] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including a solid state drive (SSD), a hard disk drive (HDD), a floppy disk, an optical disk, a CD-ROM and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to build more specialized equipment to perform the methods. The structures of a variety of these systems will appear as described in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0090] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0091] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for power simulation and estimation, comprising: A functional power consumption value associated with a memory system (110) is estimated by determining: Scan-based power estimation (361); Scan-based power measurements (363); a calibration factor (357) from correlating the scan-based power estimate with the scan-based power measurement (365); and The correlation function power (359) is then used using the calibration factor.

2. The method of claim 1 , further comprising estimating the function power consumption value by determining a function switching activity vector using: Register transfer level (RTL) (332) data and functional verification (331, 471) data, wherein using the RTL data includes estimating the functional power consumption value by using synthesis operations (334) to map the RTL data to gates and insert scan chains; or Netlist and the functional verification data.

3. The method of any of claims 1 to 2, wherein the scan-based power estimate is determined using a scan mode simulation (343), the scan mode simulation being customizable.

4. The method of claim 3, wherein the scan mode simulation is customizable as one of: High power mode; Low power mode; the number of patterns per chain; The number of chains; the number of such chains per mode; or Any combination thereof.

5. The method of claim 3, wherein the scan mode simulation is customizable with respect to one of: Clock value; Clock speed; Clock domain; The number of power domains; or Any combination thereof.

6. The method of any of claims 1-2, wherein determining the scan-based power measurement comprises measuring a sample power, wherein the measured sample power comprises measuring a standby power.

7. The method according to claim 6, wherein: The measured sample power includes a start-up mode after measuring the standby power; and The pattern targets at least a portion of the intellectual property (IP) circuitry.

8. A method for power simulation and estimation, comprising: A functional power consumption value associated with a memory system (110) is estimated by: determining a scan-based power measurement (363) using a tester (220) to apply an automatic test pattern generator (ATPG) (337) pattern to a silicon die (351); determining a scan-based power estimate (361) using the simulated (343) vector; correlating the scan-based power measurement with the scan-based power estimate (365) to produce a calibration factor (357); and The calibration factors are used to determine a final functional power estimate (359).

9. The method of claim 8, wherein the functional power consumption values ​​from the estimating include using the calibration factor by applying the calibration factor to a gate-level functional power consumption estimate (353) and an RTL-based power consumption estimate (339).

10. The method of claim 9, wherein the calibration factor mitigates errors in subsequent gate-level function power estimates.

11. The method of any one of claims 8 to 10, comprising adjusting the scan-based power measurement by adjusting a power parameter associated with an intellectual property (IP) component, wherein the power parameter is adjusted using at least one of: Scan shift (477) operation; Full-speed scan (479) operation; Single domain scan (481) operation; and Memory built-in self-test MBIST(483) operation.

12. The method of claim 11, wherein the single-domain scan operation isolates FFs and logic from memory and mixed-signal IP.

13. The method of claim 8, wherein the calibration factor modifies subsequent functional power estimates into the final functional power estimate.

14. A device (100, 202, 671) for power simulation and estimation, comprising: Memory (119, 130, 140, 604, 606); and A processing device (117, 602) coupled to the memory, the processing device being configured to: A functional power consumption value associated with a memory system (110) is estimated by determining: Function switching activity vectors using register transfer level RTL (332) data and function verification data (331, 471); gate-level functional power estimation (353), wherein the gate-level functional power estimation uses a plurality of functional vectors; scan-based power estimation (361), wherein the scan-based power estimation uses scan vectors from a scan-mode simulation (343), wherein the scan-mode simulation is generated using a final netlist; scan-based power measurement (363), wherein the scan-based power measurement uses the final netlist to determine a layout of a silicon die (351) and tests the silicon die to determine the scan-based power measurement; and A calibration factor (357) based on a comparison (365) of the scan-based power estimate to the scan-based power measurement, wherein the calibration factor is used with the gate-level functional power estimate to adjust the gate-level functional power estimate, the RTL-based functional power estimate (339), or both.

15. The apparatus of claim 14, wherein a power parameter associated with the estimate of the functional power consumption value is adjusted using: Scan shift (477) operation; Full-speed scan (479) operation; Single domain scan (481) operation; and Memory built-in self-test MBIST(483) operation.

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