Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, and the preparation method comprises the steps: providing a semiconductor substrate, and forming a gate trench on the upper surface of the semiconductor substrate, and a gate oxide layer and a polysilicon gate which are located in the gate trench; forming a body lightly doped region in the semiconductor substrate; forming a first groove in the body lightly doped region; the first groove is reused as a body contact hole; and forming a source region on the upper surface, where the first groove is not arranged, in the body lightly doped region, and forming a body lightly doped region on the side wall surface and the bottom surface of the first groove. By adopting the technical scheme, the performance of the semiconductor device can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the rapid development of semiconductor devices represented by MOSFET devices, semiconductor devices are now widely used. MOSFET devices include source, drain and body regions. The source and drain regions are of the same doping type, while the body region is of a different doping type from the source and drain regions. The source, drain and body regions constitute a parasitic BJT, where the body region is the base region of the parasitic BJT. When a semiconductor device is exposed to radiation, such as space radiation, a large current will be formed in the parasitic BJT, affecting the performance of the semiconductor device. Summary of the invention

[0003] The invention provides a semiconductor device and a preparation method thereof, so as to improve the performance of the semiconductor device.

[0004] According to one aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0005] Providing a semiconductor substrate, and forming a gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench on the upper surface of the semiconductor substrate;

[0006] forming a body lightly doped region in the semiconductor substrate;

[0007] A first groove is formed in the lightly doped body region; the first groove is reused as a body contact hole;

[0008] A source region is formed at an upper surface of the body lightly doped region where the first groove is not provided, and a heavily doped region is formed on a sidewall surface and a bottom surface of the first groove.

[0009] Optionally, the method further includes: forming metal silicide on the surface of the source region and the surface of the heavily doped region; and reusing the body contact hole as a source contact hole.

[0010] Optionally, after forming a body lightly doped region in the semiconductor substrate and before forming a first groove in the body lightly doped region, the method further includes:

[0011] A transition region is formed in the body lightly doped region; wherein the carrier concentration of the transition region is less than the carrier concentration of the body heavy doped region, and greater than the carrier concentration of the body lightly doped region;

[0012] Forming a first groove in the lightly doped body region includes:

[0013] A first groove is formed in the transition region.

[0014] Optionally, a semiconductor substrate is provided, and a gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench are formed on the upper surface of the semiconductor substrate, comprising:

[0015] Providing the semiconductor substrate; wherein the semiconductor substrate comprises an N-type substrate or a P-type substrate;

[0016] Performing epitaxial growth on the upper surface of the semiconductor substrate to form an epitaxial layer;

[0017] A gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed on the upper surface of the epitaxial layer.

[0018] Optionally, forming a source region at an upper surface of the body lightly doped region where the first groove is not provided, and forming a heavily doped region on a sidewall surface and a bottom surface of the first groove, comprises:

[0019] forming a drain region on a side of the gate trench away from the body lightly doped region, forming a source region at an upper surface of the body lightly doped region where the first groove is not provided, and forming a heavily doped region on a sidewall surface and a bottom surface of the first groove;

[0020] Wherein, along the arrangement direction of the gate trench and the lightly doped body region, the width of the heavily doped body region is greater than or equal to the width of the drain region, and the width of the drain region is greater than the width of the source region.

[0021] According to another aspect of the present invention, there is provided a semiconductor device, which is manufactured by the above-mentioned method for manufacturing a semiconductor device;

[0022] The semiconductor device comprises:

[0023] Semiconductor substrate;

[0024] A gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench; the gate oxide layer wraps the polysilicon gate;

[0025] A body region is arranged adjacent to the gate trench in a horizontal direction; wherein the body region includes a heavily doped region and a lightly doped region; the heavily doped region and the source region are arranged above the lightly doped region; the source region is located between the heavily doped region and the gate trench; the heavily doped region includes a first groove; the first groove is reused as a body contact hole.

[0026] Optionally, along the horizontal direction, the width of the first groove is smaller than the width of the body-doped region; along the vertical direction, the maximum depth of the first groove is smaller than the maximum depth of the body-doped region.

[0027] Optionally, the semiconductor substrate includes an N-type substrate or a P-type substrate;

[0028] The semiconductor device further comprises an epitaxial layer located above the semiconductor substrate; the gate trench and the body region are both located on the upper surface of the epitaxial layer.

[0029] Optionally, the semiconductor device further comprises: a drift region located in the semiconductor substrate; the gate trench and the body region are both located in the drift region;

[0030] The drift region is also provided with a drain region and a shallow trench isolation; the drain region, the shallow trench isolation, the gate trench and the body region are arranged adjacent to each other in sequence along the horizontal direction; and a field plate grid is also arranged above the shallow trench isolation.

[0031] Optionally, the semiconductor substrate further includes an isolation layer, a buried layer, and a deep well region connected to the buried layer;

[0032] The isolation layer is located below the drift region; the buried layer is located below the isolation layer; the deep well region extends in a vertical direction and is connected to the buried layer; the deep well region is not connected to the drift region.

[0033] The technical solution of the present invention forms a first groove in the body lightly doped region before forming the source region and the body heavy doped region, and forms a body heavy doped region on the side wall surface and the bottom surface of the first groove. In this way, a deep hole contact window can be formed in the body heavy doped region. On the one hand, the contact area between the body heavy doped region and the body contact hole can be increased to reduce the contact resistance, which is beneficial to reducing the base resistance of the parasitic BJT and reducing the latching effect of the parasitic BJT. On the other hand, when a large number of carriers are generated in the body region due to radiation, a large number of carriers can be quickly transmitted to the body contact hole through the body heavy doped region, avoiding a large number of carriers from flowing out through the source region, causing the parasitic BJT to be turned on, generating an amplification effect, resulting in the generation of a large current in the parasitic BJT, damaging the semiconductor device, and affecting the service life.

[0034] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0037] Figure 2 It is a structural schematic diagram of a semiconductor device manufacturing process provided by an embodiment of the present invention;

[0038] Figure 3 It is a structural schematic diagram of a manufacturing process of another semiconductor device provided by an embodiment of the present invention;

[0039] Figure 4 It is a structural schematic diagram of a manufacturing process of another semiconductor device provided by an embodiment of the present invention;

[0040] Figure 5 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0041] Figure 6 It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Figure 1 It is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. This embodiment can be applied to preparing a planar laterally diffused metal oxide semiconductor (LDMOS) device, and can also be applied to preparing a vertical high-voltage device. Figure 2is a schematic diagram of a semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 1 and Figure 2 , the method comprising:

[0045] 1001. Provide a semiconductor substrate, and form a gate trench, a gate oxide layer and a polysilicon gate located in the gate trench on the upper surface of the semiconductor substrate.

[0046] For example, a gate trench 02 may be etched in the semiconductor substrate 01 first, and the depth of the gate trench 02 may be greater than or equal to 0.3 μm and less than or equal to 3 μm; then a gate oxide layer 11 may be formed on the inner wall of the gate trench 02, and the thickness of the gate oxide layer 11 may be 20-1000 nm; finally, polysilicon may be filled in the gate trench 02 to form a polysilicon gate 12. The gate oxide layer 11 wraps the polysilicon gate 12 and exposes the upper surface of the polysilicon gate 12; "upper" refers to the side direction of the semiconductor substrate 01 used to prepare the semiconductor device.

[0047] 1002. Form a body lightly doped region in a semiconductor substrate.

[0048] Specifically, ion implantation and diffusion are performed in a preset region on the upper surface of the semiconductor substrate 01 to form a body lightly doped region 21. The preset region is adjacent to the gate trench 02, so that the body lightly doped region 21 can be arranged adjacent to the gate trench 02 in a horizontal direction; the horizontal direction refers to a direction parallel to the plane where the semiconductor substrate 01 is located, which can also be called a horizontal direction; the vertical direction refers to a direction perpendicular to the plane where the semiconductor substrate 01 is located, which can also be called a longitudinal direction.

[0049] 1003. Form a first groove in the body lightly doped region; the first groove is reused as a body contact hole.

[0050] Illustratively, before forming the first groove GV, a whole layer of photoresist (not shown in the figure) can be formed on the upper surface of the semiconductor substrate 01, and a mask plate can be placed on the side of the photoresist away from the semiconductor substrate 01. After exposure and development, the photoresist is patterned to expose the area to be etched, and the first groove GV is etched using the photoresist as a mask. The first groove GV can be a partial structure of the body contact hole H-2.

[0051] 1004. Form a source region on the upper surface of the body lightly doped region where the first groove is not provided, and form a heavily doped region on the sidewall surface and the bottom surface of the first groove.

[0052] Among them, the source region 30 and the body-lightly doped region 22 are arranged in the horizontal direction and are both located above the body-lightly doped region 21, and the body-lightly doped region 22 and the body-lightly doped region 21 constitute the body region 20. The body-weight-doped region 22 is located on the bottom surface and the sidewall surface of the first groove GV, and the body-weight-doped region 22 is arranged between the first groove GV and the source region 30. In an optional embodiment, along the arrangement direction of the source region 30 and the body-weight-doped region 22, the width of the body-weight-doped region 22 is greater than the width of the source region 30. In another embodiment, along the vertical direction, the length of the body-weight-doped region 22 is greater than the length of the source region 30. Exemplarily, along the vertical direction, the maximum depth of the source region 30 is less than or equal to the maximum depth of the first groove GV. In this way, along the vertical direction, the length of the body-weight-doped region 22 can be greater than the length of the source region 30, that is, along the vertical direction, the maximum depth of the body-weight-doped region 22 is greater than the maximum depth of the source region 30.

[0053] In an embodiment of the present invention, a first groove is formed in the body lightly doped region before forming the source region and the body heavy doped region, and a body heavy doped region is formed on the side wall surface and the bottom surface of the first groove. In this way, a deep hole contact window can be formed in the body heavy doped region. On the one hand, the contact area between the body heavy doped region and the body contact hole can be increased to reduce the contact resistance, which is beneficial to reducing the base resistance of the parasitic BJT and reducing the latching effect of the parasitic BJT. On the other hand, when a large number of carriers are generated in the body region due to the influence of radiation, a large number of carriers can be quickly transmitted to the body contact hole through the body heavy doped region, thereby avoiding a large number of carriers from flowing out through the source region, causing the parasitic BJT to be turned on, generating an amplification effect, and causing a large current to be generated in the parasitic BJT, thereby damaging the semiconductor device and affecting the service life.

[0054] In an optional embodiment, continue to refer to Figure 2 After forming a body lightly doped region 21 in the semiconductor substrate 01 and before forming a first groove GV in the body lightly doped region 21, the method further includes: forming a transition region 23 in the body lightly doped region 21; wherein the carrier concentration of the transition region 23 is less than the carrier concentration of the heavy doped region 22 and greater than the carrier concentration of the body lightly doped region 21. Forming the first groove GV in the body lightly doped region 21 includes: forming the first groove GV in the transition region 23.

[0055] The doping type of the transition region 23 is the same as that of the body lightly doped region 21 and the body heavily doped region 22. In one embodiment, along the vertical direction, the maximum depth of the transition region 23 is less than the maximum depth of the body lightly doped region 21 and greater than the maximum depth of the body heavily doped region 22.

[0056] Specifically, by setting a transition region 23 between the source region 30 and the lightly doped region 21 of the body, and between the heavily doped region 22 and the lightly doped region 21 of the body, it is beneficial to increase the threshold voltage and avoid mis-conduction of the device; it is also beneficial to form ohmic contact and reduce contact resistance. When a large number of carriers are generated in the body region 20 due to radiation, a large number of carriers can be quickly extracted, thereby reducing the generation of large parasitic BJT currents.

[0057] In yet another optional embodiment, continue to refer to Figure 2 The preparation method further includes: forming a metal silicide 60 on the surface of the source region 30 and the surface of the heavily doped region 22; and reusing the body contact hole H-2 as the source contact hole H-3.

[0058] The surface of the source region 30 includes the upper surface of the source region 30, and the surface of the heavy-doped region 22 includes the upper surface of the heavy-doped region 22 (flush with the upper surface of the source region 30), the side surface of the heavy-doped region 22 facing the side wall of the first groove GV, and the upper surface of the heavy-doped region 22 located at the bottom of the first groove GV. The resistivity of the metal silicide 60 is less than the resistivity of the source region 30 and also less than the resistivity of the heavy-doped region 22. The metal silicide 60 can enable the source region 30 and the heavy-doped region 22 to form an ohmic contact with the metal electrode, thereby reducing the contact resistance.

[0059] Exemplarily, a whole metal layer can be deposited and then annealed so that the metal layer can react with silicon to form metal silicide 60, while non-silicon areas such as silicon oxide do not react with the metal layer. After the metal silicide 60 is formed in a partial area, other unreacted metal layers can be removed, for example, a metal cleaning agent can be used to clean the unreacted metal layer while retaining the metal silicide 60. The body contact hole H-2 is reused as the source contact hole H-3, and the source region 30 is located on the side of the body doped region 22 away from the source contact hole H-3. When the body region 20 is affected by radiation to generate a large number of carriers, a large number of carriers can be quickly conducted out through the body doped region 22, thereby reducing the generation of large parasitic BJT currents.

[0060] In an optional embodiment, while forming the metal silicide 60 on the surface of the source region 30 and the surface of the heavily doped region 22, the metal silicide 60 can also be formed on the surface of the polysilicon gate 12, and a gate contact hole H-1 can be provided above the metal silicide 60 on the surface of the polysilicon gate 12. The metal silicide 60 can reduce the contact resistance between the polysilicon gate 12 and the metal electrode.

[0061] In another optional embodiment, in order to avoid the metal layer from reacting with the area of ​​the semiconductor substrate 01 that does not need to be conductive to form a metal silicide 60 and cause misconduction, before forming the gate trench 02, a shallow trench isolation STI can be formed on the surface of the semiconductor substrate 01 that does not require etching and ion implantation. Alternatively, before forming the gate trench 02, a local oxidation can be performed on the surface of the semiconductor substrate 01 that does not require etching and ion implantation to form a local oxidation isolation (not shown in the figure).

[0062] It should be noted that Figure 2 The shallow trench isolation STI is only used to isolate semiconductor devices to avoid the formation of metal silicide 60 between different devices, which may cause misconductance. The shallow trench isolation STI is adjacent to the gate trench 02 is only a feasible implementation method. In other feasible implementation methods, the shallow trench isolation STI and the gate trench 02 may not be adjacent.

[0063] Optional, Figure 3 is a structural schematic diagram of another semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 3 , providing a semiconductor substrate 01, and forming a gate trench 02, a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02 on the upper surface of the semiconductor substrate 01, including: providing a semiconductor substrate 01, wherein the semiconductor substrate 01 includes an N-type substrate or a P-type substrate; performing epitaxy on the upper surface of the semiconductor substrate 01 to form an epitaxial layer 201; forming a gate trench 02, a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02 on the upper surface of the epitaxial layer 201.

[0064] For example, taking the prepared semiconductor device as an NMOS transistor as an example, refer to Figure 3 , an N-type substrate N-sub can be provided as a semiconductor substrate 01, wherein the N-type substrate N-sub is a low-resistance substrate; epitaxy is performed on the semiconductor substrate 01 to form an N-type epitaxial layer N-epi as the epitaxial layer 201, for example, the epitaxial layer 201 can be formed first, and then the epitaxial layer 201 is formed into an N-type epitaxial layer N-epi by ion implantation and diffusion, wherein the resistivity of the N-type epitaxial layer N-epi is higher than that of the N-type substrate N-sub; then, a gate trench 02, and a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02 are formed on the upper surface of the epitaxial layer 201; finally, ion implantation and diffusion are performed on the upper surface of the epitaxial layer 201 to form a body region 20 and a source region 30, and finally a vertical semiconductor device can be obtained.

[0065] The gate (not shown in the figure) of the vertical semiconductor device can be connected to the polysilicon gate 12 through the gate contact hole H-1, the source (not shown in the figure) can be connected to the source region 30 through the source contact hole H-3, and the drain 104 is arranged below the N-type substrate N-sub, and the drain 104 is in contact with the N-type substrate. When a positive voltage is applied between the drain 104 and the source, and the voltage between the gate and the source is greater than the threshold voltage, a vertical N-type channel can be formed in the N-type epitaxial layer N-epi and turned on, and the current flows from the N-type substrate N-sub to the source region 30.

[0066] Optional, Figure 4 is a structural schematic diagram of another semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 4 , forming a source region 30 at the upper surface of the body lightly doped region 21 where the first groove GV is not set, and forming a heavily doped region 22 at the sidewall surface and the bottom surface of the first groove GV, including: forming a drain region 40 on the side of the gate trench 02 away from the body lightly doped region 21, forming a source region 30 at the upper surface of the body lightly doped region 21 where the first groove GV is not set, and forming a heavily doped region 22 at the sidewall surface and the bottom surface of the first groove GV. Wherein, along the arrangement direction of the gate trench 02 and the body lightly doped region 21, the width of the heavily doped region 22 is greater than or equal to the width of the drain region 40, and the width of the drain region 40 is greater than the width of the source region 30.

[0067] For example, taking the prepared semiconductor device as an NMOS transistor as an example, refer to Figure 4 , the source region 30 and the drain region 40 of the semiconductor device can be formed on the upper surface of the semiconductor substrate 01 in the same process, and the source region 30 and the drain region 40 can both include an N-type heavily doped region N+, and finally a lateral semiconductor device can be obtained. The gate (not shown in the figure) of the lateral semiconductor device can be connected to the polysilicon gate 12 through the gate contact hole H-1, the source (not shown in the figure) can be connected to the source region 30 through the source contact hole H-3, and the drain (not shown in the figure) can be connected to the drain region 40 through the drain contact hole H-4. When a positive voltage is applied between the drain and the source, and the voltage between the gate and the source is greater than the threshold voltage, a lateral N-type channel can be formed in the semiconductor substrate 01 and turned on, and the current flows from the drain region 40 to the source region 30.

[0068] Based on the above embodiments, continue to refer to Figure 4, providing a semiconductor substrate 01, and forming a gate trench 02, a gate oxide layer 11 and a polysilicon gate 12 in the gate trench 02 on the upper surface of the semiconductor substrate 01, including: providing a semiconductor substrate 01, and performing ion implantation and diffusion on the upper surface of the semiconductor substrate 01 to form a drift region 03; etching the surface of the drift region 03 to form a first trench 105; filling the first trench 105 with an insulating material to form a shallow trench isolation STI; forming a gate trench 02 on one side of the shallow trench isolation STI, and exposing the sidewall of the shallow trench isolation STI; forming a gate oxide layer 11 on the inner wall of the gate trench 02; then forming a polysilicon gate 12 in the gate oxide layer 11, and forming a field plate gate 50 above the shallow trench isolation STI. When forming a body lightly doped region 21 in the semiconductor substrate 01, it is necessary to perform ion implantation on the side of the gate trench 02 away from the shallow trench isolation STI to form the body lightly doped region 21.

[0069] Exemplarily, when the prepared semiconductor device is an NMOS transistor, the drift region 03 may be an N-type drift region N-drift.

[0070] It should be noted that Figure 4 Different patterns filled in the shallow trench isolation STI and the gate oxide layer 11 only represent different structures. The shallow trench isolation STI and the gate oxide layer 11 can be made of the same material or different materials, which is not limited in the embodiment of the present invention.

[0071] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device. Figure 5 is a schematic diagram of a semiconductor device provided by an embodiment of the present invention, with reference to Figure 5 The semiconductor device includes: a semiconductor substrate 01; a gate trench 02, and a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02, wherein the gate oxide layer 11 wraps the polysilicon gate 12; a body region 20, which is arranged adjacent to the gate trench 02 in a horizontal direction; wherein the body region 20 includes a heavily doped region 22 and a lightly doped body region 21; a heavily doped region 22 and a source region 30 are arranged above the lightly doped body region 21; the source region 30 is located between the heavily doped region 22 and the gate trench 02; the heavily doped region 22 includes a first groove GV; the first groove GV is reused as a body contact hole H-2.

[0072] In the horizontal direction, the width of the first groove GV is smaller than the width of the heavily doped region 22; in the vertical direction, the maximum depth of the first groove GV is smaller than the maximum depth of the heavily doped region 22, and the heavily doped region 22 is located on the bottom surface and the sidewall surface of the first groove GV, that is, the heavily doped region 22 is provided between the first groove GV and the source region 30. The semiconductor device can be a vertical semiconductor device or a horizontal semiconductor device.

[0073] In an optional embodiment, along the arrangement direction of the source region 30 and the heavy doped region 22, the width of the heavy doped region 22 is greater than the width of the source region 30. In another embodiment, along the vertical direction, the length of the heavy doped region 22 is greater than the length of the source region 30. In another embodiment, metal silicide 60 is provided on the upper surface of the polysilicon gate 12 and the source region 30; the side wall surface and the bottom surface of the first groove GV of the heavy doped region 22 are also provided with metal silicide 60. In another optional embodiment, a transition region 23 is provided between the body lightly doped region 21 and the heavy doped region 22, and between the body lightly doped region 21 and the source region 30, and the carrier concentration of the transition region 23 is less than the carrier concentration of the heavy doped region 22, and greater than the carrier concentration of the body lightly doped region 21. Among them, the doping type of the transition region 23 is the same as the doping type of the body lightly doped region 21 and the heavy doped region 22.

[0074] In the semiconductor device provided by the embodiment of the present invention, the body-doped region includes a first groove, and the body-doped region is arranged at the side wall and the bottom of the first groove. In this way, a deep hole contact window can be formed in the body-doped region. On the one hand, the contact area between the body-doped region and the body contact hole can be increased to reduce the contact resistance, which is beneficial to reducing the base resistance of the parasitic BJT and reducing the latching effect of the parasitic BJT. On the other hand, when a large number of carriers are generated in the body region due to radiation, a large number of carriers can be quickly transmitted to the body contact hole through the body-doped region, avoiding a large number of carriers from flowing out through the source region, causing the parasitic BJT to be turned on, generating an amplification effect, resulting in the generation of a large current in the parasitic BJT, damaging the semiconductor device, and affecting the service life.

[0075] In an optional embodiment, continue to refer to Figure 5 The semiconductor substrate 01 includes an N-type substrate or a P-type substrate; the semiconductor device also includes an epitaxial layer 201 located above the semiconductor substrate 01 ; the gate trench 02 and the body region 20 are both located on the upper surface of the epitaxial layer 201 .

[0076] For example, taking the semiconductor device as an NMOS transistor as an example, continue to refer to Figure 5 , the semiconductor substrate 01 may be an N-type substrate N-sub, which is a low-resistance substrate; the epitaxial layer 201 may be an N-type epitaxial layer N-epi, which has a higher resistivity than the N-type substrate N-sub; the source region 30 includes an N-type heavily doped region N+; the body heavily doped region 22 includes a P-type heavily doped region P+; and the body lightly doped region 21 includes a P-type lightly doped region PB. The semiconductor device may be a vertical semiconductor device, and a vertical conductive channel may be formed between the source region 30 and the semiconductor substrate 01.

[0077] In yet another optional embodiment, Figure 6 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, referring to Figure 6 The semiconductor device further includes: a drift region 03 located in the semiconductor substrate 01, the gate trench 02 and the body region 20 are both located in the drift region 03; the drift region 03 is also provided with a drain region 40 and a shallow trench isolation STI; the drain region 40, the shallow trench isolation STI, the gate trench 02 and the body region 20 are arranged adjacent to each other in sequence along the horizontal direction; and a field plate gate 50 is also arranged above the shallow trench isolation STI.

[0078] For example, taking the semiconductor device as an NMOS transistor as an example, continue to refer to Figure 6 , the semiconductor substrate 01 may be P-sub; the drift region 03 may be an N-type drift region N-drift; the source region 30 and the drain region 40 may both include an N-type heavily doped region N+; the heavily doped region 22 may include a P-type heavily doped region P+; the lightly doped region 21 may include a P-type lightly doped region PB. The semiconductor device may be a lateral semiconductor device, and a lateral conductive channel may be formed between the source region 30 and the drain region 40.

[0079] Based on the above embodiment, the semiconductor substrate 01 also includes an isolation layer 04, a buried layer 05, and a deep well region 06 connected to the buried layer 05; the isolation layer 04 is located below the drift region 03; the buried layer 05 is located below the isolation layer 04; the deep well region 06 extends in a vertical direction and is connected to the buried layer 05; the deep well region 06 is not connected to the drift region 03.

[0080] For example, taking the semiconductor device as an NMOS transistor as an example, continue to refer to Figure 6 , the isolation layer 04 can be a P-type isolation layer Pbot, the buried layer 05 can be an N-type buried layer NBL, and the deep well region 06 can be an N-type deep well region DNW. The isolation layer 04 and the drift region 03 can form a reverse bias to prevent the semiconductor device from leaking to the semiconductor substrate 01; the buried layer 05 and the isolation layer 04 can form a reverse bias to prevent the semiconductor substrate 01 from leaking to the semiconductor device. Among them, the deep well region 06 can provide an electrical signal to the buried layer 05, so that the buried layer 05 and the isolation layer 04 are reverse biased, which is beneficial to reducing leakage; it is also beneficial to signal interference from the external environment and the signal stability of the semiconductor device.

[0081] In an optional embodiment, a first heavily doped region 701 is provided on the upper surface of the deep well region 06, and a first heavily doped contact hole H-701 may be provided above the first heavily doped region 701, which is conducive to providing electrical signals to the deep well region 06 and the buried layer 05. On this basis, a first well region 07 may be provided between the first heavily doped region 701 and the deep well region 06, and the deep well region 06 may be formed by multiple ion implantations, which is conducive to reducing the difficulty of implantation. When the deep well region 06 is an N-type deep well region DNW, the first well region 07 may be an N-type well region NW, and the first heavily doped region 701 may include an N-type heavily doped region N+.

[0082] In another optional embodiment, a second well region 08 and a second heavily doped region 801 located on the upper surface of the second well region 08 are further provided on the upper surface of the semiconductor substrate 01, and a second heavily doped contact hole H-801 may be further provided above the second heavily doped region 801 to provide an electrical signal to the semiconductor substrate 01, for example, to be grounded, which is beneficial to maintaining the stability of the semiconductor device. When the semiconductor substrate 01 is a P-type substrate P-sub, the second well region 08 may be a P-type well region PW, and the second heavily doped region 801 may include a P-type heavily doped region P+.

[0083] The semiconductor device provided in the embodiment of the present invention is manufactured by adopting the method for preparing the semiconductor device provided in any embodiment of the present invention, and has the functional modules and beneficial effects capable of executing the method for preparing the semiconductor device provided in the embodiment of the present invention. For the contents not fully described in the embodiment of the semiconductor device, refer to the description of the method for preparing the semiconductor device above, and will not be repeated here. Similarly, the method for preparing the semiconductor device provided in the embodiment of the present invention also has the corresponding technical features and beneficial effects of the semiconductor device. For the contents not fully described in the embodiment of the method for preparing the semiconductor device, refer to the description of the semiconductor device above, and will not be repeated here.

[0084] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, and forming a gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench on the upper surface of the semiconductor substrate; forming a body lightly doped region in the semiconductor substrate; forming a first groove in the body lightly doped region; The first groove is reused as a body contact hole; A source region is formed at an upper surface of the body lightly doped region where the first groove is not provided, and a heavily doped region is formed on a sidewall surface and a bottom surface of the first groove.

2. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: Metal silicide is formed on the surface of the source region and the surface of the heavily doped region; and the body contact hole is reused as a source contact hole.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: After forming a body lightly doped region in the semiconductor substrate and before forming a first groove in the body lightly doped region, the method further includes: A transition region is formed in the body lightly doped region; wherein the carrier concentration of the transition region is less than the carrier concentration of the body heavy doped region, and greater than the carrier concentration of the body lightly doped region; Forming a first groove in the lightly doped body region includes: A first groove is formed in the transition region.

4. The method for preparing a semiconductor device according to claim 1, wherein: A semiconductor substrate is provided, and a gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed on the upper surface of the semiconductor substrate, including: Providing the semiconductor substrate; wherein the semiconductor substrate comprises an N-type substrate or a P-type substrate; Performing epitaxial growth on the upper surface of the semiconductor substrate to form an epitaxial layer; A gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed on the upper surface of the epitaxial layer.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: Forming a source region at an upper surface of the body lightly doped region where the first groove is not provided, and forming a heavily doped region on a sidewall surface and a bottom surface of the first groove, comprising: forming a drain region on a side of the gate trench away from the body lightly doped region, forming a source region at an upper surface of the body lightly doped region where the first groove is not provided, and forming a heavily doped region on a sidewall surface and a bottom surface of the first groove; Wherein, along the arrangement direction of the gate trench and the lightly doped body region, the width of the heavily doped body region is greater than or equal to the width of the drain region, and the width of the drain region is greater than the width of the source region.

6. A semiconductor device, characterized in that: Prepared by the method for preparing a semiconductor device according to any one of claims 1 to 5; The semiconductor device comprises: Semiconductor substrate; A gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench; the gate oxide layer wraps the polysilicon gate; A body region is arranged adjacent to the gate trench in a horizontal direction; wherein the body region includes a heavily doped region and a lightly doped region; the heavily doped region and the source region are arranged above the lightly doped region; the source region is located between the heavily doped region and the gate trench; the heavily doped region includes a first groove; the first groove is reused as a body contact hole.

7. The semiconductor device according to claim 6, characterized in that Along the horizontal direction, the width of the first groove is smaller than the width of the body-doped region; along the vertical direction, the maximum depth of the first groove is smaller than the maximum depth of the body-doped region.

8. The semiconductor device according to claim 6, characterized in that The semiconductor substrate includes an N-type substrate or a P-type substrate; The semiconductor device further comprises an epitaxial layer located above the semiconductor substrate; the gate trench and the body region are both located on the upper surface of the epitaxial layer.

9. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises: a drift region located in the semiconductor substrate; the gate trench and the body region are both located in the drift region; The drift region is also provided with a drain region and a shallow trench isolation; the drain region, the shallow trench isolation, the gate trench and the body region are arranged adjacent to each other in sequence along the horizontal direction; and a field plate grid is also arranged above the shallow trench isolation.

10. The semiconductor device according to claim 9, characterized in that The semiconductor substrate further comprises an isolation layer, a buried layer, and a deep well region connected to the buried layer; The isolation layer is located below the drift region; the buried layer is located below the isolation layer; the deep well region extends in a vertical direction and is connected to the buried layer; the deep well region is not connected to the drift region.

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