High-voltage superjunction VDMOS device terminal structure and manufacturing method thereof

Abstract

The present invention discloses a high-voltage superjunction VDMOS device terminal structure and its manufacturing method, comprising: growing an epitaxial layer on a heavily doped conductive substrate; forming a transition oxide layer on top of the epitaxial layer; implanting a first doped region, a second doped region, and a third doped region into the top region of the epitaxial layer; etching multiple groups of terminal trenches in the epitaxial layer; forming a vertical field plate dielectric layer on the sidewalls of the terminal trenches; filling the terminal trenches to form a vertical resistive field plate; forming a horizontal resistive field plate on top of the epitaxial region; and forming a drain metal electrode, a source metal electrode, and a floating metal electrode. In the present invention, the terminal structure utilizes superjunction, field plate, and field stop ring technologies. The horizontal resistive field plate can provide a low potential to the vertical resistive field plate and the second doped region. The provision of a stop ring can effectively reduce the electric field spike at the bottom of the resistive field plate, significantly reducing the planar terminal area and achieving device miniaturization.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices, and in particular relates to a high-voltage super junction VDMOS device terminal structure and a manufacturing method thereof. Background Art

[0002] The superjunction technology concept improves the 2.5th power proportionality limit of the breakdown voltage and on-resistance of silicon-based MOS devices due to its RESURF two-dimensional electric field principle and charge balance principle, reduces the on-resistance of medium and high voltage devices, and significantly improves the power density of the devices. Due to its high breakdown and low conduction characteristics, it has quickly entered the high-power device market, and its current target range includes smartphones, chargers, automotive electronics, and commonly used household appliance drivers. In order to solve the problem of difficult manufacturing and low yield of PN-type superjunction devices, superjunction devices modulated by resistive field plates have been proposed. For superjunction VDMOS devices modulated by resistive field plates, the resistive field plate can deplete impurities in the drift region, thereby achieving a charge balance effect. The advantages of this method compared to PN-type superjunction devices are simple, low manufacturing cost, and good breakdown consistency.

[0003] The cells of a VDMOS high-voltage power semiconductor withstand high voltages. Internally, they consist of many cells connected in parallel. Typically, breakdown does not occur within the cell, but rather at the edges where the electric field is concentrated. To improve the edge curvature effect and withstand voltage characteristics, appropriate withstand voltage terminations are required at the cell edges. Common withstand voltage termination technologies include field plate technology, lateral variable doping, and junction termination extension. In superjunction devices, the drift region concentration is higher than that of conventional VDMOS devices. Conventional planar technology results in a breakdown voltage in the termination region that is significantly lower than that of the cell. Therefore, the need for termination technology is a pressing issue. By adapting the trench longitudinal resistive field plate technology to the cell structure of a resistive field plate superjunction vertical double diffused metal-oxide semiconductor (RFP SJ-VDMOS) device, the electric field optimization effect of the termination region is guided to the cell, achieving improved withstand voltage with a smaller termination area. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a high-voltage super junction VDMOS device terminal structure and a manufacturing method thereof.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A method for manufacturing a high-voltage super-junction VDMOS device terminal structure comprises the following steps:

[0007] S1. epitaxially growing an epitaxial layer on a heavily doped conductive substrate, wherein the conductivity type of the epitaxial layer is the same as that of the heavily doped conductive substrate;

[0008] S2. performing surface oxidation on the top of the epitaxial layer to form a transition oxide layer;

[0009] S3. Implanting a first doped region, a second doped region, and a third doped region into the top region of the epitaxial layer, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region;

[0010] S4, etching the epitaxial layer to form a plurality of terminal trenches penetrating the epitaxial layer and exposing the substrate, and removing the transition oxide layer;

[0011] S5, forming a vertical field plate dielectric layer on the sidewall of the terminal trench;

[0012] S6, filling the terminal trench to form a vertical resistance field plate;

[0013] S7, forming a horizontal resistive field plate on top of the epitaxial region;

[0014] S8. Form a drain metal electrode connected to the substrate, a source metal electrode connected to the first doped region, and a floating metal electrode connected to the third doped region.

[0015] Furthermore, the S3 step includes the following sub-steps:

[0016] S301, performing a first ion implantation in a region on the top of the epitaxial layer located inside the terminal through a photoresist pattern, and then diffusing the region under high-temperature annealing conditions to connect it with the main junction region of the device, thereby forming a first doped region, wherein the conductivity type of the first doped region is opposite to that of the epitaxial layer;

[0017] S302, performing a second ion implantation on a region on the top of the epitaxial layer and adjacent to the outer side of the first doped region through a photoresist pattern to form a second doped region, wherein the conductivity type of the second doped region is consistent with the conductivity type of the first doped region and the doping concentration thereof is lower than the doping concentration of the first doped region;

[0018] S303 , performing a third ion implantation on the top of the epitaxial layer and outside the terminal through the photoresist pattern to form a third doped region, wherein the conductivity type of the third doped region is consistent with the conductivity type of the epitaxial layer.

[0019] Furthermore, in the step S4, deep trench etching is performed through the photoresist pattern, and the terminal grooves are arranged at the same regular intervals in the lateral direction; the etching depth is the thickness of the epitaxial layer, or the etching depth exceeds the thickness of the epitaxial layer by 1μm to 2μm.

[0020] Furthermore, the step S5 includes the following sub-steps:

[0021] S501, growing a silicon dioxide film on the sidewall and bottom of the terminal trench by thermal oxidation;

[0022] S502 , etching the silicon dioxide film layer at the bottom of the terminal trench by dry etching, retaining the silicon dioxide film on the sidewall, and forming a vertical field plate dielectric layer.

[0023] Furthermore, the step S6 includes the following sub-steps:

[0024] S601, growing a first resistive field plate material by chemical epitaxy to fill the terminal trench, so that the first resistive field plate material is connected to the substrate;

[0025] S602 , etching away the first resistive field plate material and the transition oxide layer on the top of the epitaxial layer using a photolithography pattern, and retaining the first resistive field plate material in the terminal trench to form a vertical resistive field plate.

[0026] Furthermore, the step S7 includes the following sub-steps:

[0027] S701, depositing a thick oxide layer on top of the epitaxial layer to form a top oxide layer;

[0028] S702, etching to form a contact through-hole penetrating the top oxide layer above each vertical resistance field plate and above the second doped region between each two adjacent groups of vertical resistance field plates;

[0029] S703 , depositing a layer of second resistive field plate material on the top oxide layer, wherein the second resistive field plate material extends into each contact through hole and contacts the top of the epitaxial layer to form a horizontal resistive field plate.

[0030] Furthermore, the step S8 includes the following sub-steps:

[0031] S801, etching and removing the top oxide layer and the horizontal resistive field plate on the inner side above the epitaxial layer to expose a portion of the first doped region; etching and removing the top oxide layer and the horizontal resistive field plate on the outer side above the epitaxial layer to expose a portion of the third doped region;

[0032] S802, forming a source metal electrode connected to the first doped region on the inner side of the epitaxial layer, and forming a floating metal electrode connected to the third doped region on the outer side of the epitaxial layer;

[0033] S803 , thinning the back side of the substrate, and forming a drain metal electrode on the back side of the substrate by metal evaporation.

[0034] Furthermore, the first doped region is implanted with boron ions at a concentration of 3e15cm -2 The second doped region is implanted with boron ions at a concentration of 3e13cm-2 The third doping region is implanted with arsenic ions or phosphorus ions at a concentration of 5e15cm -2 .

[0035] Furthermore, the thickness of the vertical field plate dielectric layer is 0.2 μm, the thickness of the vertical resistive field plate is 0.8 μm, the width of the terminal groove is 1.2 μm; the spacing between the centers of adjacent terminal grooves is 4 μm; and / or

[0036] The resistivity of the heavily doped conductive substrate is 2.8Ω·cm; the first resistance field plate material and the second resistance field plate material are both semi-insulating polysilicon materials, the resistivity of the vertical resistance field plate is le10Ω·cm; the resistivity of the horizontal resistance field plate is le7Ω·cm.

[0037] A high-voltage superjunction VDMOS device terminal structure includes a heavily doped conductive substrate and an epitaxial layer disposed on the heavily doped conductive substrate, wherein the lower end of the heavily doped conductive substrate is connected to a drain electrode; a top region of the epitaxial layer is implanted to form a first doped region, a second doped region, and a third doped region, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region; the implantation type of the first doped region and the second doped region is opposite to the conductivity type of the epitaxial layer; and the implantation type of the third doped region is the same as the conductivity type of the epitaxial layer.

[0038] A plurality of terminal grooves are formed on the epitaxial layer, and the terminal grooves penetrate the epitaxial layer; a vertical resistance field plate is respectively provided in each of the terminal grooves, and a vertical field plate dielectric layer is provided between the vertical resistance field plate and the inner wall of the terminal groove; a top oxide layer is provided on the epitaxial layer, and a contact through-hole is respectively provided on the top of the top oxide layer corresponding to each vertical resistance field plate and above the second doped region between each two adjacent groups of vertical resistance field plates, and a first notch is formed on the inner side of the top oxide layer, and the first notch exposes a part of the first doped region; a second notch is formed on the outer side of the top oxide layer, and the second notch exposes a part of the third doped region; a horizontal resistance field plate is provided on the top oxide layer, and the horizontal resistance field plate extends into each contact through-hole and contacts the top of the epitaxial layer, a source metal electrode is formed in the first notch, and a floating metal electrode is formed in the second notch.

[0039] In this invention, the terminal structure utilizes technologies such as superjunction, field plates, and field stop rings. A horizontal resistive field plate provides a low potential to the vertical resistive field plate and the second doped region, allowing the internal resistive field plate to modulate and deplete the doped region between them, thus avoiding electric field spikes similar to those observed with metal field plates. The provision of a stop ring effectively reduces the electric field spike at the bottom of the resistive field plate. Using the terminal structure of this embodiment, the terminal length is only approximately 50 μm at a breakdown voltage of 630 V, significantly reducing the planar terminal area and enabling device miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 This is a flow chart of an embodiment of a method for manufacturing a high-voltage super junction VDMOS device terminal structure according to the present invention.

[0042] Figure 2 Schematic diagram of the structure after the epitaxial layer is formed.

[0043] Figure 3 Schematic diagram of the structure after the transition oxide layer is formed.

[0044] Figure 4 Schematic diagram of the structure after forming three doping regions.

[0045] Figure 5 This is a schematic diagram of the structure after the terminal groove is opened.

[0046] Figure 6 Schematic diagram of the structure after forming the vertical field plate dielectric layer.

[0047] Figure 7 Schematic diagram of the structure after the vertical resistance field plate is formed.

[0048] Figure 8 Schematic diagram of the structure after forming a top oxide layer and opening contact holes.

[0049] Figure 9 This is a schematic diagram of the structure after a horizontal resistive field plate is formed and a first gap and a second gap are opened.

[0050] Figure 10 It is a schematic diagram of the structure after the source metal electrode and the floating metal electrode are formed.

[0051] Figure 11 Schematic diagram of the terminal potential distribution simulation results.

[0052] The accompanying drawings in this specification are numeraled as follows:

[0053] Heavily doped conductive substrate 100; epitaxial layer 200; first doped region 201; second doped region 202; third doped region 203; terminal trench 210; vertical field plate dielectric layer 220; vertical resistive field plate 230; transition oxide layer 300; top oxide layer 400; contact via 401; horizontal resistive field plate 500; first notch 501; second notch 502; source metal electrode 601; floating metal electrode 602. DETAILED DESCRIPTION

[0054] The following describes the implementation of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other unless there is any conflict.

[0055] See also Figure 1 The present invention discloses a method for manufacturing a high-voltage super-junction VDMOS device terminal structure. A preferred embodiment of the method for manufacturing a high-voltage super-junction VDMOS device terminal structure of the present invention includes the following steps:

[0056] S1. Please refer to Figure 2 An epitaxial layer 200 of a certain thickness is epitaxially grown on a heavily doped conductive substrate 100 to serve as a drift region. The resistivity of the epitaxial layer 200 is one of the determining factors for the device's breakdown voltage. A higher resistivity results in a lower breakdown voltage and a smaller specific on-resistance. The concentration of the epitaxial layer 200 is determined based on requirements. The conductivity type of the epitaxial layer 200 is the same as that of the heavily doped conductive substrate 100. In this embodiment, the heavily doped conductive substrate 100 is heavily N-type doped, with a resistivity of 2.8 Ω·cm. The epitaxial layer 200 is lightly N-type doped.

[0057] S2, please refer to Figure 3 , surface oxidation is performed on the top of the epitaxial layer 200 to form a transition oxide layer 300 to reduce damage caused by ion implantation.

[0058] S3, please refer to Figure 4 , implanting into the top region of the epitaxial layer 200 to form a first doped region 201, a second doped region 202, and a third doped region 203, wherein the first doped region 201 is located inside the terminal, the second doped region 202 is located outside the first doped region 201, and the third doped region 203 is located outside the terminal region. This step may include the following sub-steps:

[0059] S301, through the photoresist pattern, the first ion implantation is performed in the area on the top of the epitaxial layer 200 located inside the terminal. After the implantation, it is diffused under high temperature annealing conditions to connect with the main junction area of ​​the device, forming a first doped region 201; the conductivity type of the first doped region 201 is opposite to that of the epitaxial layer 200. In this embodiment, the first doped region 201 is implanted with boron ions at 80keV, 3e15cm -2 injection conditions.

[0060] S302, a second ion implantation is performed on the top of the epitaxial layer 200 and adjacent to the outer side of the first doped region 201 through the photoresist pattern to form a second doped region 202. The conductivity type of the second doped region 202 is consistent with the conductivity type of the first doped region 201, and its doping concentration is lower than the doping concentration of the first doped region 201. In this embodiment, the second doped region 202 is implanted with boron ions at an implantation concentration of 3e13cm -2 .

[0061] S303, a third ion implantation is performed on the top of the epitaxial layer 200 outside the terminal through the photoresist pattern to form a third doped region 203. The conductivity type of the third doped region 203 is consistent with the conductivity type of the epitaxial layer 200. The third doped region 203 serves as a heavily doped cutoff ring. In this embodiment, the third doped region 203 is implanted with arsenic ions or phosphorus ions at a concentration of 5e15cm -2 .

[0062] S4. Please refer to Figure 5 , multiple groups of terminal trenches 210 are etched on the epitaxial layer 200, penetrating the epitaxial layer 200 and exposing the substrate, and the transition oxide layer 300 is removed. In this step, deep trench etching is performed using a photoresist pattern, and the terminal trenches 210 are arranged at uniform intervals in the lateral direction; the etching depth can be the thickness of the epitaxial layer 200 or slightly greater than the thickness of the epitaxial layer 200. The depth, width, and number of the terminal trenches 210 can be determined based on the requirements of breakdown and operating voltage. In this embodiment, the etching depth exceeds the thickness of the epitaxial layer 200 by 1μm to 2μm, the width of the terminal trenches 210 is 1.2μm, and the number of terminal trenches 210 is 9 groups. The spacing between the centers of adjacent terminal trenches 210 is 4μm. Using the above method, high voltage resistance can be maintained while reducing the spacing between adjacent terminal trenches 210, thereby achieving device miniaturization.

[0063] S5, please refer to Figure 6 , forming a vertical field plate dielectric layer 220 on the sidewall of the terminal trench 210. This step may include the following sub-steps:

[0064] S501 , oxidizing the device by using a thermal oxidation method, and growing a layer of silicon dioxide film on the sidewall and bottom of the terminal trench 210 .

[0065] S502: Dry-etch the silicon dioxide film layer at the bottom of the terminal trench 210, leaving the silicon dioxide film on the sidewalls to form a vertical field plate dielectric layer 220. In this embodiment, the thickness of the vertical field plate dielectric layer 220 is 0.2 μm.

[0066] S6, please refer to Figure 7 , filling the terminal trench 210 to form a vertical resistive field plate 230. This step may include the following sub-steps:

[0067] S601: Use chemical epitaxy to grow a first resistive field plate material to fill the terminal trench 210, so that the first resistive field plate material is connected to the substrate. In this embodiment, the first resistive field plate material is made of semi-insulating polysilicon.

[0068] S602: Using photolithographic patterns, the semi-insulating polysilicon material (i.e., the first resistive field plate material) and the transition oxide layer 300 on top of the epitaxial layer 200 are etched away, leaving the semi-insulating polysilicon material in the terminal trench 210 to form the vertical resistive field plate 230. In this embodiment, since the width of the terminal trench 210 is 1.2 μm and the thickness of the vertical field plate dielectric layer 220 is 0.2 μm, the thickness of the vertical resistive field plate 230 is 0.8 μm. In this embodiment, the resistivity of the vertical resistive field plate 230 is 1e10 Ω·cm.

[0069] S7, forming a horizontal resistive field plate 500 on the top of the epitaxial region. This step may include the following sub-steps:

[0070] S701, please refer to Figure 8 , a thick oxide layer is deposited on top of the epitaxial layer 200 to form a top oxide layer 400 .

[0071] S702, please continue to read Figure 8 A contact through hole 401 penetrating the top oxide layer 400 is formed by etching above each vertical resistive field plate 230 and above the second doped region 202 between each two adjacent groups of vertical resistive field plates 230 .

[0072] S703, please refer to Figure 9 A layer of second resistive field plate material is deposited on the top oxide layer 400. The second resistive field plate material extends into each contact via 401 and contacts the top of the epitaxial layer 200, forming a horizontal resistive field plate 500. In this embodiment, the second resistive field plate material is semi-insulating polysilicon, and the resistivity of the horizontal resistive field plate 500 is 1 e7 Ω·cm.

[0073] S8, please refer to Figure 10 , forming a drain metal electrode connected to the substrate, a source metal electrode 601 connected to the first doped region 201, and a floating metal electrode 602 connected to the third doped region 203. This step may include the following sub-steps:

[0074] S801, etch and remove the innermost top oxide layer 400 and the horizontal resistance field plate 500 above the epitaxial layer 200 to form a first notch 501 exposing a portion of the first doped region 201; etch and remove the outermost top oxide layer 400 and the horizontal resistance field plate 500 above the epitaxial layer 200 to form a second notch 502 exposing a portion of the third doped region 203.

[0075] S802. Form a source metal electrode 601 connected to the first doped region 201 at the first notch 501 (i.e., the innermost side above the epitaxial layer 200). The lateral contact between the innermost source metal electrode 601 and the first doped region 201 does not extend beyond the outer side of the first doped region 201. Form a floating metal electrode 602 connected to the third doped region 203 at the second notch 502 (i.e., the outermost side above the epitaxial layer 200). The lateral contact between the outermost floating metal electrode 602 and the third doped region 203 does not extend beyond the inner side of the third doped region 203.

[0076] S803 , thinning the substrate by a backside thinning process, and forming a drain metal electrode on the backside of the substrate by metal evaporation.

[0077] This embodiment provides a usable terminal structure and preparation method for a super-junction VDMOS device of the resistive field plate type. The terminal structure uses technologies such as super-junction, field plate, and field stop ring. The principle is to make a hole on the field oxygen in the terminal area and cover it with a layer of resistivity slightly lower than that of the resistive field plate layer in the body (i.e., the horizontal resistive field plate 500) connected to the vertical resistive field plate 230 and the surface of the P- region (i.e., the second doped region 202) in the body to provide a low potential to both, so that the resistive field plate in the body can modulate and deplete the doped region in the middle. Because the connection is made through the resistive field plate in the lateral direction, no electric field spike similar to that of a metal field plate will appear in the terminal area. Adding a stop ring can form a leakage current path so that electrons will not continuously accumulate in the oxide layer at the bottom of the resistive field plate, effectively reducing the electric field spike at the bottom of the resistive field plate.

[0078] The effective gain of this embodiment is as follows: when the center-to-center distance between adjacent vertical resistive field plates 230 in the terminal region (i.e., the center-to-center distance between adjacent terminal trenches 210) is 4 μm, and the number of groups of vertical resistive field plates 230 (i.e., the number of groups of terminal trenches 210) increases from 4 to 9, the device breakdown voltage increases from 518 V to 630 V. Increasing the number of vertical resistive field plates 230 can reduce the peak electric field borne by each RFP (resistivity filtered plate) unit. Figure 11 As shown in FIG. 1 , the potential simulation result is obtained when the number of vertical resistance field plates 230 is 9. Figure 11 As can be seen, the resistive field plate region of the terminal is almost completely depleted, resulting in a breakdown voltage of 630V. The avalanche breakdown point occurs at the edge of the main junction, and the leakage current is concentrated through the main junction. The terminal length at a breakdown voltage of 630V is only about 50μm, which is 50% smaller than the area of ​​a traditional planar terminal. The resistive field plate pillars (i.e., vertical resistive field plates 230) of the superjunction device terminal of this embodiment can be manufactured together with the cell to save process costs, but the width and spacing can be designed separately according to the device's voltage requirements.

[0079] Please continue reading Figure 10 The present invention discloses a high-voltage superjunction VDMOS device termination structure. A preferred embodiment of the present invention comprises a heavily doped conductive substrate 100 and an epitaxial layer 200 disposed on the heavily doped conductive substrate 100. The lower end of the heavily doped conductive substrate 100 is connected to a drain electrode. In this embodiment, the heavily doped conductive substrate 100 is heavily N-type doped, with a resistivity of 2.8Ω·cm; the epitaxial layer 200 is lightly N-type doped.

[0080] The top region of the epitaxial layer 200 is implanted to form a first doped region 201, a second doped region 202, and a third doped region 203. The first doped region 201 is located inside the terminal, the second doped region 202 is located outside the first doped region 201, and the third doped region 203 is located outside the terminal region. The implantation type of the first doped region 201 and the second doped region 202 is opposite to the conductivity type of the epitaxial layer 200; the implantation type of the third doped region 203 is the same as the conductivity type of the epitaxial layer 200. In this embodiment, the first doped region 201 is implanted with boron ions at 80keV, 3e15cm -2 The second doping region 202 is implanted with boron ions at a concentration of 3e13cm -2 The third doped region 203 is implanted with arsenic ions or phosphorus ions at a concentration of 5e15 cm -2 .

[0081] Multiple groups of terminal trenches 210 are formed in the epitaxial layer 200. These trenches 210 penetrate the epitaxial layer 200. The etching depth can be equal to or slightly greater than the thickness of the epitaxial layer 200. In this embodiment, the etching depth exceeds the thickness of the epitaxial layer 200 by 1 μm to 2 μm. The width of the terminal trenches 210 is 1.2 μm. There are nine groups of terminal trenches 210. The spacing between the centers of adjacent terminal trenches 210 is 4 μm.

[0082] Each terminal trench 210 is provided with a vertical resistive field plate 230. A vertical field plate dielectric layer 220 is disposed between the vertical resistive field plate 230 and the inner wall of the terminal trench 210. In this embodiment, the vertical field plate dielectric layer 220 has a thickness of 0.2 μm. The vertical resistive field plates 230 are made of semi-insulating polycrystalline silicon and have a thickness of 0.8 μm. The resistivity of the vertical resistive field plates 230 is 1 e10 Ω·cm.

[0083] A top oxide layer 400 is disposed on the epitaxial layer 200. A contact via 401 is formed in the top oxide layer 400, extending through the top oxide layer 400, corresponding to each vertical resistive field plate 230 and above each second doped region 202 between two adjacent sets of vertical resistive field plates 230. A first notch 501 is formed inside the top oxide layer 400, exposing a portion of the first doped region 201. A second notch 502 is formed outside the top oxide layer 400, exposing a portion of the third doped region 203.

[0084] A horizontal resistive field plate 500 is disposed on the top oxide layer 400. The horizontal resistive field plate 500 extends into each contact via 401 and contacts the top of the epitaxial layer 200. The horizontal resistive field plate 500 is made of semi-insulating polysilicon and has a resistivity of 1 e7 Ω·cm. A source metal electrode 601 is formed in the first notch 501, and a floating metal electrode 602 is formed in the second notch 502.

[0085] In this embodiment, the terminal structure utilizes superjunction, field plate, and field stop ring technologies. The horizontal resistive field plate 500 provides a low potential to the vertical resistive field plate 230 and the second doped region 202, enabling the internal resistive field plate to modulate and deplete the doped region between them, thus avoiding electric field spikes similar to those observed with metal field plates. The provision of a stop ring effectively reduces electric field spikes at the bottom of the resistive field plate. With this embodiment's terminal structure, the terminal length is only approximately 50 μm at a breakdown voltage of 630 V, significantly reducing the planar terminal area and enabling device miniaturization.

[0086] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for manufacturing a high-voltage super-junction VDMOS device terminal structure, characterized in that: The following steps are involved: S1. epitaxially growing an epitaxial layer on a heavily doped conductive substrate, wherein the conductivity type of the epitaxial layer is the same as that of the heavily doped conductive substrate; S2. performing surface oxidation on the top of the epitaxial layer to form a transition oxide layer; S3. Implanting a first doped region, a second doped region, and a third doped region into the top region of the epitaxial layer, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region; The first doped region is implanted with boron ions at a concentration of 3e15cm -2 The second doped region is implanted with boron ions at a concentration of 3e13cm -2 The third doping region is implanted with arsenic ions or phosphorus ions at a concentration of 5e15cm -2 ; S4, etching the epitaxial layer to form a plurality of terminal trenches penetrating the epitaxial layer and exposing the substrate, and removing the transition oxide layer; S5, forming a vertical field plate dielectric layer on the sidewall of the terminal trench; S6. Filling the terminal trench with a first resistive field plate material to form a vertical resistive field plate; the first resistive field plate material is a semi-insulating polysilicon material; S7, forming a horizontal resistive field plate on the top of the epitaxial region using a second resistive field plate material; the second resistive field plate material is a semi-insulating polysilicon material; S8. Form a drain metal electrode connected to the substrate, a source metal electrode connected to the first doped region, and a floating metal electrode connected to the third doped region.

2. The method for manufacturing a high-voltage superjunction VDMOS device terminal structure according to claim 1, wherein: The S3 step includes the following sub-steps: S301, performing a first ion implantation in a region on the top of the epitaxial layer located inside the terminal through a photoresist pattern, and then diffusing the region under high-temperature annealing conditions to connect it with the main junction region of the device, thereby forming a first doped region, wherein the conductivity type of the first doped region is opposite to that of the epitaxial layer; S302, performing a second ion implantation on a region on the top of the epitaxial layer and adjacent to the outer side of the first doped region through a photoresist pattern to form a second doped region, wherein the conductivity type of the second doped region is consistent with the conductivity type of the first doped region and the doping concentration thereof is lower than the doping concentration of the first doped region; S303 , performing a third ion implantation on the top of the epitaxial layer and outside the terminal through the photoresist pattern to form a third doped region, wherein the conductivity type of the third doped region is consistent with the conductivity type of the epitaxial layer.

3. The method for manufacturing a high-voltage superjunction VDMOS device terminal structure according to claim 1, wherein: In the step S4, deep trench etching is performed through the photoresist pattern, and the terminal trenches are arranged at the same regular intervals in the lateral direction; the etching depth is the thickness of the epitaxial layer, or the etching depth exceeds the thickness of the epitaxial layer by 1μm to 2μm.

4. The method for manufacturing a high-voltage superjunction VDMOS device terminal structure according to claim 1, wherein: The S5 step includes the following sub-steps: S501, growing a silicon dioxide film on the sidewall and bottom of the terminal trench by thermal oxidation; S502 , etching the silicon dioxide film layer at the bottom of the terminal trench by dry etching, retaining the silicon dioxide film on the sidewall, and forming a vertical field plate dielectric layer.

5. The method for manufacturing a high-voltage super junction VDMOS device terminal structure according to claim 1, wherein: The S6 step includes the following sub-steps: S601, growing a first resistive field plate material by chemical epitaxy to fill the terminal trench, so that the first resistive field plate material is connected to the substrate; S602 , etching away the first resistive field plate material and the transition oxide layer on the top of the epitaxial layer using a photolithography pattern, and retaining the first resistive field plate material in the terminal trench to form a vertical resistive field plate.

6. The method for manufacturing a high-voltage super junction VDMOS device terminal structure according to claim 1, wherein: The S7 step includes the following sub-steps: S701, depositing a thick oxide layer on top of the epitaxial layer to form a top oxide layer; S702, etching to form a contact through-hole penetrating the top oxide layer above each vertical resistance field plate and above the second doped region between each two adjacent groups of vertical resistance field plates; S703 , depositing a layer of second resistive field plate material on the top oxide layer, wherein the second resistive field plate material extends into each contact through hole and contacts the top of the epitaxial layer to form a horizontal resistive field plate.

7. The method for manufacturing a high-voltage superjunction VDMOS device terminal structure according to claim 1, wherein: The S8 step includes the following sub-steps: S801, etching and removing the top oxide layer and the horizontal resistive field plate on the inner side above the epitaxial layer to expose a portion of the first doped region; etching and removing the top oxide layer and the horizontal resistive field plate on the outer side above the epitaxial layer to expose a portion of the third doped region; S802, forming a source metal electrode connected to the first doped region on the inner side of the epitaxial layer, and forming a floating metal electrode connected to the third doped region on the outer side of the epitaxial layer; S803 , thinning the back side of the substrate, and forming a drain metal electrode on the back side of the substrate by metal evaporation.

8. The method for manufacturing a high-voltage superjunction VDMOS device terminal structure according to any one of claims 1 to 7, wherein: The thickness of the vertical field plate dielectric layer is 0.2 μm, the thickness of the vertical resistive field plate is 0.8 μm, the width of the terminal trench is 1.2 μm; the spacing between the centers of adjacent terminal trenches is 4 μm; and / or The resistivity of the heavily doped conductive substrate is 2.8Ω·cm; the resistivity of the vertical resistive field plate is 1e10Ω·cm; and the resistivity of the horizontal resistive field plate is 1e7Ω·cm.

9. A high-voltage superjunction VDMOS device terminal structure, characterized in that: The invention comprises a heavily doped conductive substrate and an epitaxial layer arranged on the heavily doped conductive substrate, wherein the lower end of the heavily doped conductive substrate is connected to a drain electrode; the top region of the epitaxial layer is implanted to form a first doped region, a second doped region and a third doped region, wherein the first doped region is located inside the terminal, the second doped region is located outside the first doped region, and the third doped region is located outside the terminal region; the implantation type of the first doped region and the second doped region is opposite to the conductivity type of the epitaxial layer; the implantation type of the third doped region is the same as the conductivity type of the epitaxial layer; the first doped region is implanted with boron ions at an implantation concentration of 3e15cm -2 The second doped region is implanted with boron ions at a concentration of 3e13cm -2 The third doping region is implanted with arsenic ions or phosphorus ions at a concentration of 5e15cm -2 ; A plurality of terminal trenches are formed on the epitaxial layer, the terminal trenches penetrating the epitaxial layer; a vertical resistance field plate is respectively provided in each of the terminal trenches, the vertical resistance field plate being made of semi-insulating polysilicon material; a vertical field plate dielectric layer is provided between the vertical resistance field plate and the inner wall of the terminal trench; a top oxide layer is provided on the epitaxial layer, a contact through-hole is respectively provided on the top of each vertical resistance field plate and above the second doped region between each two adjacent groups of vertical resistance field plates, a first notch is formed on the inner side of the top oxide layer, the first notch exposing a portion of the first doped region; a second notch is formed on the outer side of the top oxide layer, the second notch exposing a portion of the third doped region; a horizontal resistance field plate is provided on the top oxide layer, the horizontal resistance field plate being made of semi-insulating polysilicon material; the horizontal resistance field plate extends into each contact through-hole and contacts the top of the epitaxial layer, a source metal electrode is formed in the first notch, and a floating metal electrode is formed in the second notch.

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