A method for manufacturing a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure, and is applied to the technical field of semiconductors. In the application, the part of the pad structure corresponding to the closed-loop line pattern, the grid pattern, the column array pattern and the surrounding pattern is removed, so that the defects of the pad structure derived from the continuous improvement of the storage unit density of the semiconductor structure are improved, and the collapse of the pad structure is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor memory structure. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, because it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current in the capacitor structure, it has gradually replaced DRAM cells with only planar gate structures under the current mainstream development trend. Generally, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from the bit line and word line. However, due to limitations in process technology, existing DRAM cells with recessed gate structures still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure, which improves the technical problem of partial pad structure collapse caused by the continuous increase in memory cell density in semiconductor structures by removing part of the columnar array pattern and part of the surrounding pattern on the first region used to form the corresponding pad structure and part of the closed loop line pattern on the second region.

[0004] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor structure, which may include at least:

[0005] A substrate is provided, the substrate comprising a first region and a second region;

[0006] The target layer is formed on the first and second regions of the substrate;

[0007] A hard mask layer is formed on the target layer;

[0008] A first pattern is formed on the first region of the hard mask layer, and the first pattern includes a plurality of columnar array patterns and a surrounding pattern around the columnar array patterns;

[0009] The second pattern is formed on the second region of the hard mask layer, and the second pattern includes a plurality of closed-loop line patterns;

[0010] A barrier layer is formed on the first pattern and the second pattern;

[0011] Using the barrier layer as a mask, the closed-loop line pattern of the second pattern is cut into a single line pattern;

[0012] Using the first pattern and the cut second pattern as masks, the first pattern and the second pattern are formed in the target layer.

[0013] In some optional examples, the ends of the plurality of closed-loop line patterns are connected.

[0014] In some optional examples, the second pattern further includes: a plurality of grid-like patterns, wherein one of the grid-like patterns is located in the gap of the closed region enclosed by the closed loop pattern.

[0015] In some optional examples, the step of forming the second pattern may include:

[0016] A first transition layer is formed on the hard mask layer;

[0017] The plurality of grid-like patterns are formed on the second region of the first transition layer;

[0018] The spacer walls are formed and wrapped around the sidewalls of the grid-like pattern;

[0019] A second transition layer is formed on top of the first transition layer in the second region, and the second transition layer wraps around the spacer wall;

[0020] Remove the spacer wall and form a closed loop pattern around the outside of the grid pattern and with gaps therebetween on the second transition layer in the second region;

[0021] Using the second transition layer as a mask, the grid pattern and the closed-loop line pattern are formed on the second region of the hard mask layer.

[0022] In some optional examples, the first transition layer located on the first region may also include a rectangular block pattern.

[0023] In some alternative examples, the spacer wall may also be formed on the sidewall of the rectangular block pattern.

[0024] In some optional examples, a third pattern is formed on the second region of the barrier layer, the third pattern including a plurality of grid-like opening patterns exposing the ends of the plurality of closed-loop line patterns.

[0025] In some optional examples, the third pattern may further include: a plurality of rectangular block opening patterns that expose the partial closed-loop line pattern and the partial grid-like pattern of the second pattern.

[0026] In some alternative examples, a fourth pattern is formed on the first region of the barrier layer, the fourth pattern comprising an irregular closed pattern that partially obscures the columnar array pattern and an annular frame pattern located outside of it and partially obscures the surrounding pattern.

[0027] In some optional examples, the width of the grid-like opening pattern may be greater than the sum of the widths of the ends of the plurality of closed-loop line patterns after they are connected.

[0028] In the semiconductor structure fabrication method provided by the present invention, on the one hand, by forming a closed-loop line pattern and a gate strip pattern located in the gaps within the second region of the substrate, a spacer wall is formed to fill the gaps and remove the pad structure corresponding to the spacer wall on the second region. A barrier layer with an opening pattern and a masking pattern is formed and used to remove the pad structure corresponding to part of the closed-loop line pattern and part of the gate strip pattern on the second region, so as to remove the portion of the pad structure with defects (e.g., the structural size does not meet the design requirements) on the second region. On the other hand, by forming a barrier layer with an opening pattern and a masking pattern on the first region of the substrate, the pad structure corresponding to part of the columnar array pattern and the surrounding pattern near the second region on the first region is removed, so as to remove the portion of the pad structure with defects on the first region. This also improves the pad structure defects caused by the continuous increase in the density of memory cells in the semiconductor structure and avoids the collapse of the pad structure. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0030] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0031] Figures 2 to 16 The semiconductor structure fabrication method provided in one embodiment of the present invention follows the process of fabrication. Figure 2 The top view obtained by the direction of the CC tangent.

[0032] Figures 17-24 This is a schematic diagram of the semiconductor structure fabrication method provided in one embodiment of the present invention during the fabrication process.

[0033] The attached figures are labeled as follows:

[0034] 100 - Substrate, 100A - First Region, 100B - Second Region, 110 - Target Layer, 111.1 - Columnar Array Pattern within the Target Layer, 111.2 - Annular Frame Pattern within the Target Layer, 112.1 - Single Line Pattern within the Target Layer, 120 - Hard Mask Layer, 121 - First Pattern, 121.1 - Columnar Array Pattern within the Hard Mask Layer, 121.2 - Enclosing Pattern within the Hard Mask Layer, 121.3 - First Strip Pattern, 121.4 - Second Strip Pattern, 122 - Second Pattern, 122.1 - 122.2 - Closed-loop pattern within the hard mask layer; 130 - First transition layer; 131 - Rectangular block pattern; 132 - Grid pattern within the first transition layer; 140 - Spacer wall; 150 - Second transition layer; 160 - Third transition layer; 170 - Barrier layer; 171 - Third pattern; 171.1 - Grid opening pattern; 171.2 - Rectangular block opening pattern; 172 - Fourth pattern; 172.1 - Irregular closed pattern; 172.2 - Annular frame pattern within the barrier layer.

[0035] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0036] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0037] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0038] In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0039] For ease of understanding, the following text defines a first direction D1, a second direction D2, a third direction D3, and a fourth direction D4. The first direction D1 is the direction parallel to the surface of the substrate 100; the second direction D2 is the direction perpendicular to the first direction D1 and located on the same horizontal plane; the third direction D3 is the direction located on the same horizontal plane as the first direction D1 and the second direction D2 and has an angle of inclination with both the first direction D1 and the second direction D2; and the fourth direction D4 is the direction perpendicular to the surface of the substrate 100.

[0040] Please refer to Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating the semiconductor structure provided in this embodiment. Figure 1 As shown, the method for fabricating the semiconductor structure provided in this embodiment includes at least the following steps:

[0041] Step S101: Provide a substrate, the substrate including a first region and a second region.

[0042] Step S102: Form the target layer located on the first and second regions of the substrate.

[0043] Step S103: A hard mask layer is formed on the target layer.

[0044] Step S104: A first pattern is formed on the first region of the hard mask layer. The first pattern includes a plurality of columnar array patterns and a surrounding pattern around the columnar array patterns.

[0045] Step S105: A second pattern is formed on the second region of the hard mask layer, the second pattern including a plurality of closed loop line patterns.

[0046] Step S106: A barrier layer is formed on the first pattern and the second pattern.

[0047] Step S107: Using the barrier layer as a mask, the closed-loop line pattern of the second pattern is cut into a single line pattern.

[0048] Step S108: Using the first pattern and the cut second pattern as masks, the first pattern and the second pattern are formed in the target layer.

[0049] In order to enable those skilled in the art to easily understand the semiconductor structure fabrication method in the embodiments of the present invention, the following will further explain the semiconductor structure fabrication method proposed in the present invention with reference to the various structural schematic diagrams and corresponding top views and partial enlarged views in the fabrication process.

[0050] Figures 2 to 16 The semiconductor structure fabrication method provided in one embodiment of the present invention follows the process of fabrication. Figure 2 The top view obtained by the direction of the CC tangent in the image; Figures 17-24 This is a schematic diagram of the semiconductor structure fabrication method provided in one embodiment of the present invention during the fabrication process.

[0051] Please refer to Figure 2 and Figure 17The process involves performing steps S101 to S104: providing a substrate 100 as the basis for setting the semiconductor structure in this embodiment of the invention, and dividing the substrate 100 into a first region 100A and a second region 100B surrounding it. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but not limited thereto. Next, using at least one deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., a target layer 110 and a hard mask layer 120 are sequentially stacked on the first region 100A and the second region 100B of the substrate 100. In one embodiment, the material of the hard mask layer 120 includes, for example, at least one of silicon nitride (SiN) or silicon oxynitride (SiON), and the material of the target layer 110 includes, for example, at least one conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), but not limited thereto. Next, a first pattern 121 is formed on the first region 100A of the hard mask layer 120. The first pattern 121 includes a plurality of columnar array patterns 121.1 and a surrounding pattern 121.2 surrounding the columnar array patterns 121.1. In one embodiment, the plurality of columnar array patterns 121.1 of the first pattern 121 are specifically used to form a plurality of storage nodepad (SNpad) structures as semiconductor devices (not shown, for example, dynamic random access memory devices), and are located in the middle region of the first region 100A and are separated from each other along a first direction D1 and a third direction D3, which are intersecting and not perpendicular to each other, and are arranged in multiple rows on the third direction D3. The surrounding pattern 121.2 is specifically used to form a pad boundary structure as a means of ensuring the contact range between the pad 111 and the corresponding plug (not shown), and is disposed outside the storage node pad structures corresponding to all the columnar array patterns 121.1, and extends on the second region 100B along the first direction D1 and the second direction D2. In detail, the first pattern 121 located on the first region 100A may further include a plurality of first strip patterns 121.3 and a plurality of second strip patterns 121.4 disposed between the plurality of columnar array patterns 121.1 and the surrounding pattern 121.2; in one embodiment, the plurality of first strip patterns 121.3 are separated from each other along the first direction D1 or the second direction D2, and the plurality of second strip patterns 121.4 are separated from each other along the second direction D2 and are in direct contact with the surrounding pattern 121.2 located in the first region 100A, so as to serve as branch patterns of the surrounding pattern 121.2 extending along the third direction D3. The first strip patterns 121.3 and the second strip patterns 121.4 are specifically used to form a surrounding pad structure to adjust the density of the pad structure.

[0052] It should be understood that, since the surrounding pattern 121.2 located on the first region 100A extends onto the second region 100B, therefore from Figure 2 The CC tangent in the middle corresponds to Figure 17 When viewed in cross-sectional view, the surrounding pattern 121.2 and the second strip pattern 121.4 are continuous structures, while the plurality of columnar array patterns 121.1 are independent structures arranged separately from each other.

[0053] Please refer to Figure 3 and Figure 18 and combined Figure 4 Following step S104 above: a first transition layer 130 is formed on the first region 100A and the second region 100B of the hard mask layer 120, and the first transition layer 130 has different patterns on the first region 100A and the second region 100B. In one embodiment, the portion of the first transition layer 130 located in the first region 100A has a rectangular block pattern 131, while the portion located in the second region 100B has a plurality of grid-like patterns 132; the rectangular block pattern 131 covers the first pattern 121 located on the hard mask layer 120 in the first region 100A, and the edge of the rectangular block pattern 131 is flush with the edge of the surrounding pattern 121.2 of the first pattern 121; the plurality of grid-like patterns 132 located in the first transition layer 130 are disposed outside the rectangular block pattern 131, spaced apart from each other along the first direction D1 and the second direction D2; the first transition layer 130 may be made of the same material as the hard mask layer 120, for example, silicon nitride (SiN) or silicon oxynitride (SiON), but is not limited thereto.

[0054] It should be understood that Figure 4 for Figure 3 A magnified view of the semiconductor structure at the location indicated by the dashed line on the middle ellipse, from... Figure 4 As shown, the shape of the grid-like pattern 132 located in the first transition layer 130 in the embodiment of the present invention can be a grid-like pattern extending along the second direction D2, and its width along the second direction D2 is greater than its width along the first direction D1, but is not limited thereto.

[0055] Please refer to Figure 5 and Figure 19 and combined Figure 6Following step S104 above: Spacer walls 140 are formed on the sidewalls of the rectangular block pattern 131 and the plurality of grating patterns 132 located within the first transition layer 130. In one embodiment, the spacer walls 140 enclose each sidewall of each grating pattern 132 and each rectangular block pattern 131 located within the first transition layer 130, thereby forming a... Figure 5 and its corresponding enlarged view Figure 6 The diagram shows a closed rectangular frame pattern surrounded by the four spacer walls 140. Furthermore, the materials of the spacer walls 140 and the first transition layer 130 have a high etch selectivity.

[0056] Please refer to Figure 7 and Figure 20 and combined Figure 8 Following step S104 above: a second transition layer 150 is formed to fill the gaps between the rectangular block pattern 131 formed in the first transition layer 130 of the second region 100B and the grid pattern 132 located in the first transition layer 130, as well as between the plurality of grid patterns 132 located in the first transition layer 130; in one embodiment, the material of the second transition layer 150 may also be the same as the material of the first transition layer 130, for example, silicon nitride (SiN) or silicon oxynitride (SiON), but is not limited thereto.

[0057] Please refer to Figure 9 and Figure 21 and combined Figure 10 Following step S104 above: performing a removal process, such as at least one of a dry etching process or a wet etching process, can remove the corresponding film layers of all the spacer walls 140 spaced apart within the first transition layer 130 and the second transition layer 150, forming as shown in the figure. Figure 9 and its corresponding enlarged view Figure 10 The gaps between the plurality of grid-like patterns 132 located within the second transition layer 150 and the first transition layer 130, as shown, form the second pattern in step S105 above. However, at this time, the second pattern is formed within the first transition layer 130 and the second transition layer 150. Specifically, the second pattern located within the first transition layer 130 and the second transition layer 150 may include a plurality of closed-loop line patterns (such as...) connected at the ends. Figure 9 or Figure 10 The second transition layer 150 outside the gap described herein and the grid pattern 132 located within the first transition layer 130 in the gap of the closed area enclosed by each of the closed loop patterns.

[0058] Please continue to refer to Figure 9 and Figure 10 and combined Figure 22 The above step S105 is performed: using the multiple closed-loop line patterns formed at the ends of the first transition layer 130 and the second transition layer 150 and the multiple grid strip patterns 132 located in the first transition layer 130 as masks, the multiple grid strip patterns 132 located in the first transition layer 130 and the closed-loop line patterns are transferred onto the second region 100B of the hard mask layer 120. At this time, for easy distinction, in this embodiment of the invention, the second pattern located on the second region 100B of the hard mask layer 120 is identified by the attachment mark 122, and the grid strip pattern in the second pattern 122 is identified by the reference numeral 122.1, and its closed-loop line pattern is identified by the reference numeral 122.2.

[0059] Please refer to Figure 11 and Figure 23 and combined Figure 12 Perform the above step S106: first, form a third transition layer 160 and a barrier layer 170 stacked in sequence, and use photolithography and etching processes to form a third pattern 171 on the second region 100B of the barrier layer 170 and a fourth pattern 172 on its first region 100A; it should be understood that if the third transition layer 160 is a transparent material, then the third pattern 171 and the fourth pattern 172 formed on the barrier layer 170 can be used to describe the specific positions of the third pattern 171 and the fourth pattern 172 by using their relationship with the first pattern 121 and the second pattern 122 in the hard mask layer 120 located below the third transition layer 160.

[0060] In one embodiment, the third pattern 171 includes a plurality of lattice-shaped opening patterns 171.1 that expose the ends of the plurality of closed loop line patterns 122.2; the fourth pattern 172 includes an irregular closed pattern 172.1 that partially obscures the columnar array pattern 121.1 and an annular frame pattern 172.2 located outside of it and partially obscuring the surrounding pattern 121.2 (the portion located in the first region 100A); specifically, the lattice-shaped opening pattern 171.1 of the third pattern 171 located in the second region 100B extends along the first direction D1 or the second direction D2, and its width is greater than the sum of the widths of the ends of the plurality of closed loop line patterns 122.2 connected along their respective directions, for example... Figure 11 A partial enlarged view of the semiconductor structure described in the figure. Figure 12As shown, two grid-like opening patterns 171.1 are positioned opposite each other along the second direction D2 and are respectively disposed at the two ends of the connected plurality of closed-loop line patterns 122.2. The width of each grid-like opening pattern 171.1 along the first direction D1 is greater than the sum of the widths of the ends of the connected plurality of closed-loop line patterns 122.2 along the first direction D1. This ensures that when step S107 is executed, the ends of all the connected plurality of closed-loop line patterns 122.2 can be removed, thereby cutting the closed-loop line pattern 122.2 of the second pattern 122 into a single line pattern. Figure 14 As shown; the irregular closed pattern 172.1 of the fourth pattern 172 can specifically be to only cover a portion of the plurality of columnar array patterns 121.1 located in the middle region on the first region 100A, and expose the remaining portion of the columnar array patterns 121.1 on the first region 100A, so that when etching downward along the fourth direction D4 using the blocking layer 170 as a mask, the plurality of columnar array patterns 121.1 not covered by the irregular closed pattern 172.1 of the fourth pattern 172 can be removed, thereby removing the pad structure corresponding to the portion of the columnar array patterns 121.1 on the first region 100A near the second region 100B.

[0061] In another embodiment, please refer to Figure 13 The third pattern 171 includes, in addition to a plurality of grid-like opening patterns 171.1 exposing the ends of the plurality of closed-loop line patterns 122.2, a plurality of rectangular block opening patterns 171.2 exposing portions of the closed-loop line patterns 122.2 and portions of the grid-like patterns 122.1 of the second pattern 122; in this configuration, a portion of the longer grid-like patterns 122.1 extending along the second direction D2 can be partially removed along the second direction D2 during subsequent etching processes to form Figure 15 The pattern shown is not limited to this one. In this embodiment, the fourth pattern 172 formed by the barrier layer 170 is the same as the pattern and position in the previous embodiment, and will not be repeated here.

[0062] Please refer to Figure 14 and Figure 15 and combined Figure 23 To perform step S107: an etching process can be performed downwards along the fourth direction D4, using the third pattern 171 and the fourth pattern 172 formed within the barrier layer 170 as a mask to transfer the pattern downwards. During this process, the closed-loop line pattern 122.2 of the second pattern 122 is cut into single-line patterns using the third pattern 171. Figure 14 As shown or Figure 15As shown, the portion of the columnar array pattern 121.1 on the first region 100A that is not covered by the fourth pattern 172 and the portion of the surrounding pattern 121.2 located outside it are removed.

[0063] Please refer to Figure 16 and Figure 24 Perform the above step S108: using the multiple columnar array patterns 121.1 of the remaining first pattern 121 in the hard mask layer 120 and the single line pattern of the cut second pattern 122 as masks, transfer the patterns of the first pattern 121 and the second pattern 122 to the target layer 110. At this time, for easy distinction, for example, the multiple columnar array patterns located on the first area 100A of the target layer 110 are identified by reference numeral 111.1, the annular frame pattern located on the first area 100A of the target layer 110 is identified by reference numeral 111.2, and the multiple single line patterns located on the second area 100B of the target layer 110 and arranged along the first direction D1 and the second direction D2 are identified by reference numeral 112.1.

[0064] In summary, in the semiconductor structure fabrication method provided by the present invention, on the one hand, by forming a closed-loop line pattern and a gate-like pattern located in the gaps within the second region of the substrate, a spacer wall is formed to fill the gaps and remove the pad structure corresponding to the spacer wall on the second region. A barrier layer with an opening pattern and a masking pattern is formed and used to remove the pad structure corresponding to part of the closed-loop line pattern and part of the gate-like pattern on the second region, thereby achieving the purpose of removing the portion of the pad structure with defects (e.g., structural dimensions not meeting design requirements) on the second region. On the other hand, by forming a barrier layer with an opening pattern and a masking pattern on the first region of the substrate, the pad structure corresponding to part of the columnar array pattern and the surrounding pattern near the second region on the first region is removed, thereby achieving the purpose of removing the portion of the pad structure with defects on the first region. This also achieves the purpose of improving the pad structure defects caused by the continuous increase in memory cell density in semiconductor structures and preventing the pad structure from collapsing.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; The target layer is formed on the first and second regions of the substrate; A hard mask layer is formed on the target layer; A first pattern is formed on the first region of the hard mask layer, and the first pattern includes a plurality of columnar array patterns and a surrounding pattern around the columnar array patterns; The second pattern is formed on the second region of the hard mask layer. The second pattern includes a plurality of closed loop line patterns and a plurality of grid strip patterns, and one of the grid strip patterns is located in the gap of the closed region enclosed by the closed loop line patterns. A barrier layer is formed on the first pattern and the second pattern; Using the barrier layer as a mask, the closed-loop line pattern of the second pattern is cut into a single line pattern; Using the first pattern and the cut second pattern as masks, the first pattern and the second pattern are formed in the target layer; The step of forming the second pattern includes: A first transition layer is formed on the hard mask layer; The plurality of grid-like patterns are formed on the second region of the first transition layer; The spacer walls are formed and wrapped around the sidewalls of the grid-like pattern; A second transition layer is formed on top of the first transition layer in the second region, and the second transition layer wraps around the spacer wall; Remove the spacer wall and form a closed loop pattern around the outside of the grid pattern and with gaps therebetween on the second transition layer in the second region; Using the second transition layer as a mask, the grid pattern and the closed-loop line pattern are formed on the second region of the hard mask layer.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The ends of the plurality of closed-loop line patterns are connected.

3. The method for preparing the semiconductor structure as described in claim 1, characterized in that, The first transition layer located on the first region also includes a rectangular block pattern.

4. The method for preparing a semiconductor structure as described in claim 3, characterized in that, The spacer walls are also formed on the sidewalls of the rectangular block pattern.

5. The method for preparing a semiconductor structure as described in claim 2, characterized in that, A third pattern is formed on the second region of the barrier layer, the third pattern including a plurality of grid-like opening patterns that expose the ends of the plurality of closed loop patterns.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The third pattern also includes: a rectangular block-shaped opening pattern that exposes a portion of the closed-loop line pattern and a portion of the grid-like pattern of the second pattern.

7. The method for preparing a semiconductor structure as described in claim 2, characterized in that, A fourth pattern is formed on the first region of the barrier layer, the fourth pattern including an irregular closed pattern that partially obscures the columnar array pattern and an annular frame pattern located outside of it and partially obscures the surrounding pattern.

8. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The width of the grid-like opening pattern is greater than the sum of the widths of the ends of the multiple closed-loop line patterns after they are connected.

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