Wire with molybdenum liner and tungsten filler for advanced integrated circuit structure fabrication

Abstract

The embodiment of the invention relates to the field of integrated circuit structure manufacturing. In an example, an integrated circuit structure includes a plurality of conductive lines, each conductive line of the plurality of conductive lines having a liner including molybdenum (Mo) and a filler including tungsten (W). The integrated circuit structure also includes an inter-layer dielectric (ILD) structure, portions of which are between adjacent conductive lines of the plurality of conductive lines.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of advanced integrated circuit structure fabrication, and more particularly, to conductive line schemes for integrated circuit structure fabrication and the resulting structures. Background Art

[0002] Over the past several decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables an increasing density of functional units to be implemented on the limited area of ​​a semiconductor chip. For example, shrinking the size of transistors allows a greater number of memory or logic devices to be incorporated onto a chip, thereby creating a product with increased capacity. However, the drive for ever-larger capacity is not without its problems. The necessity to optimize the performance of each device becomes greater and greater.

[0003] Changes in conventional and currently known manufacturing processes may limit the possibility of further extending them to the 15 nm node or sub-15 nm node range. Therefore, the fabrication of functional components required for future technology nodes may require the introduction of new technologies or integration of new technologies in current manufacturing processes, or the replacement of current manufacturing processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A cross-sectional view of a compositionally varied interconnect including a conductive line having a molybdenum liner and a tungsten fill is shown according to an embodiment of the present disclosure.

[0005] Figure 2A , 2B 3 illustrate oblique cross-sectional views representing various operations in a method of fabricating a metallization structure including differentiated conductive lines in accordance with an embodiment of the present disclosure.

[0006] Figures 4A-4E 5 illustrate cross-sectional views representing various operations in a dielectric plug manufacturing scheme in accordance with an embodiment of the present disclosure.

[0007] Figure 6 Schematic diagram of a pitch quartering scheme for manufacturing trenches of an interconnect structure according to an embodiment of the present disclosure.

[0008] Fig. 7A A cross-sectional view of a metallization layer fabricated using a pitch quartering scheme according to an embodiment of the present disclosure is shown.

[0009] Figure 7B A cross-sectional view of a metallization layer fabricated using a pitch-halving scheme over a metallization layer fabricated using a pitch-quartering scheme according to an embodiment of the present disclosure is shown.

[0010] Fig. 8AA cross-sectional view of an integrated circuit structure having a metallization layer of one metal line composition over metallization layers of different metal line compositions is shown in accordance with an embodiment of the present disclosure.

[0011] Figure 8B A cross-sectional view of an integrated circuit structure including a metallization layer having a metal line composition coupled to a metallization layer having a different metal line composition is shown according to an embodiment of the present disclosure.

[0012] Fig. 9 The embodiment of the present disclosure is shown in FIG. Fig. 8A and 8B A cross-sectional view of an individual interconnect line of the structure having a barrier liner and a conductive cap structure arrangement.

[0013] Fig.10 A cross-sectional view of an integrated circuit structure having four metallization layers of one metal line composition and pitch over two metallization layers of different metal line compositions and smaller pitches according to an embodiment of the present disclosure is shown.

[0014] Fig.11A A plan view and a corresponding cross-sectional view taken along an aa′ axis of a plan view of a metallization layer according to an embodiment of the present disclosure are shown.

[0015] Fig. 11B A cross-sectional view of a wire end or plug is shown in accordance with an embodiment of the present disclosure.

[0016] Fig. 11C Another cross-sectional view of a wire end or plug is shown in accordance with an embodiment of the present disclosure.

[0017] Figures 12A-12F Shown are plan views and corresponding cross-sectional views representing various operations in a plug finishing scheme in accordance with an embodiment of the present disclosure.

[0018] Fig.13A A cross-sectional view of a wire plug having a seam therein is shown according to an embodiment of the present disclosure.

[0019] Fig. 13B A cross-sectional view of a metallization layer stack including a wire plug at an underlying metal line location according to an embodiment of the present disclosure is shown.

[0020] Fig.14 A computing device according to one embodiment of the present disclosure is shown.

[0021] Fig.15 An interposer including one or more embodiments according to the present disclosure is shown.

[0022] Fig.16is an isometric view of a mobile computing platform according to an embodiment of the present disclosure, which mobile computing platform employs an IC manufactured according to one or more processes described herein or includes one or more features described herein.

[0023] Fig.17 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Conductor schemes and resulting structures for integrated circuit structure fabrication are described. In the following description, in order to provide a thorough understanding of the embodiments of the present disclosure, many specific details are set forth, such as specific integration and material systems. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts are not described in detail to avoid unnecessarily obscuring the embodiments of the present disclosure. In addition, it should be recognized that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

[0025] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "used as an example, instance, or illustration". Any embodiment described herein as exemplary is not necessarily to be understood as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory given in the aforementioned technical field, background technology, summary of the invention, or in the following detailed description.

[0026] This description includes references to "one embodiment" or "an embodiment." The appearances of the phrases "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0027] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure, including the appended claims:

[0028] "Comprising". This term is open ended. As used in the appended claims, this term does not exclude additional structures or operations.

[0029] "Configured to". Various units or components may be described or claimed as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply structure by indicating that the unit or component includes structure to perform one or more of those tasks during operation. Thus, a unit or component may be said to be configured to perform a task even when the specified unit or component is not currently in operation (e.g., not turned on or active). Reciting a unit or circuit or component as "configured to" perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, sixth paragraph, with respect to that unit or component.

[0030] As used herein, the terms "first," "second," and the like are used as labels for the nouns that follow them and do not imply any type of order (eg, spatial, temporal, logical, etc.).

[0031] “Coupled” - The following description refers to elements or nodes or features that are “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element or node or feature is directly or indirectly joined to (or directly or indirectly communicates with) another element or node or feature, and not necessarily mechanically coupled.

[0032] In addition, certain terms are used in the following description for reference purposes only, and therefore these terms are not intended to be limiting. For example, terms such as "upper," "lower," "above," or "below" refer to directions in the accompanying drawings for which reference is provided. Terms such as "front," "back," "rear," "side," "outer," and "inner" describe the orientation or position, or both, of certain portions of a component within a consistent but arbitrary frame of reference, which can be clearly understood by reference to the text describing the component in question and the associated drawings. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0033] “Inhibit” – As used herein, inhibit is used to describe reducing or minimizing an effect. When a component or structure is described as inhibiting an action, movement, or condition, it may completely prevent the result or consequence or future state. Additionally, “inhibit” may also refer to reducing or minimizing a consequence, manifestation, or effect that may occur. Thus, when a component, element, or feature is said to inhibit an outcome or state, it does not necessarily completely prevent or eliminate the outcome or state.

[0034] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically encompasses everything up to (but not including) metal interconnect layer deposition. After the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wiring).

[0035] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where the various devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring on the wafer, such as one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. During the BEOL portion of the fabrication phase, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in the BEOL.

[0036] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although exemplary processing schemes may be exemplified using the context of FEOL processing, such schemes may also be applicable to BEOL processing. Similarly, although exemplary processing schemes may be exemplified using the context of BEOL processing, such schemes may also be applicable to FEOL processing.

[0037] It should be recognized that FEOL is a technology driver for a given process. In other embodiments, FEOL considerations are driven by BEOL 10 nm or sub-10 nm processing requirements. For example, material selection and layout of FEOL layers and devices may need to accommodate BEOL processing. In one such embodiment, material selection and gate stack architecture are selected to accommodate high density metallization of BEOL layers, for example, to reduce fringe capacitance in transistor structures formed in FEOL layers but coupled together by high density metallization of BEOL layers.

[0038] The back-end of the line (BEOL) layer of an integrated circuit typically includes a conductive microelectronic structure, which is referred to in the prior art as a via, for electrically connecting a metal line or other interconnect above the via to a metal line or other interconnect below the via. The via can be formed by a photolithography process. Typically, a photoresist layer can be spun on top of the dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer can be developed to form an opening in the photoresist layer. Next, the opening in the photoresist layer can be used as an etching mask to etch an opening for the via in the dielectric layer. This opening is referred to as a via opening. Finally, the via opening can be filled with one or more metals or other conductive materials to form a via.

[0039] The size and spacing of vias have been gradually reduced, and it is expected that in the future, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.), the size and spacing of vias will continue to be gradually reduced. When very small vias are patterned with very small pitches by such photolithography processes, there are several challenges in themselves. One such challenge is the overlay between the via and the upper interconnect, and the overlay between the via and the lower contact (landing) interconnect, which usually needs to be controlled to a high tolerance on the order of one-quarter the via pitch. Because the via pitch has been shrinking over time, the overlay tolerance tends to scale with it at a greater rate than the photolithography equipment can keep up.

[0040] Another such challenge is that the critical dimensions of via openings generally tend to scale faster than the resolution capabilities of the lithography scanners. Shrinking techniques exist to shrink the critical dimensions of via openings. However, the amount of shrinkage is often limited by the minimum via pitch and the ability of the shrinking process to be sufficiently optical proximity correction (OPC) neutral without significantly affecting line width roughness (LWR) or critical dimension uniformity (CDU), or both. Yet another such challenge is that the LWR or CDU characteristics of the photoresist, or both, typically need to be reduced as the critical dimensions of the via openings are reduced in order to maintain the same overall fraction of the critical dimension budget.

[0041] The above factors are also relevant to consider the placement and scaling of non-conductive spaces or breaks between metal lines (referred to as "plugs," "dielectric plugs," or "metal line ends" in metal lines of back-end-of-line (BEOL) metal interconnect structures). Thus, improvements are needed in the art of back-end-of-line metallization manufacturing for fabricating metal lines, metal vias, and dielectric plugs.

[0042] One or more embodiments described herein relate to structures including high performance tungsten fill for integrated circuit features using molybdenum liner layers, such as BEOL structures.

[0043] To provide context, chemical vapor deposition (CVD) of tungsten is typically performed using thermal decomposition of the precursors WF6 and H2. WF6-based deposition has several fundamental limitations, including (1) selectivity relative to dielectrics (tungsten will not grow without a metal or metal nitride as a substrate), (2) high stress, which can lead to delamination of the metal film without sufficient thickness of the adhesion layer (the adhesion layer is typically titanium or titanium nitride, or Ti / W carbonitride), and (3) generation of HF as a byproduct (HF becomes an etchant for Si, a known defect mode in metal-semiconductor contacts).

[0044] According to embodiments of the present disclosure, molybdenum films are inherently better suited for growth on oxides because they address all three of the challenges described above. Molybdenum can be conformally grown in dielectric features (or mixed metal / dielectric features) using appropriate precursors or conformal physical vapor deposition. The adhesion of molybdenum to these substrates is very similar to that of the more resistive titanium nitride (TiN), providing healthy adhesion for tungsten deposited using Mo as a substrate. Mo can be deposited in the desired temperature range using non-fluoride precursors, eliminating interactions at the semiconductor interface. The Mo film can also be used as a fluorine barrier during subsequent tungsten deposition.

[0045] To provide further context, there are two approaches to filling tungsten features without a nitride (or similar liner). Both approaches have significant limitations. (1) The first approach involves selectively growing tungsten in the via feature, followed by deposition of an adhesion layer and a capping layer for downstream polishing. However, due to the difficulty in achieving the decomposition of WF6 to tungsten on oxidized metal surfaces, this technique requires destructive substrate processing and is limited to vias with low aspect ratios. This also requires the use of an adhesion layer for capping layer deposition to allow polishing after deposition. (2) The second approach involves physical vapor deposition using a "conformal" deposition technique, followed by conventional CVD processing using PVD as a substrate for nucleation and growth. However, physical vapor deposition cannot perform true conformal growth, so its application is limited to limited geometry features with low aspect ratios. Due to poor PVD spatial coverage, re-entrant features or deep features cannot be adequately filled. PVD has a poor fluorine barrier to contacts, which prevents its use in industry standard applications.

[0046] According to one or more embodiments of the present disclosure, a conformal molybdenum layer is deposited into the feature with a thickness of 2-5 nanometers depending on the application. Depending on the feature, thermal atomic layer deposition (ALD), plasma ALD, physical vapor deposition (PVD) or organic ALD may be suitable for this operation. Tungsten is then deposited using, for example, CVD using WF6 and H2 as precursors. In one embodiment, the Mo liner enables the growth of tungsten without delamination from the semiconductor substrate. In one embodiment, this operation is performed in situ to prevent the Mo film from reacting adversely with the atmosphere gas during air flow blocking (air break). In one embodiment, the Mo liner includes greater than 98 atomic percent Mo. In one embodiment, the W filler includes greater than 98 atomic percent W.

[0047] Advantages of implementing the embodiments described herein may include a CPU or server chip that is approximately 3% faster. Embodiments may be implemented to achieve this performance gain without the need for molybdenum slurry, which is not available. Embodiments may be implemented for ease of integration because the use of tungsten (filler metal) is expanded, which can reduce timeline risk due to unexpected interactions with other processes. This molybdenum nucleation scheme for tungsten fillers can provide resistive linerless fillers for high aspect ratio features, especially when encapsulated in dielectrics. This scheme can enable fast polishing development and drop-in integration for cleaning and etching. Performance gains can be achieved using the increased conductive volume in the features, with a 30-50% drop in feature resistance depending on the structure. Detectability of the embodiments described herein can be performed by elemental distribution of target features in cross-sectional TEM to indicate the molybdenum signal around the tungsten core.

[0048] Figure 1 A cross-sectional view of an interconnect line with compositional variations according to an embodiment of the present disclosure is shown, as shown in table 100, the interconnect line including a conductive line having a molybdenum liner and a tungsten filler.

[0049] refer to Figure 1 In the upper left corner, interconnect 110 includes tungsten carbonitride (WCN) liner 112 and tungsten (W) filler 114. Interconnect 110 has large grains to achieve cobalt resistance, low temperature manufacturing and good F barrier, and is compatible with trench contacts and copper. The relative characteristic resistance of interconnect 110 is about 0.8-1x.

[0050] refer to Figure 1 In the upper middle portion of FIG. 1 , the interconnection line 120 includes a metal substrate 122 having a tungsten (W) structure 124 selectively formed thereon. The relative characteristic resistance of the interconnection line 120 is about 0.5x.

[0051] refer to Figure 1In the upper right corner of FIG. 1 , interconnect 130 includes a physical vapor deposition tungsten (PVD W) liner 132 and a chemical vapor deposition tungsten (CVD W) filler 134. Since there is no nitride layer, interconnect 130 reduces the via Kelvin. The relative characteristic resistance of interconnect 110 is about 0.5x.

[0052] refer to Figure 1 In the lower left corner of FIG. 1 , according to an embodiment of the present disclosure, the interconnection line 140 includes a molybdenum (Mo) liner 142 and a tungsten (W) filler 144. The relative characteristic resistance of the interconnection line 140 is about 0.4-5x.

[0053] refer to Figure 1 In the lower middle portion, the interconnect line 150 is a molybdenum (Mo) structure 152 that may have a relative characteristic resistance of about 0.4x. However, the interconnect line 150 may be difficult and / or costly to manufacture.

[0054] refer to Figure 1 In the lower right corner of FIG. 1 , interconnect 160 includes a metal substrate 162 having a molybdenum (Mo) structure 164 selectively formed thereon. The relative characteristic resistance of interconnect 160 is about 0.3x. However, interconnect 160 may be difficult and / or costly to manufacture.

[0055] In another aspect, one or more embodiments described herein relate to structures, such as BEOL structures, including mixed metal layers.

[0056] To provide context, with each technology node, the demand for finer features, such as thinner metal lines and fine-pitch separated vias, has been there. A combination of optical systems and self-aligned schemes has been supporting the industry by providing the required lithography plus patterning schemes for the lines. Extreme ultraviolet (EUV) technology has recently enabled a large variation in printable via and pattern sizes. Even so, EUV printing may not be sufficient to meet the needs of scaling technology nodes. Deposition and / or etch based schemes may be needed that can complement EUV printing and meet the technology gap.

[0057] To provide context, for a metal layer containing metal lines of multiple widths, sometimes one metal may not provide optimal performance at both narrow and wide metal lines, and it may be beneficial to use two different metals to achieve optimal performance. For example, for narrower lines, a non-copper wire without a barrier layer may be optimal, while for wider lines, a tungsten wire with a molybdenum barrier layer, such as described above, may be optimal.

[0058] According to one or more embodiments of the present disclosure, Co or Ru is used for the initial metallization of all wide and narrow metal lines. A patterning process is then used to recess the first metal deposition for the wider lines and backfill the recesses with tungsten conductive lines with a molybdenum barrier layer.

[0059] As an exemplary process flow, Figure 2A , 2B 3 illustrate oblique cross-sectional views representing various operations in a method of fabricating a metallization structure including differentiated conductive lines in accordance with an embodiment of the present disclosure.

[0060] refer to Figure 2A , the starting structure 200 includes a conductive line layer 207 located on a conductive via layer 203, which is located on a substrate or underlying metallization structure 202. The conductive via layer 203 includes one or more conductive vias 206 located in a dielectric layer 204, such as an interlayer dielectric (ILD) layer. As shown, an etch stop layer 209, such as a silicon nitride etch stop layer, can be located between the conductive line layer 207 and the conductive via layer 203. The combination of the conductive line layer 207 and the conductive via layer 203 can be referred to as a metallization layer of the BEOL portion of the integrated circuit structure.

[0061] Reference again Figure 2A , the wire layer 207 includes a plurality of wires 210 / 212 at the same level and along the same direction. A first wire 210 in the plurality of wires 210 / 212 has a first width (W1) and a first component. A second wire 212 in the plurality of wires 210 / 212 has a second width (W2) and a second component. In an embodiment, the second width (W2) is greater than the first width (W1). In an embodiment, the second component is the same as the first component. The wire layer 207 also includes an ILD structure 208, some portions of the ILD structure being between adjacent wires of the plurality of wires 210 / 212.

[0062] In an embodiment, the first conductive line 210 of the plurality of conductive lines 210 / 212 includes a first conductive filler without a conductive barrier. The second conductive line 212 of the plurality of conductive lines 210 / 212 includes a first conductive filler without a conductive barrier. In an embodiment, the first conductive filler includes Co or Ru.

[0063] In an embodiment, a first conductor 210 of the plurality of conductors 210 / 212 has a break therein. A first dielectric plug 214A is located at the break location in the first conductor 210 of the plurality of conductors 210 / 212. A second conductor 212 of the plurality of conductors 210 / 212 has a break therein. A second dielectric plug 214B is located at the break location in the second conductor 212 of the plurality of conductors 210 / 212.

[0064] refer to Figure 2B, a mask layer 250 is formed to cover the narrower wires 210 of the plurality of wires 210 / 212. The mask 250 exposes the wider wires 212 of the plurality of wires 212 / 212. An etching process is used to remove the exposed wider wires 212 of the plurality of wires 210 / 212 or at least substantially recess the exposed wider wires 212 (e.g., reduce the thickness of the exposed wider wires 212 by 90%-100%), thereby forming trenches 252. In one such embodiment, the exposed wider wires 212 of the plurality of wires 210 / 212 are not completely removed, and a layer 212A of the first conductive fill material remains, as shown.

[0065] refer to Figure 3 , remove the mask 250. Figure 2B The conductive line 302 is formed in the groove 252 of the conductive line 302. In an embodiment, the conductive line 302 includes a conductive barrier 304 and a second conductive filler 306. In an embodiment, the second conductive filler 306 is different from the first conductive filler. In an embodiment, the second conductive filler 306 includes W. In an embodiment, the conductive barrier 304 includes molybdenum.

[0066] Reference again Figure 2A , 2B 3, according to an embodiment of the present disclosure, the integrated circuit structure 300 includes a plurality of conductive lines 210 / 302 at the same level and along the same direction. The first conductive line 210 of the plurality of conductive lines 210 / 302 has a first width (W1) and a first component. The second conductive line 302 of the plurality of conductive lines 210 / 302 has a second width (W2) and a second component. In an embodiment, the second width (W2) is greater than the first width (W1). In an embodiment, the second component is different from the first component. The integrated circuit structure 300 also includes an interlayer dielectric (ILD) structure 208, some portions of the ILD structure 208 being between adjacent conductive lines of the plurality of conductive lines 210 / 302.

[0067] In an embodiment, a first conductive line 210 of the plurality of conductive lines 210 / 302 includes a first conductive filler without a conductive barrier. A second conductive line 302 of the plurality of conductive lines 210 / 302 includes a conductive barrier 304 and a second conductive filler 306. The second conductive filler 306 is different from the first conductive filler. In an embodiment, the conductive barrier 304 of the second conductive line 302 of the plurality of conductive lines 210 / 302 is on a conductive layer 212B having the same composition as the first conductive filler. In an embodiment, the first conductive filler includes Co or Ru, and the second conductive filler 306 includes W.

[0068] In an embodiment, a first conductor 210 of the plurality of conductors 210 / 302 has a break therein. A first dielectric plug 214A is located at the break location of the first conductor 210 of the plurality of conductors 210 / 302. A second conductor 302 of the plurality of conductors 210 / 302 has a break therein. A second dielectric plug 214B is located at the break location of the second conductor 302 of the plurality of conductors 210 / 302.

[0069] In an embodiment, a first conductive line 210 of the plurality of conductive lines 210 / 302 has a break in it, and the ILD structure has a dielectric plug portion at the break location of the first conductive line 210 of the plurality of conductive lines 210 / 302. The dielectric plug portion of the ILD structure is continuous with one or more portions of the ILD structure between adjacent conductive lines of the plurality of conductive lines 210 / 302. Figure 5 An exemplary such structure is described, and the similar structure may be a representative structure of a plurality of narrower ( W1 ) conductive lines 210 .

[0070] In another aspect, one or more embodiments described herein relate to a scheme for implementing a cut plug for metal and inter-layer dielectric (ILD) last process flow for metal process and process window applications.

[0071] The embodiments described herein may involve a process initiated by generating a grid in which metal lines will eventually be fabricated. The process involves cutting the grid that will generate metal plugs, adding a shrink liner to increase the metal line CD to the desired size, backfilling with dielectric and removing the dummy grid and replacing with the final metal. The various embodiments may be implemented to achieve extremely small plug CDs that would otherwise be impossible.

[0072] The embodiments described herein may be implemented to manufacture a more scalable plug process (e.g., much smaller plug CDs may be achieved using the processes described herein). The embodiments described herein may be implemented to provide much greater plug-to-metal edge placement error (EPE) tolerance (process robustness and yield).

[0073] As an exemplary processing scheme and exemplary resulting structure, Figures 4A-4E 5 and 6 show cross-sectional views showing various operations in a dielectric plug manufacturing scheme according to an embodiment of the present disclosure. It should be appreciated that the scheme described below can be used to manufacture a dielectric plug. Figure 3 at least a portion of the conductive line 210 / 302 , for example, the narrower ( W1 ) line 210 .

[0074] The grid can be generated where the metal lines will eventually form. The critical dimension (CD) of the grid can be reduced to allow the grid to be cut with greater tolerance. Figure 4A, the starting structure 400 includes a grid 404 on a hard mask layer 403 on an underlying substrate or dielectric layer 402 (e.g., an underlying metallization layer or a layer in which a via structure is formed). In an embodiment, the grid 404 is formed by a pitch halving or spacer division scheme, where, for example, an initial amorphous carbon backbone grid of 48nm pitch is pitch halved by forming amorphous silicon spacers on the backbone and then removing the backbone to provide an amorphous silicon grid. In an embodiment, the grid 404 defines the location of the final metal line, and the size reduction provides edge placement error (EPE) tolerance for subsequent operations.

[0075] refer to Figure 4B , a cutting process is performed on the grid 404. For example, a masking layer may be formed over the structure 400, and an etching process may be performed to provide a cut grid 404A having gaps 406 therein. In an embodiment, the etching process is performed at a location where a dielectric plug for a metal line will eventually be formed.

[0076] After the cutting process, the grid size can be increased using the same or similar material as the initial grid material to achieve a grid CD equal to the final metal width. The increase in grid CD can also reduce the final plug CD. Figure 4C , a deposition process is performed on the grid 404A to effectively grow, thereby forming the grid 404B. In an embodiment, this process operation may be referred to as forming an EPE liner / CD adjustment liner (and may be the same material as 404). In an embodiment, this process operation returns the CD to the target value for both the plug and metal line dimensions.

[0077] After the growth process, the grid may be backfilled with a dielectric material, such as an interlayer dielectric material, and polished to expose the sacrificial grid. Figure 4D ,exist Figure 4C A dielectric material is formed over the structure of planarization grid 404C and the resulting structure is planarized to provide planarization grid 404C having dielectric structures 408 therein. Dielectric structures 408 occupy locations between features of planarization grid 404C and plug locations 406 to form plugs 410.

[0078] The sacrificial grid can then be replaced by the final metal material. Figure 4E , the planarization grid 404C is removed to leave the dielectric structure 408. In addition, the exposed portion of the hard mask 403 may be removed to form a patterned hard mask 403A, as shown.

[0079] refer to Figure 5, for example, by a deposition and planarization process, a conductive structure 502 is formed in the location previously occupied by the planarization grid 404C to provide structure 500. In one embodiment, the conductive structure 502 includes a conductive barrier 504 and a conductive filler 506. In an embodiment, the conductive structure 502 is a plurality of conductive lines along the same direction. Some of the conductive lines may have interruptions due to being partially disconnected by dielectric structures 408, which effectively act as dielectric plugs 410 in those locations. Although not shown, in one embodiment, the conductive lines are aligned with underlying vias in the underlying metallization layer.

[0080] In another aspect, a pitch-quadrant scheme is implemented for patterning trenches in a dielectric layer for forming BEOL interconnect structures. According to embodiments of the present disclosure, pitch-quadrant is applied to fabricate metal lines in a BEOL fabrication scheme. Embodiments can achieve continuous scaling of metal layer pitches, exceeding the resolution capabilities of existing lithography equipment.

[0081] Figure 6 FIG. 6 is a schematic diagram of a pitch quadrant scheme 600 for manufacturing a trench of an interconnect structure according to an embodiment of the present disclosure. It should be appreciated that the scheme described below can be used to manufacture Figure 3 at least a portion of the conductive line 210 / 302 , for example, the narrower ( W1 ) line 210 .

[0082] refer to Figure 6 In operation (a), direct photolithography is used to form the backbone feature 602. For example, a photoresist layer or stack may be patterned and the pattern may be transferred to a hard mask material to ultimately form the backbone feature 602. The photoresist layer or stack used to form the backbone feature 602 may be patterned using standard photolithography processing techniques, such as 193 immersion lithography. A first spacer feature 604 is then formed adjacent to the sidewalls of the backbone feature 602.

[0083] In operation (b), the backbone features 602 are removed to leave only the first spacer features 604. At this stage, the first spacer features 604 are actually half-pitch masks, for example, representing a pitch-halved process. The first spacer features 604 can be used directly in a pitch-quartered process, or the pattern of the first spacer features 604 can first be transferred to a new hard mask material, the latter of which is illustrated here.

[0084] At operation (c), the pattern of the first spacer feature 604 is transferred to a new hard mask material to form a first spacer feature 604'. A second spacer feature 606 is then formed adjacent to the sidewalls of the first spacer feature 604'.

[0085] At operation (d), the first spacer features 604' are removed to leave only the second spacer features 606. At this stage, the second spacer features 606 are actually a quarter pitch mask, for example, representing a pitch quartering process.

[0086] In operation (e), the second spacer feature 606 is used as a mask to pattern a plurality of trenches 608 in the dielectric or hard mask layer. The trenches may eventually be filled with a conductive material to form conductive interconnects in the metallization layer of the integrated circuit. The trenches 608 labeled "B" correspond to the backbone features 602. The trenches 608 labeled "S" correspond to the first spacer features 604 or 604'. The trenches 608 labeled "C" correspond to the complementary regions 607 between the backbone features 602.

[0087] It should be recognized that due to Figure 6 Each groove 608 has a Figure 6 The patterning origin of one of the backbone features 602, the first spacer features 604 or 604', or the complementary regions 607, so the difference in width and / or pitch of such features may appear as an artifact of the pitch quartering process in the conductive interconnects ultimately formed in the metallization layers of the integrated circuit. Fig. 7A A cross-sectional view of a metallization layer fabricated using a pitch quartering scheme according to an embodiment of the present disclosure is shown. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., such as a combination of Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Fig. 7A interconnect layer.

[0088] refer to Fig. 7A , the integrated circuit structure 700 includes an interlayer dielectric (ILD) layer 704 on a substrate 702. A plurality of conductive interconnect lines 706 are located in the ILD layer 704, and each of the plurality of conductive interconnect lines 706 is separated from each other by a portion of the ILD layer 704. Each of the plurality of conductive interconnect lines 706 includes a conductive barrier layer 708 and a conductive filling material 710.

[0089] refer to Figure 6 and 7A Both, conductive interconnect 706B is formed in trenches with a pattern derived from backbone features 602. Conductive interconnect 706S is formed in trenches with a pattern derived from first spacer features 604 or 604'. Conductive interconnect 706C is formed in trenches with a pattern derived from complementary regions 607 between backbone features 602.

[0090] Reference again Fig. 7AIn an embodiment, the plurality of conductive interconnects 706 include a first interconnect 706B having a width (W1). The second interconnect 706S is adjacent to the first interconnect 706B, and the width (W2) of the second interconnect 706S is different from the width (W1) of the first interconnect 706B. The third interconnect 706C is adjacent to the second interconnect 706S, and the third interconnect 706C has a width (W3). The fourth interconnect (second 706S) is adjacent to the third interconnect 706C, and the width (W2) of the fourth interconnect is the same as the width (W2) of the second interconnect 706S. The fifth interconnect (second 706B) is adjacent to the fourth interconnect (second 706S), and the width (W1) of the fifth interconnect (second 706B) is the same as the width (W1) of the first interconnect 706B.

[0091] In an embodiment, the width (W3) of the third interconnect line 706C is different from the width (W1) of the first interconnect line 706B. In one such embodiment, the width (W3) of the third interconnect line 706C is different from the width (W2) of the second interconnect line 706S. In another such embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W2) of the second interconnect line 706S. In another embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W1) of the first interconnect line 706B.

[0092] In an embodiment, the spacing (P1) between the first interconnection line 706B and the third interconnection line 706C is the same as the spacing (P2) between the second interconnection line 706S and the fourth interconnection line (second 706S). In another embodiment, the spacing (P1) between the first interconnection line 706B and the third interconnection line 706C is different from the spacing (P2) between the second interconnection line 706S and the fourth interconnection line (second 706S).

[0093] Reference again Fig. 7A In another embodiment, the plurality of conductive interconnects 706 include a first interconnect 706B having a width (W1). The second interconnect 706S is adjacent to the first interconnect 706B, and the second interconnect 706S has a width (W2). The third interconnect 706C is adjacent to the second interconnect 706S, and the width (W3) of the third interconnect 706S is different from the width (W1) of the first interconnect 706B. The fourth interconnect (second 706S) is adjacent to the third interconnect 706C, and the width (W2) of the fourth interconnect is the same as the width (W2) of the second interconnect 706S. The fifth interconnect (second 706B) is adjacent to the fourth interconnect (second 706S), and the width (W1) of the fifth interconnect (second 706B) is the same as the width (W1) of the first interconnect 706B.

[0094] In an embodiment, the width (W2) of the second interconnect line 706S is different from the width (W1) of the first interconnect line 706B. In one such embodiment, the width (W3) of the third interconnect line 706C is different from the width (W2) of the second interconnect line 706S. In another such embodiment, the width (W3) of the third interconnect line 706C is the same as the width (W2) of the second interconnect line 706S.

[0095] In an embodiment, the width (W2) of the second interconnect line 706S is the same as the width (W1) of the first interconnect line 706B. In an embodiment, the spacing (P1) between the first interconnect line 706B and the third interconnect line 706C is the same as the spacing (P2) between the second interconnect line 706S and the fourth interconnect line (second 706S). In an embodiment, the spacing (P1) between the first interconnect line 706B and the third interconnect line 706C is different from the spacing (P2) between the second interconnect line 706S and the fourth interconnect line (second 706S).

[0096] Figure 7B FIG. 1 shows a cross-sectional view of a metallization layer fabricated using a pitch-halving scheme on top of a metallization layer fabricated using a pitch-quartering scheme according to an embodiment of the present disclosure. In an embodiment, a molybdenum liner and tungsten filler conductor scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Figure 7B interconnect layer.

[0097] refer to Figure 7B , the integrated circuit structure 750 includes a first interlayer dielectric (ILD) layer 754 above a substrate 752. A first plurality of conductive interconnects 756 are in the first ILD layer 754, and each conductive interconnect of the first plurality of conductive interconnects 756 is separated from each other by a portion of the first ILD layer 754. Each conductive interconnect of the first plurality of conductive interconnects 756 includes a conductive barrier layer 758 and a conductive fill material 760. The integrated circuit structure 750 also includes a second interlayer dielectric (ILD) layer 774 above the substrate 752. A second plurality of conductive interconnects 776 are in the second ILD layer 774, and each conductive interconnect of the second plurality of conductive interconnects 776 is separated from each other by a portion of the second ILD layer 774. Each conductive interconnect of the second plurality of conductive interconnects 776 includes a conductive barrier layer 778 and a conductive fill material 780.

[0098] According to the embodiments of the present disclosure, referring again to Figure 7B, a method of manufacturing an integrated circuit structure includes forming a first plurality of conductive interconnect lines 756 spaced apart by a first interlayer dielectric (ILD) layer 754 in a first interlayer dielectric (ILD) layer 754 over a substrate 752. Using a spacer-based pitch quadrature process, for example, in combination with Figure 6 The scheme described in operations (a)-(e) of FIG. 7 is used to form a first plurality of conductive interconnect lines 756. A second plurality of conductive interconnect lines 776 separated by the second ILD layer 774 is formed in the second ILD layer 774 on the first ILD layer 754. Using a spacer-based pitch-halving process, for example, in combination with Figure 6 The scheme described in operations (a) and (b) is used to form a second plurality of conductive interconnect lines 776.

[0099] In an embodiment, the first plurality of conductive interconnect lines 756 have a pitch (P1) of 40 nanometers between adjacent lines. The second plurality of conductive interconnect lines 776 have a pitch (P2) of 44 nanometers or greater between adjacent lines. In an embodiment, the spacer-based pitch quartering process and the spacer-based pitch halving process are based on an immersion 193nm lithography process.

[0100] In an embodiment, each conductive interconnect line of the first plurality of conductive interconnect lines 754 includes a first conductive barrier liner 758 and a first conductive fill material 760. Each conductive interconnect line of the second plurality of conductive interconnect lines 756 includes a second conductive barrier liner 778 and a second conductive fill material 780. In one such embodiment, the composition of the first conductive fill material 760 is different from the second conductive fill material 780. In another embodiment, the composition of the first conductive fill material 760 is the same as the second conductive fill material 780.

[0101] Although not shown, in an embodiment, the method further includes forming a third plurality of conductive interconnect lines separated by the third ILD layer in a third ILD layer over the second ILD layer 774. The third plurality of conductive interconnect lines is formed without using pitch division.

[0102] Although not shown, in an embodiment, the method further includes, before forming the second plurality of conductive interconnects 776, forming a third plurality of conductive interconnects separated by the third ILD layer in the third ILD layer above the first ILD layer 754. The third plurality of conductive interconnects are formed using a spacer-based pitch quartering process. In one such embodiment, after forming the second plurality of conductive interconnects 776, a fourth plurality of conductive interconnects separated by the fourth ILD layer are formed in the fourth ILD layer above the second ILD layer 774. The fourth plurality of conductive interconnects are formed using a spacer-based pitch halfing process. In an embodiment, such a method further includes forming a fifth plurality of conductive interconnects separated by the fifth ILD layer in the fifth ILD layer above the fourth ILD layer, the fifth plurality of conductive interconnects being formed using a spacer-based pitch halfing process. Then a sixth plurality of conductive interconnects separated by the sixth ILD layer are formed in the sixth ILD layer above the fifth ILD layer, the sixth plurality of conductive interconnects being formed using a spacer-based pitch halfing process. A seventh plurality of conductive interconnect lines are then formed in a seventh ILD layer over the sixth ILD layer, separated by the seventh ILD layer. The seventh plurality of conductive interconnect lines are formed without using pitch division.

[0103] In another aspect, the metal line composition varies between metallization layers. Such an arrangement may be referred to as a heterogeneous metallization layer. In an embodiment, tungsten (with a Mo liner) is used as a conductive fill material for larger interconnects, while cobalt is used as a conductive fill material for smaller interconnects. Smaller lines with cobalt as a fill material may provide reduced electromigration while maintaining low resistivity. Using cobalt for smaller interconnects may address scaling issues where a conductive barrier consumes a greater amount of interconnect volume and reduces the conductive fill, substantially obstructing the advantages normally associated with interconnects.

[0104] In the first example, Fig. 8A A cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is shown, wherein the integrated circuit structure has a metallization layer of one metal line composition on top of a metallization layer of a different metal line composition. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Fig. 8A interconnect layer.

[0105] refer to Fig. 8A, the integrated circuit structure 800 includes a first plurality of conductive interconnect lines 806 spaced apart by a first inter-layer dielectric (ILD) layer 804 in a first inter-layer dielectric (ILD) layer 804 over a substrate 802. One of the conductive interconnect lines 806A is shown as having an underlying via 807. Each of the first plurality of conductive interconnect lines 806 includes a first conductive barrier material 808 along sidewalls and a bottom of a first conductive fill material 810.

[0106] The second plurality of conductive interconnects 816 are in and separated by the second ILD layer 814 above the first ILD layer 804. One of the conductive interconnects 816A is shown as having a lower via 817. Each conductive interconnect of the second plurality of conductive interconnects 816 includes a second conductive barrier material 818 along the sidewalls and bottom of a second conductive fill material 820. The composition of the second conductive fill material 820 is different from that of the first conductive fill material 810. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form interconnection lines.

[0107] Reference again Fig. 8A , the second ILD layer 814 is on the etch stop layer 822. The conductive via 817 is in the second ILD layer 814 and in the opening of the etch stop layer 822. In an embodiment, the first and second ILD layers 804 and 814 include silicon, carbon, and oxygen, and the etch stop layer 822 includes silicon and nitrogen. In an embodiment, each conductive interconnect line of the first plurality of conductive interconnect lines 806 has a first width (W1), and each conductive interconnect line of the second plurality of conductive interconnect lines 816 has a second width (W2) greater than the first width (W1).

[0108] In the second example, Figure 8B A cross-sectional view of an integrated circuit structure according to an embodiment of the present disclosure is shown, the integrated circuit structure including a metallization layer having a metal line composition coupled to a metallization layer having a different metal line composition. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Figure 8B interconnect layer.

[0109] refer to Figure 8B, the integrated circuit structure 850 includes a first plurality of conductive interconnect lines 856 spaced apart by a first inter-layer dielectric (ILD) layer 854 in a first inter-layer dielectric (ILD) layer 854 over a substrate 852. One of the conductive interconnect lines 856A is shown as having an underlying via 857. Each of the first plurality of conductive interconnect lines 856 includes a first conductive barrier material 858 along sidewalls and a bottom of a first conductive fill material 860.

[0110] The second plurality of conductive interconnects 866 are in and separated by a second ILD layer 864 above the first ILD layer 854. One of the conductive interconnects 866A is shown as having a via 867 underneath. Each conductive interconnect of the second plurality of conductive interconnects 866 includes a second conductive barrier material 868 along the sidewalls and bottom of a second conductive fill material 870. The composition of the second conductive fill material 870 is different from that of the first conductive fill material 860. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form interconnection lines.

[0111] In an embodiment, the conductive via 867 is on and electrically coupled to an individual conductive interconnect line 856B of the first plurality of conductive interconnect lines 856, electrically coupling an individual conductive interconnect line 866A of the second plurality of conductive interconnect lines 866 to an individual conductive interconnect line 856B of the first plurality of conductive interconnect lines 856. In an embodiment, the individual conductive interconnect lines of the first plurality of conductive interconnect lines 856 are along a first direction 898 (e.g., into and out of the page), and the individual conductive interconnect lines of the second plurality of conductive interconnect lines 866 are along a second direction 899 orthogonal to the first direction 898, as shown. In an embodiment, the conductive via 867 includes a second conductive barrier material 868 along the sidewalls and bottom of the second conductive fill material 870, as shown.

[0112] In an embodiment, the second ILD layer 864 is on the etch stop layer 872, and the etch stop layer 872 is on the first ILD layer 854. The conductive via 867 is in the second ILD layer 864 and in the opening of the etch stop layer 872. In an embodiment, the first and second ILD layers 854 and 864 include silicon, carbon, and oxygen, and the etch stop layer 872 includes silicon and nitrogen. In an embodiment, each conductive interconnect line of the first plurality of conductive interconnect lines 856 has a first width (W1), and each conductive interconnect line of the second plurality of conductive interconnect lines 866 has a second width (W2) greater than the first width (W1).

[0113] In an embodiment, the second conductive fill material 870 consists essentially of tungsten and the first conductive fill material 860 consists essentially of cobalt. In one such embodiment, the composition of the first conductive barrier material 858 is different from the second conductive barrier material 868. In another such embodiment, the composition of the first conductive barrier material 858 is the same as the second conductive barrier material 868.

[0114] Fig. 9 The embodiment of the present disclosure is shown in FIG. Fig. 8A and 8B Cross-sectional view of an individual interconnect line of the structure, the interconnect line having a barrier liner and a conductive cap structure arrangement. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Fig. 9 interconnect layer.

[0115] refer to Fig. 9 , the interconnect line 920 in the dielectric layer 921 includes a molybdenum barrier material 922 and a tungsten fill 924. A conductive capping layer 930 is located on top of the tungsten fill material 924. In one such embodiment, the conductive capping layer 930 is also located on top of the molybdenum barrier material 922, as shown. In another embodiment, the conductive capping layer 930 is not on top of the molybdenum barrier material 922. In an embodiment, the conductive capping layer 930 consists essentially of cobalt, and the conductive fill material 924 consists essentially of tungsten.

[0116] Fig.10 A cross-sectional view of an integrated circuit structure having four metallization layers of one metal line composition and pitch on top of two metallization layers of different metal line compositions and smaller pitches according to an embodiment of the present disclosure is shown. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Fig.10 interconnect layer.

[0117] refer to Fig.10, the integrated circuit structure 1000 includes a first plurality of conductive interconnect lines 1004 spaced apart by a first inter-layer dielectric (ILD) layer 1002 in a first inter-layer dielectric (ILD) layer 1002 over a substrate 1001. Each conductive interconnect line of the first plurality of conductive interconnect lines 1004 includes a first conductive barrier material 1006 along sidewalls and a bottom of a first conductive fill material 1008. Each conductive interconnect line of the first plurality of conductive interconnect lines 1004 is arranged along a first direction 1098 (e.g., into and out of the page).

[0118] The second plurality of conductive interconnect lines 1014 are in and separated by the second ILD layer 1012 above the first ILD layer 1002. Each conductive interconnect line of the second plurality of conductive interconnect lines 1014 includes the first conductive barrier material 1006 along the sidewalls and bottom of the first conductive fill material 1008. Each conductive interconnect line of the second plurality of conductive interconnect lines 1014 is along a second direction 1099 orthogonal to the first direction 1098.

[0119] The third plurality of conductive interconnects 1024 are in and separated by a third ILD layer 1022 over the second ILD layer 1012. Each conductive interconnect of the third plurality of conductive interconnects 1024 includes a second conductive barrier layer 1026 along a sidewall and a bottom of a second conductive fill material 1028. The second conductive fill material 1028 has a different composition than the first conductive fill material 1008. Each conductive interconnect of the third plurality of conductive interconnects 1024 is along a first direction 1098.

[0120] The fourth plurality of conductive interconnect lines 1034 are in and spaced apart by the fourth ILD layer 1032 over the third ILD layer 1022. Each conductive interconnect line of the fourth plurality of conductive interconnect lines 1034 includes the second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filling material 1028. Each conductive interconnect line of the fourth plurality of conductive interconnect lines 1034 is along the second direction 1099.

[0121] The fifth plurality of conductive interconnect lines 1044 are in and spaced apart by the fifth ILD layer 1042 over the fourth ILD layer 1032. Each conductive interconnect line of the fifth plurality of conductive interconnect lines 1044 includes the second conductive barrier material 1026 along the sidewalls and bottom of the second conductive fill material 1028. Each conductive interconnect line of the fifth plurality of conductive interconnect lines 1044 is along the first direction 1098.

[0122] The sixth plurality of conductive interconnect lines 1054 are in and spaced apart by the sixth ILD layer 1052 over the fifth ILD layer 1042. Each conductive interconnect line of the sixth plurality of conductive interconnect lines 1054 includes the second conductive barrier material 1026 along the sidewalls and bottom of the second conductive fill material 1028. Each conductive interconnect line of the sixth plurality of conductive interconnect lines 1054 is along the second direction 1099.

[0123] In an embodiment, the second conductive fill material 1028 consists essentially of tungsten and the first conductive fill material 1008 consists essentially of cobalt.

[0124] In an embodiment, the composition of the first conductive barrier material 1006 is different from the second conductive barrier material 1026. In another embodiment, the first conductive barrier material 1006 and the second conductive barrier material 1026 have the same composition.

[0125] In an embodiment, first conductive via 1019 is on and electrically coupled to single conductive interconnect line 1004A of first plurality of conductive interconnect lines 1004. Single conductive interconnect line 1014A of second plurality of conductive interconnect lines 1014 is on and electrically coupled to first conductive via 1019.

[0126] The second conductive via 1029 is on and electrically coupled to the single conductive interconnect line 1014B of the second plurality of conductive interconnect lines 1014. The single conductive interconnect line 1024A of the third plurality of conductive interconnect lines 1024 is on and electrically coupled to the second conductive via 1029.

[0127] The third conductive via 1039 is on and electrically coupled to the single conductive interconnect line 1024B of the third plurality of conductive interconnect lines 1024. The single conductive interconnect line 1034A of the fourth plurality of conductive interconnect lines 1034 is on and electrically coupled to the third conductive via 1039.

[0128] The fourth conductive via 1049 is on and electrically coupled to the single conductive interconnect line 1034B of the fourth plurality of conductive interconnect lines 1034. The single conductive interconnect line 1044A of the fifth plurality of conductive interconnect lines 1044 is on and electrically coupled to the fourth conductive via 1049.

[0129] The fifth conductive via 1059 is on and electrically coupled to the single conductive interconnect line 1044B of the fifth plurality of conductive interconnect lines 1044. The single conductive interconnect line 1054A of the sixth plurality of conductive interconnect lines 1054 is on and electrically coupled to the fifth conductive via 1059.

[0130] In one embodiment, the first conductive via 1019 includes the first conductive barrier material 1006 along the sidewalls and bottom of the first conductive filling material 1008. The second conductive via 1029, the third conductive via 1039, the fourth conductive via 1049, and the fifth conductive via 1059 include the second conductive barrier material 1026 along the sidewalls and bottom of the second conductive filling material 1028.

[0131] In an embodiment, the first ILD layer 1002, the second ILD layer 1012, the third ILD layer 1022, the fourth ILD layer 1032, the fifth ILD layer 1042, and the sixth ILD layer 1052 are separated from each other by a corresponding etch stop layer 1090 between adjacent ILD layers. In an embodiment, the first ILD layer 1002, the second ILD layer 1012, the third ILD layer 1022, the fourth ILD layer 1032, the fifth ILD layer 1042, and the sixth ILD layer 1052 include silicon, carbon, and oxygen.

[0132] In an embodiment, each conductive interconnect line of the first plurality of conductive interconnect lines 1004 and the second plurality of conductive interconnect lines 1014 has a first width (W1). Each conductive interconnect line of the third plurality of conductive interconnect lines 1024, the fourth plurality of conductive interconnect lines 1034, the fifth plurality of conductive interconnect lines 1044, and the sixth plurality of conductive interconnect lines 1054 has a second width (W2) greater than the first width (W1).

[0133] In another aspect, techniques for patterning metal line endings are described. To provide context, in advanced nodes of semiconductor manufacturing, low-level interconnects may be generated by independent patterning processes for wire grids, line endings, and vias. However, the fidelity of the composite pattern may degrade as vias erode line endings and line endings erode vias. Embodiments described herein provide an end-of-line process, also known as a plug process, that eliminates the associated approximation rule. Embodiments may allow placement of vias at line endings and allow large vias to span across line endings.

[0134] To provide further context, Fig.11A A plan view and a corresponding cross-sectional view taken along an aa′ axis of a plan view of a metallization layer according to an embodiment of the present disclosure are shown. Fig. 11B A cross-sectional view of a wire end or plug is shown in accordance with an embodiment of the present disclosure. Fig. 11C Another cross-sectional view of a wire end or plug according to an embodiment of the present disclosure is shown. In an embodiment, a molybdenum liner and tungsten filler wire solution (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Figures 11A-11C interconnect layer.

[0135] refer to Fig.11A , the metallization layer 1100 includes a metal line 1102 formed in a dielectric layer 1104. The metal line 1102 can be coupled to a via 1103 below. The dielectric layer 1104 can include a line end or plug region 1105. Fig. 11B , the line end or plug region 1105 of the dielectric layer 1104 can be fabricated by patterning the hard mask layer 1110 on the dielectric layer 1104 and then etching the exposed portion of the dielectric layer 1104. The exposed portion of the dielectric layer 1104 can be etched to a depth suitable for forming the line trench 1106 or further etched to a depth suitable for forming the via trench 1108. Fig. 11C , two vias adjacent to opposite sidewalls of the line end or plug 1105 can be fabricated in a single large exposure 1116 to ultimately form a line trench 1112 and a via trench 1114 .

[0136] However, again referring to Figures 11A-11C , fidelity issues and / or hard mask erosion issues may result in imperfect patterning schemes. In contrast, one or more embodiments described herein include implementations of a process flow involving construction of an end-of-line dielectric (plug) after trench and via patterning processes.

[0137] In one aspect, then, one or more embodiments described herein relate to schemes for constructing non-conductive spaces or interruptions (referred to as "line ends," "plugs," or "cuts") between metal lines and, in some embodiments, associated conductive vias. Conductive vias, by definition, are used to contact a previous layer metal pattern. In this way, the embodiments described herein enable a more robust interconnect manufacturing scheme because there is less reliance on alignment of the lithographic equipment. Such an interconnect manufacturing scheme can be used to relax constraints on alignment / exposure, can be used to improve electrical contact (e.g., by reducing via resistance), and can be used to reduce the total process operations and processing time that would otherwise be required to pattern such features using conventional means.

[0138] Figures 12A-12F 1 and 2 show plan views and corresponding cross-sectional views of various operations in a plug finishing scheme representing an embodiment of the present disclosure. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Figures 12A-12F interconnect layer.

[0139] refer to Fig. 12A, a method of manufacturing an integrated circuit structure includes forming a line trench 1206 in an upper portion 1204 of an interlayer dielectric (ILD) material layer 1202 formed above a lower metallization layer 1200. A via trench 1208 is formed in a lower portion 1210 of the ILD material layer 1202. The via trench 1208 exposes a metal line 1212 of the lower metallization layer 1200.

[0140] refer to Fig. 12B A sacrificial material 1214 is formed on the ILD material layer 1202 and in the line trench 1206 and the via trench 1208. A hard mask 1215 may be formed on the sacrificial material 1214. Fig. 12B In one embodiment, sacrificial material 1214 includes carbon.

[0141] refer to Fig. 12C The sacrificial material 1214 is patterned to interrupt the continuity of the sacrificial material 1214 in the line trench 1206 , for example, to provide an opening 1216 in the sacrificial material 1214 .

[0142] refer to Fig.12D , the opening 1216 in the sacrificial material 1214 is filled with a dielectric material to form a dielectric plug 1218. In an embodiment, after the opening 1216 in the sacrificial material 1214 is filled with a dielectric material, the hard mask 1215 is removed to provide a dielectric plug 1218 having an upper surface 1220 above an upper surface 1222 of the ILD material 1202, as shown in FIG. Fig.12D The sacrificial material 1214 is removed to leave the dielectric plug 1218 .

[0143] In an embodiment, filling the opening 1216 of the sacrificial material 1214 with a dielectric material includes filling with a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In an embodiment, filling the opening 1216 of the sacrificial material 1214 with a dielectric material includes filling with atomic layer deposition (ALD).

[0144] refer to Fig.12E , the line trench 1206 and the via trench 1208 are filled with a conductive material 1224. In an embodiment, the conductive material 1224 is formed over the dielectric plug 1218 and the ILD layer 1202, as shown.

[0145] refer to Fig.12F , the conductive material 1224 and the dielectric plug 1218 are planarized to provide a planarized dielectric plug 1218 ′ that breaks the continuity of the conductive material 1224 in the line trench 1206 .

[0146] Reference again Fig.12FAccording to an embodiment of the present disclosure, an integrated circuit structure 1250 includes an interlayer dielectric (ILD) layer 1202 above a substrate. A conductive interconnect 1224 is in a trench 1206 in the ILD layer 1202. The conductive interconnect 1224 has a first portion 1224A and a second portion 1224B, the first portion 1224A being laterally adjacent to the second portion 1224B. A dielectric plug 1218' is between and laterally adjacent to the first portion 1224A and the second portion 1224B of the conductive interconnect 1224. Although not shown, in an embodiment, the conductive interconnect 1224 includes a conductive barrier liner and a conductive fill material, exemplary materials for which are described above. In one such embodiment, the conductive fill material includes cobalt.

[0147] In an embodiment, the dielectric plug 1218 ′ includes a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In an embodiment, the dielectric plug 1218 ′ is in direct contact with the first portion 1224A and the second portion 1224B of the conductive interconnect line 1224 .

[0148] In an embodiment, the dielectric plug 1218′ has a bottom 1218A that is substantially coplanar with the bottom 1224C of the conductive interconnect line 1224. In an embodiment, the first conductive via 1226 is in the trench 1208 in the ILD layer 1202. In one such embodiment, the first conductive via 1226 is lower than the bottom 1224C of the interconnect line 1224, and the first conductive via 1226 is electrically coupled to the first portion 1224A of the conductive interconnect line 1224.

[0149] In an embodiment, the second conductive via 1228 is in the third trench 1230 in the ILD layer 1202. The second conductive via 1228 is lower than the bottom 1224C of the interconnect line 1224, and the second conductive via 1228 is electrically coupled to the second portion 1224B of the conductive interconnect line 1224.

[0150] The dielectric plug may be formed using a filling process such as a chemical vapor deposition process. Artifacts may remain in the manufactured dielectric plug. As an example, Fig.13A A cross-sectional view of a wire plug having a seam therein according to an embodiment of the present disclosure is shown. In an embodiment, a molybdenum liner and tungsten filler wire solution (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Fig.13A interconnect layer.

[0151] refer to Fig.13A, the dielectric plug 1318 has a substantially vertical seam 1300 that is substantially equally spaced from the first portion 1224A of the conductive interconnect line 1224 and the second portion 1224B of the conductive interconnect line 1224 .

[0152] It should be appreciated that dielectric plugs having a composition different from the ILD material in which they are housed may be included only on selected metallization layers, such as the underlying metallization layer. Fig. 13B A cross-sectional view of a metallization layer stack including a wire plug at the location of an underlying metal line according to an embodiment of the present disclosure is shown. In an embodiment, a molybdenum liner and tungsten filler wire scheme (e.g., as combined with Figure 1 ) and / or a differentiated wire scheme (e.g., as described above in conjunction with Figure 2A , 2B and 3) to form Fig. 13B interconnect layer.

[0153] refer to Fig. 13B , the integrated circuit structure 1350 includes a first plurality of conductive interconnects 1356 in a first inter-layer dielectric (ILD) layer 1354 over a substrate 1352 and separated by a first inter-layer dielectric layer 1354. Each conductive interconnect of the first plurality of conductive interconnects 1356 has continuity broken by one or more dielectric plugs 1358. In an embodiment, the one or more dielectric plugs 1358 include a different material than the ILD layer 1354. A second plurality of conductive interconnects 1366 are in a second ILD layer 1364 over the first ILD layer 1354 and separated by the second ILD layer 1364. In an embodiment, each conductive interconnect of the second plurality of conductive interconnects 1366 has continuity broken by one or more portions 1368 of the second ILD layer 1364. It should be appreciated that other metallization layers may be included in the integrated circuit structure 1350 as shown.

[0154] In one embodiment, one or more dielectric plugs 1358 include a metal oxide material. In one such embodiment, the metal oxide material is aluminum oxide. In one embodiment, the first ILD layer 1354 and the second ILD layer 1364 (and therefore, one or more portions 1368 of the second ILD layer 1364) include a carbon-doped silicon oxide material.

[0155] In one embodiment, each conductive interconnect line of the first plurality of conductive interconnect lines 1356 includes a first conductive barrier liner 1356A and a first conductive fill material 1356B. Each conductive interconnect line of the second plurality of conductive interconnect lines 1366 includes a second conductive barrier liner 1366A and a second conductive fill material 1366B. In one such embodiment, the composition of the first conductive fill material 1356B is different from that of the second conductive fill material 1366B. In a specific such embodiment, the first conductive fill material 1356B includes cobalt and the second conductive fill material 1366B includes tungsten (e.g., on a molybdenum liner).

[0156] In one embodiment, the first plurality of conductive interconnects 1356 have a first pitch (P1, as shown in similar layer 1370). The second plurality of conductive interconnects 1366 have a second pitch (P2, as shown in similar layer 1380). The second pitch (P2) is greater than the first pitch (P1). In one embodiment, each conductive interconnect of the first plurality of conductive interconnects 1356 has a first width (W1, as shown in similar layer 1370). Each conductive interconnect of the second plurality of conductive interconnects 1366 has a second width (W2, as shown in similar layer 1380). The second width (W2) is greater than the first width (W1).

[0157] It should be appreciated that the layers and materials described in conjunction with back-end-of-line (BEOL) structures and processing may be formed on or above a lower semiconductor substrate or structure, such as one or more lower device layers of an integrated circuit. In an embodiment, the lower semiconductor substrate represents a general workpiece object for manufacturing an integrated circuit. Semiconductor substrates often include wafers or other objects composed of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon, and silicon on insulator (ILD) and similar substrates formed of other semiconductor materials, such as substrates including germanium, carbon, or III-V materials. Depending on the stage of manufacturing, semiconductor substrates often include transistors, integrated circuit systems, etc. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In addition, the structure shown may be fabricated on an interconnect layer at a lower level below.

[0158] Although the foregoing methods of fabricating a metallization layer or a portion of a metallization layer of a BEOL metallization layer are described in detail in conjunction with selected operations, it should be appreciated that additional or intervening operations for fabrication may include standard microelectronics fabrication processes, such as photolithography, etching, thin film deposition, planarization (e.g., chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other action associated with microelectronic component fabrication. Furthermore, it should be appreciated that the process operations described for the foregoing process flows may be practiced in an alternative order, not every operation need be performed, or additional process operations may be performed, or both.

[0159] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. For example, the interlayer dielectric layer may be formed by techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0160] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are composed of one or more metals or other conductive structures. The interconnects can be a single material layer, or can be formed by several layers, including a conductor layer and a filling layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form the interconnects. In an embodiment, the interconnects are composed of conductive materials, such as a molybdenum liner and a tungsten filler. In the art, interconnects are sometimes also referred to as traces, lines, lines, metals, or simply interconnects.

[0161] In an embodiment, as also used throughout this specification, the hard mask material is composed of a dielectric material that is different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etching selectivities relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes a metallic substance. For example, a hard mask or other covering material may include a layer of titanium or another metal nitride (e.g., titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used, depending on the particular embodiment. The hard mask layer may be formed by CVD, PVD, or other deposition methods.

[0162] In an embodiment, as also used throughout this specification, lithography operations are performed using 193nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography. Positive or negative resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topography masking portion, an anti-reflective coating (ARC), and a photoresist layer. In a specific such embodiment, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating is a silicon ARC layer.

[0163] The embodiments described herein can be used to manufacture a wide range of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in a wide range of various electronic devices known in the prior art. For example, in computer systems (e.g., desktops, laptops, servers), cellular phones, personal electronic devices, etc. The integrated circuit can be coupled to buses and other components in the system. For example, a processor can be coupled to a memory, a chipset, etc. by one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0164] Fig.14 A computing device 1400 is shown according to one embodiment of the present disclosure. The computing device 1400 houses a board 1402. The board 1402 may include several components, including, but not limited to, a processor 1404 and at least one communication chip 1406. The processor 1404 is physically and electrically coupled to the board 1402. In some embodiments, the at least one communication chip 1406 is also physically and electrically coupled to the board 1402. In other embodiments, the communication chip 1406 is part of the processor 1404.

[0165] Depending on its application, the computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0166] The communication chip 1406 can implement wireless communications for transmitting data to and from the computing device 1400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wiring, although in some embodiments they may not. The communication chip 1406 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, EDCT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher versions. The computing device 1400 may include multiple communication chips 1406. For example, the first communication chip 1406 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 1406 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0167] The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of the disclosed embodiments, the integrated circuit die of the processor includes one or more structures, for example, integrated circuit structures constructed according to the disclosed embodiments. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0168] The communication chip 1406 also includes an integrated circuit die packaged within the semiconductor chip 1406. According to another embodiment of the present disclosure, the integrated circuit die of the communication chip is constructed according to the embodiments of the present disclosure.

[0169] In other implementations, another component housed within computing device 1400 may include an integrated circuit die constructed in accordance with implementations of the disclosed embodiments.

[0170] In various embodiments, computing device 1400 may be a laptop computer, a netbook, a notebook, an ultrabook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other embodiments, computing device 1400 may be any other electronic device that processes data.

[0171] Fig.15 An interposer 1500 is shown that includes one or more embodiments of the present disclosure. Interposer 1500 is an intermediate substrate for bridging a first substrate 1502 to a second substrate 1504. First substrate 1502 may be, for example, an integrated circuit die. Second substrate 1504 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1500 is to spread connections to a wider spacing or to reroute connections to different connections. For example, interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 1506, which in turn may be coupled to a second substrate 1504. In some embodiments, first and second substrates 1502 / 1504 are attached to opposite sides of interposer 1500. In other embodiments, first and second substrates 1502 / 1504 are attached to the same side of interposer 1500. In other embodiments, three or more substrates are interconnected by interposer 1500.

[0172] Interposer 1500 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other embodiments, interposer 1500 may be formed of alternating rigid or flexible materials, which may include the same materials as described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0173] The interposer 1500 may include metal interconnects 1508 and vias 1510, including but not limited to through silicon vias (TSVs) 1512. The interposer 1500 may further include embedded devices 1514, which include both passive devices and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices may also be formed on the interposer 1500, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices. According to an embodiment of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the interposer 1500 or in the manufacture of components included in the interposer 1500.

[0174] Fig.16 is an isometric view of a mobile computing platform 1600 according to an embodiment of the present disclosure, the mobile computing platform employing an integrated circuit (IC) manufactured according to one or more processes described herein or including one or more features described herein.

[0175] The mobile computing platform 1600 can be any portable device configured for electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1600 can be any one of a tablet computer, a smart phone, a laptop computer, etc., including a display screen 1605, a chip-level (SoC) or package-level integrated system 1610 and a battery 1613. In an exemplary embodiment, the display screen 1605 is a touch screen (capacitive, inductive, resistive, etc.). As shown in the figure, the higher the integration level achieved in the system 1610 with a higher transistor stacking density, the larger the part that can be occupied by the battery 1613 or a non-volatile storage device, such as a solid-state drive, in the mobile computing platform 1600, or the larger the number of transistor gates used to improve the platform function. Similarly, the greater the carrier mobility of each transistor in the system 1610, the more powerful the function. Therefore, the technology described herein can achieve improvements in performance and form factor in the mobile computing platform 1600.

[0176] The integrated system 1610 is further illustrated in the enlarged view 1620. In an exemplary embodiment, the packaged device 1677 includes at least one memory chip (e.g., RAM) manufactured according to one or more processes described herein or including one or more processor features described herein, or at least one processor chip (e.g., a multi-core microprocessor and / or a graphics processor). The packaged device 1677 is further coupled to the circuit board 1660 along with a power management integrated circuit (PMIC) 1615, an RF (wireless) integrated circuit (RFIC) 1625 including a broadband RF (wireless) transmitter and / or receiver (e.g., including a digital baseband and analog front-end module, and also including a power amplifier on the transmit path and a low noise amplifier on the receive path) and its controller 1611. Functionally, the PMIC 1615 performs battery power regulation, DC to DC conversion, etc., and therefore has an input terminal coupled to the battery 1613 and has an output terminal that provides current supply to all other functional modules. As further shown, in an exemplary embodiment, RFIC 1625 has an output coupled to an antenna to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, EDCT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In alternative embodiments, each of these board-level modules can be integrated into a separate IC coupled to the packaging substrate of the packaged device 1677, or integrated into a single IC (SoC) coupled to the packaging substrate of the packaged device 1677.

[0177] In another aspect, semiconductor packaging is used to protect an integrated circuit (IC) chip or die and also provide the die with an electrical interface to an external circuit system. As the demand for smaller electronic devices increases, semiconductor packages are designed to be more compact and must support greater circuit density. In addition, the demand for higher performance devices has led to a need for improved semiconductor packages that can achieve a thin package profile and low overall warpage that is compatible with subsequent assembly processes.

[0178] In an embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a die is mounted to a ceramic or organic package substrate using a C4 process. Specifically, a C4 solder ball connection can be implemented to provide a flip chip interconnection between a semiconductor device and a substrate. Flip chip or controlled collapse chip connection (C4) is a mounting technology for semiconductor devices that utilizes solder bumps instead of wire bonding, and the semiconductor device is, for example, an integrated circuit (IC) chip, MEMS or component. Solder bumps are deposited on C4 pads located on the top side of the substrate package. In order to mount the semiconductor device to the substrate, it is turned upside down, with the active side facing down above the mounting area. Solder bumps are used to connect the semiconductor device directly to the substrate.

[0179] Fig.17 A cross-sectional view of a flip-chip mounted die is shown in accordance with an embodiment of the present disclosure.

[0180] refer to Fig.17 , device 1700 includes a die 1702, such as an integrated circuit (IC) manufactured according to one or more processes described herein or including one or more features described herein. Die 1702 includes metallization pads 1704 thereon. A package substrate 1706, such as a ceramic or organic substrate, includes connections 1708 thereon. Die 1702 and package substrate 1706 are electrically connected via solder balls 1710 coupled to metallization pads 1704 and connections 1708. An underfill material 1712 surrounds solder balls 1710.

[0181] Processing a flip chip can be similar to conventional IC manufacturing, with a few additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several processes. Small dots of solder are then deposited on each metallized pad. The chip is then cut from the wafer as normal. To attach the flip chip to the circuit, the chip is turned upside down and the solder dots are lowered down onto the connectors on the underlying electronics or circuit board. The solder is then remelted to create an electrical connection, usually using an ultrasonic or reflow process. This also leaves a small space between the chip's circuitry and the underlying mounting. In most cases, an electrically insulating adhesive is then "bottom-filled" to provide a stronger mechanical connection, provide a thermal bridge, and ensure that the solder joints are not stressed due to differential heating of the chip and the rest of the system.

[0182] In other embodiments, according to embodiments of the present disclosure, newer packaging and die-to-die interconnect methods, such as through-silicon vias (TSVs) and silicon interposers, are implemented to manufacture high-performance multi-chip modules (MCMs) and systems in packages (SiPs) that incorporate integrated circuits (ICs) manufactured according to one or more processes described herein or that include one or more features described herein.

[0183] Thus, embodiments of the present disclosure include the fabrication of advanced integrated circuit structures, including conductive schemes for integrated circuit structure fabrication and resulting structures.

[0184] Although specific embodiments have been described above, even if only a single embodiment is described with respect to a particular feature, these embodiments are not intended to limit the scope of the present disclosure. The examples of features provided in the present disclosure are intended to be illustrative rather than restrictive unless otherwise stated. The above description is intended to cover those alternatives, modifications, and equivalents that will be apparent to those skilled in the art that have the beneficial effects of the present disclosure.

[0185] The scope of the present disclosure includes any feature or combination of features disclosed herein (expressly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be made during the prosecution of the present application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined with features of the independent claims, and features from corresponding independent claims may be combined in any appropriate manner and not merely by the specific combinations listed in the appended claims.

[0186] The following examples relate to other embodiments. The various features of the different embodiments can be combined in various ways with some included features and other features excluded to suit a variety of different applications.

[0187] Example embodiment 1: An integrated circuit structure includes a plurality of conductive lines on the same level and along the same direction, each conductive line of the plurality of conductive lines having a liner including molybdenum (Mo) and a filler including tungsten (W). The integrated circuit structure also includes an interlayer dielectric (ILD) structure, some portions of the ILD structure being located between adjacent conductive lines of the plurality of conductive lines.

[0188] Example Embodiment 2: The integrated circuit structure according to Example Embodiment 1, wherein the liner layer including molybdenum (Mo) has a thickness in the range of 2-5 nanometers.

[0189] Example Embodiment 3: The integrated circuit structure according to Example Embodiment 1 or 2, wherein the liner layer including molybdenum (Mo) includes greater than 98 atomic percent Mo.

[0190] Example Embodiment 4: The integrated circuit structure of Example Embodiment 1, 2 or 3, wherein the filler including tungsten (W) includes greater than 98 atomic percent W.

[0191] Exemplary embodiment 5: An integrated circuit structure according to exemplary embodiments 1, 2, 3 or 4, wherein the liner including molybdenum (Mo) is a thermal atomic layer deposition (ALD) liner, a plasma ALD liner, a physical vapor deposition (PVD) liner or an organic ALD liner, and wherein the filler including tungsten (W) is a chemical vapor deposition (CVD) filler.

[0192] Exemplary embodiment 6: An integrated circuit structure includes a plurality of conductive lines at the same level and along the same direction, a first conductive line of the plurality of conductive lines having a first width and a first composition, and a second conductive line of the plurality of conductive lines having a second width and a second composition. The second width is greater than the first width, and the second composition is different from the first composition. The second conductive line of the plurality of conductive lines has a liner including molybdenum (Mo) and a filler including tungsten (W). The integrated circuit structure also includes an interlayer dielectric (ILD) structure, some portions of the ILD structure being located between adjacent conductive lines of the plurality of conductive lines.

[0193] Exemplary Embodiment 7: The integrated circuit structure according to Exemplary Embodiment 6, wherein the first conductive line of the plurality of conductive lines includes a conductive filler without a conductive barrier.

[0194] Example 8: The integrated circuit structure according to Example 6 or 7, wherein the liner layer including molybdenum (Mo) has a thickness in the range of 2-5 nanometers.

[0195] Exemplary embodiment 9: The integrated circuit structure according to exemplary embodiments 6, 7 or 8, wherein the liner including molybdenum (Mo) includes greater than 98 atomic percent Mo, and wherein the filler including tungsten (W) includes greater than 98 atomic percent W.

[0196] Exemplary embodiment 10: An integrated circuit structure according to exemplary embodiments 6, 7, 8 or 9, wherein the liner including molybdenum (Mo) is a thermal atomic layer deposition (ALD) liner, a plasma ALD liner, a physical vapor deposition (PVD) liner or an organic ALD liner, and wherein the filler including tungsten (W) is a chemical vapor deposition (CVD) filler.

[0197] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a plurality of conductive lines on the same level and along the same direction, each conductive line of the plurality of conductive lines having a liner including molybdenum (Mo) and a filler including tungsten (W). The integrated circuit structure also includes an interlayer dielectric (ILD) structure, some portions of the ILD structure being located between adjacent conductive lines of the plurality of conductive lines.

[0198] Exemplary Embodiment 12: The computing device of Exemplary Embodiment 11, further comprising a memory coupled to the board.

[0199] Exemplary Embodiment 13: The computing device of Exemplary Embodiment 11 or 12, further comprising a communication chip coupled to the board.

[0200] Example Embodiment 14: The computing device of Example Embodiment 11, 12 or 13, further comprising a camera coupled to the board.

[0201] Exemplary Embodiment 15: The computing device of Exemplary Embodiment 11, 12, 13 or 14, further comprising a battery coupled to the board.

[0202] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14 or 15, further comprising a speaker coupled to the board.

[0203] Exemplary Embodiment 17: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15 or 16, further comprising a compass coupled to the board.

[0204] Exemplary Embodiment 18: The computing device of Exemplary Embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a GPS coupled to the board.

[0205] Example Embodiment 19: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17 or 18, further comprising a display coupled to the board.

[0206] Example Embodiment 20: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is a packaged integrated circuit die.

Claims

1. An integrated circuit structure, comprising: a plurality of conductive lines, each conductive line of the plurality of conductive lines having a liner including molybdenum (Mo) and a filler including tungsten (W); as well as An interlayer dielectric (ILD) structure, portions of which are located between adjacent ones of the plurality of conductive lines.

2. The integrated circuit structure according to claim 1, wherein: The liner layer including molybdenum (Mo) has a thickness in the range of 2-5 nanometers.

3. The integrated circuit structure according to claim 1 or 2, wherein: The liner including molybdenum (Mo) includes greater than 98 atomic percent Mo.

4. The integrated circuit structure according to claim 1 or 2, wherein: The fill including tungsten (W) includes greater than 98 atomic percent W.

5. The integrated circuit structure according to claim 1 or 2, wherein: The liner including molybdenum (Mo) is a thermal atomic layer deposition (ALD) liner, a plasma ALD liner, a physical vapor deposition (PVD) liner or an organic ALD liner, and wherein the filler including tungsten (W) is a chemical vapor deposition (CVD) filler.

6. An integrated circuit structure comprising: A plurality of conductive lines at the same level and along the same direction, a first conductive line of the plurality of conductive lines having a first width and a first composition, and a second conductive line of the plurality of conductive lines having a second width and a second composition, the second width being greater than the first width and the second composition being different from the first composition, the second conductive line of the plurality of conductive lines having a liner including molybdenum (Mo) and a filler including tungsten (W); as well as An interlayer dielectric (ILD) structure, portions of which are located between adjacent ones of the plurality of conductive lines.

7. The integrated circuit structure according to claim 6, wherein: The first conductive line of the plurality of conductive lines includes a conductive filler without a conductive barrier.

8. The integrated circuit structure according to claim 6 or 7, wherein: The liner layer including molybdenum (Mo) has a thickness in the range of 2-5 nanometers.

9. The integrated circuit structure according to claim 6 or 7, wherein: The liner including molybdenum (Mo) includes more than 98 atomic percent of Mo, and wherein the filler including tungsten (W) includes more than 98 atomic percent of W.

10. The integrated circuit structure according to claim 6 or 7, wherein: The liner including molybdenum (Mo) is a thermal atomic layer deposition (ALD) liner, a plasma ALD liner, a physical vapor deposition (PVD) liner or an organic ALD liner, and wherein the filler including tungsten (W) is a chemical vapor deposition (CVD) filler.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: a plurality of conductive lines, each conductive line of the plurality of conductive lines having a liner including molybdenum (Mo) and a filler including tungsten (W); as well as An interlayer dielectric (ILD) structure, portions of which are located between adjacent ones of the plurality of conductive lines.

12. The computing device of claim 11, further comprising: A memory is coupled to the board.

13. The computing device according to claim 11 or 12, further comprising: A communication chip is coupled to the board.

14. The computing device according to claim 11 or 12, further comprising: A camera is coupled to the board.

15. The computing device according to claim 11 or 12, further comprising: A battery is coupled to the board.

16. The computing device according to claim 11 or 12, further comprising: A speaker is coupled to the board.

17. The computing device according to claim 11 or 12, further comprising: A compass is coupled to the board.

18. The computing device according to claim 11 or 12, further comprising: Coupled to the board's GPS.

19. The computing device according to claim 11 or 12, further comprising: A display is coupled to the panel.

20. The computing device according to claim 11 or 12, wherein: The component is a packaged integrated circuit die.

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