Contact hole test structure and manufacturing method thereof, method for detecting contact hole over-etching and semiconductor device structure

Abstract

The present invention provides a contact hole test structure and a manufacturing method thereof, a method for detecting contact hole over-etching, and a semiconductor device structure. The contact hole test structure includes: a substrate; a first well region located in the substrate, and a second well region located in the first well region; a second metal silicide layer located on the surface of the second well region and a first metal silicide layer located on a portion of the surface of the first well region, the first metal silicide layer and the second metal silicide layer being spaced apart; a dielectric layer located on the first metal silicide layer and the second metal silicide layer, and a first contact hole structure electrically connected to the first metal silicide layer and a second contact hole structure electrically connected to the second metal silicide layer located in the dielectric layer; a first test terminal electrically connected to the first contact hole structure and a second test terminal electrically connected to the second contact hole structure, respectively. The present invention can determine whether a contact hole has etched through based on the obtained electrical performance test data, thereby saving time and effort.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a contact hole test structure and a manufacturing method thereof, a method for detecting over-etching of a contact hole, and a semiconductor device structure. Background Art

[0002] In the related art, after etching the contact holes in the semiconductor device, Figure 1 As shown, the etched contact hole is first photographed, and then the presence of small black spots at the bottom of the contact hole in the photo is determined by the naked eye to determine whether the contact hole has been etched through (the presence of small black spots at the bottom of the hole indicates that the contact hole has been etched through).

[0003] This method requires manual visual judgment, is time-consuming and labor-intensive, and cannot confirm the depth of the contact hole.

[0004] In view of the above technical problems, the present invention provides a new contact hole test structure and a manufacturing method thereof, a method for detecting over-etching of a contact hole, and a semiconductor device structure. Summary of the Invention

[0005] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] In order to solve the existing problems, the present invention provides a contact hole test structure, which includes:

[0007] substrate;

[0008] a first well region of a first conductivity type located in the substrate, and a second well region of a second conductivity type located in the first well region;

[0009] a second metal silicide layer located on a surface of the second well region and a first metal silicide layer located on a portion of a surface of the first well region, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other;

[0010] a dielectric layer located on the first metal silicide layer and the second metal silicide layer, and a first contact hole structure and a second contact hole structure located in the dielectric layer, wherein the first contact hole structure is electrically connected to the first metal silicide layer, and the second contact hole structure is electrically connected to the second metal silicide layer;

[0011] A first test end and a second test end, wherein the first test end is electrically connected to the first contact hole structure, and the second test end is electrically connected to the second contact hole structure.

[0012] In some embodiments of the present application, a plurality of second contact hole structures are provided in the dielectric layer, and the plurality of second contact hole structures are electrically connected to the same second test terminal.

[0013] In some embodiments of the present application,

[0014] The first well region is a p-type well region, and the second well region is an n-type well region; or,

[0015] The first well region is an n-type well region, and the second well region is a p-type well region.

[0016] In some embodiments of the present application, the metal silicide includes cobalt silicide.

[0017] In some embodiments of the present application, the contact hole test structure further includes:

[0018] A gate structure is provided in the second dielectric layer.

[0019] Another aspect of the present invention provides a semiconductor device structure, comprising at least one contact hole test structure as described above, wherein the contact hole test structure is formed in a cutting path of the semiconductor device structure.

[0020] In some embodiments of the present application, the size of the contact hole structure in the contact hole test structure is consistent with the size of the contact hole structure in the semiconductor device between the dicing streets.

[0021] Another aspect of the present invention provides a method for manufacturing a contact hole test structure, the manufacturing method comprising:

[0022] providing a substrate;

[0023] forming a first well region having a first conductivity type in the substrate, and forming a second well region having a second conductivity type in the first well region;

[0024] forming a second metal silicide layer on a surface of the second well region, and forming a first metal silicide layer on a portion of a surface of the first well region, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other;

[0025] forming a dielectric layer on the first metal silicide layer and the second metal silicide layer;

[0026] A first contact hole structure and a second contact hole structure are formed in the dielectric layer, wherein the first contact hole structure is electrically connected to the first metal silicide layer, and the second contact hole structure is electrically connected to the second metal silicide layer.

[0027] Another aspect of the present invention provides a method for detecting over-etching of a contact hole, the method comprising:

[0028] Performing an electrical performance test through the first test end and the second test end of any one of the contact hole test structures described above to obtain electrical performance test data;

[0029] It is determined whether the contact hole in the contact hole test structure is etched through according to the electrical performance test data.

[0030] In some embodiments, the method further comprises:

[0031] When the contact hole is etched through, the etch depth of the contact hole is determined according to the electrical performance test data.

[0032] The contact hole test structure and its manufacturing method, the method for detecting over-etching of the contact hole and the semiconductor device structure of the present invention form a first well region and a second well region on a substrate, and form a second metal silicide layer on the surface of the second well region, form a first metal silicide layer on a portion of the surface of the first well region, and form a first contact hole structure electrically connected to the first metal silicide layer and a second contact hole structure electrically connected to the second metal silicide layer in a dielectric layer. When the electrical performance of the first contact hole structure and the second contact hole structure are tested through the first test end and the second test end, it is possible to determine whether the contact hole has been etched through based on the obtained electrical performance test data, which saves time and effort.

[0033] Moreover, the numerical value of the electrical performance test data can be used to further determine the depth of the contact hole to indicate the risk of leakage.

[0034] In addition, when the contact hole is etched through, the affected range can be locked through the full image of the wafer acceptability test, achieving large-scale inspection with high coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0036] In the attached figure:

[0037] Figure 1 A schematic diagram showing a method of photographing an etched contact hole in the related art is shown.

[0038] Figure 2 A cross-sectional schematic diagram of a contact hole test structure according to a specific embodiment of the present invention is shown.

[0039] Figure 3 Shown Figure 2 Top view of the mid-contact hole test structure.

[0040] Figure 4 A cross-sectional schematic diagram of a contact hole test structure according to another specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0041] In the following description, numerous specific details are provided to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, certain technical features well known in the art are not described to avoid confusion with the present invention.

[0042] It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0044] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In the related art, after etching the contact holes in the semiconductor device, Figure 1 As shown, the etched contact hole is first photographed, and then the photo is visually identified to determine whether there are small black spots at the bottom of the contact hole. This is used to determine whether the contact hole has been etched through (the presence of small black spots at the bottom of the hole indicates that the contact hole has been etched through). This method has at least the following disadvantages:

[0047] 1. It requires manual visual judgment, which is time-consuming and labor-intensive;

[0048] 2. Unable to confirm the penetration depth of the contact hole;

[0049] 3. The photography method can only be used for sampling inspection, not large-scale inspection, and the coverage rate is low;

[0050] 4. A single WAT (Wafer Acceptance Test) test key cannot reflect the actual conditions of a series of contact hole structures in a semiconductor device.

[0051] Therefore, in view of the existence of the aforementioned technical problems, the present invention proposes a contact hole test structure, comprising: a substrate; a first well region with a first conductivity type located in the substrate, and a second well region with a second conductivity type located in the first well region; a second metal silicide layer located on the surface of the second well region and a first metal silicide layer located on a portion of the surface of the first well region, the first metal silicide layer and the second metal silicide layer being spaced apart; a dielectric layer located on the first metal silicide layer and the second metal silicide layer, and a first contact hole structure and a second contact hole structure located in the dielectric layer, the first contact hole structure being electrically connected to the first metal silicide layer, and the second contact hole structure being electrically connected to the second metal silicide layer; a first test end and a second test end, the first test end being electrically connected to the first contact hole structure, and the second test end being electrically connected to the second contact hole structure.

[0052] According to the contact hole test structure of the present application, by forming a first well region and a second well region on the substrate, and forming a second metal silicide layer on the surface of the second well region, a first metal silicide layer is formed on a portion of the surface of the first well region, and a first contact hole structure electrically connected to the first metal silicide layer and a second contact hole structure electrically connected to the second metal silicide layer are formed in the dielectric layer. When the electrical performance of the first contact hole structure and the second contact hole structure are tested through the first test end and the second test end, it is possible to determine whether the contact hole has a punch-through phenomenon through the obtained electrical performance test data, which saves time and effort.

[0053] Moreover, the numerical value of the electrical performance test data can be used to further determine the depth of the contact hole to indicate the risk of leakage.

[0054] In addition, when the contact hole is etched through, the affected range can be locked through the full image of the wafer acceptability test, achieving large-scale inspection with high coverage.

[0055] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0056] Example 1

[0057] Reference below Figures 2 to 4A contact hole test structure according to one embodiment of the present application is described. The contact hole test structure includes: a substrate 110; a first well region 121 of a first conductivity type located in the substrate 110, and a second well region 122 of a second conductivity type located in the first well region 121; a second metal silicide layer 132 located on a surface of the second well region 122, and a first metal silicide layer 131 located on a portion of a surface of the first well region 121, wherein the first metal silicide layer 131 is separated from the second metal silicide layer 132; a dielectric layer 140 located on the first metal silicide layer 131 and the second metal silicide layer 132, and a first contact hole structure 151 and a second contact hole structure 152 located in the dielectric layer, wherein the first contact hole structure 151 is electrically connected to the first metal silicide layer 131, and the second contact hole structure 152 is electrically connected to the second metal silicide layer 132; a first test terminal 161 and a second test terminal 162, wherein the first test terminal 161 is electrically connected to the first contact hole structure 151, and the second test terminal 162 is electrically connected to the second contact hole structure 152.

[0058] Specifically, when the second contact hole structure 152 does not show a punch-through phenomenon, the second contact hole structure 152 is only electrically connected to the second metal silicide layer 132, and is not electrically connected to the well region below the second metal silicide layer 132. At this time, an electrical performance test can be performed through the first test terminal 161 and the second test terminal 162 to obtain electrical performance test data when no punch-through phenomenon occurs. When the second contact hole structure 152 shows a punch-through phenomenon, the second contact hole structure 152 passes through the second metal silicide layer 132 and is electrically connected to the well region below. At this time, an electrical performance test can be performed through the first test terminal 161 and the second test terminal 162 to obtain electrical performance test data when a punch-through phenomenon occurs.

[0059] Based on this, the present application forms a first well region 121 and a second well region 122 on the substrate 110, and forms a second metal silicide layer 152 on the surface of the second well region 122, forms a first metal silicide layer 151 on a portion of the surface of the first well region, and forms a first contact hole structure 151 electrically connected to the first metal silicide layer 151 and a second contact hole structure 152 electrically connected to the second metal silicide layer 152 in the dielectric layer 140, so that when the electrical performance of the first contact hole structure 151 and the second contact hole structure 152 are tested through the first test end 161 and the second test end 162, it is possible to determine whether the contact hole has a through-hole phenomenon through the obtained electrical performance test data, which saves time and effort.

[0060] Moreover, the numerical value of the electrical performance test data can be used to further determine the depth of the contact hole to indicate the risk of leakage.

[0061] In addition, when the contact hole is etched through, the wafer acceptability test full map (WAT fullmap) can be used to lock the affected area, achieving large-scale inspection with high coverage.

[0062] In some embodiments, the substrate 110 can be any suitable semiconductor wafer, such as a bulk silicon wafer, and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or can be ceramic wafers such as alumina, quartz or glass wafers, etc.

[0063] In some embodiments, the first well region 121 and the second well region 122 may form a PN junction. The PN junction of this embodiment may be obtained by ion implantation, and no additional process or mask is required during the formation process.

[0064] For example, Figure 2 and Figure 3 As shown, the first well region 121 may be a P-type well region (ie, PW), and the second well region 122 may be an N-type well region (ie, NW, which may be obtained by high-voltage n-type implantation (NLH)) to form a PN junction; or, as shown Figure 4 As shown, the first well region 121 may be an N-type well region (ie, NW), and the second well region 122 may be a P-type well region (ie, PW, which may be obtained by high-voltage p-type implantation (PLH)) to form a PN junction.

[0065] In some embodiments, the first metal silicide layer 131 and the second metal silicide layer 132 can be obtained by metal deposition and annealing to react the metal with substrate silicon. The metal silicide can be cobalt silicide (CoSi) or any other suitable metal silicide material, which is not limited.

[0066] In some embodiments, the dielectric layer 150 may be formed by depositing a dielectric material on the first metal silicide layer 131 and the second metal silicide layer 132 . The dielectric material may be any suitable material such as silicon dioxide, which is not limited thereto.

[0067] In some embodiments, the first contact hole structure 151 and the second contact hole structure 152 can be composed of a contact hole and a metal material filled therein. Any suitable metal material can be selected, including but not limited to at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W and Al. Preferably, the metal material filled in the contact hole includes W.

[0068] In some embodiments, as Figure 2 As shown, a plurality of second contact hole structures 152 arranged at intervals may be provided in the dielectric layer 150 , and the plurality of second contact hole structures 152 are connected to the same second test terminal 162 .

[0069] Specifically, related art techniques typically only have a single WAT test key, which cannot reflect the conditions of a series of contact hole structures in an actual semiconductor device structure. In this embodiment, by providing multiple second contact hole structures 152 spaced apart, the density of the second contact hole structures 152 in the contact hole test structure is increased, thereby being able to reflect the conditions of a series of contact hole structures in an actual semiconductor device structure.

[0070] In some embodiments, as Figure 2 As shown, when the contact hole corresponding to the second contact hole structure 152 is etched through, the lower end of at least one second contact hole structure 152 passes through the second metal silicide layer 132 and is electrically connected to the PN junction below the second metal silicide layer 132. For example, Figure 2 As shown, the lower end of one of the second contact hole structures 152 passes through the second metal silicide layer 132 and the second well region 122, electrically connecting to the first well region 121. When the second contact hole structure 152 is electrically connected to the PN junction below the second metal silicide layer 132, it will cause the PN junction to fail. Electrical performance testing (e.g., leakage current measurement, BV measurement, etc.) can be performed through the first test terminal 161 and the second test terminal 162 to calculate the depth of the contact hole.

[0071] In some embodiments, the first test terminal 161 and the second test terminal 162 may also be referred to as pads. The material of the first test terminal 161 and the second test terminal 162 may include any suitable metal material, including but not limited to at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al. Preferably, the material of the first test terminal 161 and the second test terminal 162 includes Al.

[0072] In some embodiments, as Figure 2 and Figure 3As shown, the contact hole test structure further includes a gate structure 170, which is disposed in the dielectric layer 150. The gate structure 170 may be a polysilicon gate (Poly) structure or any other type of gate structure, without limitation. In this embodiment, by providing the gate structure 170, the morphology of the contact hole test structure can be made more consistent with the morphology of the actual semiconductor device, thereby making the test results obtained through the contact hole test structure more consistent with the actual situation.

[0073] Example 2

[0074] According to another aspect of the present application, a semiconductor device structure is provided. The semiconductor device structure includes at least one contact hole test structure formed in a cutting path of the semiconductor device structure.

[0075] The contact hole test structure may be implemented as the contact hole test structure described above, and reference may be made to the above description, which will not be repeated here.

[0076] In some embodiments, the dimensions of the contact hole structures in the contact hole test structure are consistent with the dimensions of the contact hole structures in the semiconductor devices between the scribe lines. By ensuring the dimensions of the contact hole structures are consistent, the conditions of the contact hole structures in the contact hole test structure can be further aligned with the conditions of the contact hole structures in the actual semiconductor devices, thereby making the test results obtained using the contact hole test structure more consistent with the actual conditions. The semiconductor devices between the scribe lines may be MOS transistors, etc., without limitation.

[0077] Example 3

[0078] According to yet another aspect of the present application, a method for manufacturing a contact hole test structure is provided.

[0079] Exemplarily, the method for manufacturing a contact hole test structure of the present invention includes the following steps:

[0080] First, step 1 is performed to provide a substrate 110 .

[0081] Among them, the substrate 110 can be any suitable semiconductor wafer, such as a bulk silicon wafer, and it can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or it can be ceramic wafers such as alumina, quartz or glass wafers, etc.

[0082] Next, step two is performed to form a first well region 121 having the first conductivity type in the substrate 110 , and a second well region 122 having the second conductivity type in the first well region 121 .

[0083] Specifically, ion implantation may be performed on the substrate 110 to form the first well region 121 in the substrate 110 . The formed first well region 121 may include dopant ions of the first conductivity type.

[0084] For example, the first conductivity type may be a P-type, and accordingly, the first well region 121 may be a P-type well region (eg, Figure 2 and Figure 3 As shown), the doping ions of the first conductive type may be P-type ions; or, the first conductive type may be N-type, and accordingly, the first well region 121 may be an N-type well region (as shown). Figure 4 As shown), the first conductive type doping ions may be N-type ions.

[0085] After forming the first well region, a relevant mask can be used to block part of the first well region 121, and then ion implantation is performed on the remaining first well region 121 to form a second well region 122 in the remaining first well region 121. The formed second well region 122 may include doped ions of the second conductive type.

[0086] The second conductivity type is different from the first conductivity type. For example, when the first conductivity type is P type, the second conductivity type may be N type, and accordingly, the second well region 122 may be an N type well region (e.g., Figure 2 and Figure 3 As shown), the second conductive type doping ions may be N-type ions; or, when the first conductive type is N-type, the second conductive type may be P-type, and accordingly, the second well region 122 may be a P-type well region (as shown). Figure 4 As shown), the second conductive type doping ions can be P-type ions.

[0087] Next, step three is performed to form a second metal silicide layer 132 on the surface of the second well region 122 and a first metal silicide layer 131 on the surface of a portion of the first well region 121 , with the first metal silicide layer 131 and the second metal silicide layer 132 spaced apart.

[0088] Specifically, the second well region 122 can be shielded by a relevant mask, and metal is deposited and annealed to allow the metal to react with the substrate silicon to form a first metal silicide layer 131 on the first well region 121. Then, the mask and the deposits on the mask on the second well region 122 are partially removed, and the first metal silicide layer 131 is shielded by a relevant mask, and metal is deposited and annealed to allow the metal to react with the substrate silicon to form a second metal silicide layer 132 on the second well region 122. Of course, it is understood that the first metal silicide layer 131 can be formed first and then the second metal silicide layer 132 as described above, or the second metal silicide layer 132 can be formed first and then the first metal silicide layer 131.

[0089] In other embodiments, metal may be deposited directly on the substrate 110 and annealed to allow the metal to react with the substrate silicon to form a metal silicide layer, and then the metal silicide layer may be etched to form a first metal silicide layer 131 and a second metal silicide layer 132 that are spaced apart.

[0090] The metal silicide may be cobalt silicate or any other suitable metal silicide material, which is not limited.

[0091] Next, step four is performed to form a dielectric layer 140 on the first metal silicide layer 131 and the second metal silicide layer 132 .

[0092] Specifically, a dielectric material may be deposited on the first metal silicide layer 131 and the second metal silicide layer 132 to form a dielectric layer 140 on the first metal silicide layer 131 and the second metal silicide layer 132. The dielectric material may be any suitable material such as silicon dioxide, which is not limited thereto.

[0093] Next, step five is performed to form a first contact hole structure 151 and a second contact hole structure 152 in the dielectric layer 140 . The first contact hole structure 151 is electrically connected to the first metal silicide layer 131 , and the second contact hole structure 152 is electrically connected to the second metal silicide layer 132 .

[0094] Taking the formation of the first contact hole structure 151 in the dielectric layer 140 as an example, this step can be implemented through photolithography and deposition processes. Specifically, a photoresist mask layer can be formed on the dielectric layer 140. The photoresist mask layer is patterned through exposure, development, and other processes to form a patterned mask layer for defining the first contact hole to be formed. Then, the first dielectric layer 131 is etched using the patterned mask layer to form the first contact hole.

[0095] Then, a metal material may be filled in the first contact hole to form a first contact hole structure 151. Any suitable metal material may be selected, including but not limited to at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al. Preferably, the metal material filled in the first contact hole includes W.

[0096] The specific process of forming the second contact hole structure 152 in the dielectric layer 150 can refer to the above description of forming the first contact hole structure 151 in the dielectric layer 140, and will not be repeated here. Of course, it is understood that the first contact hole structure 151 and the second contact hole structure 152 can be formed separately or simultaneously, and this is not limited to this.

[0097] Next, step six is ​​performed to form a first test terminal 161 and a second test terminal 162 . The first test terminal 161 is connected to the first contact hole structure 151 , and the second test terminal 162 is connected to the second contact hole structure 152 .

[0098] Taking the formation of the first test terminal 161 at one end of the first contact hole structure 151 as an example, this step can be implemented through photolithography and deposition processes. Specifically, a photoresist mask layer can be first formed, and then patterned through exposure, development, and other processes to form a patterned mask layer for defining the groove to be formed. Then, etching is performed using the patterned mask layer to form the groove.

[0099] Afterwards, a metal material may be filled into the groove to form the first test terminal 161. Any suitable metal material may be selected, including but not limited to at least one of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, Sn, W, and Al. Preferably, the metal material filled into the groove includes Al.

[0100] The specific process of forming the second test terminal 162 can refer to the description of forming the first test terminal 161 above, and will not be repeated here. Of course, it is understood that the first test terminal 161 and the second test terminal 162 can be formed separately or simultaneously, and this is not limited.

[0101] It is worth mentioning that the order of the above steps is only an example. Under the premise of no conflict, the order of the above steps can also be swapped or performed alternately.

[0102] This concludes the introduction to the key manufacturing method of the contact hole test structure of the present invention. The production of a complete device still requires other preceding steps, intermediate steps, or subsequent steps, which will not be detailed here.

[0103] In summary, the manufacturing method of the contact hole test structure of the present invention forms a first well region 121 and a second well region 122 on the substrate 110, and forms a second metal silicide layer 152 on the surface of the second well region 122, forms a first metal silicide layer 151 on a portion of the surface of the first well region, and forms a first contact hole structure 151 electrically connected to the first metal silicide layer 151 and a second contact hole structure 152 electrically connected to the second metal silicide layer 152 in the dielectric layer 140, so that when the electrical performance of the first contact hole structure 151 and the second contact hole structure 152 are tested through the first test end 161 and the second test end 162, it is possible to determine whether the contact hole has a through-hole phenomenon through the obtained electrical performance test data, which saves time and effort.

[0104] Moreover, the numerical value of the electrical performance test data can be used to further determine the depth of the contact hole to indicate the risk of leakage.

[0105] In addition, when the contact hole is etched through, the affected range can be locked through the full image of the wafer acceptability test, achieving large-scale inspection with high coverage.

[0106] Example 4

[0107] According to another aspect of the present application, a method for detecting over-etching of a contact hole is provided, comprising:

[0108] Performing an electrical performance test through the first test end 161 and the second test end 162 of the contact hole test structure to obtain electrical performance test data;

[0109] Confirm whether the contact hole in the contact hole test structure is etched through based on the electrical performance test data.

[0110] Specifically, the first test end 161 and the second test end 162 of the contact hole test structure can be connected to the electrical performance test equipment, and then the electrical performance test can be performed by the electrical performance test equipment to obtain electrical performance test data. Afterwards, it can be determined whether the contact hole has a through-hole phenomenon based on the obtained electrical performance test data, which saves time and effort.

[0111] Moreover, when there is a penetration in the contact hole, the penetration depth of the contact hole can be further determined by the numerical value of the electrical performance test data to indicate the leakage risk.

[0112] In some embodiments, the electrical performance test may include measuring leakage, measuring BV, etc., which is not limited.

[0113] The present invention has been described through the above-described embodiments. However, it should be understood that the above-described embodiments are for illustrative and illustrative purposes only and are not intended to limit the present invention to the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments and that various variations and modifications may be made based on the teachings of the present invention, all of which fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A contact hole test structure, characterized in that: The contact hole test structure includes: substrate; a first well region of a first conductivity type located in the substrate, and a second well region of a second conductivity type located in the first well region; a second metal silicide layer located on a surface of the second well region and a first metal silicide layer located on a portion of a surface of the first well region, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other; a dielectric layer located on the first metal silicide layer and the second metal silicide layer, and a first contact hole structure and a second contact hole structure located in the dielectric layer, wherein the first contact hole structure is electrically connected to the first metal silicide layer, and the second contact hole structure is electrically connected to the second metal silicide layer; A first test end and a second test end, wherein the first test end is electrically connected to the first contact hole structure, and the second test end is electrically connected to the second contact hole structure.

2. The contact hole test structure according to claim 1, wherein: A plurality of second contact hole structures arranged at intervals are provided in the dielectric layer, and the plurality of second contact hole structures are electrically connected to the same second test end.

3. The contact hole test structure according to claim 1, wherein: The first well region is a p-type well region, and the second well region is an n-type well region; or, The first well region is an n-type well region, and the second well region is a p-type well region.

4. The contact hole test structure according to claim 1, wherein: The metal silicide includes cobalt silicide.

5. The contact hole test structure according to claim 1, wherein: The contact hole test structure further includes: A gate structure is provided in the dielectric layer.

6. A semiconductor device structure, characterized in that: The semiconductor device structure comprises at least one contact hole test structure according to any one of claims 1 to 5, wherein the contact hole test structure is formed in a dicing street of the semiconductor device structure.

7. The semiconductor device structure according to claim 6, wherein: The size of the contact hole structure in the contact hole test structure is consistent with the size of the contact hole structure in the semiconductor device between the dicing streets.

8. A method for manufacturing a contact hole test structure, characterized in that: The manufacturing method comprises: providing a substrate; forming a first well region having a first conductivity type in the substrate, and forming a second well region having a second conductivity type in the first well region; forming a second metal silicide layer on a surface of the second well region, and forming a first metal silicide layer on a portion of a surface of the first well region, wherein the first metal silicide layer and the second metal silicide layer are spaced apart from each other; forming a dielectric layer on the first metal silicide layer and the second metal silicide layer; forming a first contact hole structure and a second contact hole structure in the dielectric layer, wherein the first contact hole structure is electrically connected to the first metal silicide layer, and the second contact hole structure is electrically connected to the second metal silicide layer; A first test end and a second test end are formed, wherein the first test end is connected to the first contact hole structure, and the second test end is connected to the second contact hole structure.

9. A method for detecting over-etching of contact holes, characterized in that: The method comprises: Performing an electrical performance test through the first test end and the second test end of the contact hole test structure according to any one of claims 1 to 5 to obtain electrical performance test data; It is determined whether the contact hole in the contact hole test structure is etched through according to the electrical performance test data.

10. The method for detecting over-etching of contact holes according to claim 9, wherein: The method further comprises: When the contact hole is etched through, the etch depth of the contact hole is determined according to the electrical performance test data.

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