semiconductor devices

Abstract

A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first vertical MOS transistor formed in a first region of the semiconductor layer, and a second vertical MOS transistor formed in a second region adjacent to the first region in a planar view of the semiconductor layer. In a planar view, the first region and the second region are one side and the other side that divide the semiconductor layer into two equal halves in terms of area. A first source electrode and a first source pad, as well as a first gate electrode and a first gate pad, of the first vertical MOS transistor are formed in the first region. A second source electrode and a second source pad, as well as a second gate electrode and a second gate pad, of the second vertical MOS transistor are formed in the second region. The shapes of the first source electrode and the second source electrode are not point-symmetrical about the center of the semiconductor layer, and the shapes of the first source electrode and the second source electrode are not line-symmetrical about the boundary between the first region and the second region as the axis of symmetry.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 202380011458.4 filed on April 26, 2023 and invention name “Semiconductor Device”. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly to a chip-scale package type semiconductor device. Background Art

[0003] To protect lithium-ion batteries from overcharge and / or overdischarge, a dual-structure vertical MOS transistor is used, capable of controlling bidirectional conduction using a single chip. Patent Documents 1 and 2 disclose the structure of a dual-structure vertical MOS transistor, showing a structure in which the two vertical MOS transistors included in a single chip are arranged in a line-symmetrical or point-symmetrical manner in plan view.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-368217

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2002-368219 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] There is a demand for improved switching responsiveness while maintaining ESD (Electro Static Discharge) resistance in dual-structure vertical MOS transistors capable of controlling bidirectional conduction used to protect lithium-ion batteries from overcharge and / or overdischarge.

[0010] Means used to solve problems

[0011] In order to solve the above-mentioned problems, the semiconductor device disclosed in the present invention is a chip-scale package type semiconductor device that can be mounted face-down, and is characterized in that it comprises: a semiconductor substrate; a semiconductor layer formed on the above-mentioned semiconductor substrate; a first vertical MOS transistor formed in a first region of the above-mentioned semiconductor layer, having a plurality of first gate trenches; a second vertical MOS transistor formed in a second region adjacent to the above-mentioned first region in a plan view of the above-mentioned semiconductor layer, having a plurality of second gate trenches; and a metal layer formed in contact with the back surface of the above-mentioned semiconductor substrate; the above-mentioned semiconductor substrate is a common drain region of the above-mentioned first vertical MOS transistor and the above-mentioned second vertical MOS transistor; in the above-mentioned plan view, the above-mentioned first region and the above-mentioned second region are One side and the other side of the semiconductor layer are divided into two equal parts in terms of area; in the above-mentioned plan view, the first source electrode and the first source pad, as well as the first gate electrode and the first gate pad of the above-mentioned first vertical MOS transistor are formed in the above-mentioned first region; in the above-mentioned plan view, the second source electrode and the second source pad, as well as the second gate electrode and the second gate pad of the above-mentioned second vertical MOS transistor are formed in the above-mentioned second region; in the above-mentioned plan view, the shape of the above-mentioned first source electrode and the shape of the above-mentioned second source electrode are not in a point-symmetrical relationship with the center of the above-mentioned semiconductor layer as the center of symmetry; the shape of the above-mentioned first source electrode and the shape of the above-mentioned second source electrode are not in a line-symmetrical relationship with the boundary line between the above-mentioned first region and the above-mentioned second region as the axis of symmetry.

[0012] According to the above structure, in a dual-structure vertical MOS transistor capable of controlling bidirectional conduction, the switching responsiveness can be improved in one vertical MOS transistor, the ESD resistance can be improved in the other vertical MOS transistor, and the first vertical MOS transistor and the second vertical MOS transistor can be distinguished relatively easily from the surface side (pad surface side).

[0013] Furthermore, the semiconductor device disclosed herein is a chip-scale package type semiconductor device capable of face-down mounting, characterized in that it comprises: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first vertical MOS transistor formed in a first region of the semiconductor layer and having a plurality of first gate trenches; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer and having a plurality of second gate trenches; and a metal layer formed in contact with the back surface of the semiconductor substrate; the semiconductor substrate being a common drain region for the first vertical MOS transistor and the second vertical MOS transistor; in the plan view, the first region and the second region are one side and the other side that divide the semiconductor layer into two equal halves in terms of area; In the above-mentioned plan view, the first source electrode and one or more first source pads, as well as the first gate electrode and the first gate pad of the above-mentioned first vertical MOS transistor are formed in the above-mentioned first region; in the above-mentioned plan view, the second source electrode and one or more second source pads, as well as the second gate electrode and the second gate pad of the above-mentioned second vertical MOS transistor are formed in the above-mentioned second region; in the above-mentioned plan view, the shapes of the above-mentioned one or more first source pads and the shapes of the above-mentioned one or more second source pads are not in a point-symmetrical relationship with the center of the above-mentioned semiconductor layer as the center of symmetry; the shapes of the above-mentioned one or more first source pads and the shapes of the above-mentioned one or more second source pads are not in a line-symmetrical relationship with the boundary line between the above-mentioned first region and the above-mentioned second region as the axis of symmetry.

[0014] According to the above structure, in a dual-structure vertical MOS transistor capable of controlling bidirectional conduction, the bias occurring with respect to bidirectional conduction can be suppressed, and the first vertical MOS transistor and the second vertical MOS transistor can be distinguished relatively easily from the surface side (pad surface side).

[0015] Effects of the Invention

[0016] According to the present disclosure, in a dual-structure vertical MOS transistor capable of controlling bidirectional conduction, the first vertical MOS transistor and the second vertical MOS transistor can be relatively easily distinguished from the front surface side (pad side). BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0018] Figure 2A This is a schematic plan view showing an example of the structure of a semiconductor device according to a typical example of the first embodiment.

[0019] Figure 2BThis is a schematic cross-sectional view showing the main current flowing in the semiconductor device according to the first embodiment.

[0020] Figure 3A This is a schematic plan view showing an example of the structure of a semiconductor device according to a typical example of the first embodiment.

[0021] Figure 3B This is a schematic plan view showing an example of the structure of a semiconductor device according to a typical example of the first embodiment.

[0022] Figure 4A This is a schematic plan view of a rough unit structure of the first transistor in the first embodiment.

[0023] Figure 4B This is a schematic perspective view of a rough unit structure of the first transistor in the first embodiment.

[0024] Figure 5A This is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 1.

[0025] Figure 5B This is a schematic plan view showing an example of the structure of a semiconductor device according to Modification 1 of Embodiment 1.

[0026] Figure 6 This is a schematic plan view showing an example of the structure of a semiconductor device according to a second modification of the first embodiment.

[0027] Figure 7A This is a schematic plan view showing an example of the structure of a semiconductor device according to a third modification of the first embodiment.

[0028] Figure 7B This is a schematic plan view showing an example of the structure of a semiconductor device according to a third modification of the first embodiment.

[0029] Figure 8 It is a schematic plan view showing an example of the structure of a semiconductor device according to the second embodiment.

[0030] Figure 9A It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment.

[0031] Figure 9B It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment.

[0032] Figure 9C It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment.

[0033] Figure 9D It is a schematic plan view showing the structure of a semiconductor device according to a comparative example of the third embodiment.

[0034] Figure 9E It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment.

[0035] Figure 9F It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment.

[0036] Figure 9G It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment.

[0037] Figure 9H It is a schematic plan view showing an example of the structure of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0038] Below, a specific example of a semiconductor device according to a technical solution of the present disclosure is described with reference to the accompanying drawings. The embodiments shown here each represent a specific example of the present disclosure. Therefore, the numerical values, shapes, components, configurations of components, and connection forms shown in the following embodiments are provided as examples and are not intended to limit the present disclosure. In addition, each figure is a schematic diagram and is not necessarily a strict illustration. In each figure, substantially the same structure is given the same reference numeral, and repeated descriptions are omitted or simplified.

[0039] (Implementation 1)

[0040] [1. Structure of Semiconductor Device]

[0041] Figure 1 It is a cross-sectional view showing an example of the structure of a semiconductor device. Figure 2A This is a plan view of a typical example. The semiconductor device is rectangular, and its size and shape are examples. Furthermore, the size, shape, and placement of the pads are also examples. Figure 2B This is a cross-sectional view schematically showing the main current flowing in the semiconductor device. Figure 1 and Figure 2B It is along Figure 2A The cross section when the shape is cut II-I. In addition, in the present disclosure, the term "rectangular" is defined to exclude squares. In the case where both a rectangular shape and a square shape are possible, the term "rectangular" is used to distinguish them.

[0042] like Figure 1 and Figure 2A As shown, the semiconductor device 1 has a semiconductor substrate 32, a metal layer 30, a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 within a low-concentration impurity layer 33 formed on the semiconductor substrate 32, and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 within the low-concentration impurity layer 33.

[0043] Here, as Figure 2A As shown, the first region A1 and the second region A2 are adjacent to each other in a plan view of the semiconductor layer 40, and are one side and the other side that divide the semiconductor layer 40 into two equal parts in terms of area. Figure 2A In the embodiment 1, the imaginary boundary line 90 between the first region A1 and the second region A2 is represented by a dotted line (for ease of understanding, the dotted line representing the boundary line 90 is extended to the outside of the semiconductor layer 40). In the first embodiment, the boundary line 90 is a straight line parallel to the long side of the semiconductor layer 40 in a plan view. Figure 2A and the following Figure 5A In the figure, the dotted lines representing the first area A1 and the second area A2 are not strictly aligned with the semiconductor layer 40 and the boundary line 90 for ease of understanding, but are represented on the inside with a slight blank space. However, in essence, the outer periphery of the first area A1 and the outer periphery of the second area A2 are aligned with the outer periphery of the semiconductor layer 40 and the boundary line 90.

[0044] In this disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as the semiconductor layer 40. The semiconductor substrate 32 is disposed on the back side of the semiconductor layer 40 and is composed of first-conductivity-type silicon containing first-conductivity-type impurities. The low-concentration impurity layer 33 is disposed on the front side of the semiconductor layer 40 and is formed in contact with the semiconductor substrate 32. It contains first-conductivity-type impurities at a lower concentration than the first-conductivity-type impurities of the semiconductor substrate 32 and is of the first-conductivity-type.

[0045] The low-concentration impurity layer 33 can be formed, for example, by epitaxial growth on the semiconductor substrate 32. The low-concentration impurity layer 33 is also a drift layer common to the transistor 10 and the transistor 20 and is sometimes referred to as a drift layer in this specification.

[0046] The metal layer 30 is formed in contact with the back side of the semiconductor layer 40 (semiconductor substrate 32) and is composed of silver (Ag) or copper (Cu). The metal layer 30 may also contain trace amounts of elements other than metals that have been introduced as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 30 may or may not be formed entirely on the back side of the semiconductor layer 40 (semiconductor substrate 32).

[0047] like Figure 1 and Figure 2AAs shown, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed in the first region A1 of the low-concentration impurity layer 33. A first source region 14 containing impurities of the first conductivity type, a first gate conductor 15, and a first gate insulating film 16 are formed in the first body region 18. The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 formed from the upper surface of the semiconductor layer 40 through the first source region 14 and the first body region 18 to a depth extending to a portion of the low-concentration impurity layer 33. The first gate conductor 15 is formed on the first gate insulating film 16 within the first gate trenches 17.

[0048] First source electrode 11 includes portion 12 and portion 13 . Portion 12 is connected to first source region 14 and first body region 18 via portion 13 . First gate conductor 15 is a buried gate electrode embedded in semiconductor layer 40 and electrically connected to first gate pad 119 .

[0049] Portion 12 of the first source electrode 11 is a layer that is bonded to solder during reflow in face-down mounting. As a non-limiting example, it can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium. The surface of portion 12 can be plated with gold or other materials.

[0050] The portion 13 of the first source electrode 11 is a layer connecting the portion 12 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0051] A second body region 28 containing impurities of the second conductivity type is formed in the second region A2 of the low-concentration impurity layer 33. A second source region 24 containing impurities of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed in the second body region 28. The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 formed from the upper surface of the semiconductor layer 40 to a depth extending through the second source region 24 and the second body region 28 to a portion of the low-concentration impurity layer 33. The second gate conductor 25 is formed on the second gate insulating film 26 within the second gate trenches 27.

[0052] Second source electrode 21 includes portion 22 and portion 23 . Portion 22 is connected to second source region 24 and second body region 28 via portion 23 . Second gate conductor 25 is a buried gate electrode embedded in semiconductor layer 40 and electrically connected to second gate pad 129 .

[0053] Portion 22 of the second source electrode 21 is a layer that is bonded to solder during reflow in face-down mounting. As a non-limiting example, it can be made of a metal material containing one or more of nickel, titanium, tungsten, and palladium. The surface of portion 22 can be plated with gold or other materials.

[0054] The portion 23 of the second source electrode 21 is a layer connecting the portion 22 and the semiconductor layer 40 , and may be made of a metal material including one or more of aluminum, copper, gold, and silver, as a non-limiting example.

[0055] With the above-described structures of transistors 10 and 20, semiconductor substrate 32 functions as a common drain region, commonizing the first drain region of transistor 10 and the second drain region of transistor 20. A portion of the low-concentration impurity layer 33 that contacts semiconductor substrate 32 may also function as a common drain region. Furthermore, metal layer 30 functions as a common drain electrode, commonizing the drain electrodes of transistors 10 and 20.

[0056] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 having an opening, and a portion 13 of the first source electrode 11 is provided, connected to the first source region 14 via the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode are covered by a passivation layer 35 having an opening, and a portion 12 is provided, connected to the portion 13 of the first source electrode via the opening of the passivation layer 35.

[0057] The second body region 28 is covered by an interlayer insulating layer 34 having an opening, and is provided with a portion 23 of the second source electrode 21 connected to the second source region 24 via the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode are covered by a passivation layer 35 having an opening, and is provided with a portion 22 connected to the portion 23 of the second source electrode via the opening of the passivation layer 35.

[0058] Therefore, the plurality of first source pads 111 and the plurality of second source pads 121 refer to regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, so-called terminal portions. Similarly, the one or more first gate pads 119 and the one or more second gate pads 129 refer to the first gate electrode 19 (on the Figure 1 、 Figure 2A 、 Figure 2B Not shown in the figure) and the second gate electrode 29 (in Figure 1 、 Figure 2A 、 Figure 2B (not shown) An area partially exposed on the surface of the semiconductor device 1, a so-called terminal portion.

[0059] In the semiconductor device 1, for example, the first conductivity type may be set to N type, the second conductivity type may be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be N type semiconductors, and the first body region 18 and the second body region 28 may be P type semiconductors.

[0060] In addition, in the semiconductor device 1, for example, the first conductivity type may be set to P type, the second conductivity type may be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32 and the low-concentration impurity layer 33 may be P type semiconductors, and the first body region 18 and the second body region 28 may be N type semiconductors.

[0061] Figure 3A This is a plan view showing a typical example of the shape of the semiconductor layer 40 (low-concentration impurity layer 33) in a plan view, including the first body region 18 and the second body region 28, the first active region 112 and the second active region 122, which are components of the semiconductor device 1. Figure 3A and the following Figure 3B 、 Figure 5B 、 Figure 6 、 Figure 7B In order to make the structure of the upper surface of the semiconductor layer 40, which is actually not visually recognizable, easier to understand, the passivation layer 35, the first source electrode 11, the second source electrode 21, and the interlayer insulating layer 34 are omitted and shown as if they were transparent. In addition, the first source region 14 and the second source region 24 are also omitted from illustration.

[0062] The first active region 112 is the minimum area encompassing the entire portion where a conducting channel is formed when a voltage above the threshold is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10. The portion where the conducting channel is formed is the portion of each of the plurality of first gate trenches 17 adjacent to the first source region 14. In a plan view of the semiconductor layer 40, the first active region 112 is contained within the first body region 18.

[0063] The second active region 122 is the minimum area encompassing the entire portion where a conductive channel is formed when a voltage above the threshold is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20. The portion where the conductive channel is formed is the portion of each of the plurality of second gate trenches 27 adjacent to the second source region 24. In a plan view of the semiconductor layer 40, the second active region 122 is contained within the second body region 28.

[0064] In the first region A1, the region outside the first active region 112 and surrounding the first active region 112 is referred to as the first peripheral region 113, and in the second region A2, the region outside the second active region 122 and surrounding the second active region 122 is referred to as the second peripheral region 123. Figure 3B As shown, the first peripheral region 113 includes a first gate electrode 19 and a first gate wiring (first gate runner) 114 that is directly connected to the first gate electrode 19 and surrounds the first active region 112. The second peripheral region 123 includes a second gate electrode 29 and a second gate wiring (second gate runner) 124 that is connected in series to the second gate electrode 29 via a second gate resistor 125 and surrounds the second active region 122.

[0065] In addition, if Figure 3B As shown in FIG, a first gate resistor 115 may be provided between the first gate electrode 19 and the first gate wiring (first gate flow channel) 114. However, it should be noted that the first gate electrode 19 and the first gate wiring (first gate flow channel) 114 are directly connected, not electrically connected via the first gate resistor 115. Therefore, the first gate wiring (first gate flow channel) 114 and the second gate wiring (second gate flow channel) 124 are not symmetrical in shape in a plan view and are not arranged symmetrically.

[0066] The gate resistor element is provided in anticipation of a protective function, which prevents damage to the transistor when an excessive voltage is applied to the gate electrode. In other words, it is provided to improve ESD resistance. Even if the first gate resistor element 115 is provided as in the first embodiment, it will not serve a protective function in the transistor 10 unless it is electrically connected between the first gate electrode 19 and the first gate wiring (first gate flow path) 114. Alternatively, the first gate resistor element 115 and the second gate resistor element 125 may be polysilicon implanted with a dopant and formed simultaneously with the first gate conductor 15 and the second gate conductor 25.

[0067] The first gate wiring (first gate channel) 114 and the second gate wiring (second gate channel) 124 are formed of polysilicon injected with dopants or the same metal material as the first gate electrode 19 and the second gate electrode 29, and are respectively connected to the first gate conductor 15 and the second gate conductor 25.

[0068] In the first peripheral region 113 , a first EQR (EQui Potential Ring) 116 may be provided on the outer side of the first gate wiring (first gate channel) 114 . Similarly, in the second peripheral region 123 , a second EQR 126 may be provided on the outer side of the second gate wiring (second gate channel) 124 .

[0069] The first EQR 116 is provided at the outermost periphery of the first area A1 so as to surround the first active area 112, and the second EQR 126 is provided at the outermost periphery of the second area A2 so as to surround the second active area 122. The first EQR 116 and the second EQR 126 are each formed of a metal material, are not connected to the first gate electrode 19 and the second gate electrode 29, or the first source electrode 11 and the second source electrode 21, and are formed to have the same potential as the semiconductor substrate 32. The first EQR 116 and the second EQR 126 may be in common at the boundary between the first area A1 and the second area A2.

[0070] The first EQR 116 is provided for the transistor 10 to prevent leakage current from flowing between the outside and the first active region 112 . The second EQR 126 is provided for the transistor 20 to prevent leakage current from flowing between the outside and the second active region 122 .

[0071] exist Figure 3B Schematically illustrating the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25). In the first embodiment, both the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) extend in a direction parallel to the short side of the semiconductor device 1 in a plan view.

[0072] exist Figure 3B , the circular marks at both ends of the black line representing the first gate trench 17 (first gate conductor 15) schematically indicate that the first gate trench 17 (first gate conductor 15) is connected to the first gate wiring 114. Similarly, the circular marks at both ends of the black line representing the second gate trench 27 (second gate conductor 25) schematically indicate that the second gate trench 27 (second gate conductor 25) is connected to the second gate wiring 124.

[0073] For simplicity, Figure 3B and the following Figure 5B 、 Figure 6 、 Figure 7B, only a portion of the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are shown. In reality, the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are repeatedly formed throughout the entire surface of the first active region 112 and the second active region 122, respectively.

[0074] [2. Operation of a Dual-Structure Vertical MOS Transistor]

[0075] In the following description, the on-state operation of the semiconductor device 1 is described assuming that the transistor 10 and the transistor 20 are so-called N-channel transistors having N-type as a first conductivity type and P-type as a second conductivity type.

[0076] Figure 4A and Figure 4B 1 and 2 are a plan view and a perspective view of a rough unit structure of a transistor 10 (or transistor 20) repeatedly formed in the X direction and the Y direction of the semiconductor device 1. Figure 4A and Figure 4B In the figure, for easy understanding, the semiconductor substrate 32 and the metal layer 30 are not shown, and the passivation layer 35, the first source electrode 11 (or the second source electrode 21), and the interlayer insulating layer 34 are not shown.

[0077] The Y direction is parallel to the upper surface of the semiconductor layer 40 and is the direction in which the first gate trench 17 extends. Furthermore, the X direction is parallel to the upper surface of the semiconductor layer 40 and perpendicular to the Y direction. The Z direction is perpendicular to both the X and Y directions and indicates the height direction of the semiconductor device. In this disclosure, the Y direction may be referred to as the first direction, the X direction as the second direction, and the Z direction as the third direction.

[0078] like Figure 4A and Figure 4B As shown, transistor 10 includes a first connecting portion 18a that electrically connects first body region 18 to first source electrode 11. First connecting portion 18a is a region of first body region 18 where first source region 14 is not formed, and contains the same second conductivity type impurities as first body region 18. First source regions 14 and first connecting portion 18a are alternately and periodically arranged along the Y direction. The same applies to transistor 20.

[0079] In the semiconductor device 1, when a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage above the threshold is applied to the second gate electrode 29 (second gate conductor 25) relative to the second source electrode 21, a conductive channel is formed near the second gate insulating film 26 in the second body region 28. As a result, the main current flows along the path: first source electrode 11 - first connecting portion 18a - first body region 18 - low-concentration impurity layer 33 - semiconductor substrate 32 - metal layer 30 - semiconductor substrate 32 - low-concentration impurity layer 33 - conductive channel formed in the second body region 28 - second source region 24 - second source electrode 21, putting the semiconductor device 1 into an on state. Furthermore, a PN junction forms at the interface between the second body region 28 and the low-concentration impurity layer 33 in this conductive path, functioning as a body diode. Furthermore, since the main current flows through the metal layer 30 , by making the metal layer 30 thicker, the cross-sectional area of ​​the main current path is increased, and the on-resistance of the semiconductor device 1 can be reduced.

[0080] Similarly, in semiconductor device 1, when a high voltage is applied to second source electrode 21 and a low voltage is applied to first source electrode 11, and a voltage above the threshold is applied to first gate electrode 19 (first gate conductor 15) relative to first source electrode 11, a conductive channel is formed near first gate insulating film 16 in first body region 18. As a result, the main current flows along the path: second source electrode 21 - second connecting portion 28a - second body region 28 - low-concentration impurity layer 33 - semiconductor substrate 32 - metal layer 30 - semiconductor substrate 32 - low-concentration impurity layer 33 - conductive channel formed in first body region 18 - first source region 14 - first source electrode 11, putting semiconductor device 1 into an on state. Furthermore, a PN junction forms at the interface between first body region 18 and low-concentration impurity layer 33 in this conductive path, functioning as a body diode.

[0081] [3. Effects of the Semiconductor Device of the First Embodiment]

[0082] In the following description, the effects achieved by the semiconductor device 1 according to the first embodiment will be described.

[0083] like Figure 2A As shown, the semiconductor device 1 shown in the typical example of the first embodiment has a rectangular shape in plan view, and the transistors 10 and 20 are each rectangular. Furthermore, the transistor 10 is arranged so that the length of the long side of the semiconductor layer 40 in plan view coincides with the length of the longest side among the sides forming the outer periphery of the first area A1. Similarly, the transistor 20 is arranged so that the length of the long side of the semiconductor layer 40 in plan view coincides with the length of the longest side among the sides forming the outer periphery of the second area A2.

[0084] In addition, if Figure 3B As shown, the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) extend in a direction parallel to the short side of the semiconductor layer 40 in a plan view. In other words, both transistors 10 and 20 are formed so that the finger length is as short as possible, thereby reducing the gate resistance of each transistor 10 and transistor 20.

[0085] Furthermore, in the transistor 10 , the first gate electrode 19 and the first gate wiring 114 are directly connected without interposing the first gate resistor 115 , so that the gate resistance can be further reduced. Therefore, the switching responsiveness of the transistor 10 can be improved.

[0086] In the transistor 20, the second gate electrode 29 and the second gate wiring 124 are connected in series via the second gate resistor 125. Therefore, by appropriately setting the resistivity of the second gate resistor 125, the transistor 20 can be prevented from being damaged by an excessive applied voltage. In other words, this structure can improve ESD resistance.

[0087] In a dual-structure vertical MOS transistor used to protect a lithium-ion battery from overcharge and / or overdischarge, each transistor plays a different role, such as transistor 10 controlling overcharge and transistor 20 controlling overdischarge. Depending on the design of the battery protection circuit, there may be a need to improve the switching responsiveness of only one of the dual-structure vertical MOS transistors. In this case, the semiconductor device 1 of this embodiment 1 can meet the requirement for improved switching responsiveness by simply applying transistor 10 to this application. At the same time, in transistor 20, where improved switching responsiveness is not particularly required, by interposing the second gate resistor 125 between the second gate electrode 29 and the second gate wiring 124, it is possible to prevent damage to transistor 20 due to excessive applied voltage.

[0088] This is achieved by taking into account the respective uses of transistors 10 and 20 in the dual-structure vertical MOS transistor. By creating separate structures for transistors 10 and 20, semiconductor device 1 achieves a balance between switching responsiveness and ESD resistance, which are inherently in a trade-off relationship. Creating separate structures means that transistors 10 and 20 are intentionally formed into an asymmetric structure.

[0089] However, in a dual-structure vertical MOS transistor that is required to control bidirectional conduction, it is undesirable for the total gate width of transistor 10 on one side and transistor 20 to vary. Therefore, it is preferable that the asymmetric structure provided in transistors 10 and 20 is formed only in the first peripheral region 113 and the second peripheral region 123. Furthermore, it is preferable that the structure provided in the first active region 112 and the second active region 122 be symmetrical.

[0090] That is, the semiconductor device 1 disclosed in the present invention is a chip-scale package type semiconductor device 1 that can be mounted face-down, and is characterized by comprising: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10, which is formed in a first region A1 of the semiconductor layer 40 when the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40, and has a plurality of first gate trenches 17; a second vertical MOS transistor 20, which is formed in a second region A2 adjacent to the first region A1 in a plan view of the semiconductor layer 40, and has a plurality of second gate trenches 27; and a metal layer 30 formed in contact with the back surface of the semiconductor substrate 32; the semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20; in a plan view, the semiconductor layer 40 is rectangular, and the first region A1 and the second region A2 are such that the length of the long side of the semiconductor layer 40 is equal to the length of the side forming the outer periphery of the first region A1. The semiconductor layer 40 is divided into two equal parts in area in a manner such that the length of the longest side is consistent; in the first area A1, there are a first gate electrode 19 for controlling the conduction of the first vertical MOS transistor 10, and a first gate wiring 114 connected to the first gate electrode 19; in the second area A2, there are a second gate electrode 29 for controlling the conduction of the second vertical MOS transistor 20, and a second gate wiring 124 connected to the second gate electrode 29; in a plan view, the shape formed by the first gate electrode 19 and the first gate wiring 114 and the shape formed by the second gate electrode 29 and the second gate wiring 124 are not in a line symmetric relationship with the boundary line 90 between the first area A1 and the second area A2 as the axis of symmetry; in a plan view, the shape formed by the first gate electrode 19 and the first gate wiring 114 and the shape formed by the second gate electrode 29 and the second gate wiring 124 are not in a point symmetric relationship with the center of the semiconductor layer 40 as the center of symmetry.

[0091] The boundary line 90 between the transistors 10 and 20 can be understood as an imaginary line extending along the center of the gap between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21 in a plan view of the semiconductor layer 40. Alternatively, it can be understood as an EQR (a portion common to the first EQR 116 and the second EQR 126) that is sometimes provided at this center. Although it has a finite width, it can be understood as the gap itself. Even in the case of this gap, it can be recognized as a line with the naked eye or at low magnification.

[0092] In addition, the center of the semiconductor layer 40 refers to an intersection of two diagonal lines of the semiconductor layer 40 which is rectangular in a plan view.

[0093] In the first embodiment, the shape formed by the first gate electrode 19 and the first gate wiring 114, and the shape formed by the second gate electrode 29 and the second gate wiring 124, in plan view, are asymmetrical because one is directly connected and the other is not directly connected. Asymmetry means that, in plan view, the relationship is not line-symmetrical with the boundary line 90 between the first area A1 and the second area A2 as the axis of symmetry, and the relationship is not point-symmetrical with the center of the semiconductor layer 40 as the center of symmetry.

[0094] In the structure of this first embodiment, in addition to improving switching responsiveness through transistor 10 on one side and improving ESD resistance through transistor 20 on the other side, there are two other advantages. First, because the asymmetric structure is provided in the first peripheral region 113 and the second peripheral region 123, the total gate width can be made the same in transistor 10 on one side and transistor 20 on the other side. Alternatively, the structure provided in the first active region 112 and the second active region 122 can be made symmetrical. Therefore, in the bidirectional conduction of the dual-structure vertical MOS transistor, bias depending on the conduction direction can be prevented.

[0095] Another advantage is that the transistor 10 can be distinguished from the transistor 20 by visual inspection or observation with a low-magnification microscope. In conventional dual-structure vertical MOS transistors, the transistors 10 and 20 are typically symmetrical, making it difficult to distinguish the transistors 10 from the surface (pad side) in the event of a malfunction or other failure. In the present disclosure, by creating a slight difference that allows the transistors 10 and 20 to be distinguished, distinguishing them from the pad side becomes easier.

[0096] exist Figure 5A 、 Figure 5B 1 shows a semiconductor device 1 according to a first modification of the first embodiment. Figure 5A 、 Figure 5BIn the modification example 1 shown, Figure 3A 、 Figure 3B Compared to the typical example of the first embodiment shown, the shapes of the first area A1 and the second area A2 in plan view are different. The characteristic is that the boundary line 90 between the first area A1 and the second area A2 is not a straight line but has a meandering shape.

[0097] like Figure 5A As shown, in Modification 1 of Embodiment 1, the first region A1 and the second region A2 are polygonal. Therefore, the shapes of transistor 10 and transistor 20 are also polygonal in plan view. However, in Modification 1, the same point remains: in plan view, the semiconductor layer 40 is rectangular, and the first region A1 and the second region A2 are formed by bisecting the semiconductor layer 40 in area so that the length of the long side of the semiconductor layer 40 is consistent with the length of the longest side of the sides forming the periphery of the first region A1. Therefore, even with the structure of Modification 1, the effects of the present disclosure can be achieved.

[0098] In addition, along Figure 5A The cut surface of I-I cutting is Figure 1 are equal.

[0099] In a typical example of this embodiment 1 ( Figure 3A 、 Figure 3B ), in a plan view, the first region A1 and the second region A2 are each rectangular. Furthermore, the plurality of first gate trenches 17 (first gate conductor 15) extend parallel to the short sides of the semiconductor layer 40 and, in a plan view, parallel to the short sides of the first region A1 (i.e., transistor 10). Consequently, at least in transistor 10, the interdigitation length is minimized, which contributes to minimizing gate resistance.

[0100] In addition, when the semiconductor layer 40 is square, since there is no distinction between long sides and short sides in the semiconductor layer 40, any side can be understood as the long side. Figure 3A As shown, by arranging the transistors 10 and 20 so that the boundary line 90 between the transistors 10 and 20 is a straight line, the transistors 10 and 20 become rectangular in plan view, thereby achieving the effects of the present disclosure.

[0101] Furthermore, in order to reduce the gate resistance in the transistor 10, the first gate trench 17 (first gate conductor 15) is preferably connected to the first gate wiring 114 at both ends. Therefore, it is preferable that, in a plan view, regardless of whether the semiconductor layer 40 is rectangular or square, the first region A1 and the second region A2 are both rectangular, and among the four sides forming the periphery of the first region A1, the side overlapping the boundary line 90 is set as the first side 301, the side opposite to the first side 301 is set as the second side 302, the side perpendicular to the first side 301 and the second side 302 and opposite to each other is set as the third side 303, and the other side is set as the fourth side 304 (see FIG. Figure 2A ), the first gate wiring 114 is continuously arranged at least along the approximately entire length of the first side 301, the second side 302, and the third side 303, and the plurality of first gate grooves 17 (first gate conductors 15) are arranged so that they have the most connections with the first gate wiring 114 in the portion along the first side 301 and the portion along the second side 302.

[0102] In addition, the approximate total length of each side forming the periphery of the first area A1 refers to the following length: in a plan view, when the first gate wiring 114 has a structure such as the first EQR116 on its outer periphery, the length after deducting the width of the structure, the space required for setting the structure, and the space required for setting the structure and each side forming the periphery of the first area A1 from the length of each side forming the periphery of the first area A1.

[0103] exist Figure 6 1 shows a semiconductor device 1 according to a second modification of the first embodiment. Figure 6 In the modification example 2 shown, Figure 3B Compared to the typical example of the present embodiment 1 shown in FIG, the direction in which the second gate trenches 27 (second gate conductors 25) extend in a plan view is different. The characteristic is that, in a plan view, the plurality of first gate trenches 17 (first gate conductors 15) extend in a direction parallel to the short side of the first area A1, while the plurality of second gate trenches 27 (second gate conductors 25) extend in a direction parallel to the long side of the second area A2. That is, compared to the typical example of the present embodiment 1 ( Figure 3B ), the finger length of transistor 20 is longer than that of transistor 10, and the gate resistance of transistor 20 is further increased compared with the gate resistance of transistor 10.

[0104] In the first embodiment, the switching responsiveness of the transistor 10 is improved and the ESD resistance of the transistor 20 is improved. Therefore, the second modification of the first embodiment ( Figure 6) is more suitable for achieving this purpose. In addition, in the second modification, there is a case where the total gate width cannot be made equal in the transistor 10 and the transistor 20. Figure 6 The cut surface of I-I cutting is Figure 1 are equal.

[0105] As a typical example of this embodiment 1 ( Figure 3B ), in a plan view, the first gate wiring 114 is preferably connected to the first gate electrode 19 in a portion along the third side 303. In the case of such a structure, the potential of the first gate electrode 19 is evenly transmitted to the portions along the first side 301 and the second side 302, respectively, and it is possible to prevent the occurrence of bias in the potential transmission from each end of each first gate conductor 15.

[0106] In contrast, in Figure 7A 、 Figure 7B FIG. 1 shows a semiconductor device 1 according to a third variation of the first embodiment. Figure 7A 、 Figure 7B As shown, the first gate electrode 19 may be connected to the first gate wiring 114 at a portion along the first side 301 or a portion along the second side 302. In such a structure, the potential of the first gate electrode 19 is most rapidly transmitted to each first gate conductor 15 from either the portion along the first side 301 or the portion along the second side 302 connected at both ends thereof, thereby further promoting a reduction in gate resistance.

[0107] In addition, along Figure 7A The cut surface of I-I cutting is Figure 1 are equal.

[0108] In the typical example of the present embodiment 1 described so far ( Figure 3B ) and Modification 1( Figure 5B )、Variant 2( Figure 6 )、Variant 3( Figure 7B ), in a plan view, the first gate electrode 19 is continuous with the first gate wiring 114, the second gate electrode 29 is discontinuous with the second gate wiring 124, and the second gate electrode 29 and the second gate wiring 124 are connected in series via a second gate resistor 125. With such a structure, the switching responsiveness of the transistor 10 on one side can be improved, and the ESD resistance of the transistor 20 on the other side can be improved.

[0109] (Implementation Method 2)

[0110] Hereinafter, a semiconductor device 1A according to a second embodiment, which is partially modified from the semiconductor device 1 according to the first embodiment, will be described. Regarding the semiconductor device 1A according to the second embodiment, the same components as those of the semiconductor device 1 have been assigned the same reference numerals, and detailed descriptions thereof will be omitted. The description will focus on the differences from the semiconductor device 1.

[0111] exist Figure 8 FIG. 1 shows a semiconductor device 1A according to the second embodiment in a plan view. Figure 8 The cut surface of I-I cutting is Figure 1 are equal. In addition, Figure 8 In order to make the structure of the upper surface of the semiconductor layer 40, which is actually not visually recognizable, easier to understand, the passivation layer 35, the first source electrode 11, the second source electrode 21, and the interlayer insulating layer 34 are omitted and shown as if they are transparent. In addition, the first source region 14 and the second source region 24 are also omitted. In addition, for simplicity, Figure 8 , only a portion of the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are shown. In reality, the first gate trench 17 (first gate conductor 15) and the second gate trench 27 (second gate conductor 25) are repeatedly formed throughout the entire surface of the first active region 112A and the second active region 122, respectively.

[0112] and Figure 3B Compared with the first vertical MOS transistor 10 shown as a typical example of the first embodiment, the first vertical MOS transistor 10A of the second embodiment is as follows. Figure 8 As shown, the first gate electrode 19A is connected in series to the first gate wiring 114A via the first gate resistor 115. Therefore, in the second embodiment, the first vertical MOS transistor 10A has a structure capable of improving ESD resistance to a level close to that of the second vertical MOS transistor 20.

[0113] Furthermore, regarding the first vertical MOS transistor 10A, in plan view, the first gate interconnect 114A is continuously provided along substantially the entire length of the first side 301, the second side 302, and the third side 303 of the four sides forming the outer periphery of the first region A1, but is not provided along the portion along the fourth side 304. Furthermore, in plan view, the first gate interconnect 114A includes, in addition to the portion along the third side 303, a portion (hereinafter referred to as the connecting portion 114b) that connects the portion along the first side 301 and the portion along the second side 302 at the shortest possible distance. Therefore, compared to the first active region 112 of the first embodiment, the first active region 112A has a truncated shape at the connecting portion 114b.

[0114] about Figure 8 In the structure of the second embodiment shown, in a plan view, for the shape formed by the first gate electrode 19A and the first gate wiring 114A and the shape formed by the second gate electrode 29 and the second gate wiring 124, only the first gate wiring 114A does not have a portion along the fourth side 304 of the first area A1, or only the first gate wiring 114A has a connecting portion 114b, and they are neither symmetrical in shape nor symmetrically arranged.

[0115] Furthermore, in the first region A1, in order to distinguish the region other than the first active region 112A from the first peripheral region 113A, the connection portion 114b is provided in the first peripheral region 113A. Figure 8 2 shows an example in which only one connection portion 114 b is provided. However, the connection portions 114 b may be provided at a plurality of locations in the first vertical MOS transistor 10A.

[0116] In the case where the connection portion 114b is provided, compared with the typical example of the first embodiment ( Figure 3B ), in the first vertical MOS transistor 10A, the voltage applied to the first gate electrode 19A is easily and quickly transmitted to the entire first gate wiring 114A. Therefore, the gate resistance of the first vertical MOS transistor 10A can be reduced. Consequently, a structure can be provided that improves the switching responsiveness of the first vertical MOS transistor 10A.

[0117] Furthermore, in a plan view, in the first vertical MOS transistor 10A, the first EQR 116A is continuously provided along substantially the entire length of the first side 301, the second side 302, and the third side 303 of the four sides forming the outer periphery of the first region A1, but is not provided along the portion along the fourth side 304. Therefore, in the first vertical MOS transistor 10A, neither the first gate wiring 114A nor the first EQR 116A is provided along the portion along the fourth side 304 in the first region A1. Consequently, the first active region 112A expands toward the portion along the fourth side 304 of the first region A1.

[0118] Since the first active region 112A expands toward the side of the fourth side 304, in a planar view, the first vertical MOS transistor 10A is configured as follows: the distance between the first gate trench 17 closest to the fourth side 304 among the multiple first gate trenches 17 and the fourth side 304 is smaller than the distance between the first gate trench 17 closest to the third side 303 among the multiple first gate trenches 17 and the third side 303.

[0119] With this structure, the reduction in the first active region 112A required to provide the connection portion 114b in the first region A1 can be compensated by expanding the first active region 112A toward the fourth side 304. Preferably, even though their shapes differ, the first active region 112A and the second active region 122 have the same area. Furthermore, preferably, the total gate width of the first vertical MOS transistor 10A and the total gate width of the second vertical MOS transistor 20 are the same. With this structure, the bidirectional conduction of the semiconductor device 1A, which is a dual-structure vertical MOS transistor, can be prevented from being biased between the first vertical MOS transistor 10A and the transistor 20 depending on the direction of conduction.

[0120] Therefore, in the structure of the second embodiment, it is possible to improve the switching responsiveness by the first vertical MOS transistor 10A on one side and improve the ESD resistance by the transistor 20 on the other side without causing bias in the bidirectional conduction. Figure 8 ), the difference in switching responsiveness and ESD resistance between the first vertical MOS transistor 10A and the transistor 20 is greater than that in the structure of the typical example of the first embodiment ( Figure 3B ) becomes smaller.

[0121] (Implementation 3)

[0122] In the first embodiment, the following advantage was discussed: in a dual-structure vertical MOS transistor capable of bidirectional conduction control, one vertical MOS transistor can be distinguished from the other vertical MOS transistor from the front surface side (pad side). In the third embodiment, structural features that specify this advantage are described.

[0123] In other words, in this third embodiment, there is no consideration of improving switching responsiveness with the first vertical MOS transistor and improving ESD resistance with the second vertical MOS transistor. Therefore, there is no need to pay attention to shortening the finger length as in transistor 10 (first vertical MOS transistor 10A) in the first and second embodiments. Therefore, in semiconductor device 1B of this third embodiment, first vertical MOS transistor 10B and second vertical MOS transistor 20B only need to be one side and the other side of the area that divides semiconductor layer 40 into two equal halves.

[0124] The following describes a semiconductor device 1B according to a third embodiment, which is partially modified from the semiconductor device 1 according to the first embodiment. Regarding the semiconductor device 1B of the third embodiment, the same components as those of the semiconductor device 1 are designated by the same reference numerals as those already described, and detailed descriptions thereof are omitted. The description will focus on the differences from the semiconductor device 1.

[0125] exist Figures 9A to 9C and Figures 9E to 9H 1 shows an example of a semiconductor device 1B according to the third embodiment in a plan view. Figure 9D This is a diagram showing a comparative example of the present embodiment 3, which will be described later.

[0126] exist Figure 9B 、 Figure 9C In order to facilitate understanding of the upper surface structure of the semiconductor device 1B, the interlayer insulating layer 34 and the passivation layer 35 that are originally provided are omitted. Figure 9B In the figure, the first source electrode 11B, the second source electrode 21B, the first gate electrode 19B, the first gate wiring 114B, the second gate electrode 29B, the second gate wiring 124B, and the like are omitted.

[0127] exist Figures 9D to 9H In order to easily understand the structure of the upper surface of the semiconductor layer 40, the passivation layer 35 and the interlayer insulating layer 34 are illustrated as if they are transparent, and the shapes of the first source electrode 11B and the second source electrode 21B are illustrated so that the shapes can be clearly visually identified.

[0128] like Figure 9A As shown, the semiconductor device 1B (semiconductor layer 40) is rectangular, which is different from the semiconductor device 1 ( Figure 2A ), the boundary line 90B between the first vertical MOS transistor 10B and the second vertical MOS transistor 20B is a straight line parallel to the short side of the semiconductor layer 40. Furthermore, the first region A1B and the second region A2B are one side and the other side that divide the semiconductor layer 40 into two equal parts in terms of area, and are each rectangular in plan view.

[0129] In addition, Figure 9A In the figure, the dotted lines representing the first area A1B and the second area A2B are not strictly consistent with the semiconductor layer 40 and the boundary line 90B for easy understanding, but are shown on the inside with a slight blank space. However, in fact, the outer periphery of the first area A1B and the outer periphery of the second area A2B are consistent with the outer periphery of the semiconductor layer 40 and the boundary line 90B.

[0130] exist Figure 9B exemplifies the arrangement of the first active region 112B and the first peripheral region 113B, and the second active region 122B and the second peripheral region 123B in the semiconductor device 1B (semiconductor layer 40). Figure 9B Configuration, in Figure 9C, the arrangement of the first gate electrode 19B and the first gate wiring 114B, and the second gate electrode 29B and the second gate wiring 124B in the semiconductor device 1B (semiconductor layer 40) is illustrated. Figure 9C , the configuration of the first source electrode 11B (part 13B) and the second source electrode 21B (part 23B) is also illustrated. Figure 9B and Figure 9C As shown, in a plan view, the first active region 112B and the first source electrode 11B are arranged so as to substantially coincide with and overlap, and the second active region 122B and the second source electrode 21B are arranged so as to substantially coincide with and overlap.

[0131] Although Figure 9A 、 Figure 9B 、 Figure 9C Although not shown, in a plan view, the first gate trench 17 (first gate conductor 15) extends in a direction parallel to the short side of the semiconductor layer 40, and this direction is referred to as the Y direction. Figures 9A to 9C In the example shown, the first region A1B and the second region A2B are rectangular in plan view, each having its long side parallel to the boundary line 90B. Therefore, the first gate trench 17 (first gate conductor 15) extends in a direction parallel to the long side of the first vertical MOS transistor 10B. Figures 9A to 9C In the example shown, the finger length of the first vertical MOS transistor 10B is not necessarily arranged to be the shortest.

[0132] However, the first gate trench 17 (first gate conductor 15) may extend in a direction parallel to the long side of the semiconductor layer 40, that is, in a direction parallel to the short side of the first vertical MOS transistor 10B in a plan view. In the third embodiment, the direction in which the first gate trench 17 (first gate conductor 15) extends is not important.

[0133] In addition, Figure 9D A comparative example of the third embodiment is shown in FIG. Figure 9D Relative to Figure 9C The configuration of the first gate pad 119B and the second gate pad 129B and the configuration of the first source pad 111B and the second source pad 121B are exemplified. Figure 9D In the plan view, all the components shown are arranged line-symmetrically with the boundary line 90B as the axis of symmetry, and it is difficult to distinguish the first vertical MOS transistor 10B and the second vertical MOS transistor 20B from the surface side (pad side).

[0134] In contrast, in Figure 9E and Figure 9F hereinafter shows an example of a semiconductor device 1B according to the third embodiment. Figure 9Eand Figure 9F The example of the semiconductor device 1B shown is based on Figure 9C The semiconductor device 1B shown is an example of a configuration. Its features will be described below.

[0135] In order to distinguish the first vertical MOS transistor 10B and the second vertical MOS transistor 20B from the surface side (pad side), it is preferable to physically provide some difference that serves as a mark in a plan view. Figure 9E and Figure 9F In the example of the semiconductor device 1B shown, portions X are provided as symbols. For easier understanding, the portions X provided with symbols are surrounded by dotted lines in the drawing.

[0136] Preferably, the marked portion X is a shape that is provided on the first structure provided in the first area A1B and is not provided on the second structure corresponding to the first structure in the second area A2B, so that a judgment can be made instantly by comparing the first area A1B and the second area A2B in a plan view.

[0137] The correspondence relationship described here means that the first structure performs the same function in the first vertical MOS transistor 10B as the second structure performs in the second vertical MOS transistor 20B. For example, if the first structure is the first source electrode, the second structure is the second source electrode. If the first structure is the first gate wiring, the second structure is the second gate wiring.

[0138] If the marked portion X is too small or placed in a hard-to-find location, it becomes difficult to distinguish. Therefore, it is preferably placed inside the active region so that it can be instantly detected with the naked eye or at least with a low-magnification microscope. Therefore, in this third embodiment, the marked portion X is a portion that can be detected by comparing the first active region 112B with the second active region 122B. In other words, the structures provided in the first peripheral region 113B and the second peripheral region 123B can be symmetrical.

[0139] However, when the marked portion X is located within the active region, the first structure in the first active region 112B and the second structure in the second active region 122B are intentionally asymmetrical in plan view. This can cause a directional bias in the bidirectional conduction of the dual-structure vertical MOS transistor. To minimize the bias in bidirectional conduction, it is preferable that the marked portion X have the following two features.

[0140] First, while the area of ​​the first and second structures differs in plan view due to the difference in shape at the marked portion X, this area difference is limited to less than 5%. If the area difference due to the shape difference is less than 5%, it is possible to prevent the bias in bidirectional conduction from causing adverse effects.

[0141] The second point is that the marked portion X is provided so as not to be close to the boundary line 90B between the first vertical MOS transistor 10B and the second vertical MOS transistor 20B. In other words, it is preferable that the marked portion X provided on the first structure be provided at a position on the first structure opposite to the side facing the second active region 122B in a plan view. The term "provided on the first structure opposite to the side facing the second active region 122B" means that, when the first structure is viewed alone in a plan view, the portion X is provided in a range farther from the second active region 122B than its center or centerline.

[0142] If the marked portion X is provided on the side facing the second active region 122B, the difference in shape at the marked portion X may occur in a region close to the boundary line 90B in plan view. Since the region close to the boundary line 90B has the highest current density in bidirectional conduction, providing a difference in shape at the marked portion X may increase the bias in bidirectional conduction.

[0143] Therefore, in the third embodiment, it is preferred that a semiconductor device 1B is a chip-scale package type semiconductor device 1B capable of face-down mounting, comprising: a semiconductor substrate 32; a low-concentration impurity layer 33 formed on the semiconductor substrate 32; a first vertical MOS transistor 10B, formed in a first region A1B of the semiconductor layer 40 (when the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40), and having a plurality of first gate trenches 17; and a second vertical MOS transistor 20B, formed in a plan view of the semiconductor layer 40. In the second region A2B adjacent to the first region A1B, there are a plurality of second gate trenches 27; and a metal layer 30 formed in contact with the back surface of the semiconductor substrate 32; the semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10B and the second vertical MOS transistor 20B; in a plan view, the first region A1B and the second region A2B are one side and the other side that divide the semiconductor layer 40 into two equal parts in terms of area; in a plan view, the first region A1B includes a first active region in which a conduction channel of the first vertical MOS transistor 10B is formed. 112B and a first peripheral region 113B adjacent to and surrounding the first active region 112B; in a plan view, the second region A2B includes a second active region 122B in which a conduction channel of the second vertical MOS transistor 20B is formed, and a second peripheral region 123B adjacent to and surrounding the second active region 122B; in a plan view, the shape of the first structure included in the first active region 112B is similar to the shape of the first structure included in the second vertical MOS transistor 20B. Compared to the shape of the second structure having the same function as that of the vertical MOS transistor 10B, the first structure has a portion X that is not in a line-symmetric relationship with the boundary line 90B between the first area A1B and the second area A2B as the axis of symmetry, and is not in a point-symmetric relationship with the center of the semiconductor layer 40 as the center of symmetry. The second structure is provided in the second active area 122B. In a plan view, the portion X of the shape of the first structure is located in the first structure and is provided at a position opposite to the side facing the second active area 122B.

[0144] Comparative example with the part X not marked ( Figure 9D ) compared to Figure 9E In the plan view, one of the plurality of first source pads 111B has a portion X having a different end shape. On the other hand, second source pad 121B does not have such a portion.

[0145] In addition, Figure 9FIn the plan view, one of the plurality of first source pads 111B is provided with an inwardly-directed cutout portion X. On the other hand, such a portion is not provided in the second source pad 121B.

[0146] That is, in a plan view, the first structure is the first source pad 111B of the first vertical MOS transistor 10B, and the second structure is the second source pad 121B of the second vertical MOS transistor 20B. In a plan view, the total number of corners provided on the periphery of the first source pad 111B of the first vertical MOS transistor 10B is different from the total number of corners provided on the periphery of the second source pad 121B of the second vertical MOS transistor 20B.

[0147] In addition, in the plan view, the first structure is the first source pad 111B of the first vertical MOS transistor 10B, and the second structure is the second source pad 121B of the second vertical MOS transistor 20B. In the plan view, the total area of ​​the first source pad 111B of the first vertical MOS transistor 10B is different from the total area of ​​the second source pad 121B of the second vertical MOS transistor 20B.

[0148] The marked part X is Figure 9E 、 Figure 9F In plan view, the first source pads 111B and the second source pads 121B are all located on the side closest to the long side of the semiconductor layer 40, and are not located on the side closest to the boundary line 90B. Furthermore, the total area of ​​the first source pads 111B and the total area of ​​the second source pads 121B differ due to the provision of the marked portion X, but this area difference is less than 5% of the total area of ​​the second source pads 121B.

[0149] Therefore, if Figure 9E and Figure 9F As shown, by providing a marked portion X, the first vertical MOS transistor 10B and the second vertical MOS transistor 20B can be easily distinguished from the surface side (pad side). On the other hand, the bias of directional differences in the bidirectional conduction of the semiconductor device 1B, which is a dual-structure vertical MOS transistor, can be suppressed as much as possible.

[0150] As another example of the semiconductor device 1B of the third embodiment, Figure 9G and Figure 9H . Figure 9G and Figure 9H The example of the semiconductor device 1B shown is based on Figure 9B An example of the configuration of a semiconductor device 1B is shown.

[0151] exist Figure 9G and Figure 9H In the diagram, only the first source electrode 11B has a chamfered corner X in a plan view. On the other hand, the second source electrode 21B does not have such a chamfered corner. That is, in a plan view, the first structure is the first source electrode 11B of the first vertical MOS transistor 10B, and the second structure is the second source electrode 21B of the second vertical MOS transistor 20B. The number of corners on the periphery of the first source electrode 11B of the first vertical MOS transistor 10B is different from the number of corners on the periphery of the second source electrode 21B of the second vertical MOS transistor 20B.

[0152] In addition, the first structure is the first source electrode 11B of the first vertical MOS transistor 10B, and the second structure is the second source electrode 21B of the second vertical MOS transistor 20B. In a plan view, the area of ​​the first source electrode 11B of the first vertical MOS transistor 10B is different from the area of ​​the second source electrode 21B of the second vertical MOS transistor 20B.

[0153] The chamfered part X is Figure 9G 、 Figure 9H In the plan view, the first source electrode 11B is located on the side close to the long side end of the semiconductor layer 40, and is not located on the side close to the boundary line 90B. In addition, the area of ​​the first source electrode 11B removed in the chamfered portion X is less than 5% of the area of ​​the second source electrode 21B. Figure 9B As shown, the portion X where the first source electrode 11B is chamfered is simply not provided with the first source electrode 11B, and is located within the original range of the first active region 112B.

[0154] Therefore, if Figure 9G and Figure 9H As shown, by providing a marked portion X, the first vertical MOS transistor 10B and the second vertical MOS transistor 20B can be easily distinguished from the surface side (pad side). On the other hand, the bias of directional differences in the bidirectional conduction of the semiconductor device 1B, which is a dual-structure vertical MOS transistor, can be suppressed as much as possible.

[0155] In addition, Figures 9E to 9GIn the example shown, in a plan view, the first gate pad 119B and the second gate pad 129B are respectively arranged at positions close to the ends of one and the other long sides of the semiconductor layer 40. In addition, in a plan view, the plurality of first source pads 111B and the plurality of second source pads 121B are respectively substantially rectangular with semicircular ends, and are all arranged in strips at equal intervals with the direction parallel to the long side of the semiconductor layer 40 as the longer direction. However, in the present embodiment 3 (the present disclosure), there are no restrictions on the number, shape, size, and arrangement of the first gate pad 119B, the second gate pad 129B, and the first source pad 111B and the second source pad 121B. Figures 9E to 9H What is shown are merely examples of them.

[0156] Industrial Applicability

[0157] The semiconductor device including the vertical MOS transistor of the present invention can be widely used as a device for controlling the conduction state of a current path.

[0158] Description of labels

[0159] 1, 1A, 1B semiconductor devices

[0160] Transistors 10, 10A, and 10B (first vertical MOS transistors)

[0161] 11, 11B first source electrode

[0162] Sections 12, 13, and 13B

[0163] 14 1st source region

[0164] 15 1st gate conductor

[0165] 16 first gate insulating film

[0166] 171st gate trench

[0167] 18 1st body area

[0168] 18a 1st connecting part

[0169] 19, 19A, 19B first gate electrode

[0170] 20, 20B transistor (second vertical MOS transistor)

[0171] 21, 21B second source electrode

[0172] Sections 22, 23, and 23B

[0173] 24 second source region

[0174] 25 2nd gate conductor

[0175] 26 second gate insulating film

[0176] 27 2nd gate trench

[0177] 28 Second body area

[0178] 28a Second connecting portion

[0179] 29, 29B second gate electrode

[0180] 30 metal layers

[0181] 32 semiconductor substrate

[0182] 33 Low concentration impurity layer or drift layer

[0183] 34 interlayer insulation layer

[0184] 35 passivation layer

[0185] 40 semiconductor layer

[0186] 90, 90B boundary line

[0187] 111, 111B first source pad

[0188] 112, 112A, 112B first active area

[0189] 113, 113A, 113B first surrounding area

[0190] 114, 114A, 114B: first gate wiring (first gate flow channel)

[0191] 114b connection part

[0192] 115 1st gate resistance element

[0193] 116, 116A No. 1EQR

[0194] 119, 119B first gate pad

[0195] 121, 121B second source pad

[0196] 122, 122B second active region

[0197] 123, 123B Second Surrounding Area

[0198] 124, 124B second gate wiring (second gate flow channel)

[0199] 125 2nd gate resistance element

[0200] 126 2nd EQR

[0201] 129, 129B second gate pad

[0202] 301 Side 1

[0203] 302 Side 2

[0204] 303 Third Side

[0205] 304 4th side

[0206] A1, A1B Area 1

[0207] A2, A2B Area 2

[0208] X mark, the marked area

Claims

1. A semiconductor device, which is a chip-size package type semiconductor device capable of face-down mounting, characterized in that: have: semiconductor substrates; a semiconductor layer formed on the semiconductor substrate; a first vertical MOS transistor formed in the first region of the semiconductor layer and having a plurality of first gate trenches; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer and having a plurality of second gate trenches; as well as a metal layer formed in contact with the back surface of the semiconductor substrate; The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; In the plan view, the first region and the second region are one side and the other side that divide the semiconductor layer into two equal parts in terms of area; In the plan view, a first source electrode and a first source pad, and a first gate electrode and a first gate pad of the first vertical MOS transistor are formed in the first region; In the plan view, a second source electrode and a second source pad, and a second gate electrode and a second gate pad of the second vertical MOS transistor are formed in the second region; The above-mentioned first source electrode has a position in which the shape of the above-mentioned first source electrode and the shape of the above-mentioned second source electrode in the above-mentioned planar view are not in a point-symmetrical relationship with the center of the above-mentioned semiconductor layer as the symmetry center and are not in a line-symmetrical relationship with the boundary line between the above-mentioned first region and the above-mentioned second region as the symmetry axis.

2. The semiconductor device according to claim 1, wherein In the plan view, the number of corner portions provided on the outer periphery of the first source electrode is different from the number of corner portions provided on the outer periphery of the second source electrode.

3. The semiconductor device according to claim 1, wherein In the plan view, the area of ​​the first source electrode is different from the area of ​​the second source electrode.

4. The semiconductor device according to claim 3, wherein In the plan view, a difference between an area of ​​the first source electrode and an area of ​​the second source electrode is less than 5% of an area of ​​the first source electrode.

5. The semiconductor device according to claim 1, wherein The portion of the first source electrode is located in a range farther from the second region than the center of the first source electrode in the plan view.

6. A semiconductor device, which is a chip size package type semiconductor device capable of face-down mounting, characterized in that: have: semiconductor substrates; a semiconductor layer formed on the semiconductor substrate; a first vertical MOS transistor formed in the first region of the semiconductor layer and having a plurality of first gate trenches; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer and having a plurality of second gate trenches; as well as a metal layer formed in contact with the back surface of the semiconductor substrate; The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor; In the plan view, the first region and the second region are one side and the other side that divide the semiconductor layer into two equal parts in terms of area; In the plan view, a first source electrode and one or more first source pads, a first gate electrode, and a first gate pad of the first vertical MOS transistor are formed in the first region; In the plan view, a second source electrode and one or more second source pads, a second gate electrode, and a second gate pad of the second vertical MOS transistor are formed in the second region; The above-mentioned one or more first source welding pads have a position in which the shape of the above-mentioned one or more first source welding pads and the shape of the above-mentioned one or more second source welding pads are not in a point-symmetrical relationship with the center of the above-mentioned semiconductor layer as the center of symmetry and are not in a line-symmetrical relationship with the boundary line between the above-mentioned first region and the above-mentioned second region as the axis of symmetry in the above-mentioned plan view.

7. The semiconductor device according to claim 6, wherein In the plan view, the total number of corners provided on the outer peripheries of the one or more first source pads is different from the total number of corners provided on the outer peripheries of the one or more second source pads.

8. The semiconductor device according to claim 6, wherein In the plan view, the total area of ​​the one or more first source pads is different from the total area of ​​the one or more second source pads.

9. The semiconductor device according to claim 8, wherein In the plan view, a difference between a total area of ​​the one or more first source pads and a total area of ​​the one or more second source pads is less than 5% of the total area of ​​the one or more first source pads.

10. The semiconductor device according to claim 6, wherein The portion of the one or more first source pads is located farther from the second region than the center of the one or more first source pads in the plan view.

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