Array substrate and display device

Abstract

The embodiment of the invention provides an array substrate and a display device, relates to the technical field of display, and aims to improve the hot carrier effect and prolong the service life of the array substrate. The array substrate comprises a plurality of pixel units arranged in an array; a plurality of cascaded shift registers; the output end of one shifting register is electrically connected with at least one row of pixel units, and the shifting register is used for providing grid scanning signals for the at least one row of pixel units; the shift register comprises a first transistor, the first transistor comprises a grid electrode and an active layer, and the active layer comprises a first conductor region, a second conductor region and a channel region located between the first conductor region and the second conductor region; the active layer further comprises a first lightly doped region located between the channel region and the first conductor region and a second lightly doped region located between the channel region and the second conductor region, and the width of the first lightly doped region is larger than that of the second lightly doped region. The array substrate is used for the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] In recent years, the development of displays has shown a trend of high integration and low cost. One of the very important technologies is the mass production of GOA (Gate Driver on Array, Chinese: array substrate row drive). The gate switch circuit is integrated on the array substrate of the display panel using GOA technology, so that the gate driver integrated circuit part can be omitted to reduce product costs in terms of material cost and manufacturing process. This gate switch circuit integrated on the array substrate using GOA technology is also called a GOA circuit or a shift register circuit.

[0003] The GOA circuit includes a plurality of GOA units, and each level of GOA units (i.e., shift registers) is connected to at least one gate line for outputting a gate scanning signal to the at least one gate line. In this way, by controlling the plurality of gate lines in the array substrate through the multi-level cascaded GOA units, the line-by-line scanning of each frame of the display screen can be realized.

[0004] Each GOA unit includes a number of TFTs (Thin Film Transistors), and the TFTs included in the GOA unit may experience hot carrier effects, which in turn may affect the performance of the array substrate. Summary of the invention

[0005] An object of the embodiments of the present disclosure is to provide an array substrate and a display device, which are used to improve the hot carrier effect and extend the service life of the array substrate.

[0006] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0007] On the one hand, an array substrate is provided. The array substrate includes a plurality of pixel units arranged in an array; and a plurality of cascaded shift registers. The output end of one of the shift registers is electrically connected to at least one row of the pixel units, and is used to provide a gate scanning signal to at least one row of the pixel units; the shift register includes a first transistor, the first transistor includes a gate and an active layer, the active layer includes a first conductor region, a second conductor region, and a channel region located between the first conductor region and the second conductor region; the first conductor region is connected to a clock signal end, and the second conductor region is connected to the output end of the shift register; the first transistor is used to receive a clock signal from the clock signal end and output the gate scanning signal; the active layer also includes a first lightly doped region located between the channel region and the first conductor region, and a second lightly doped region located between the channel region and the second conductor region, and the width of the first lightly doped region is greater than the width of the second lightly doped region; wherein the width is the size of the first lightly doped region or the second lightly doped region in a first direction, and the first direction is the arrangement direction of the first conductor region, the channel region, and the second conductor region.

[0008] In the above array substrate, by setting the first lightly doped region and the second lightly doped region, the first lightly doped region and the second lightly doped region act as resistors, so that the first lightly doped region and the second lightly doped region can share the voltage drop, that is, the first lightly doped region and the second lightly doped region can bear part of the voltage, thereby reducing the voltage division of the channel region, achieving high voltage resistance of the channel region, thereby improving the voltage resistance performance of the first transistor, extending the service life of the first transistor, and thus extending the service life of the array substrate; by setting the first lightly doped region and the second lightly doped region, the leakage current of the first transistor can be effectively reduced, the power consumption of the first transistor can be reduced, and then the performance of the array substrate can be improved; on the other hand, the width of the first lightly doped region located at the input end of the first transistor is greater than the width of the second lightly doped region located at the output end of the first transistor, which improves the problem that the input end of the first transistor is more easily damaged due to hot carrier effect and self-heating effect due to the harsh working conditions of the first transistor and the input end of the first transistor is always in an AC bias state, thereby improving the performance of the first transistor and extending the service life of the array substrate.

[0009] In some embodiments, a ratio of a width of the first lightly doped region to a width of the second lightly doped region is greater than 1 and less than or equal to 1.8.

[0010] In some embodiments, the width of the first lightly doped region is greater than 1.4 μm and less than or equal to 1.8 μm; the width of the second lightly doped region is greater than or equal to 1 μm and less than 1.4 μm.

[0011] In some embodiments, the gate of the first transistor includes at least two sub-gates arranged along the first direction; the channel region of the first transistor includes at least two sub-channel regions, each of the sub-channel regions and one of the sub-gates overlap in the thickness direction of the array substrate; the active layer also includes at least one third lightly doped region located between two adjacent sub-channel regions; the width of the third lightly doped region is smaller than the width of the first lightly doped region.

[0012] In some embodiments, a width of the third lightly doped region is equal to a width of the second lightly doped region.

[0013] In some embodiments, the active layer includes at least two active patterns arranged along a second direction, and the second direction is perpendicular to the first direction; each of the sub-gates extends along the second direction and overlaps with the at least two active patterns in the thickness direction of the array substrate; each of the active patterns includes a first conductor region, a first lightly doped region, at least two sub-channel regions, a second lightly doped region and a second conductor region arranged along the first direction, and also includes at least one third lightly doped region located between two adjacent sub-channel regions.

[0014] In some embodiments, the shift register also includes: a plurality of second transistors, the second transistors including: a gate and an active layer; the active layer of the second transistor includes a first conductor region, a second conductor region, and a channel region located between the first conductor region of the second transistor and the second conductor region of the second transistor; the active layer of the second transistor also includes a lightly doped region located between the channel region of the second transistor and the first conductor region of the second transistor and between the channel region of the second transistor and the second conductor region of the second transistor; along the arrangement direction of the channel region of the second transistor, the first conductor region of the second transistor and the second conductor region of the second transistor, the width of the lightly doped region of the second transistor ranges from 1.2 μm to 1.6 μm.

[0015] In some embodiments, the pixel unit includes: a third transistor; the third transistor includes: a gate and an active layer; the active layer of the third transistor includes a first conductor region, a second conductor region, and a channel region located between the first conductor region of the third transistor and the second conductor region of the third transistor; the active layer of the third transistor also includes a lightly doped region located between the channel region of the third transistor and the first conductor region of the third transistor and between the channel region of the third transistor and the second conductor region of the third transistor; along the arrangement direction of the channel region of the third transistor, the first conductor region of the third transistor and the second conductor region of the third transistor, the width of the lightly doped region of the third transistor ranges from 1.2μm to 1.6μm.

[0016] In some embodiments, the width of the lightly doped region of the second transistor is equal to the width of the lightly doped region of the third transistor.

[0017] In some embodiments, a width of the first lightly doped region of the first transistor is greater than a width of the lightly doped region of the second transistor; and a width of the second lightly doped region of the first transistor is less than a width of the lightly doped region of the second transistor.

[0018] In some embodiments, a sum of a width of the first lightly doped region of the first transistor and a width of the second lightly doped region of the first transistor is equal to a sum of widths of the two lightly doped regions of the second transistor.

[0019] In some embodiments, the array substrate further comprises a plurality of gating circuits, the gating circuits being electrically connected to at least two columns of the pixel units and being used for transmitting data signals to at least two columns of the pixel units in a time-sharing manner; the gating circuit comprises a fourth transistor, the fourth transistor comprising: a gate and an active layer; the active layer of the fourth transistor comprising a first conductor region, a second conductor region, and a channel region between the first conductor region of the fourth transistor and the second conductor region of the fourth transistor; the active layer of the fourth transistor further comprises a lightly doped region between the channel region of the fourth transistor and the first conductor region of the fourth transistor and between the channel region of the fourth transistor and the second conductor region of the fourth transistor; along the arrangement direction of the channel region of the fourth transistor, the first conductor region of the fourth transistor and the second conductor region of the fourth transistor, the width of the lightly doped region of the fourth transistor ranges from 1.0 μm to 1.4 μm.

[0020] In some embodiments, a width of the lightly doped region of the fourth transistor is smaller than a width of the lightly doped region of the second transistor.

[0021] In some embodiments, the ion dose in the first conductor region is 1E15 / cm2; and / or the ion dose in the second conductor region is 1E15 / cm2.

[0022] In another aspect, a display device is provided, comprising: an array substrate as described in any one of the above embodiments.

[0023] The above-mentioned display device has the same structure and beneficial technical effects as the array substrate provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products involved in the embodiments of the present disclosure.

[0025] Figure 1A is a structural diagram of a display device according to some embodiments;

[0026] Figure 1B is a structural diagram of another display device according to some embodiments;

[0027] Figure 2 is a top view of a display panel according to some embodiments;

[0028] Figure 3A is a structural diagram of a backlight module according to some embodiments;

[0029] Figure 3B is a structural diagram of another backlight module according to some embodiments;

[0030] Figure 4 is a structural diagram of an array substrate according to some embodiments;

[0031] Figure 5 is a structural diagram of another array substrate according to some embodiments;

[0032] Figure 6 is an equivalent circuit diagram of a shift register according to some embodiments;

[0033] Figure 7 is a structural diagram of a first transistor according to some embodiments;

[0034] Figure 8A to Figure 8E is a structural diagram of a first transistor during preparation according to some embodiments;

[0035] Fig. 9 is a structural diagram of another first transistor according to some embodiments;

[0036] Figures 10A to 10F is a structural diagram of another first transistor during preparation according to some embodiments;

[0037] Fig.11 is a film layer diagram of a first transistor according to some embodiments;

[0038] Fig.12is a film layer diagram of a shift register according to some embodiments;

[0039] Fig.13 is a film layer diagram of a third transistor according to some embodiments;

[0040] Fig.14 is a structural diagram of another display device according to some embodiments;

[0041] Fig.15 A partial film layer diagram of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0046] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0047] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0048] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0050] Some embodiments of the present disclosure provide a display device, which can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or text. More specifically, it is expected that the display device of the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0051] Figure 1A FIG. 1 is a structural diagram of a display device according to some embodiments. Figure 1A As shown, the display device 1000 includes a frame 100, a cover plate 200, a display panel 300, a circuit board 400, and other electronic components including a camera.

[0052] The longitudinal section of the frame 100 is U-shaped, the display panel 300, the circuit board 400 and other electronic accessories including the camera are arranged in the frame 100, the circuit board 400 is located between the display panel 300 and the frame 100, and the cover plate 200 is located on the light-emitting side of the display panel 300. The side of the display panel 300 used for displaying an image is the light-emitting side of the display panel 300, and the side facing away from the light-emitting side of the display panel 300 is the non-light-emitting side of the display panel 300.

[0053] In some embodiments, the display panel 300 may be: a liquid crystal display panel (LCD), a light emitting diode (LED) display panel, a Micro LED display device, or a Mini LED display panel, and the present disclosure does not specifically limit this. The liquid crystal display panel includes an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate.

[0054] In other embodiments, the display panel 300 is an electroluminescent display panel, such as an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED). The OLED display panel includes an array substrate, a plurality of OLEDs arranged in the array substrate, and an encapsulation layer. The encapsulation layer is used to well encapsulate the OLEDs in the array substrate to prevent the luminous performance and service life of the OLEDs from being affected by the external environment.

[0055] In the following, some embodiments of the present disclosure are described by taking the display panel 300 as a liquid crystal display panel as an example.

[0056] In some embodiments, Figure 1B As shown, when the display panel 300 is a liquid crystal display panel, the display device 1000 further includes: a backlight module 500. The display panel 300 is stacked on the light-emitting side of the backlight module 500. The light-emitting side of the backlight module 500 refers to the side from which the backlight module 500 emits light.

[0057] Exemplarily, the backlight module 500 can be used as a light source to provide backlight. For example, the backlight provided by the backlight module 500 can be white light or blue light.

[0058] For example, Figure 2 As shown, the display panel 300 may include an array substrate 10 , a liquid crystal layer 20 , and a color film substrate 30 which are stacked in sequence.

[0059] For example, Figure 2 As shown, the array substrate 10 may include: a plurality of pixel electrodes 101 and a plurality of pixel driving circuits 102, which are arranged in an array, for example. The plurality of pixel electrodes 101 are electrically connected to the plurality of pixel driving circuits 102 in a one-to-one correspondence, and the pixel driving circuits 102 provide pixel voltages for the corresponding pixel electrodes 101.

[0060] Exemplarily, the display panel 300 further includes a common electrode. The common electrode can receive a common voltage.

[0061] The setting position of the common electrode is related to the display type of the display panel 300. In the embodiment of the present disclosure, when the display panel 300 is an LED display panel, the display type of the display panel 300 can be an ADS (Advanced SuperDimension Switch) display type, an IPS (In-Plane Switching) display type, a VA (Vertical Alignment) display type, an FFS (Fringe Field Switching) display type, a TN (Twisted Nematic) display type, etc. Therefore, there are various setting positions of the common electrode in the embodiment of the present disclosure.

[0062] For example, when the display panel 300 is an IPS display type, the common electrode can be set on the array substrate 10 and set on the same layer as the pixel electrode 101. Thus, the common electrode and the pixel electrode 101 can be formed simultaneously in one composition process, thereby simplifying the preparation process of the display panel 300.

[0063] For another example, when the display panel 300 is of FFS display type or ADS display type, the common electrode can be disposed on the array substrate 10 and located at a different layer from the pixel electrode 101. Thus, mutual interference between the pixel voltage signal on the pixel electrode 101 and the common voltage on the common electrode can be avoided, thereby improving the signal accuracy of the pixel voltage signal and the common voltage.

[0064] For another example, when the display panel 300 is of a TN display type or a VA display type, the common electrode may be disposed on the color filter substrate 30 .

[0065] Exemplarily, the liquid crystal layer 20 includes a plurality of liquid crystal molecules. For example, taking the display panel 300 as a TN display type, an electric field can be formed between the pixel electrode 101 and the common electrode, and by controlling the voltage value of each pixel electrode 101, the intensity of the electric field formed between the common electrode and each pixel electrode 101 can be controlled, thereby controlling the deflection angle of the liquid crystal molecules in the liquid crystal layer 20, that is, the liquid crystal molecules between the pixel electrode 101 and the common electrode can be deflected under the action of the electric field.

[0066] It is understandable that the backlight provided by the backlight module 500 can pass through the array substrate 10 and be incident on the liquid crystal molecules in the liquid crystal layer 20. Under the action of the electric field formed between the pixel electrode 101 and the common electrode, the liquid crystal molecules flip to a certain extent, thereby changing the amount of light passing through the liquid crystal molecules, so that the light emitted by the liquid crystal molecules reaches a preset brightness. The above light passes through the filter films of different colors in the color filter substrate 30 and then emits. The emitted light includes light of various colors, such as red light, green light, blue light, etc. The light of various colors cooperates with each other to enable the display device 1000 to achieve display.

[0067] In some examples, when the backlight provided by the backlight module 500 is white light, the color filter substrate 30 may include a red filter film, a green filter film, a blue filter film, etc. By controlling the intensity of light irradiated to the red filter film, the green filter film, and the blue filter film, red light, green light, and blue light of different intensities can be obtained, so that the display device 1000 can display a color image. For example, the red filter film can only allow the red light in the incident light to pass through, the green filter film can only allow the green light in the incident light to pass through, and the blue filter film can only allow the blue light in the incident light to pass through.

[0068] In other examples, when the backlight provided by the backlight module 500 is blue light, the color filter substrate 30 may include a color conversion film. For example, the color conversion film may be a quantum dot film. After the blue light is irradiated to the red quantum dot film, it can be converted to red light. After the blue light is irradiated to the green quantum dot film, it can be converted to green light. The red light and green light obtained after the conversion of the quantum dot film are mixed with the blue light provided by the backlight module 500, so that the display device 1000 can realize full-color graphic display.

[0069] In addition, the color filter substrate 30 also includes a black matrix, which can be used to prevent light mixing.

[0070] Exemplarily, the backlight module 500 includes a light source and a reflector, and the light emitted by the light source is light of a first wavelength. The backlight module 500 is used to provide light of a first wavelength to the liquid crystal display panel as incident light of the liquid crystal display panel. In the embodiment of the present disclosure, the light of the first wavelength can be any one of white light, blue light, purple light or ultraviolet light. The embodiment of the present disclosure does not limit this.

[0071] Exemplarily, the backlight module 500 may be an edge-type backlight module, or the backlight module 500 may be a direct-type backlight module.

[0072] like Figure 3AAs shown, the edge-type backlight module 500 includes, for example, a light bar 501, a light guide plate 503, an optical film 504 disposed on the light-emitting side of the light guide plate 503, and a reflective sheet 502 disposed on the other side of the light guide plate 503 opposite to the light-emitting side, and the light bar 501 is disposed on the side of the light guide plate 503. The light bar 501 is the above-mentioned light source.

[0073] The light bar 501 can be, for example, a blue light emitting diode (LED) light bar. Since white light generally comes from the light emitted by blue light exciting phosphors, and about 40% of energy is lost in the process of blue light exciting phosphors, when the light bar 501 is set as a blue light LED light bar, that is, the blue light emitted by the blue light LED light bar is directly used as the output light of the backlight module 500, the above energy loss can be avoided.

[0074] The optical film 504 may include a diffuser and / or a brightness enhancement film, etc. The brightness enhancement film may include a prism film (Brightness Enhancement Film, referred to as BEF), a reflective polarized brightness enhancement film (Dual Brightness Enhancement Film, referred to as DBEF), etc. The two may be used in combination.

[0075] like Figure 3B As shown, the direct-type backlight module 500 can be made of a light board 505 with tiny blue LEDs arranged in an array, and the light emitting direction of the light board 505 faces the liquid crystal display panel. Figure 3B As shown, the backlight module 500 may further include, for example, a reflective sheet 502, a light guide plate 503 disposed on the upper side of the reflective sheet 502, and an optical film 504 disposed on the upper side of the light guide plate 503. The light board 505 is the above-mentioned light source.

[0076] Taking the blue light as an example, the wavelength of the blue light emitted by the light bar 501 and the light board 505 is in the range of 421 nm to 505 nm, and the central wavelength is 454 nm.

[0077] In addition, the optical film 504 includes: a diffuser plate, a quantum dot film, a diffuser sheet and a composite film, etc., which are stacked in sequence on the light-emitting side.

[0078] For example, the diffuser plate and diffuser sheet are used to eliminate lamp shadows and to homogenize the light emitted by the light bar 501 and the light board 505 to improve the uniformity of the light. For example, the quantum dot film is used to convert the light emitted by the light bar 501 and the light board 505. Optionally, when the light emitted by the light bar 501 and the light board 505 is blue light, the quantum dot film can convert the blue light into white light and improve the purity of the white light. For example, the composite film is used to increase the brightness of the light emitted by the light bar 501 and the light board 505.

[0079] It can be understood that the brightness of the light emitted by the light bar 501 and the light board 505 after being incident on the optical film 504 is enhanced, and the emitted light has higher purity and better uniformity.

[0080] In some examples, such as Figure 4 As shown, some embodiments of the present disclosure provide an array substrate 10. The array substrate 10 has a display area AA and a peripheral area BB disposed around the display area AA.

[0081] like Figure 4 As shown, the array substrate 10 includes a plurality of gate lines GL, a plurality of data lines DL and a plurality of pixel units 1 located in the display area AA.

[0082] Exemplarily, a plurality of pixel units 1 are arranged in an array. Thus, the pixel units 1 arranged in a row along the X-axis direction are referred to as a row of pixel units 1. The pixel units 1 arranged in a row along the Y-axis direction are referred to as a column of pixel units 1. The plurality of pixel units 1 at least include: a first color pixel unit, a second color pixel unit, and a third color pixel unit. The first color, the second color, and the third color are three primary colors (e.g., red, green, and blue).

[0083] Exemplarily, the plurality of gate lines GL extend along the X-axis direction, and the data lines DL extend along the Y-axis direction. Each gate line GL is coupled to a row of pixel units 1 , and each data line DL is coupled to a column of pixel units 1 .

[0084] like Figure 4 As shown, the array substrate 10 further includes a gate driving circuit 103 and a data driving circuit 104 disposed in the peripheral area BB.

[0085] Exemplarily, the gate driver circuit 103 is a GOA (Gate Driver on Array, GOA) circuit, that is, a circuit formed by directly integrating the gate driver circuit 103 into the array substrate 10. The GOA circuit has the advantages of low cost, fewer processes, high production capacity, and narrow border width of the display device 1000.

[0086] For example, the gate driving circuit 103 can be arranged in the peripheral area BB of the array substrate 10 along the arrangement direction of the plurality of data lines DL, and the data driving circuit 104 can be arranged in the peripheral area BB of the array substrate 10 along the arrangement direction of the plurality of data lines DL. In this way, it is convenient to realize the electrical connection between the gate driving circuit 103 and the plurality of gate lines GL, and the electrical connection between the data driving circuit 104 and the plurality of data lines DL.

[0087] Exemplarily, the gate drive circuit 103 outputs gate scanning signals to the plurality of gate lines GL row by row, thereby turning on the transistors in each pixel unit 1 in the array substrate 10 row by row through the gate drive circuit 103. After controlling the transistors in a row of pixel units 1 to turn on, the data drive circuit 104 writes the pixel data voltage into the pixel electrode 101 in the pixel unit 1 through the transistors in the pixel unit 1; thereby, the charge carried in the data signal is loaded on the pixel electrode 101, and the liquid crystal is deflected through the electric field between the pixel electrode 101 and the common electrode, thereby realizing the display of the LCD.

[0088] Exemplarily, one output terminal of the gate driving circuit 103 is electrically connected to one gate line GL. In other words, the number of the output terminals of the gate driving circuit 103 is equal to the number of the gate lines GL in the array substrate 10 .

[0089] In some examples, the gate drive circuit 103 includes a plurality of cascaded GOA units, which are also shift registers. The output end of the gate drive circuit 103 is the output end of the plurality of shift registers included in the gate drive circuit 103. The output end of a shift register is connected to at least one gate line GL, and is used to output a gate scan signal to the at least one gate line GL, thereby turning on the transistor in the pixel unit 1 of the row corresponding to the at least one gate line GL.

[0090] For example, Figure 4 As shown, the multi-stage cascaded shift registers in the gate drive circuit 103 are respectively represented as RS1, RS2...RS(N), where N is a positive integer. Each stage of the shift register is connected to a gate line GL, and is used to output a gate scanning signal to the gate line GL. In this way, by controlling multiple gate lines GL through the multi-stage cascaded shift registers, progressive scanning of each frame of display screen can be achieved.

[0091] It should be noted that Figure 4 The present invention only illustrates a method of arranging the gate driving circuit 103 on one side of the peripheral area BB of the array substrate 10. The structure of the gate driving circuit 103 is as follows: Figure 4As shown, the multi-stage cascaded shift registers are connected to the plurality of gate lines GL in a one-to-one correspondence. In this way, the multi-stage cascaded shift registers output gate scanning signals to each gate line GL in sequence from one side of the array substrate 10 row by row.

[0092] The distribution of the gate driving circuit 103 in the array substrate 10 is not limited to this. In other examples, such as Figure 5 As shown, a gate driving circuit 103 is respectively arranged on opposite sides of the peripheral area BB of the array substrate 10, and the arrangement direction of each level of shift registers in each gate driving circuit 103 is the same as the arrangement direction of the plurality of gate lines GL. In this way, the two ends of each gate line GL are respectively connected to a gate driving circuit 103, so that the two gate driving circuits 103 can output gate scanning signals to each gate line GL row by row from the two ends of the gate line GL.

[0093] In the case where two gate drive circuits 103 are provided in the array substrate 10, the connection mode between the two gate drive circuits 103 and each gate line GL may be different from the above. For example, the gate drive circuit 103 located at one end (e.g., the left end) of the plurality of gate lines GL is connected to the gate lines GL of the odd rows, and the gate drive circuit 103 located at the other end (e.g., the right end) of the plurality of gate lines GL is connected to the gate lines GL of the even rows. In this way, the gate drive circuit 103 located at the left end of the plurality of gate lines GL outputs gate scanning signals to the gate lines GL of the odd rows row by row, and the gate drive circuit 103 located at the right end of the plurality of gate lines GL outputs gate scanning signals to the gate lines GL of the even rows row by row, thereby realizing the cross output of the gate drive circuit 103 to the plurality of gate lines GL.

[0094] In some examples, such as Figure 6 , which is an equivalent circuit diagram of a shift register RS ​​according to some embodiments.

[0095] For example, Figure 6 As shown, the shift register RS ​​includes: a first input module 201 , a pull-down control module 202 , a first output module 203 and a pull-down module 204 .

[0096] The first input module 201 is electrically connected to the first input signal terminal STV, the first control signal terminal CN, and the first pull-up node PUCN respectively; the first input module 201 is configured to provide a signal of the first control signal terminal CN to the first pull-up node PUCN under the control of the signal of the first input signal terminal STV. During the input period of each frame, the first input signal terminal STV provides an input signal to the first input module 201, controls the first input module 201 to be turned on, and transmits the voltage of the first control signal terminal CN to the first pull-up node PUCN.

[0097] The pull-down control module 202 is electrically connected to the second clock signal terminal CKB, the first pull-up node PUCN, the first power signal terminal VGL-G, and the pull-down node PD, respectively. The pull-down control module 202 is configured to output the voltage of the first power signal terminal VGL-G to the pull-down node PD under the control of the first pull-up node PUCN. The pull-down control module 202 is also configured to keep the pull-down node PD at a first potential under the control of the signal of the second clock signal terminal CKB, and the first potential is different from the potential of the first power signal terminal VGL-G. Specifically, the pull-down control module 202 is used to store the voltage of the second clock signal terminal CKB under the control of the signal of the second clock signal terminal CKB, and output the voltage of the second clock signal terminal CKB to the pull-down node PD, or to release the stored voltage to the pull-down node PD.

[0098] The first output module 203 is electrically connected to the pull-up node PU, the first clock signal terminal CK, and the output terminal OUTPUT, respectively. The first output module 203 is configured to provide the clock signal of the first clock signal terminal CK to the output terminal OUTPUT under the control of the potential of the pull-up node PU, so that the output terminal OUTPUT outputs the clock signal of the first clock signal terminal CK. In the output period of each frame, the potential of the pull-up node PU controls the first output module 203 to be turned on, and the clock signal provided by the first clock signal terminal CK is output to the output terminal OUTPUT. The clock signal provided by the first clock signal terminal CK is the gate scanning signal output by the output terminal OUTPUT of the shift register RS.

[0099] The pull-down module 204 is electrically connected to the first pull-up node PUCN, the pull-down node PD, the first power signal terminal VGL-G, and the output terminal OUTPUT respectively; the first pull-down module 204 is configured to provide the potential of the first power signal terminal VGL-G to the output terminal OUTPUT under the control of the potential of the pull-down node PD.

[0100] The structure of the first output module 203 can be set selectively. For example, Figure 6 As shown, the first output module 203 includes a first transistor T1. The first transistor T1 is used to receive a clock signal from a clock signal terminal (ie, a first clock signal terminal CK) and output a gate scanning signal.

[0101] Specifically, Figure 6 As shown, the gate of the first transistor T1 is connected to the pull-up node PU, the first electrode is connected to the first clock signal terminal CK, and the second electrode is connected to the output terminal OUTPUT. Under the control of the potential of the pull-up node PU, the first electrode of the first transistor T1 receives the clock signal provided by the first clock signal terminal CK and outputs a gate scanning signal to OUTPUT.

[0102] For example, Figure 6 As shown, the first output module 203 further includes a first capacitor C1. One end of the first capacitor C1 is connected to the pull-up node PU, and the other end is connected to the pull-up node PU. The first capacitor C1 is used to maintain a high potential of the pull-up node PU.

[0103] For example, Figure 7 , which is a structural diagram of a first transistor T1 according to some embodiments.

[0104] like Figure 7 As shown, the first transistor T1 includes a gate 11 and an active layer 12. The active layer 12 includes a first conductor region 121, a second conductor region 122, and a channel region 120 located between the first conductor region 121 and the second conductor region 122. The first conductor region 121 is connected to the clock signal terminal (that is, the first clock signal terminal CK), and the second conductor region 122 is connected to the output terminal OUTPUT of the shift register RS.

[0105] In some implementations, in order to improve the off-state leakage current of the transistor and the stability of the transistor operation, light doping is performed between the source and drain of the transistor to form a lightly doped source and drain (LDD) region, which is used to reduce the electric field at the contact between the drain or source and the channel, thereby reducing the leakage current.

[0106] It should be noted that lightly doped source and drain is a technology that changes the current characteristics of the device by introducing lightly doped materials between the source and drain. It is based on the energy level and band structure of the doped material, and controls the current through mechanisms such as band bending effect, energy level modulation effect and space charge limitation effect, thereby reducing the leakage current of the transistor, thereby optimizing the performance of the transistor and reducing the power consumption of the transistor.

[0107] Specifically, Figure 7 As shown, in the first transistor T1 , the active layer 12 further includes a first lightly doped region 123 located between the channel region 120 and the first conductor region 121 , and a second lightly doped region 124 located between the channel region 120 and the second conductor region 122 .

[0108] It can be understood that the doping type of the first lightly doped region 123, the second lightly doped region 124, the first conductor region 121 and the second conductor region 122 is the same, and the ion dose doped in the first lightly doped region 123 and the second lightly doped region 124 is less than the ion dose doped in the first conductor region 121 and the second conductor region 122. Here, the type, energy and dose of ions when doping the first lightly doped region 123 and the second lightly doped region 124 are not specifically limited.

[0109] For example, the first lightly doped region 123, the second lightly doped region 124, the first conductor region 121, and the second conductor region 122 are all P-type doped; the ions injected during doping may be, for example, boron ions, indium ions, etc. For another example, the first lightly doped region 123, the second lightly doped region 124, the first conductor region 121, and the second conductor region 122 are all N-type doped; the ions injected during doping may be, for example, phosphorus ions, arsenic ions, etc.

[0110] In addition, the doping type of the channel region 120 is opposite to the doping type of the first lightly doped region 123, the second lightly doped region 124, the first conductor region 121, and the second conductor region 122. For example, the first lightly doped region 123, the second lightly doped region 124, the first conductor region 121, and the second conductor region 122 are P-type doped, and the channel region 120 is N-type doped. For another example, the first lightly doped region 123, the second lightly doped region 124, the first conductor region 121, and the second conductor region 122 are N-type doped, and the channel region 120 is P-type doped. The embodiments of the present disclosure are not limited to this.

[0111] In some implementations, the first transistor T1 is prepared by a self-alignment process, which may specifically include:

[0112] (1): For example Fig. 8A and Figure 8B As shown, a light shielding layer LS, an active layer PL, a gate insulating layer GI, and a gate conductive layer GT are sequentially formed on a substrate 01. The active layer PL includes a channel region 120, a first pattern 021 located on both sides of the channel region 120, and a second pattern 022 located on one side of the first pattern 021 relative to the channel region 120.

[0113] (2) Figure 8C As shown, a photoresist layer is formed on the gate conductive layer GT, and after the photoresist layer is exposed, developed, and etched, a gate 11 of the first transistor T1 and a first photoresist pattern 03 located above the gate 11 are formed. The first photoresist pattern 03 is arranged corresponding to the first pattern 021 and the channel region 120, and the gate 11 is arranged corresponding to the channel region 120. For example, the first photoresist pattern 03 completely covers the first pattern 021 and the channel region 120. The gate 11 completely covers the channel region 120.

[0114] For example, Figure 8C As shown, in the arrangement direction of the second pattern 022, the first pattern 021 and the channel region 120, the edge of the gate 11 is retracted relative to the edge of the first photoresist pattern 03. The size between the edge of the first photoresist pattern 03 and the edge of the gate 11 determines the length of the first pattern 021.

[0115] The length of the first pattern 021 can be adjusted by controlling the size of the gate 11 , the size of the first photoresist pattern 03 , and the size of the edge of the gate 11 that is retracted relative to the edge of the first photoresist pattern 03 .

[0116] (3) Fig.8D As shown, the first photoresist pattern 03 is used as a mask to perform a heavy doping process on the portion of the active layer PL not blocked by the first photoresist pattern 03 (i.e., the second pattern 022). A heavily doped region (respectively: the first conductor region 121 and the second conductor region 122) is formed at the two second patterns 022.

[0117] Here, a heavy doping process is performed using the first photoresist pattern 03 as a mask, and the heavily doped region formed can be P-type or N-type; when the heavily doped region formed is P-type, the injected ions can be, for example, boron ions, and when the heavily doped region formed is N-type, the injected ions can be, for example, phosphorus ions.

[0118] (4) Combination Fig.8D and Fig. 8E As shown, the first photoresist pattern 03 is stripped, and a light doping process is performed using the gate 11 of the first transistor T1 as a mask to form lightly doped regions (respectively: the first lightly doped region 123 and the second lightly doped region 124 ) at the two first patterns 021 .

[0119] In the process of preparing and forming the first transistor T1 by the self-alignment process, the lengths of the LDDs of transistors with different width / length ratios are the same; and due to process reasons, in the same transistor, for example, in the first transistor T1, the lengths of the first lightly doped region 123 and the second lightly doped region 124 are the same. For example, in the first transistor T1 formed by the above self-alignment process, the lengths of the first lightly doped region 123 and the second lightly doped region 124 are both 0.75 μm.

[0120] The inventors of the present disclosure have discovered through research that during the operation of the shift register RS, the operating conditions of the first transistor T1 in the first output module 203 are more stringent than those of other transistors, and the input end of the first transistor T1 is always in an AC bias state. Due to the hot carrier effect and the self-heating effect, the input end of the first transistor T1 is more easily damaged, resulting in device failure, which affects the service life of the array substrate 10.

[0121] Based on this, in the embodiment of the present disclosure, the first transistor T1 is improved. Fig. 9As shown, in the first transistor T1, the width of the first lightly doped region 123 is greater than the width of the second lightly doped region 124; wherein the width is the size of the first lightly doped region 123 or the second lightly doped region 124 in the first direction X, and the first direction X is the arrangement direction of the first conductor region 121, the channel region 120 and the second conductor region 122.

[0122] Exemplarily, the first transistor T1 provided in the embodiment of the present disclosure may be manufactured by a non-self-aligned process, for example. Specifically, the process may include:

[0123] (1): For example Fig. 10A As shown, a light shielding layer LS, an active layer PL, and a gate insulating layer GI are sequentially formed on a substrate 01. The active layer PL includes a channel region 120, a first pattern 021 located on both sides of the channel region 120, and a second pattern 022 located on one side of the first pattern 021 opposite to the channel region 120.

[0124] (2): If Fig. 10B As shown, a second photoresist pattern 04 is formed on the gate insulating layer GI; the second photoresist pattern 04 is used as a mask to perform a heavy doping process on the portion of the active layer PL not blocked by the second photoresist pattern 04 (i.e., the second pattern 022). Heavy doping regions (respectively: the above-mentioned first conductor region 121 and the second conductor region 122) are formed at the two second patterns 022.

[0125] The second photoresist pattern 04 is disposed corresponding to the first pattern 021 and the channel region 120. For example, the first photoresist pattern 03 completely covers the first pattern 021 and the channel region 120.

[0126] (3) Combination Fig. 10B , Fig. 10C , Fig. 10D and Fig. 10E As shown, the second photoresist pattern 04 is stripped off; a gate conductive layer GT and a third photoresist pattern 05 are formed on the gate insulating layer GI, and the gate conductive layer GT is patterned using the third photoresist pattern 05 as a mask to form a gate 11.

[0127] (4) Combination Fig. 10E and Fig.10F As shown, the third photoresist pattern 05 is stripped, and a light doping process is performed using the gate 11 of the first transistor T1 as a mask to form lightly doped regions (respectively: the first lightly doped region 123 and the second lightly doped region 124 ) at the two first patterns 021 .

[0128] Compared with the self-aligned process, in the first transistor T1 prepared by the non-self-aligned process, the widths of the first lightly doped region 123 and the second lightly doped region 124 can be customized respectively by setting the position of the gate 11. That is, the widths of the first lightly doped region 123 and the second lightly doped region 124 in the first transistor T1 prepared by the non-self-aligned process can be different.

[0129] In addition, it can be understood that the first lightly doped region 123 and the second lightly doped region 124 can be equivalent to a resistor. When carriers flow from the first conductor region 121 to the second conductor region 122, the first lightly doped region 123 and the second lightly doped region 124 can bear part of the voltage.

[0130] In the present disclosure, the feasibility of the array substrate 10 is verified. The widths of the first lightly doped region 123 and the second lightly doped region 124 of the reference array substrate 10 are equal, and the widths of the first lightly doped region 123 and the second lightly doped region 124 are both 0.75 μm. Under the same working conditions, the reference array substrate 10 will have NG (No Good) phenomenon after 3 hours. When the width of the first lightly doped region 123 is greater than the width of the second lightly doped region 124, under the same working conditions, the working state of the array substrate 10 is still good after 24 hours.

[0131] In the embodiment of the present disclosure, by setting the first lightly doped region 123 and the second lightly doped region 124, the first lightly doped region 123 and the second lightly doped region 124 act as resistors, so that the first lightly doped region 123 and the second lightly doped region 124 can share the voltage drop, that is, the first lightly doped region 123 and the second lightly doped region 124 can bear part of the voltage, thereby reducing the voltage division of the channel region 120, achieving high voltage resistance of the channel region 120, thereby improving the voltage resistance performance of the first transistor T1, extending the service life of the first transistor T1, and thus extending the service life of the array substrate 10; by setting the first lightly doped region 123 and the second lightly doped region 124, it is also possible to effectively The leakage current of the first transistor T1 is reduced, the power consumption of the first transistor T1 is reduced, and the performance of the array substrate 10 is improved; on the other hand, the width of the first lightly doped region 123 located at the input end of the first transistor T1 is greater than the width of the second lightly doped region 124 located at the output end of the first transistor T1, which improves the problem that the input end of the first transistor T1 is more easily damaged due to hot carrier effect and self-heating effect and device failure occurs due to the harsh working conditions of the first transistor T1 and the input end of the first transistor T1 is always in an AC bias state, thereby improving the performance of the first transistor T1 and extending the service life of the array substrate 10.

[0132] In some embodiments, a ratio of the width of the first lightly doped region 123 to the width of the second lightly doped region 124 is greater than 1 and less than or equal to 1.8.

[0133] For example, the ratio of the width of the first lightly doped region 123 to the width of the second lightly doped region 124 may be 1.1, 1.2, 1.4, 1.6, 1.8, etc. The embodiments of the present disclosure are not limited to this.

[0134] For example, when the width of the first lightly doped region 123 is 1.8 μm, the width of the second lightly doped region 124 is 1.0 μm, 1.2 μm, and so on.

[0135] By adopting the above-mentioned setting, it is ensured that the width of the first lightly doped region 123 is greater than the width of the second lightly doped region 124, thereby improving the problem that the input end of the first transistor T1 is more easily damaged due to hot carrier effect and self-heating effect and device failure occurs due to the harsh working conditions of the first transistor T1 and the input end of the first transistor T1 is always in an AC bias state, thereby improving the performance of the first transistor T1 and extending the service life of the array substrate 10.

[0136] In some embodiments, the width of the first lightly doped region 123 is greater than 1.4 μm and less than or equal to 1.8 μm; the width of the second lightly doped region 124 is greater than or equal to 1 μm and less than 1.4 μm.

[0137] For example, the width of the first lightly doped region 123 may be 1.5 μm, 1.55 μm, 1.6 μm, 1.7 μm, 1.8 μm, etc. The embodiments of the present disclosure are not limited thereto. For example, the width of the second lightly doped region 124 may be 1 μm, 1.1 μm, 1.15 μm, 1.2 μm, 1.3 μm, etc. The embodiments of the present disclosure are not limited thereto.

[0138] As can be seen from the above, the first lightly doped region 123 and the second lightly doped region 124 can be equivalent to a resistor. Compared with the transistor in the prior art, by increasing the width of the first lightly doped region 123 and the width of the second lightly doped region 124, the voltage that the first lightly doped region 123 and the second lightly doped region 124 can bear is further increased, and the voltage division of the channel region 120 is further reduced to achieve a high withstand voltage of the channel region 120, thereby improving the withstand voltage performance of the first transistor T1; on the other hand, the width of the first lightly doped region 123 and the width of the second lightly doped region 124 of the first transistor T1 are longer than the width of the lightly doped region of the transistor in the prior art. It can also make the leakage current of the first transistor T1 smaller and the power consumption lower; at the same time, it ensures that the width of the first lightly doped region 123 located at the input end of the first transistor T1 is greater than the width of the second lightly doped region 124 located at the output end of the first transistor T1, which can improve the problem that the input end of the first transistor T1 is more easily damaged due to hot carrier effect and self-heating effect and device failure occurs due to the harsh working conditions of the first transistor T1 and the input end of the first transistor T1 is always in an AC bias state, thereby improving the performance of the first transistor T1 and extending the service life of the array substrate 10.

[0139] In addition, while increasing the width of the first lightly doped region 123 at the input end of the first transistor T1 and improving the problem that the input end of the first transistor T1 is more easily damaged and thus causes device failure, the width of the second lightly doped region 124 at the output end of the first transistor T1 is relatively reduced, that is, the sum of the width of the first lightly doped region 123 and the width of the second lightly doped region 124 is ensured to be within a certain range, thereby ensuring that the first transistor T1 has a higher on-state current and better switching performance, thereby ensuring the charging efficiency of the first transistor T1.

[0140] In some embodiments, Fig.11 As shown, the gate 11 of the first transistor T1 includes at least two sub-gates arranged along the first direction X; the channel region 120 of the first transistor T1 includes at least two sub-channel regions, each sub-channel region and a sub-gate overlap in the thickness direction of the array substrate 10; the active layer 12 also includes at least one third lightly doped region 125 located between two adjacent sub-channel regions; the width of the third lightly doped region 125 is smaller than the width of the first lightly doped region 123.

[0141] Exemplarily, the gate 11 of the first transistor T1 may include two or more sub-gates, which is not limited in the embodiments of the present disclosure.

[0142] It is understandable that one sub-gate is provided corresponding to one sub-channel region. That is, the number of sub-gates is equal to the number of sub-channel regions. For example, the gate 11 of the first transistor T1 includes two sub-gates, and the channel region 120 of the first transistor T1 also includes two sub-channel regions.

[0143] For example, Fig.11 As shown, the gate 11 of the first transistor T1 includes two sub-gates, namely a first sub-gate 111 and a second sub-gate 112. The channel region 120 of the first transistor T1 includes two sub-channel regions, namely a first sub-channel region 1201 and a second sub-channel region 1202.

[0144] The first sub-channel region 1201 and the first sub-gate 111 are arranged correspondingly, and the second sub-channel region 1202 and the second sub-gate 112 are arranged correspondingly. For example, the first sub-gate 111 completely covers the first sub-channel region 1201 ; the second sub-gate 112 completely covers the second sub-channel region 1202 .

[0145] For example, Fig.11 As shown, in the case where the gate 11 of the first transistor T1 includes two sub-gates, the active layer 12 includes two third lightly doped regions 125 located between the adjacent first sub-channel regions 1201 and the second sub-channel regions 1202 .

[0146] Exemplarily, the widths of the two third lightly doped regions 125 located between the adjacent first sub-channel regions 1201 and the second sub-channel regions 1202 are equal or substantially equal.

[0147] Furthermore, the widths of the two third lightly doped regions 125 located between the adjacent first sub-channel regions 1201 and the second sub-channel regions 1202 are equal to or substantially equal to the width of the second lightly doped region 124 .

[0148] In this embodiment, the first transistor T1 adopts a dual-gate structure, which can further reduce the leakage current of the first transistor T1, reduce the probability of hot carrier effect, ensure the working performance of the first transistor T1, and improve the performance of the array substrate 10; at the same time, at least one third lightly doped region 125 is set between two adjacent sub-channel regions, which further increases the sum of the widths of multiple lightly doped regions of the first transistor T1 (including: the first lightly doped region 123, the second lightly doped region 124 and the third lightly doped region 125), further reduces the leakage current of the first transistor T1, and reduces the probability of hot carrier occurrence.

[0149] In addition, the width of the third lightly doped region 125 is smaller than the width of the first lightly doped region 123, which ensures that the width of the first lightly doped region 123 located at the input end of the first transistor T1 in the first transistor T1 is larger than the width of the third lightly doped region 125 and the second lightly doped region 124 located at the output end of the first transistor T1, thereby improving the problem that the input end of the first transistor T1 is more easily damaged due to the hot carrier effect and the self-heating effect and the device fails due to the harsh working conditions of the first transistor T1 and the input end of the first transistor T1 is always in the AC bias state, thereby improving the performance of the first transistor T1 and extending the service life of the array substrate 10; it can also ensure that the sum of the widths of multiple lightly doped regions (including: the first lightly doped region 123, the second lightly doped region 124 and the third lightly doped region 125) in the first transistor T1 is not too large, thereby ensuring that the first transistor T1 has a higher on-state current, ensuring that the switching performance of the first transistor T1 is good, and thus ensuring the charging efficiency of the first transistor T1.

[0150] In some embodiments, Fig.11 As shown, the width of the third lightly doped region 125 is equal to the width of the second lightly doped region 124. For example, the width of the second lightly doped region 124 and the width of the third lightly doped region 125 are both 1.2 μm. For another example, the width of the second lightly doped region 124 and the width of the third lightly doped region 125 are both 1.3 μm. The embodiments of the present disclosure are not limited to this.

[0151] In the present embodiment, on the basis of increasing the sum of the widths of the plurality of lightly doped regions (including: the first lightly doped region 123, the second lightly doped region 124 and the third lightly doped region 125) of the first transistor T1, further reducing the leakage current of the first transistor T1 and reducing the probability of occurrence of hot carriers, the width of the third lightly doped region 125 is made equal to the width of the second lightly doped region 124 having a smaller width, thereby ensuring that the sum of the widths of the plurality of lightly doped regions (including: the first lightly doped region 123, the second lightly doped region 124 and the third lightly doped region 125) of the first transistor T1 is within a certain range, and also being able to reduce the problem that due to the large size of the first transistor T1, the shift register occupies a large area, resulting in a large size of the peripheral area BB of the array substrate 10, which is not conducive to the narrow frame design of the array substrate 10.

[0152] In addition, it can be known from the above that the multiple lightly doped regions (including: the first lightly doped region 123, the second lightly doped region 124 and the third lightly doped region 125) are equivalent to resistors. In this embodiment, the sum of the widths of the multiple lightly doped regions (including: the first lightly doped region 123, the second lightly doped region 124 and the third lightly doped region 125) of the first transistor T1 is within a certain range, and it is also possible to avoid the sum of the widths of the multiple lightly doped regions of the first transistor T1 being too large, thereby ensuring that the resistance between the first conductor region 121 and the second conductor region 122 is within a certain range, ensuring that the first transistor T1 has a higher on-state current, ensuring that the switching performance of the first transistor T1 is good, and thus ensuring the charging efficiency of the first transistor T1.

[0153] In some embodiments, Fig.11 As shown, the active layer 12 includes at least two active patterns 1200 arranged along the second direction Y, and the second direction Y is perpendicular to the first direction X. Each sub-gate extends along the second direction Y and overlaps with at least two active patterns in the thickness direction of the array substrate 10;

[0154] Each active pattern 1200 includes a first conductor region, a first lightly doped region, at least two sub-channel regions, a second lightly doped region and a second conductor region arranged along a first direction, and also includes at least one third lightly doped region located between two adjacent sub-channel regions.

[0155] For example, the number of active patterns 1200 included in the active layer 12 may be two or more, etc. The embodiments of the present disclosure are not limited to this.

[0156] Exemplarily, the gate 11 of the first transistor T1 is arranged in a comb shape in the first direction X. Thus, the stability of the first transistor T1 can be improved.

[0157] In some embodiments, Figure 6 and Fig.12 As shown, the shift register RS ​​further includes: a plurality of second transistors T2.

[0158] It should be noted that, for clearer labeling in the drawings and description in the specification, the plurality of second transistors T2 are respectively represented as a second transistor T21 , a second transistor T22 , a second transistor T23 , a second transistor T24 , and so on.

[0159] In some examples, combined Figure 6 and Fig.11 As shown, in the shift register RS, the first input module 201 includes a second transistor T21. The gate of the second transistor T21 in the first input module 201 is connected to the first input signal terminal STV, the first electrode is connected to the first control signal terminal CN, and the second electrode is connected to the first pull-up node PUCN.

[0160] In some examples, combined Figure 6 and Fig.12 As shown, the pull-down control module 202 includes three second transistors and a second capacitor C2. The two second transistors are respectively a second transistor T22, a second transistor T23, and a second transistor T24. In the pull-down control module 202, the gate and the first electrode of the second transistor T22 are connected to the second clock signal terminal CKB, and the second electrode is connected to the pull-down node PD; the gate of the second transistor T23 is connected to the first pull-up node PUCN, the first electrode is connected to the pull-down node PD, and the second electrode is connected to the first power signal terminal VGL-G. One end of the second capacitor C2 is connected to the first power signal terminal VGL-G, and the other end of the second capacitor C2 is connected to the pull-down node PD. The gate of the second transistor T24 is connected to the output terminal OUTPUT, the first electrode is connected to the pull-down node PD, and the second electrode is connected to the first power signal terminal VGL-G.

[0161] In some examples, combined Figure 6 and Fig.12 As shown, the pull-down module 204 includes two second transistors T2. The two second transistors are respectively a second transistor T25 and a second transistor T26. In the pull-down module 204, the gate of the second transistor T25 is connected to the pull-down node PD, the first electrode is connected to the first pull-up node PUCN, and the second electrode is connected to the first power signal terminal VGL-G; the gate of the second transistor T26 is connected to the pull-down node PD, the first electrode is connected to the output terminal OUTPUT, and the second electrode is connected to the first power signal terminal VGL-G.

[0162] In some examples, combined Figure 6 and Fig.12 As shown, the shift register RS ​​further includes: a second input module 205 .

[0163] The second input module 205 includes a second transistor T27. The second transistor T27 in the second input module 205 has a gate connected to the second signal input terminal RST, a first electrode connected to the second control voltage terminal CNB, and a second electrode connected to the first pull-up node PUCN.

[0164] The second input module 205 is configured to output the voltage of the second control voltage terminal CNB to the first pull-up node PUCN under the control of the signal of the second signal input terminal RST.

[0165] In some examples, combined Figure 6 and Fig.12 As shown, the shift register RS ​​further includes an anti-leakage module 206 .

[0166] The anti-leakage module 206 includes a second transistor T28. The gate of the second transistor T28 in the anti-leakage module 206 is connected to the second power signal terminal VGH-G, the first electrode is connected to the first pull-up node PUCN, and the second electrode is connected to the pull-up node PU.

[0167] The anti-leakage module 206 is configured to output the voltage of the first pull-up node PUCN to the pull-up node PU under the control of the signal of the second power signal terminal VGH-G.

[0168] In some examples, combined Figure 6 and Fig.12 As shown, the shift register RS ​​further includes: a reset module 207 .

[0169] The reset module 207 includes a second transistor T29. The gate of the second transistor T29 in the reset module 207 is connected to the reset signal terminal RESET, the first electrode is connected to the first pull-up node PUCN, and the second electrode is connected to the first power signal terminal VGL-G.

[0170] The reset module 207 is configured to reset the potential of the first pull-up node PUCN based on the signal of the first power signal terminal VGL-G under the control of the signal of the reset signal terminal RESET.

[0171] In some examples, combined Figure 6 and Fig.12 As shown, the shift register RS ​​further includes: a second output module 208 .

[0172] The second output module 208 includes a second transistor T210. The second transistor T210 in the second output module 208 has a gate connected to the touch signal terminal EN-Touch, a first electrode connected to the first power signal terminal VGL-G, and a second electrode connected to the output terminal OUTPUT.

[0173] The second output module 208 is configured to provide the signal of the first power signal terminal VGL-G to the output terminal OUTPUT under the control of the touch signal terminal EN-Touch, so that the output terminal OUTPUT outputs the signal of the first power signal terminal VGL-G.

[0174] Specifically, the second output module 208 can realize the signal output in the touch stage. In the touch stage, the signal of the touch signal terminal EN_Touch is at a high level, the internal circuit of the second output module 208 is turned on, and the signal of the first power signal terminal VGL-G can be output to the output terminal OUTPUT. The touch stage can be a stage in the output display stage of the shift register, or a stage in the non-display stage (such as the pre-charging stage or the reset stage) outside the output display stage. When the touch stage is a stage in the output display stage and the signal of the first power signal terminal VGL-G is at a low level, the output terminal OUTPUT outputs a low level, the shift register suspends driving the pixel, and the pixel connected to the shift register can suspend display.

[0175] It should be noted that the above structural descriptions of the first input module 201, the pull-down control module 202, the pull-down module 204, the second input module 205, the anti-leakage module 206, the reset module 207 and the second output module 208 are all exemplary descriptions, and are not limitations on the specific structures of each circuit. The specific structures of the first input module 201, the pull-down control module 202, the pull-down module 204, the second input module 205, the anti-leakage module 206, the reset module 207 and the second output module 208 can be selected and set according to actual needs, and it is only necessary to ensure that the functions of the corresponding circuits are realized.

[0176] In some examples, the second transistor T2 includes: a gate and an active layer; the active layer of the second transistor T2 includes a first conductor region, a second conductor region, and a channel region between the first conductor region of the second transistor T2 and the second conductor region of the second transistor T2. The active layer of the second transistor T2 also includes a lightly doped region between the channel region of the second transistor T2 and the first conductor region of the second transistor T2 and between the channel region of the second transistor T2 and the second conductor region of the second transistor T2.

[0177] Wherein, along the arrangement direction of the channel region of the second transistor T2, the first conductor region of the second transistor T2, and the second conductor region of the second transistor, the width of the lightly doped region of the second transistor T2 ranges from 1.2 μm to 1.6 μm. For example, the width of the lightly doped region of the second transistor T2 may be 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, etc. The embodiments of the present disclosure are not limited to this.

[0178] Exemplarily, the widths of the two lightly doped regions on both sides of the channel region of the second transistor T2 may be equal or unequal. The embodiments of the present disclosure are not limited to this. For example, in the shift register provided in the embodiments of the present disclosure, the widths of the two lightly doped regions on both sides of the channel region of the second transistor T2 are equal, both of which are 1.4 μm.

[0179] In this embodiment, the width of the lightly doped region of the second transistor T2 is longer than that of the lightly doped region of the transistor in the prior art, so that the leakage current of the second transistor T2 is smaller and the power consumption is lower.

[0180] In addition, the widths of the two lightly doped regions on both sides of the channel region of the second transistor T2 are within a certain range, ensuring that the electron mobility of the second transistor T2 is high, that is, the second transistor T2 has a high on-state current, thereby ensuring that the switching performance of the second transistor T2 is good.

[0181] In some embodiments, in combination Figure 4 , the pixel unit 1 includes: a third transistor T3. That is, the pixel driving circuit 102 in the pixel unit 1 includes the third transistor T3.

[0182] As can be seen from the above, the shift register RS ​​is connected to a gate line GL, and is used to output a gate scanning signal to the gate line GL. A gate line GL is connected to the gate of the third transistor T3 in a row of pixel units 1. Under the control of the gate scanning signal output by the gate line GL, the third transistors T3 in a plurality of pixel units 1 connected to the gate line GL are turned on, and the data driving circuit 104 writes the pixel data voltage into the pixel electrode 101 in the pixel unit 1 through the third transistor T3 in the pixel unit 1.

[0183] For example, Fig.13 As shown, the third transistor T3 includes: a gate 31 and an active layer 32; the active layer 32 of the third transistor T3 includes a first conductor region 321, a second conductor region 322, and a channel region 320 located between the first conductor region 321 of the third transistor T3 and the second conductor region 322 of the third transistor T3.

[0184] The active layer 32 of the third transistor T3 further includes a lightly doped region 323 between the channel region 320 of the third transistor T3 and the first conductor region 321 of the third transistor T3 and between the channel region 320 of the third transistor T3 and the second conductor region 322 of the third transistor T3 .

[0185] Exemplarily, the third transistor T3 included in the pixel unit 1 may have a U-shaped double-gate structure. Fig.13 As shown, Fig.13 Schematic diagram of the U-shaped dual-gate planar structure of the transistor.

[0186] like Fig.13 As shown, the active layer 32 is substantially U-shaped. The first conductor region 321 and the second conductor region 322 are respectively located at two ends of the U-shaped structure.

[0187] In the direction perpendicular to the paper surface, the gate 31 and the active layer 32 partially overlap. The overlapping portion of the active layer 32 and the gate 31 is the channel region 320. The channel region 320 includes two sub-channel regions 3201. The active layer 32 of the third transistor T3 also includes two lightly doped regions 323 located between the two sub-channel regions 3201. That is. Both sides of each sub-channel region 3201 are adjacent to the sub-channel region 3201 and are provided with lightly doped regions 323. The third transistor T3 adopts a U-shaped dual-gate structure, which is conducive to saving space and improving the pixel aperture ratio of the array substrate 10; at the same time, the dual-gate structure also increases the length of the channel region 320 of the third transistor T3, and lightly doped regions 323 are provided on both sides of each sub-channel region 3201, thereby effectively reducing the leakage current of the third transistor T3.

[0188] In some examples, along the arrangement direction of the channel region 320 of the third transistor T3, the first conductor region 321 of the third transistor T3, and the second conductor region 322 of the third transistor T3, the width of the lightly doped region 323 of the third transistor T3 ranges from 1.2 μm to 1.6 μm. For example, the width of the lightly doped region 323 of the third transistor T3 may be 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, etc. The embodiments of the present disclosure are not limited to this.

[0189] In the present disclosure, the feasibility of the third transistor T3 is verified. The width of the lightly doped region of the reference third transistor T3 is 0.75 μm; the width of the lightly doped region 323 of the third transistor T3 in this embodiment is 1.4 μm. Under the same working conditions, for example, when the electron mobility of the reference third transistor T3 and the third transistor T3 in this embodiment is 78, the leakage current of the reference third transistor T3 is 7.25E-13; the leakage current of the third transistor T3 in this embodiment is 3.5E-13. Obviously, the leakage current of the third transistor T3 in this embodiment is small.

[0190] By adopting the above-mentioned configuration, the width of the lightly doped region 323 of the third transistor T3 is increased, and the lightly doped region 323 of the third transistor T3 can further reduce the electric field on the active layer 32 of the third transistor T3, reduce the hot carriers generated by the collision ionization caused by the electric field acceleration, thereby further reducing the leakage current of the third transistor T3 and reducing the power consumption; on the other hand, the width of the lightly doped region 323 of the third transistor T3 is ensured to be within a certain range, thereby ensuring that the third transistor T3 has a higher on-state current, ensuring that the switching performance of the third transistor T3 is better, thereby ensuring the charging efficiency of the third transistor T3, and realizing sufficient charging of the pixel electrode 101.

[0191] In some embodiments, the width of the lightly doped region of the second transistor T2 is equal to the width of the lightly doped region 323 of the third transistor T3. For example, the width of the lightly doped region of the second transistor T2 and the width of the lightly doped region 323 of the third transistor T3 are both 1.2 μm. For another example, the width of the lightly doped region of the second transistor T2 and the width of the lightly doped region 323 of the third transistor T3 are both 1.4 μm. The embodiments of the present disclosure are not limited to this.

[0192] In this embodiment, the width of the lightly doped region of the second transistor T2 is equal to the width of the lightly doped region 323 of the third transistor T3. Therefore, in the process of forming the lightly doped region of the second transistor T2 and the lightly doped region 323 of the third transistor T3, the same mask can be used, thereby saving masks, simplifying the preparation process of the array substrate 10, and reducing the production cost of the array substrate 10.

[0193] In some embodiments, the width of the first lightly doped region 123 of the first transistor T1 is greater than the width of the lightly doped region of the second transistor T2; and the width of the second lightly doped region 124 of the first transistor T1 is less than the width of the lightly doped region of the second transistor T2.

[0194] For example, the width of the lightly doped region of the second transistor T2 is 1.4 μm, the width of the first lightly doped region 123 of the first transistor T1 is 1.6 μm, and the width of the second lightly doped region 124 of the first transistor T1 is 1.2 μm.

[0195] In this embodiment, relative to the second transistor T2, the width of the second lightly doped region 124 of the first transistor T1 is reduced, and the width of the first lightly doped region 123 of the first transistor T1 is increased, so that the width of the first lightly doped region 123 located at the input end of the first transistor T1 in the first transistor T1 is ensured to be greater than the widths of the third lightly doped region 125 and the second lightly doped region 124 located at the output end of the first transistor T1, thereby improving the problem that the input end of the first transistor T1 is more easily damaged due to the hot carrier effect and the self-heating effect and thus the device fails due to the harsh working conditions of the first transistor T1 and the fact that the input end of the first transistor T1 is always in an AC bias state, thereby improving the performance of the first transistor T1 and extending the service life of the array substrate 10; and also ensuring that the sum of the width of the first lightly doped region 123 of the first transistor T1 and the width of the lightly doped region of the second transistor T2 is within a certain range, ensuring that the resistance between the first conductor region of the second transistor T2 and the second conductor region of the second transistor T2 is within a certain range, ensuring that the second transistor T2 has a higher on-state current, and ensuring that the switching performance of the second transistor T2 is better.

[0196] In some embodiments, the sum of the widths of the first lightly doped region 123 of the first transistor T1 and the second lightly doped region 124 of the first transistor T1 is equal to the sum of the widths of the lightly doped region of the second transistor T2 .

[0197] For example, the width of the lightly doped region between the channel region of the second transistor T2 and the first conductor region of the second transistor T2 and between the channel region of the second transistor T2 and the second conductor region of the second transistor T2 are both 1.4 μm. In this case, the width of the first lightly doped region 123 of the first transistor T1 may be 1.6 μm, and the width of the second lightly doped region 124 of the first transistor T1 may be 1.2 μm. For another example, the width of the first lightly doped region 123 of the first transistor T1 may be 1.5 μm, and the width of the second lightly doped region 124 of the first transistor T1 may be 1.3 μm. The embodiments of the present disclosure are not limited to this.

[0198] As can be seen from the above, the width of the first lightly doped region 123 of the first transistor T1 is greater than the width of the second lightly doped region 124 of the first transistor T1; on this basis, the sum of the widths of the first lightly doped region 123 of the first transistor T1 and the second lightly doped region 124 of the first transistor T1 is equal to the sum of the widths of the lightly doped regions of the second transistor T2, that is, on the basis of ensuring that the sum of the widths of the lightly doped regions in the first transistor T1 remains unchanged, the width of the first lightly doped region 123 of the first transistor T1 is increased, and the width of the second lightly doped region 124 of the first transistor T1 is reduced, which can avoid the widths of multiple lightly doped regions of the first transistor T1. The sum of the values ​​of the first and second conductor regions 121 and 122 is too large, thereby ensuring that the resistance between the first conductor region 121 and the second conductor region 122 is within a certain range, ensuring that the first transistor T1 has a higher on-state current, ensuring that the switching performance of the first transistor T1 is better, thereby ensuring the charging efficiency of the first transistor T1; it can also improve the problem that the input end of the first transistor T1 is more easily damaged due to the hot carrier effect and the self-heating effect and the device fails due to the harsh working conditions of the first transistor T1 and the fact that the input end of the first transistor T1 is always in the AC bias state, thereby improving the performance of the first transistor T1 and extending the service life of the array substrate 10.

[0199] In some embodiments, in combination Fig.14 and Fig.15 As shown, the array substrate 10 further includes a plurality of gate circuits (DEMUX) 105, which are electrically connected to at least two columns of pixel units 1 and are used to transmit data signals to at least two columns of pixel units 1 in a time-sharing manner. The gate circuit 105 includes a fourth transistor T4.

[0200] For example, Fig.14As shown, the data driving circuit 104 includes a first sub-data driving sub-circuit 1041 and a second sub-data driving sub-circuit 1042. The first sub-data driving sub-circuit 1041 and the second sub-data driving sub-circuit 1042 output data signals through the data lines DL.

[0201] Exemplarily, each gating circuit 105 may include at least two fourth transistors T4 .

[0202] For example, Fig.14 As shown, each gating circuit 105 includes two fourth transistors, and the two fourth transistors are respectively a fourth transistor T41 and a fourth transistor T42. The gates of the fourth transistors T41 and T42 are respectively connected to two MUX control lines (i.e., MUX-1 and MUX-2), the first electrodes of the fourth transistors T41 and T42 are both connected to the data driving circuit 104, and the second electrodes of the fourth transistors T41 and T42 are connected to two data signal output terminals in a one-to-one correspondence. Each data signal output terminal is respectively connected to a column of data lines DL, and is used to control the charging of the pixel unit 1 of the column.

[0203] In some examples, such as Fig.14 As shown, the display device 1000 may further include a main board 600 , which may be, for example, a printed circuit board (PCB) and may be used to provide electrical signals to the selection circuit 105 , that is, the signals of MUX- 1 and MUX- 2 are sent from the main board 600 .

[0204] For example Fig.14 The working process of the display device 1000 is schematically described as follows:

[0205] During the charging process of the pixel unit 1 , the gate lines GL are turned on row by row. After each row of gate lines GL is turned on, the working process of the display device is the same. Therefore, the working process of the display device 1000 after the first row of gate lines GL is turned on is described as an example.

[0206] like Fig.14As shown, MUX-1 and MUX-2 input the start signal in sequence, the fourth transistor T41 in the gating circuit 105 connected to MUX-1 is turned on, and the data signal is sequentially transmitted to the corresponding data signal output terminal, etc., and the data lines DL of the odd columns connected to these data signal output terminals receive the corresponding data signals, so that the pixel units 1 located in the odd columns are charged. Then, when MUX-2 inputs the start signal, the fourth transistor T42 in the gating circuit 105 connected to MUX-2 is turned on, and the data signal is sequentially transmitted to the corresponding first data signal output terminal, etc., and the data lines DL of the even columns connected to these data signal output terminals receive the corresponding data signals, so that the pixel units 1 located in the even columns are charged.

[0207] After a row of pixel units 1 is fully charged, the pixel units 1 continue to display corresponding grayscale colors under the action of the pixel circuits in the pixel units 1 .

[0208] After each row of gate lines GL is input with a scanning signal, the display device 1000 repeats the above process until the scanning of pixel units 1 in all rows is completed, and finally the full-screen display is completed.

[0209] In some examples, the fourth transistor T4 includes: a gate and an active layer; the active layer of the fourth transistor T4 includes a first conductor region, a second conductor region, and a channel region between the first conductor region of the fourth transistor T4 and the second conductor region of the fourth transistor T4. The active layer of the fourth transistor T4 also includes a lightly doped region between the channel region of the fourth transistor T4 and the first conductor region of the fourth transistor T4 and between the channel region of the fourth transistor T4 and the second conductor region of the fourth transistor T4.

[0210] Among them, along the arrangement direction of the channel region of the fourth transistor T4, the first conductor region of the fourth transistor T4, and the second conductor region of the fourth transistor T4, the width of the lightly doped region of the fourth transistor T4 ranges from 1.0 μm to 1.4 μm. For example, the width of the lightly doped region of the fourth transistor T4 may be 1.0 μm, 1.05 μm, 1.2 μm, 1.3 μm, 1.4 μm, etc. The embodiments of the present disclosure are not limited to this.

[0211] Exemplarily, the widths of the two lightly doped regions on both sides of the channel region of the fourth transistor T4 may be equal or unequal. The embodiments of the present disclosure are not limited to this. For example, in the array substrate 10 provided in the embodiments of the present disclosure, the widths of the two lightly doped regions on both sides of the channel region of the fourth transistor T4 are equal, both of which are 1.3 μm.

[0212] It can be understood that the thin film transistor in the gating circuit 105 has a relatively high requirement on leakage current and a relatively high requirement on charging capability.

[0213] In this embodiment, the width of the lightly doped region of the fourth transistor T4 is longer than that of the lightly doped region of the transistor in the prior art, so that the leakage current of the fourth transistor T4 is smaller and the power consumption is lower; and the widths of the two lightly doped regions on both sides of the channel region of the fourth transistor T4 are within a certain range, thereby ensuring that the electron mobility of the fourth transistor T4 is high, that is, the fourth transistor T4 has a higher on-state current, thereby ensuring that the switching performance of the fourth transistor T4 is better and has a higher charging capacity.

[0214] In some embodiments, the width of the lightly doped region of the fourth transistor T4 is smaller than the width of the lightly doped region of the second transistor T2. For example, when the width of the lightly doped region of the second transistor T2 is 1.5 μm, the width of the lightly doped region of the fourth transistor T4 may be 1.2 μm, 1.3 μm, etc.

[0215] As can be seen from the above, the first transistor T1 is more likely to have a hot carrier effect at the drain end, thereby causing the performance degradation of the thin film transistor, that is, the fourth transistor T4 is less likely to have a hot carrier effect at the drain end than the first transistor T1. In this embodiment, the width of the lightly doped region of the fourth transistor T4 is relatively small, and when the carriers flow from the first conductor region to the second conductor region of the fourth transistor T4, it is equivalent to reducing the resistance and increasing the voltage drop, thereby ensuring a higher on-state current, improving the switching characteristics of the fourth transistor T4, and improving the charging capacity of the gating circuit 105.

[0216] In addition, in the embodiments of the present disclosure, the widths of the lightly doped regions of the first transistor T1 with relatively stringent working conditions in the shift register, the plurality of second transistors T2 other than the first transistor T1 in the shift register, the third transistor T3 in the pixel unit 1, and the fourth transistor T4 in the selection circuit 105 are customized respectively, that is, the lengths of the lightly doped regions of the plurality of thin film transistors with different functions are set differently, so that the performances of the plurality of thin film transistors with different functions are matched with the functions, thereby improving the performance of the thin film transistors, reducing the power consumption of the thin film transistors, and thus improving the performance of the array substrate 10.

[0217] In some embodiments, the ion dose in the first conductor region is 1E15 / cm2; and / or, the ion dose in the second conductor region is 1E15 / cm2.

[0218] It should be noted that the first conductor region here may be the first conductor region of the first transistor T1, the first conductor region of the second transistor T2, the first conductor region of the third transistor T3 and / or the first conductor region of the fourth transistor T4; the second conductor region here may be the second conductor region of the first transistor T1, the second conductor region of the second transistor T2, the second conductor region of the third transistor T3 and / or the second conductor region of the fourth transistor T4.

[0219] In some examples, the ion dose in the first conductor region is 1E15 / cm2; in other examples, the ion dose in the second conductor region is 1E15 / cm2; in still other examples, the ion dose in the first conductor region is 1E15 / cm2; and the ion dose in the second conductor region is 1E15 / cm2.

[0220] Exemplarily, after adjusting the ion dose in the first conductor region and the ion dose in the second conductor region, the electron mobility of the corresponding thin film transistor (for example, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4) is maintained at the same level as the electron mobility of the thin film transistor in the prior art. That is, while reducing the leakage current of the thin film transistor by adjusting the width of the lightly doped region of the thin film transistor, by adjusting the ion dose in the first conductor region and the second conductor region, the corresponding thin film transistor has a higher on-state current, ensuring that the switching performance of the thin film transistor is better.

[0221] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: A plurality of pixel units arranged in an array; Multiple cascaded shift registers; An output end of the shift register is electrically connected to at least one row of pixel units, and is used to provide a gate scanning signal to at least one row of pixel units; The shift register comprises a first transistor, the first transistor comprises a gate and an active layer, the active layer comprises a first conductor region, a second conductor region, and a channel region located between the first conductor region and the second conductor region; the first conductor region is connected to a clock signal terminal, and the second conductor region is connected to an output terminal of the shift register; the first transistor is used to receive a clock signal from the clock signal terminal and output the gate scanning signal; The active layer also includes a first lightly doped region located between the channel region and the first conductor region, and a second lightly doped region located between the channel region and the second conductor region, and the width of the first lightly doped region is greater than the width of the second lightly doped region; wherein the width is the size of the first lightly doped region or the second lightly doped region in a first direction, and the first direction is the arrangement direction of the first conductor region, the channel region, and the second conductor region.

2. The array substrate according to claim 1, characterized in that: A ratio of a width of the first lightly doped region to a width of the second lightly doped region is greater than 1 and less than or equal to 1.

8.

3. The array substrate according to claim 2, characterized in that: The width of the first lightly doped region is greater than 1.4 μm and less than or equal to 1.8 μm; The width of the second lightly doped region is greater than or equal to 1 μm and less than 1.4 μm.

4. The array substrate according to claim 1, characterized in that: The gate of the first transistor includes at least two sub-gates arranged along the first direction; The channel region of the first transistor includes at least two sub-channel regions, and each of the sub-channel regions overlaps with one of the sub-gates in the thickness direction of the array substrate; The active layer further includes at least one third lightly doped region located between two adjacent sub-channel regions; a width of the third lightly doped region is smaller than a width of the first lightly doped region.

5. The array substrate according to claim 4, characterized in that: The width of the third lightly doped region is equal to the width of the second lightly doped region.

6. The array substrate according to claim 4, characterized in that: The active layer includes at least two active patterns arranged along a second direction, the second direction being perpendicular to the first direction; each of the sub-gates extends along the second direction and overlaps with the at least two active patterns in a thickness direction of the array substrate; Each of the active patterns includes a first conductor region, a first lightly doped region, at least two sub-channel regions, a second lightly doped region and a second conductor region arranged along the first direction, and also includes at least one third lightly doped region located between two adjacent sub-channel regions.

7. The array substrate according to claim 1, characterized in that: The shift register further includes: a plurality of second transistors, wherein the second transistors include: a gate and an active layer; the active layer of the second transistors includes a first conductor region, a second conductor region, and a channel region located between the first conductor region of the second transistor and the second conductor region of the second transistor; The active layer of the second transistor further includes a lightly doped region between the channel region of the second transistor and the first conductor region of the second transistor and between the channel region of the second transistor and the second conductor region of the second transistor; Along the arrangement direction of the channel region of the second transistor, the first conductor region of the second transistor and the second conductor region of the second transistor, the width of the lightly doped region of the second transistor ranges from 1.2 μm to 1.6 μm.

8. The array substrate according to claim 7, characterized in that: The pixel unit comprises: a third transistor; the third transistor comprises: a gate and an active layer; the active layer of the third transistor comprises a first conductor region, a second conductor region, and a channel region located between the first conductor region of the third transistor and the second conductor region of the third transistor; The active layer of the third transistor further includes a lightly doped region between the channel region of the third transistor and the first conductor region of the third transistor and between the channel region of the third transistor and the second conductor region of the third transistor; Along the arrangement direction of the channel region of the third transistor, the first conductor region of the third transistor and the second conductor region of the third transistor, the width of the lightly doped region of the third transistor ranges from 1.2 μm to 1.6 μm.

9. The array substrate according to claim 8, characterized in that: The width of the lightly doped region of the second transistor is equal to the width of the lightly doped region of the third transistor.

10. The array substrate according to claim 7, characterized in that: The width of the first lightly doped region of the first transistor is greater than the width of the lightly doped region of the second transistor; and the width of the second lightly doped region of the first transistor is less than the width of the lightly doped region of the second transistor.

11. The array substrate according to claim 7, characterized in that: A sum of a width of the first lightly doped region of the first transistor and a width of the second lightly doped region of the first transistor is equal to a sum of widths of the two lightly doped regions of the second transistor.

12. The array substrate according to claim 7, characterized in that: The array substrate further comprises a plurality of gating circuits, wherein the gating circuits are electrically connected to at least two columns of the pixel units and are used to transmit data signals to the at least two columns of the pixel units in a time-sharing manner; The gating circuit includes a fourth transistor, the fourth transistor includes: a gate and an active layer; the active layer of the fourth transistor includes a first conductor region, a second conductor region, and a channel region located between the first conductor region of the fourth transistor and the second conductor region of the fourth transistor; The active layer of the fourth transistor further includes a lightly doped region between the channel region of the fourth transistor and the first conductor region of the fourth transistor and between the channel region of the fourth transistor and the second conductor region of the fourth transistor; Along the arrangement direction of the channel region of the fourth transistor, the first conductor region of the fourth transistor and the second conductor region of the fourth transistor, the width of the lightly doped region of the fourth transistor ranges from 1.0 μm to 1.4 μm.

13. The array substrate according to claim 12, characterized in that ； The width of the lightly doped region of the fourth transistor is smaller than the width of the lightly doped region of the second transistor.

14. The array substrate according to any one of claims 1 to 13, characterized in that: The ion dose of the first conductor region is 1E15 / cm2; and / or, The ion dose in the second conductor region is 1E15 / cm2.

15. A display device, characterized in that: include: The array substrate according to any one of claims 1 to 14.

Images