Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a manufacturing method thereof, the semiconductor device comprising: a substrate; a conductive layer, arranged on the substrate; an interlayer dielectric layer, covering the conductive layer; a MIM capacitor structure, arranged in the interlayer dielectric layer, wherein the MIM capacitor structure comprises: a first substrate layer, extending along a first direction, the first direction being parallel to the surface of the conductive layer; an insulating layer, covering at least part of the outer surface of the first substrate layer parallel to the first direction; a second substrate layer, covering at least part of the outer surface of the insulating layer parallel to the first direction, and the second substrate layer is in contact with the conductive layer, and the first substrate layer and the second substrate layer are electrically isolated by the insulating layer. The solution of the present application can increase the area of ​​the MIM capacitor structure along the first direction, thereby increasing the capacitance value of the MIM capacitor structure, so that the capacitance value of the MIM capacitor structure is not limited by its height.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) sensing technology has been widely used in machine vision, automobiles, analytical instruments, absorption imaging, and medical applications. In order to improve the accuracy of sensing under a wide range of lighting conditions, wide dynamic range (WDR) performance and higher signal-to-noise ratio (SNR) are required.

[0003] In the related technology, the Lateral Overflow Integrated Capacitor (LOFIC) technology is generally used to meet the WDR and high and low SNR of CIS. Among them, the LOFIC technology generally uses a trench metal-insulator-metal (MIM) capacitor structure, among which the capacitance value of the trench MIM capacitor structure is the key factor affecting the WDR performance and SNR.

[0004] The capacitance value of the trench MIM capacitor structure is positively correlated with the area. However, the trench MIM capacitor structure in the related art is affected by its height, and the capacitor area cannot be further increased, resulting in failure to meet WDR performance and SNR requirements.

[0005] Improvements are therefore needed to at least partially address the above-mentioned problems. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] In view of the existing problems, the present application provides a semiconductor device, including:

[0008] substrate;

[0009] A conductive layer is disposed on the substrate;

[0010] an interlayer dielectric layer, covering the conductive layer;

[0011] A MIM capacitor structure is disposed in the interlayer dielectric layer, wherein the MIM capacitor structure includes:

[0012] A first substrate layer extending along a first direction, wherein the first direction is parallel to a surface of the conductive layer;

[0013] an insulating layer covering at least a portion of an outer surface of the first substrate layer parallel to the first direction;

[0014] The second substrate layer covers at least a portion of the outer surface of the insulating layer parallel to the first direction, and the second substrate layer is in contact with the conductive layer, and the first substrate layer and the second substrate layer are electrically isolated by the insulating layer.

[0015] Exemplarily, one end of the first substrate layer along the first direction has a connecting portion, and the connecting portion protrudes from the second substrate layer along the first direction;

[0016] The invention also includes a first connection structure and a second connection structure which are arranged at intervals. The first connection structure penetrates the interlayer dielectric layer and is in electrical contact with the conductive layer, and the second connection structure is in electrical contact with the connection portion.

[0017] Exemplarily, the connecting portion further protrudes from the insulating layer along the first direction.

[0018] Exemplarily, the material of the first substrate layer and the second substrate layer includes Ti or TiN;

[0019] The material of the insulating layer includes oxide or nitride.

[0020] Exemplarily, the material of the conductive layer, the first connection structure and the second connection structure includes Cu, Mn or Cu-Mn alloy;

[0021] The material of the interlayer dielectric layer includes silicon oxide, optional coated glass or tetraethoxysilane.

[0022] Exemplarily, the semiconductor device is a CMOS image sensor.

[0023] Another aspect of the present application provides a method for manufacturing a semiconductor device, comprising:

[0024] Providing a substrate, on which a conductive layer is disposed;

[0025] An interlayer dielectric layer covering the conductive layer and a MIM capacitor structure located in the interlayer dielectric layer are formed, wherein the MIM capacitor structure comprises:

[0026] A first substrate layer extending along a first direction, wherein the first direction is parallel to a surface of the conductive layer;

[0027] an insulating layer covering at least a portion of an outer surface of the first substrate layer parallel to the first direction;

[0028] The second substrate layer covers at least a portion of the outer surface of the insulating layer parallel to the first direction, and the second substrate layer is in contact with the conductive layer, and the first substrate layer and the second substrate layer are electrically isolated by the insulating layer.

[0029] Exemplarily, one end of the first substrate layer along the first direction has a connecting portion, and the connecting portion protrudes from the second substrate layer and the insulating layer;

[0030] An interlayer dielectric layer covering the conductive layer and a MIM capacitor structure located in the interlayer dielectric layer are formed, comprising:

[0031] forming a first interlayer dielectric material layer on the conductive layer;

[0032] Etching the first interlayer dielectric material layer to form a first trench exposing a portion of the surface of the conductive layer;

[0033] sequentially forming a first substrate material layer and a first insulating material layer on the bottom and sidewalls of the first trench;

[0034] Etching and removing the first substrate material layer and the first insulating material layer located on the sidewall of the first trench perpendicular to the first direction;

[0035] forming a second interlayer dielectric material layer filling the first trench;

[0036] At least partially etching the second interlayer dielectric material layer to form a second trench, wherein the bottom and sidewalls of the second trench expose the first insulating material layer, and one end of the second trench along the first direction protrudes from the first insulating material layer and the first substrate material layer;

[0037] forming a first substrate layer filling the second groove, wherein one end of the first substrate layer protruding from the first insulating material layer and the first substrate material layer along the first direction is the connecting portion;

[0038] forming a second insulating material layer, wherein the second insulating material layer covers a portion of the surface of the first substrate layer and the first insulating material layer, and the first insulating material layer and the second insulating material layer constitute the insulating layer;

[0039] forming a second substrate material layer, wherein the second substrate material layer covers the second insulating material layer and the first substrate material layer, and the first substrate material layer and the second substrate material layer constitute the second substrate layer;

[0040] A third interlayer dielectric material layer is formed, and the third interlayer dielectric material layer covers a portion of the surface of the first substrate layer, the second substrate material layer, the first interlayer dielectric material layer and the second interlayer dielectric material layer, and the first interlayer dielectric material layer, the second interlayer dielectric material layer and the third interlayer dielectric material layer constitute the interlayer dielectric layer.

[0041] Exemplarily, after forming an interlayer dielectric layer covering the conductive layer and a MIM capacitor structure located in the interlayer dielectric layer, the step also includes forming a first connection structure and a second connection structure that are spaced apart, wherein the first connection structure passes through the interlayer dielectric layer and is in electrical contact with the conductive layer, and the second connection structure is in electrical contact with the connection portion.

[0042] Exemplarily, forming the first connection structure and the second connection structure that are spaced apart includes:

[0043] Etching the interlayer dielectric layer to form a first through hole exposing the conductive layer and a second through hole exposing the connecting portion, respectively;

[0044] Conductive materials are filled into the first through hole and the second through hole respectively to obtain the first connection structure and the second connection structure.

[0045] The semiconductor device and the manufacturing method thereof according to the embodiments of the present application can increase the area of ​​the MIM capacitor structure along the first direction, thereby increasing the capacitance value of the MIM capacitor structure, so that the capacitance value of the MIM capacitor structure is not limited by its height. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, and are used to explain the principles of the present application. In the drawings:

[0047] Figure 1-Figure 12 A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;

[0048] Fig.13 A flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0049] Reference numerals:

[0050] 100, substrate; 110, conductive layer; 120, interlayer dielectric layer; 121, first interlayer dielectric material layer; 122, second interlayer dielectric material layer; 123, third interlayer dielectric material layer; 131, first groove; 132, second groove; 140, second substrate layer; 141, first substrate material layer; 142, second substrate material layer; 150, insulating layer; 151, first insulating material layer; 152, second insulating material layer; 160, first substrate layer; 161, connecting portion; 171, first connecting structure; 172, second connecting structure. DETAILED DESCRIPTION

[0051] Next, the present application will be described more completely in conjunction with the accompanying drawings, in which embodiments of the present application are shown. However, the present application can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated. The same reference numerals throughout represent the same elements.

[0052] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part.

[0053] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0054] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field of this application. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0057] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementations.

[0058] Therefore, in view of the existence of the aforementioned technical problems, the present application proposes a semiconductor device, comprising:

[0059] substrate;

[0060] A conductive layer is disposed on the substrate;

[0061] an interlayer dielectric layer covering the conductive layer;

[0062] The MIM capacitor structure is arranged in the interlayer dielectric layer, wherein the MIM capacitor structure includes:

[0063] A first substrate layer extending along a first direction, wherein the first direction is parallel to a surface of the conductive layer;

[0064] an insulating layer covering at least a portion of an outer surface of the first substrate layer parallel to the first direction;

[0065] The second substrate layer covers at least a portion of the outer surface of the insulating layer parallel to the first direction, and the second substrate layer is in contact with the conductive layer, and the first substrate layer and the second substrate layer are electrically isolated by the insulating layer.

[0066] The semiconductor device of the present application can increase the area of ​​the MIM capacitor structure along the first direction, thereby increasing the capacitance value of the MIM capacitor structure, so that the capacitance value of the MIM capacitor structure is not limited by its height.

[0067] Embodiment 1

[0068] Below, reference Figure 1-Figure 12 The semiconductor device of the present application is described in detail, wherein: Figure 1-Figure 12 The cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. Figure 1-Figure 5 as well as Fig.12 All shown are cross-sectional schematic diagrams along the first direction, Figure 6 (a) Figure 7 (a) Figure 8 (a) Fig. 9 (a) Fig.10 (a) and Fig.11 (a) is a cross-sectional schematic diagram along the first direction, Figure 6 (b) Figure 7 (b) Figure 8 (b) Fig. 9 (b) Fig.10 (b) and Fig.11 (b) is a schematic cross-sectional view along the second direction, and the second direction is perpendicular to the first direction.

[0069] In one example, if Fig.12 As shown, the semiconductor device of the present application includes: a substrate 100, a conductive layer 110, an interlayer dielectric layer 120 and a MIM capacitor structure.

[0070] In one example, the substrate 100 is a silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 100 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI). Although several examples of materials that can form the substrate 100 are described herein, any material that can be used as the substrate 100 falls within the spirit and scope of the present invention. In some examples, the substrate 100 may also include a silicon substrate and active devices or passive devices such as transistors and diodes formed in and / or on the silicon substrate.

[0071] In one example, if Fig.12 As shown, the conductive layer 110 is disposed on the substrate 100. The material of the conductive layer 110 includes Cu, Mn or Cu-Mn alloy, or it can also be any other suitable conductive material, or it can also be a conductive layer used to electrically connect to other devices in the substrate, such as transistors, photodiodes, etc.

[0072] In one example, if Fig.12 As shown, the interlayer dielectric layer 120 covers the conductive layer 110, and the material of the interlayer dielectric layer 120 includes silicon oxide, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, such as undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). The material of the interlayer dielectric layer 120 may also include boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).

[0073] In one example, if Fig.12As shown, the MIM capacitor structure is arranged in the interlayer dielectric layer 120, and the MIM capacitor structure includes a first substrate layer 160, an insulating layer 150 and a second substrate layer 140, the second substrate layer 140 is in contact with the conductive layer 110, and the first substrate layer 160 and the second substrate layer 140 are electrically isolated by the insulating layer 150. Exemplarily, the material of the first substrate layer 160 and the second substrate layer 140 includes Ti or TiN, or can also be any other suitable conductive material, which is not limited in this application. Exemplarily, the material of the insulating layer 150 includes oxides or nitrides, such as silicon oxide, silicon nitride, etc.

[0074] In one example, if Fig.12 As shown, the first substrate layer 160, the insulating layer 150 and the second substrate layer 140 all extend along a first direction, and the first direction is parallel to the surface of the conductive layer 110. The insulating layer 150 covers at least a portion of the surface of the first substrate layer 160 parallel to the first direction, and the second substrate layer 140 covers at least a portion of the surface of the insulating layer 150 parallel to the first direction. Fig.12 As shown, the second direction is perpendicular to the first direction. Taking the first substrate layer 160 as an example, which is generally in the shape of a rectangle extending along the first direction, the insulating layer 150 covers at least part of the four outer surfaces of the first substrate layer 160 parallel to the first direction, and the second substrate layer 140 covers at least part of the four outer surfaces of the insulating layer 150 parallel to the first direction. At this time, in the direction perpendicular to the first direction, the first substrate layer 160, the insulating layer 150 and the second substrate layer 140 constitute a MIM capacitor structure.

[0075] In one example, taking the stacking of the conductive layer 110 and the substrate 100 along the vertical direction as an example, the vertical direction is the height direction of the MIM capacitor structure, and the first direction is the horizontal direction. The first substrate layer 160, the insulating layer 150 and the second substrate layer 140 all extend along the first direction, and the insulating layer 150 covers at least part of the surface of the first substrate layer 160 parallel to the first direction, and the second substrate layer 140 covers at least part of the surface of the insulating layer 150 parallel to the first direction. The area of ​​the MIM capacitor structure can be increased along the first direction (i.e., the horizontal direction), thereby increasing the capacitance value of the MIM capacitor structure, so that the capacitance value of the MIM capacitor structure will not be limited by the height. At the same time, the MIM capacitor structure of the present application is a 3D fully-encapsulated structure, the insulating layer 150 covers at least a portion of the entire outer surface of the first substrate layer 160 parallel to the first direction, and the second substrate layer 140 covers at least a portion of the entire outer surface of the insulating layer 150 parallel to the first direction. Compared with the planar MIM capacitor structure in the related art, the MIM capacitor structure of the present application has a larger area and a larger capacitance value when the length is the same (taking extension along the first direction as an example, the length is the length along the first direction).

[0076] In one example, the semiconductor device of the present application may be a CMOS image processor, and the MIM capacitor structure of the present application may be a MIM capacitor structure in LOFIC technology. The capacitance value of the MIM capacitor structure of the present application is not limited by its height, and the area of ​​the MIM capacitor structure can be increased along the first direction, that is, the capacitance value of the MIM capacitor structure can be increased, so that more electrons can be stored, sensitivity and clarity can be improved, and WDR performance and higher SNR requirements can be met.

[0077] In one example, if Fig.12 As shown, one end of the first substrate layer 160 along the first direction has a connecting portion 161, and the connecting portion 161 protrudes from the second substrate layer 140 along the first direction; Fig.12 As shown, the semiconductor device of the present application also includes: a first connection structure 171 and a second connection structure 172 arranged at intervals, the first connection structure 171 penetrates the interlayer dielectric layer 120 and is in electrical contact with the conductive layer 110, the second connection structure 172 is in electrical contact with the connection portion 161, the first connection structure 171 is used to lead out the second substrate layer 140, and the second connection structure 172 is used to lead out the first substrate layer 160. Exemplarily, the second substrate layer 140 is in contact with the conductive layer 110, and the first connection structure 171 leads out the second substrate layer 140 by being in electrical contact with the conductive layer 110. Exemplarily, the second connection structure 172 leads out the first substrate layer 160 by being in electrical contact with the connection portion 161 protruding from the second substrate layer 140 along the first direction, thereby avoiding damage to the second substrate layer 140 and affecting the capacitance value and reliability of the MIM capacitor structure. Exemplarily, as Fig.12 As shown, the connecting portion 161 also protrudes from the insulating layer 150 along the first direction, so as to prevent the second connecting structure 172 from damaging the insulating layer 150 and affecting the reliability of the MIM capacitor structure. Exemplarily, the material of the first connecting structure 171 and the second connecting structure 172 includes Cu, Mn or Cu-Mn alloy, or can also be any other suitable conductive material.

[0078] In some embodiments, in the first direction, the two opposite ends of the insulating layer 150 may also protrude outward from the end of the second substrate layer 140, or may be flush with each other. In other embodiments, in the first direction, one end of the first substrate layer 160 away from its connection portion may protrude outward from the end of the second substrate layer 140, or may be flush with each other. This completes the introduction to the structure of the semiconductor device of the present application. The complete device may also include other components, which will not be described one by one here.

[0079] In summary, the semiconductor device of the present application can increase the area of ​​the MIM capacitor structure along the first direction, thereby increasing the capacitance of the MIM capacitor structure, so that the capacitance of the MIM capacitor structure is not limited by its height.

[0080] Embodiment 2

[0081] The present application also provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device of the first embodiment. Figure 1-Figure 12 as well as Fig.13 The method for manufacturing the semiconductor device of the present application is described in detail, wherein: Figure 1-Figure 12 A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown, Fig.13 The flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. Figure 1-Figure 5 as well as Fig.12 All shown are cross-sectional schematic diagrams along the first direction, Figure 6 (a) Figure 7 (a) Figure 8 (a) Fig. 9 (a) Fig.10 (a) and Fig.11 (a) is a cross-sectional schematic diagram along the first direction, Figure 6 (b) Figure 7 (b) Figure 8 (b) Fig. 9 (b) Fig.10 (b) and Fig.11 (b) is a schematic cross-sectional view along the second direction, and the second direction is perpendicular to the first direction.

[0082] Exemplarily, the method for manufacturing a semiconductor device of the present application includes the following steps:

[0083] First, execute step S1, such as Figure 1 As shown, a substrate 100 is provided, and a conductive layer 110 is disposed on the substrate 100 .

[0084] In one example, the substrate 100 is a silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 100 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 100 are described herein, any material that can be used as the substrate 100 falls within the spirit and scope of the present invention.

[0085] In one example, the material of the conductive layer 110 includes Cu, Mn, or a Cu-Mn alloy, or may be any other suitable conductive material.

[0086] Next, execute step S2, such as Figure 2-Figure 12 As shown, an interlayer dielectric layer 120 covering the conductive layer 110 and a MIM capacitor structure located in the interlayer dielectric layer 120 are formed, wherein the MIM capacitor structure includes: a first substrate layer 160 extending along a first direction, the first direction being parallel to the surface of the conductive layer; an insulating layer 150 covering at least part of the outer surface of the first substrate layer 160 parallel to the first direction; a second substrate layer 140 covering at least part of the outer surface of the insulating layer 150 parallel to the first direction, and the second substrate layer 140 is in contact with the conductive layer 110, and the first substrate layer 160 and the second substrate layer 140 are electrically isolated by the insulating layer 150. Exemplarily, the material of the first substrate layer 160 and the second substrate layer 140 includes Ti or TiN, or can also be any other suitable conductive material, which is not limited in the present application. Exemplarily; the material of the insulating layer 150 includes oxide or nitride, such as silicon oxide, silicon nitride, etc.

[0087] In one example, if Fig.12 As shown, the interlayer dielectric layer 120 covers the conductive layer 110, and the material of the interlayer dielectric layer 120 includes silicon oxide, including a material layer of doped or undoped silicon oxide formed by a thermal chemical vapor deposition (thermal CVD) manufacturing process or a high-density plasma (HDP) manufacturing process, such as undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). The material of the interlayer dielectric layer 120 may also include boron-doped or phosphorus-doped spin-on-glass (SOG), phosphorus-doped tetraethoxysilane (PTEOS) or boron-doped tetraethoxysilane (BTEOS).

[0088] In one example, if Fig.12As shown, one end of the first substrate layer 160 along the first direction has a connecting portion 161, and the connecting portion 161 protrudes from the second substrate layer 140 and the insulating layer 150. An interlayer dielectric layer 120 covering the conductive layer 110 and a MIM capacitor structure located in the interlayer dielectric layer 120 are formed, including:

[0089] First, if Figure 2 As shown, a first interlayer dielectric material layer 121 is formed on the conductive layer 110. The first interlayer dielectric material layer 121 can be formed by various deposition processes commonly used in the art, such as low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD), etc., and the present application does not impose any restrictions on this.

[0090] Then, if Figure 3 As shown, the first interlayer dielectric material layer 121 is etched to form a first groove 131 exposing a portion of the surface of the conductive layer 110. The first interlayer dielectric material layer 121 can be etched to form the first groove 131 using an etching process commonly used in the art, such as dry etching or wet etching, etc., and the present application does not impose any restrictions on this.

[0091] Then, if Figure 4 As shown, a first substrate material layer 141 and a first insulating material layer 151 are sequentially formed at the bottom and sidewalls of the first groove 131. The first substrate material layer 141 and the first insulating material layer 151 can be formed by various deposition processes commonly used in the art, and the present application does not limit this.

[0092] Then, if Figure 5 As shown, the first substrate material layer 141 and the first insulating material layer 151 located on the sidewalls of the first groove 131 perpendicular to the first direction are removed by etching. In this step, an etching process commonly used in the art can be used, and the present application does not limit this.

[0093] Then, if Figures 5 and 6 As shown, a second interlayer dielectric material layer 122 filling the first trench 131 is formed. Various deposition processes commonly used in the art may be used to form the second interlayer dielectric material layer 122, which is not limited in the present application.

[0094] Then, if Figure 7 As shown, at least a portion of the second interlayer dielectric material layer 122 is etched to form a second groove 132, the bottom and sidewalls of the second groove 132 are exposed to the first insulating material layer 151, and one end of the second groove 132 along the first direction protrudes from the first insulating material layer 151 and the first substrate material layer 141. In this step, an etching process commonly used in the art can be used, and this application does not limit this. For example, as Figure 7As shown, during the process of forming the second trench 132 , a portion of the first interlayer dielectric material layer 121 may also be etched.

[0095] Then, if Figure 8 As shown, a first substrate layer 160 is formed to fill the second groove 132, and one end of the first substrate layer 160 protruding from the first insulating material layer 151 and the first substrate material layer 141 along the first direction is a connecting portion 161. Exemplarily, the first substrate layer 160 can be formed by various deposition processes commonly used in the art, and this application is not limited thereto.

[0096] Then, if Fig. 9 As shown, a second insulating material layer 152 is formed, the second insulating material layer 152 covers a portion of the surface of the first substrate layer 160 and the first insulating material layer 151, and the second insulating material layer 152 and the first insulating material layer 151 constitute an insulating layer 150, wherein the connecting portion 161 protrudes from the insulating layer 150 along the first direction. Exemplarily, the second insulating material layer 152 can be formed by various deposition processes commonly used in the art, and the present application is not limited thereto.

[0097] Then, if Fig.10 As shown, a second substrate material layer 142 is formed, the second substrate material layer 142 covers the second insulating material layer 152 and the first substrate material layer 141, the first substrate material layer 141 and the second substrate material layer 142 constitute the second substrate layer 140, wherein the connecting portion 161 protrudes from the second substrate layer 140 along the first direction. Exemplarily, the second substrate material layer 142 can be formed by various deposition processes commonly used in the art, and the present application does not limit this.

[0098] Then, if Fig.11 As shown, a third interlayer dielectric material layer 123 is formed, and the third interlayer dielectric material layer 123 covers a portion of the surface of the first substrate layer 160, the second substrate material layer 142, the first interlayer dielectric material layer 121, and the second interlayer dielectric material layer 122. The first interlayer dielectric material layer 121, the second interlayer dielectric material layer 122, and the third interlayer dielectric material layer 123 constitute the interlayer dielectric layer 120. Exemplarily, the third interlayer dielectric material layer 123 can be formed by various deposition processes commonly used in the art, and the present application is not limited thereto.

[0099] In one example, if Fig.12 As shown, after forming the interlayer dielectric layer 120 covering the conductive layer 110 and the MIM capacitor structure located in the interlayer dielectric layer 120, the step of forming a first connection structure 171 and a second connection structure 172 arranged at intervals is also included, the first connection structure 171 penetrates the interlayer dielectric layer 120 and is in electrical contact with the conductive layer 110, and the second connection structure 172 is in electrical contact with the connection portion 161.

[0100] Specifically, the first connection structure 171 and the second connection structure 172 are formed to be spaced apart, including: first, etching the interlayer dielectric layer 120 to respectively form a first through hole exposing the conductive layer 110 and a second through hole exposing the connecting portion 161; then, filling the first through hole and the second through hole with conductive materials, such as Cu, Mn or Cu-Mn alloy, to obtain the first connection structure 171 and the second connection structure 172.

[0101] In one example, taking the stacking of the conductive layer 110 and the substrate 100 along the vertical direction as an example, the vertical direction is the height direction of the MIM capacitor structure, and the first direction is the horizontal direction. The first substrate layer 160, the insulating layer 150 and the second substrate layer 140 all extend along the first direction, and the insulating layer 150 covers at least part of the surface of the first substrate layer 160 parallel to the first direction, and the second substrate layer 140 covers at least part of the surface of the insulating layer 150 parallel to the first direction. The area of ​​the MIM capacitor structure can be increased along the first direction (i.e., the horizontal direction), thereby increasing the capacitance value of the MIM capacitor structure, so that the capacitance value of the MIM capacitor structure will not be limited by the height. At the same time, the MIM capacitor structure of the present application is a 3D fully-encapsulated structure, the insulating layer 150 covers at least a portion of the entire outer surface of the first substrate layer 160 parallel to the first direction, and the second substrate layer 140 covers at least a portion of the entire outer surface of the insulating layer 150 parallel to the first direction. Compared with the planar MIM capacitor structure in the related art, the MIM capacitor structure of the present application has a larger area and a larger capacitance value when the length is the same (taking extension along the first direction as an example, the length is the length along the first direction).

[0102] So far, the description of the key steps of the manufacturing method of the semiconductor device of the present application has been completed. It is worth mentioning that the above method for making a MIM capacitor structure is only for illustration. The preparation of a complete semiconductor device may also include other steps, which will not be repeated here. It is worth mentioning that the order of the above steps can be adjusted without conflict. For example, after forming the first substrate material layer 141, the side walls of the first substrate material layer 141 that are spaced and opposite in the first direction are first etched away, and then a groove is etched to form. The groove can extend a portion of the length along the first direction toward the outside of one end of the first substrate material layer 141, and then a first insulating material layer 151 is formed on the side wall and bottom of the groove to form a first substrate layer 160 to fill the groove, and subsequent steps of forming a second insulating material layer 152 and a second substrate material layer 142 are performed to form a MIM capacitor.

[0103] In summary, the method for manufacturing a semiconductor device according to the embodiment of the present application can increase the area of ​​the MIM capacitor structure along the first direction, thereby increasing the capacitance of the MIM capacitor structure, so that the capacitance of the MIM capacitor structure is not limited by its height.

[0104] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed herein. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the disclosure, drawings, and appended claims of the present application. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a conductive layer is disposed; An interlayer dielectric layer covering the conductive layer and a MIM capacitor structure located in the interlayer dielectric layer are formed, wherein the MIM capacitor structure is a MIM capacitor structure in the LOFIC technology, and the MIM capacitor structure includes: A first substrate layer extending along a first direction, wherein the first direction is parallel to a surface of the conductive layer; an insulating layer covering at least a portion of an outer surface of the first substrate layer parallel to the first direction; a second substrate layer, covering at least a portion of an outer surface of the insulating layer parallel to the first direction, and the second substrate layer is in contact with the conductive layer, and the first substrate layer and the second substrate layer are electrically isolated by the insulating layer; One end of the first substrate layer along the first direction has a connecting portion, and the connecting portion protrudes from the second substrate layer and the insulating layer; An interlayer dielectric layer covering the conductive layer and a MIM capacitor structure located in the interlayer dielectric layer are formed, comprising: forming a first interlayer dielectric material layer on the conductive layer; Etching the first interlayer dielectric material layer to form a first trench exposing a portion of the surface of the conductive layer; sequentially forming a first substrate material layer and a first insulating material layer on the bottom and sidewalls of the first trench; Etching and removing the first substrate material layer and the first insulating material layer located on the sidewall of the first trench perpendicular to the first direction; forming a second interlayer dielectric material layer filling the first trench; At least partially etching the second interlayer dielectric material layer to form a second trench, wherein the bottom and sidewalls of the second trench expose the first insulating material layer, and one end of the second trench along the first direction protrudes from the first insulating material layer and the first substrate material layer; forming a first substrate layer filling the second groove, wherein one end of the first substrate layer protruding from the first insulating material layer and the first substrate material layer along the first direction is the connecting portion; forming a second insulating material layer, wherein the second insulating material layer covers a portion of the surface of the first substrate layer and the first insulating material layer, and the first insulating material layer and the second insulating material layer constitute the insulating layer; forming a second substrate material layer, wherein the second substrate material layer covers the second insulating material layer and the first substrate material layer, and the first substrate material layer and the second substrate material layer constitute the second substrate layer; A third interlayer dielectric material layer is formed, and the third interlayer dielectric material layer covers a portion of the surface of the first substrate layer, the second substrate material layer, the first interlayer dielectric material layer and the second interlayer dielectric material layer, and the first interlayer dielectric material layer, the second interlayer dielectric material layer and the third interlayer dielectric material layer constitute the interlayer dielectric layer.

2. The manufacturing method according to claim 1, characterized in that: After forming an interlayer dielectric layer covering the conductive layer and a MIM capacitor structure located in the interlayer dielectric layer, the method also includes forming a first connection structure and a second connection structure that are spaced apart, wherein the first connection structure penetrates the interlayer dielectric layer and is in electrical contact with the conductive layer, and the second connection structure is in electrical contact with the connection portion.

3. The manufacturing method according to claim 2, characterized in that: The first connection structure and the second connection structure are formed to be spaced apart from each other, including: Etching the interlayer dielectric layer to form a first through hole exposing the conductive layer and a second through hole exposing the connecting portion, respectively; Conductive materials are filled into the first through hole and the second through hole respectively to obtain the first connection structure and the second connection structure.

4. The manufacturing method according to claim 1, characterized in that: The material of the first substrate layer and the second substrate layer includes Ti or TiN; The material of the insulating layer includes oxide or nitride.

5. The manufacturing method according to claim 2, characterized in that: The conductive layer, the first connection structure and the second connection structure are made of Cu, Mn or Cu-Mn alloy; The material of the interlayer dielectric layer includes silicon oxide, optional coated glass or tetraethoxysilane.

6. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 5.

7. The semiconductor device according to claim 6, characterized in that The semiconductor device is a CMOS image sensor.

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