An interlayer ferroelectric transistor with a 25 polarization state and its fabrication method

Abstract

This invention relates to an interlayer ferroelectric transistor with 25 polarization states and its fabrication method, belonging to the field of ferroelectric functional devices. The interlayer ferroelectric transistor is fabricated based on a graphene / hexagonal boron nitride (hBN) heterostructure. The heterojunction graphene / hBN is placed on a SiO2 / Si substrate, with an hBN sheet as the bottom layer and a monolayer graphene as the top layer. The rotation angle between the graphene and hBN is controlled within 1° by dry transfer. The graphene / hBN interlayer ferroelectric transistor is further fabricated using electron beam lithography and electron beam evaporation processes. It can achieve more than 25 stable polarization states at room temperature and can be further used as an artificial neural synapse in neuromorphic computing, exhibiting excellent computational accuracy.

Description

Technical Field

[0001] This invention relates to the field of transistor manufacturing technology, specifically to an interlayer ferroelectric transistor with a 25 polarization state and its fabrication method. Background Technology

[0002] The emergence of artificial intelligence and machine learning has spurred neuromorphic computing to overcome the memory wall bottleneck in the von Neumann framework. In this context, ferroelectric materials, capable of generating a variety of electrically addressable polarization states, have emerged as strong candidates for neuromorphic hardware. The number of polarization states significantly determines the computational accuracy and storage density of neuromorphic hardware. In traditional three-dimensional oxide ferroelectrics, early attempts involved tuning dipole states and nucleation energies by introducing lattice defects, heterojunctions, or phase transitions. However, when three-dimensional ferroelectrics are used for device integration in thin film form, the count of discrete polarization states is reduced to less than four. In contrast, emerging van der Waals ferroelectrics can exhibit quadruple / sixfold polarization states through unique ion migration mechanisms. Despite extensive efforts to create stable multi-state polarizations in existing ferroelectric materials, the number of stable polarization states at room temperature remains less than 16 (<4-bit) due to limited tunable degrees of freedom. Furthermore, the high thickness and complex stacking structures of existing ferroelectric devices further restrict miniaturization and high-density integration. To address the shortcomings of existing technologies, this invention designs and fabricates a simple interlayer ferroelectric transistor with 25 polarization states. Summary of the Invention

[0003] Technical problems solved: Existing technologies suffer from limited adjustable degrees of freedom, with fewer than 16 stable polarization states at room temperature. Furthermore, the high thickness and complex stacking structure of existing ferroelectric devices further restrict miniaturization and high-density integration. This invention provides an interlayer ferroelectric transistor with 25 polarization states and its fabrication method. Based on a graphene / hBN heterostructure, a ferroelectric transistor with a simple stacking structure is fabricated, capable of generating more than 25 polarization states at room temperature. This lays the foundation for the development of high-density non-volatile memory and high-precision in-memory computing systems.

[0004] Technical solution: A method for fabricating an interlayer ferroelectric transistor with a 25 polarization state, specifically including the following steps:

[0005] S1, Two-dimensional material preparation: Single-layer graphene and hBN sheets were exfoliated separately;

[0006] S2: Cut PDMS and place it on a clean glass slide, and perform surface treatment using oxygen plasma; spin-coat PPC reagent on the PDMS surface, and then place it on a hot stage at 105℃ for 3 min. Perform surface treatment on the PDMS spin-coated with PPC using oxygen plasma.

[0007] S3: Take two clean glass slides, add 3ml of PC reagent to one of them, and then immediately cover it with the other glass slide. Slowly slide the two glass slides apart to form a PC film. Cut a square hole in the middle of a 3M white tape. The area of ​​the square hole should be slightly larger than the PDMS surface-treated in S2. Then use it to stick the PC film onto the PDMS surface-treated in S2 to prepare the PC / PPC / PDMS dry transfer carrier.

[0008] S4: At 90℃, the PC / PPC / PDMS dry transfer carrier is applied to the monolayer graphene obtained in S1. Then, the PC / PPC / PDMS dry transfer carrier is slowly lifted to adhere the monolayer graphene, and its position on the PC / PPC / PDMS dry transfer carrier is marked. Next, the straight edge of the monolayer graphene on the PC / PPC / PDMS dry transfer carrier is aligned with the straight edge of the hBN film on the silicon wafer and covered. After covering, the temperature is heated to 180℃ and held for 2 minutes. Finally, the carrier is slowly lifted, and the PPC / PC film is released to the silicon wafer by heat. The PPC and PC are cleaned to complete the construction of the graphene / hBN heterojunction.

[0009] S5: Spin-coat PMMA at 4000 r / s for 1 min on the silicon wafer surface containing the graphene / hBN heterojunction, then heat at 170℃ for 2 min; spin-coat PMMA again at 4000 r / s for 1 min, then heat at 180℃ for 5 min on a hot stage; expose the electrodes using a field emission electron microscope and electron beam exposure system, then place the silicon wafer in a developer solution of isopropanol:water = 3:1 for 30 s; deposit 5 nm Ti / 60 nm Au on the silicon wafer surface using an electron beam deposition device; immerse the silicon wafer in acetone and heat at 65℃ on a hot stage to allow the PMMA carrying the metal thin layer in the unexposed areas to detach; immerse the silicon wafer in isopropanol for 5 min and then dry it with nitrogen to obtain the graphene / hBN ferroelectric transistor, which is an interlayer ferroelectric transistor with 25 polarization states.

[0010] Furthermore, the specific steps of S1 are as follows:

[0011] S101. The silicon wafer was pre-cleaned using an oxygen plasma system at 50W / 50sccm / 2min.

[0012] S102. Use blue tape to stick two-dimensional material crystals of 4-5 square millimeters each, and then stick the tape together so that the crystals are evenly distributed in a 1 square centimeter area on the tape, and then cover it on the silicon wafer.

[0013] S103. Place the silicon wafer covered with blue tape on a hot table and heat it at 100°C for 1 minute. After cooling, slowly peel off the blue tape to complete the mechanical peeling. Obtain single-layer graphene and hBN sheets by mechanical peeling.

[0014] Furthermore, the specific steps of S2 are as follows:

[0015] S201. Cut a small piece of PDMS and place it on a clean glass slide. Treat its surface with oxygen plasma under the conditions of 30W / 20sccm / 30s.

[0016] S202. Turn the PDMS over and treat the surface again with oxygen plasma at 50W / 50sccm / 2min.

[0017] S203. Using a spin coater, PPC reagent was spin-coated onto the PDMS surface at a speed of 4000 r / s for 1 min. Then, the PDMS was heated at 105℃ for 3 min on a hot stage. The spin-coated PDMS was then treated with oxygen plasma at 20W / 10sccm / 3s.

[0018] Furthermore, the PPC reagent in S203 has a mass fraction of 15%, and the solvent is anisole.

[0019] Furthermore, the mass fraction of PC reagent in S3 is 5%, and the solvent is dichloromethane.

[0020] Furthermore, the process of cleaning PPC and PC in S4 is as follows: the silicon wafer is cleaned in dichloromethane for 20 minutes, in acetone for 15 minutes, and in isopropanol for 5 minutes in sequence.

[0021] An interlayer ferroelectric transistor with a polarization state of 25 is prepared by any of the above preparation methods. The heterojunction graphene / hBN is placed on a SiO2 / Si substrate, the bottom layer is an hBN sheet, the top layer is a monolayer graphene, and a 5nm Ti / 60nm Au electrode is constructed as the source and drain electrode by electron beam exposure and electron beam evaporation.

[0022] Furthermore, the thicknesses of the monolayer graphene and the hBN sheet are 0.34 nm and 20 nm, respectively.

[0023] Explanation of principle: Graphene and hBN have similar hexagonal honeycomb lattices. It is predicted that graphene / hBN heterojunctions should exhibit upward and downward interlayer polarization in AB and BA stacking configurations, respectively. In principle, the reversal of interlayer polarization can be achieved by sliding the upper graphene layer by one BN bond length within one moiré cycle, thereby resulting in sliding ferroelectricity. In this invention, the ferroelectric polarization intensity is controlled by applying a source-drain DC pulse to the graphene channel.

[0024] Beneficial effects: (1) This application proposes for the first time an interlayer ferroelectric transistor with 25 polarization states and its fabrication method. At room temperature, by changing the bias pulse between the source and drain electrodes, the ferroelectric transistor exhibits at least 25 stable and discrete polarization states.

[0025] By using different current levels corresponding to multi-state polarization as weights, the constructed convolutional neural network can achieve a recognition accuracy of 98.4% for MNIST handwritten digits.

[0026] Furthermore, the device features a simple stacking structure and operating mode, laying the foundation for the development of high-performance nanoscale in-memory computing systems.

[0027] Attached image description: Figure 1 This is a schematic diagram of the graphene / hBN interlayer ferroelectric transistor structure and its operating mode in the embodiments of this application;

[0028] Figure 2 The images show the Raman spectral characterization and optical images of the graphene / hBN interlayer ferroelectric transistors in the embodiments of this application, where the left image is the Raman spectral characterization image and the right image is the optical image.

[0029] Figure 3 This is an electrical characterization diagram of the slip ferroelectricity of the graphene / hBN interlayer ferroelectric transistor in the embodiments of this application; Figure 3 The top left image shows the channel resistance of the device measured at 1.5 K as the pulse amplitude. V pulse ) and gate voltage ( V G The function of ). Figure 3 The lower left image and Figure 3 The top left image is the same, but... V pulse The direction of application is reversed; Figure 3 The middle right image is extracted from the two images on the left. V pulse = -9 / -6 / +0.5 / +6 / +9 V R - V G curve;

[0030] Figure 4 Characterization of the slip ferroelectric hysteresis window of the graphene / hBN interlayer ferroelectric transistor in the embodiments of this application;

[0031] Figure 5 The graph shows the polarization intensity of the graphene / hBN interlayer ferroelectric transistor in the embodiments of this application as a function of pulse bias voltage.

[0032] Figure 6The graph shows the current levels of the graphene / hBN interlayer ferroelectric transistors in the embodiments of this application under increasing positive and negative bias voltages, and the cumulative frequency diagrams at different current levels. The upper graph shows the cycle enhancement and suppression diagrams, and the lower graph shows the cumulative frequency diagrams at different current levels.

[0033] Figure 7 This is a diagram illustrating the 4-bit operating mode of the graphene / hBN interlayer ferroelectric transistor in the embodiments of this application;

[0034] Figure 8 The diagram shows the convolutional neural network flowchart and the corresponding handwritten digit recognition accuracy of the graphene / hBN interlayer ferroelectric transistors in the embodiments of this application. The upper diagram is the convolutional neural network flowchart, and the lower diagram is the handwritten digit recognition accuracy graph. Detailed Implementation

[0035] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0036] The following reagents and instruments will be needed:

[0037] Graphite crystals (HQ graphene aphene); hBN crystals (HQ graphene aphene);

[0038] Silicon wafer (University, 300 nm SiO2 / Si); blue adhesive tape for mechanical peeling (ultronsystems); white adhesive tape (3M).

[0039] PDMS (DOW CORNING 184); PC (Sigma-Aldrich); PPC (Sigma-Aldrich); PMMA (MicroChem 495 A4);

[0040] Dichloromethane (Bailingwei, pesticide residue grade 99.9%); anisole (alladin, chromatographic grade 99.9%); acetone (Wokai, chromatographic grade 99.9%); isopropanol (Tedia, chromatographic grade 99.9%).

[0041] Two-dimensional material transfer stage (Meta Photonics), electron beam deposition equipment (Syskey E-Beam Evaporation system), oxygen plasma system (Femto Science Convance), spin coater (Spin Processor POLOS), optical microscope (Nikon LV100ND), field emission electron microscope (Zeiss Sigma 300), electron beam exposure system (Raith Quantum), atomic force microscope (SmartSPM-1000), Raman spectrometer (Horiba JY Labram EVO, 532nm), cryogenic transport equipment (OXFORD TeslatronPT), source table (Keithley 2400 / Keithley 6430).

[0042] Example 1: This example provides a method for fabricating a single-layer interlayer ferroelectric transistor with a 25 polarization state, comprising the following steps:

[0043] S1, Two-dimensional material preparation: The silicon wafer was pre-cleaned using an oxygen plasma system at 50W / 50sccm / 2min. Two-dimensional material crystals of 4-5 square millimeters were adhered to the wafer using blue adhesive tape, ensuring the crystals were evenly distributed over a 1 square centimeter area on the tape. These crystals were then applied to the silicon wafer. The silicon wafer covered with blue adhesive tape was heated to 100℃ for 1 min on a hot stage. After cooling, the blue adhesive tape was slowly peeled off to complete the mechanical exfoliation, yielding monolayer graphene and hBN sheets. The positions of the monolayer graphene and hBN sheets on the silicon wafer were confirmed using an optical microscope by observing the difference in optical contrast. The thickness and surface cleanliness of the two-dimensional materials at the corresponding positions were confirmed using an atomic force microscope.

[0044] S2: Cut a small piece of PDMS and place it on a clean glass slide. Treat its surface with oxygen plasma at 30W / 20sccm / 30s. Turn the PDMS over and treat its surface again with oxygen plasma at 50W / 50sccm / 2min. Spin coat the PDMS surface with PPC reagent at 4000 r / s for 1 min using a spin coater. Then heat it at 105℃ for 3 min on a hot stage. Treat the spin-coated PDMS with oxygen plasma at 20W / 10sccm / 3s.

[0045] S3: Take two clean glass slides, add 3ml of PC reagent to one of them, and then immediately cover it with the other glass slide. Slowly slide the two glass slides apart to form a PC film. Cut a square hole in the middle of a 3M white tape. The area of ​​the square hole should be slightly larger than the PDMS surface-treated in S2. Then use it to stick the PC film onto the PDMS surface-treated in S2 to prepare the PC / PPC / PDMS dry transfer carrier.

[0046] S4: At 90℃, the PC / PPC / PDMS dry transfer carrier is applied to the monolayer graphene obtained in S1. Then, the PC / PPC / PDMS dry transfer carrier is slowly lifted to adhere the monolayer graphene, and its position on the PC / PPC / PDMS dry transfer carrier is marked. Next, the straight edge of the monolayer graphene on the PC / PPC / PDMS dry transfer carrier is aligned with the straight edge of the hBN film on the silicon wafer and covered. After covering, the temperature is heated to 180℃ and held for 2 minutes. Finally, the carrier is slowly lifted, and the PPC / PC film is released to the silicon wafer by heat. The PPC and PC are cleaned to complete the construction of the graphene / hBN heterojunction.

[0047] S5: Spin-coat PMMA at 4000 r / s for 1 min on the silicon wafer surface containing the graphene / hBN heterojunction, then heat at 170℃ for 2 min; spin-coat PMMA again at 4000 r / s for 1 min, then heat at 180℃ for 5 min on a hot stage; expose the electrodes using a field emission electron microscope and electron beam exposure system, then place the silicon wafer in a developer solution of isopropanol:water = 3:1 for 30 s; deposit 5 nm Ti / 60 nm Au on the silicon wafer surface using an electron beam deposition device; immerse the silicon wafer in acetone and heat at 65℃ on a hot stage to allow the PMMA carrying the metal thin layer in the unexposed areas to detach; immerse the silicon wafer in isopropanol for 5 min and then dry it with nitrogen to obtain the graphene / hBN ferroelectric transistor, which is an interlayer ferroelectric transistor with 25 polarization states.

[0048] The PPC reagent in S203 has a mass fraction of 15%, and the solvent is anisole.

[0049] The mass fraction of PC reagent in S3 is 5%, and the solvent is dichloromethane.

[0050] The interlayer ferroelectric transistor with 25 polarization states prepared by the method comprises heterojunction graphene / hBN placed on a SiO2 / Si substrate, with an hBN sheet as the bottom layer and a monolayer graphene as the top layer. A 5nm Ti / 60nm Au electrode is constructed as the source and drain electrode via electron beam lithography and electron beam evaporation. The thicknesses of the monolayer graphene and the hBN sheet are 0.34 nm and 20 nm, respectively.

[0051] Source-drain bias pulse modulation and electrical transport testing of graphene / hBN ferroelectric transistors: The device leads were constructed using a sample holder based on a cryogenic transport apparatus; the sample was placed into the chamber, and a vacuum of 1×10⁻⁶ was applied. -6 torr, and reduce the chamber temperature to 1.5 K. To achieve multi-state polarization control, a source-drain bias pulse with monotonically varying amplitude was designed ( V pulse ) at gate voltage ( V G The polarization tendency and intensity are applied to the graphene channel under conditions where the polarization is zero. Changes in polarization tendency and intensity create carrier concentration differences within the graphene, allowing the shift in the system's polarization state to be detected by measuring the Dirac point offset. After each pulse, the polarization is measured by executing... V G The transmission characteristics of the scanning recording device, such as Figure 3 As shown. An application of V at a spacing of 0.5 V is applied from... V pulse With a pulse ranging from +10 V to -10 V, it can be observed that all Dirac points gradually shift towards hole doping, and conversely, they reversibly shift towards electron doping. Extraction data was obtained during the forward and reverse pulse evolution processes. V pulse The transmission curves under the conditions of +9 / +6 / +0.5 / -6 / -9 V can be observed. The offset of DPs can be observed to first increase and then decrease as the pulse monotonically decreases, thus exhibiting the physical picture of ferroelectric hysteresis, as shown below. Figure 3 As shown in the middle right figure. A visualized ferroelectric hysteresis image can be obtained by subtracting the forward and reverse mappings, as follows: Figure 4 As shown, the three prominent memory windows correspond to the primary Dirac point (PDP) and two secondary Dirac points (SDP). The corresponding interlayer polarization values ​​can be calculated using a two-dimensional polarization model, thereby extracting the hysteresis loops corresponding to the three Dirac points, as shown below. Figure 5 As shown.

[0052] Multistate polarization modulation and applications of graphene / hBN ferroelectric transistors: The slip ferroelectricity in graphene / hBN devices can be extended to room temperature (300 K). Reversible modulation of 25 uniformly distributed polarization states within the graphene / hBN ferroelectric transistor was achieved by applying continuously increasing positive / negative pulses, resulting in cyclically increasing and decreasing current levels over long periods. Figure 6 As shown in the upper middle figure; the current levels corresponding to the 25 polarization states do not show significant degradation over a period of more than 20 s and can be well separated, as shown in the figure above. Figure 6As shown in the lower figure, 16 independent polarization states are extracted from a single cycle. The stable and distinguishable current states enable the device to be applied to 4-bit high-density non-volatile memories, such as… Figure 7 As shown, a deep convolutional neural network was constructed based on the uniform multi-state polarization exhibited by graphene / hBN ferroelectric transistors, as illustrated. Figure 8 As shown in the upper figure, the recognition accuracy of MNIST handwritten digit images is as high as 98.4%, with an accuracy loss of only 0.2% compared to the baseline. Figure 8 As shown in the lower middle figure.

[0053] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an interlayer ferroelectric transistor with a 25 polarization state, characterized in that, Includes the following steps: S1, Two-dimensional material preparation: Single-layer graphene and hBN sheets were exfoliated separately; S2: Cut PDMS and place it on a clean glass slide, and perform surface treatment using oxygen plasma; spin-coat polypropylene carbonate (PPC) reagent on the PDMS surface, and then place it on a hot stage at 105°C for 3 min. PDMS spin-coated with PPC is then surface-treated using oxygen plasma. S3: Take two clean glass slides, add 3 ml of polycarbonate (PC) reagent to one of them, and then immediately cover it with the other glass slide. Slowly slide the two glass slides apart to form a polycarbonate (PC) film. Cut a square hole in the middle of the white adhesive tape. The area of ​​the square hole should be slightly larger than the PDMS surface-treated in S2. Then use it to stick the polycarbonate (PC) film onto the PDMS surface-treated in S2 to prepare the PC / PPC / PDMS dry transfer carrier. S4: At 90℃, a PC / PPC / PDMS dry transfer carrier is applied to the monolayer graphene obtained in S1. The PC / PPC / PDMS dry transfer carrier is then slowly lifted to adhere the monolayer graphene, and its position on the PC / PPC / PDMS dry transfer carrier is marked. Next, the straight edge of the monolayer graphene on the PC / PPC / PDMS dry transfer carrier is aligned with the straight edge of the hBN film on the silicon wafer and covered. After covering, the temperature is heated to 180℃ and held for 2 minutes. Finally, the carrier is slowly lifted, and the PPC / PC film is released to the silicon wafer by heat. The polypropylene carbonate (PPC) and polycarbonate (PC) are cleaned to complete the construction of the graphene / hBN heterojunction. S5: Spin-coat PMMA at 4000 r / s for 1 min on the silicon wafer surface containing the graphene / hBN heterojunction, then heat at 170℃ for 2 min; spin-coat PMMA again at 4000 r / s for 1 min, then heat at 180℃ for 5 min on a hot stage; expose the electrodes using a field emission electron microscope and electron beam exposure system, then place the silicon wafer in a developer solution of isopropanol:water = 3:1 for 30 s; deposit 5 nm Ti / 60 nm Au on the silicon wafer surface using an electron beam deposition device; immerse the silicon wafer in acetone and heat at 65℃ on a hot stage to allow the PMMA carrying the metal thin layer in the unexposed areas to detach; immerse the silicon wafer in isopropanol for 5 min and then dry it with nitrogen to obtain the graphene / hBN ferroelectric transistor, which is an interlayer ferroelectric transistor with 25 polarization states.

2. The method for fabricating an interlayer ferroelectric transistor with a 25 polarization state according to claim 1, characterized in that, The specific steps of S1 are as follows: S101. The silicon wafer was pre-cleaned using an oxygen plasma system at 50W / 50sccm / 2min. S102. Use blue tape to stick two-dimensional material crystals of 4-5 square millimeters each, and then stick the tape together so that the crystals are evenly distributed in a 1 square centimeter area on the tape, and then cover it on the silicon wafer. S103. Place the silicon wafer covered with blue tape on a hot table and heat it at 100°C for 1 minute. After cooling, slowly peel off the blue tape to complete the mechanical peeling. Obtain single-layer graphene and hBN sheets by mechanical peeling.

3. The method for fabricating an interlayer ferroelectric transistor with a 25 polarization state according to claim 1, characterized in that, The specific steps of S2 are as follows: S201. Cut a small piece of PDMS and place it on a clean glass slide. Treat its surface with oxygen plasma under the conditions of 30W / 20sccm / 30s. S202. Turn the PDMS over and treat the surface again with oxygen plasma at 50W / 50sccm / 2min. S203. Using a spin coater, spin coat the PDMS surface with PPC reagent at a speed of 4000 r / s for 1 min, then place it on a hot stage at 105℃ for 3 min, and treat the spin-coated PDMS with oxygen plasma at 20W / 10sccm / 3s.

4. The method for fabricating an interlayer ferroelectric transistor with a 25 polarization state according to claim 3, characterized in that, The polypropylene carbonate (PPC) reagent in S203 has a mass fraction of 15%, and the solvent is anisole.

5. The method for fabricating an interlayer ferroelectric transistor with a 25 polarization state according to claim 1, characterized in that, The polycarbonate (PC) reagent in S3 has a mass fraction of 5%, and the solvent is dichloromethane.

6. The method for fabricating an interlayer ferroelectric transistor with a 25 polarization state according to claim 1, characterized in that, The process of cleaning polypropylene carbonate (PPC) and polycarbonate (PC) in S4 is as follows: the silicon wafer is cleaned in dichloromethane for 20 min, in acetone for 15 min, and in isopropanol for 5 min in sequence.

7. An interlayer ferroelectric transistor with a 25 polarization state prepared by any one of the preparation methods described in claims 1-6, characterized in that: Heterogeneous graphene / hBN is placed on a SiO2 / Si substrate, with an hBN sheet as the bottom layer and a monolayer graphene as the top layer. A 5nm Ti / 60nm Au electrode is constructed as the source and drain electrode by electron beam exposure and electron beam evaporation.

8. The interlayer ferroelectric transistor with 25 polarization states according to claim 7, characterized in that, The thicknesses of the single-layer graphene and hBN sheet are 0.34 nm and 20 nm, respectively.

Images