Light absorption surface point contact double-sided TOPCon battery structure and manufacturing method thereof
The light-absorbing surface point contact TOPCon cell structure addresses parasitic absorption and manufacturing complexity by applying passivation contacts to both surfaces, enhancing efficiency and simplifying production.
Patent Information
- Application Number
- CN202411325300.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-27
AI Technical Summary
Existing TOPCon cell structures face issues with parasitic absorption of the polysilicon layer on the light-absorbing surface, leading to reduced short-circuit current density and conversion efficiency, particularly when applied to the front surface, and the manufacturing process is complex and not conducive to industrial application.
A light-absorbing surface point contact TOPCon cell structure is designed with a silicon wafer divided into regions, featuring suede and polished surfaces, and a passivation contact structure applied to both front and back surfaces, utilizing point contacts and metal electrodes to minimize parasitic absorption and surface recombination.
The structure achieves higher cell conversion efficiency by reducing parasitic absorption and surface recombination, while simplifying the manufacturing process through a point contact and line connection method.
Smart Images
Figure CN119208407A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of battery processing, relates to a double-sided TOPCon battery structure with point contact on a light-absorbing surface, and also relates to a manufacturing method of the double-sided TOPCon battery structure with point contact on a light-absorbing surface. Background Art
[0002] TOPCon (tunneling oxide passivation contact) cell technology was first proposed by the Fraunhofer Institute for Solar Energy in Germany in 2014 as a new type of passivated contact solar cell. Structurally, TOPCon is a solar cell technology based on the principle of carrier selective tunneling. Its cell structure uses N-type or P-type silicon as the substrate, prepares an ultra-thin tunneling oxide layer on the back surface of the cell, and then deposits a layer of doped polysilicon film. The two together form a passivation contact structure, which effectively reduces surface recombination and metal recombination. At present, the most mature TOPCon cell technology for industrial application is based on N-type silicon substrate. On the back surface of the N-type silicon substrate, an ultra-thin tunneling oxide layer and an N-type doped polysilicon layer are sequentially arranged to form an N-TOPCon structure. The front surface of the N-type silicon substrate is sequentially provided with a diffused P+ emitter, a dielectric layer and an anti-reflection layer. According to the theoretical calculation results of ISFH (Institute for Solar Energy Hamelin), the theoretical limit efficiency of a single electron selective TOPCon (N-TOPCon) cell is 27.1%. If the TOPCon cell that realizes the selective transmission of electrons and holes at the same time achieves a theoretical conversion efficiency of up to 28.7%. For this reason, some people have proposed to apply the hole selective transmission TOPCon (P-TOPCon) structure to the front surface of the battery, and realize the selective transmission of back surface electrons and front surface holes at the same time. However, the polysilicon layer applied to the front surface has a strong parasitic absorption effect on the incident light, resulting in an extremely low short-circuit current density of the battery. Later, MKStodolny et al. proposed the Poly-fingers structure to solve this problem, that is, the tunnel passivation contact structure is applied to the front surface of the battery structure directly below the strip metal grid line, and the polysilicon layer is distributed in a strip-shaped manner on the front surface of the battery. Although this structure reduces the parasitic absorption of the polysilicon layer, since the width of the strip metal grid line is always smaller than the design width of the polysilicon layer in the battery manufacturing, the area where the metal grid line is not made still has a parasitic absorption effect, and the manufacturing process of this battery structure is complicated, and additional masking and etching and other process steps are required to realize the manufacturing of the above battery structure, which is not conducive to industrial application and promotion. At the same time, the polysilicon layer has a serious parasitic absorption effect on light, especially when the structure is applied to the light-absorbing surface, it will significantly reduce the short-circuit current density of the battery, thereby affecting the battery conversion efficiency. Summary of the invention
[0003] The first purpose of the present invention is to provide a light-absorbing surface point contact TOPCon cell structure. By adopting the passivation contact technology of the TOPCon structure on both the front surface and the back surface, the parasitic absorption effect of the polysilicon layer on light is reduced. At the same time, the production of metal electrodes greatly reduces the surface recombination of the metal contact area, thereby achieving a higher cell conversion efficiency.
[0004] The second object of the present invention is to provide a method for manufacturing a light-absorbing surface point contact TOPCon cell.
[0005] The first technical solution adopted by the present invention is that the light-absorbing surface point contact TOPCon cell comprises a silicon wafer, the front surface of which is divided into a first area, a plurality of second areas and a plurality of third areas;
[0006] The first area is set to a suede structure, and the second areas and the third areas are respectively set to a suede structure or a polished surface structure;
[0007] The plurality of second regions are evenly distributed in the first region, and the plurality of third regions are arranged in a one-to-one correspondence in the plurality of second regions.
[0008] The first region is provided with a first anti-reflection layer, a dielectric layer, a light-absorbing surface doping layer, a silicon substrate, a first tunneling oxide layer, a first doped polysilicon layer, a second anti-reflection layer and a first metal contact electrode in order from top to bottom;
[0009] The second region includes a second doped polysilicon layer and a second tunneling oxide layer, the second doped polysilicon layer and the second tunneling oxide layer are located between the dielectric layer and the silicon substrate, the second doped polysilicon layer is located on the lower surface of the dielectric layer, and the second tunneling oxide layer is located on the upper surface of the silicon substrate; the first metal contact electrode penetrates the first anti-reflection layer and contacts the dielectric layer and the first doped polysilicon layer;
[0010] The third region includes a plurality of second metal contact electrodes, and the plurality of second metal contact electrodes are in contact with the second doped polysilicon layer.
[0011] The first metal contact electrodes are distributed in strips, and the second metal contact electrodes are distributed in rectangular, circular or elliptical shapes; a plurality of second metal contact electrodes are connected by metal grid lines, which are distributed in strips and contact the first anti-reflection layer.
[0012] The contact area between the second metal contact electrode and the first anti-reflection layer is smaller than the area where the second doped polysilicon layer is arranged, and the lateral width of the metal gate line is smaller than the lateral width of the second doped polysilicon layer.
[0013] The silicon substrate is selected from an N-type or P-type silicon wafer, the first doped polysilicon layer is N-type or P-type doped, and the second doped polysilicon layer is P-type or N-type doped.
[0014] The second doped polysilicon layer 9 is in any one of a rectangular, diamond, circular or elliptical shape.
[0015] The second technical solution adopted by the present invention is a method for manufacturing a light-absorbing surface point-contact TOPCon battery, which adopts a light-absorbing surface point-contact TOPCon battery structure, and the specific steps are as follows:
[0016] S1: polishing the silicon wafer and preparing a first tunneling oxide layer and a first doped polysilicon layer;
[0017] S2: preparing a second doped polysilicon layer and a second tunneling oxide layer;
[0018] S3: performing texturing treatment on the first region using a mixed solution of a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropanol or a texturing additive with a volume fraction of 0.5% to 1%, to obtain a treated silicon wafer;
[0019] S4: Load the silicon wafer processed in S3 into a tubular low-pressure diffusion furnace, and then maintain the temperature at 800°C to 1050°C for 20 to 100 minutes to complete the doping of the light-absorbing surface doping layer;
[0020] S5: The S4-doped silicon wafer is cleaned with an HF solution, and a dielectric layer is first grown on the surface of the light-absorbing surface doped layer and the second doped polysilicon layer; and then a first anti-reflection layer and a second anti-reflection layer are grown on the front surface and the back surface respectively;
[0021] S6: Prepare and connect the first metal contact electrode, the second metal contact electrode and the metal gate line to complete the battery manufacturing.
[0022] The second technical solution of the present invention is also characterized in that:
[0023] S1 is specifically:
[0024] S1.1: Immerse the silicon wafer in a mixed solution of KOH or NaOH with a mass fraction of 2-5% and H2O2 with a mass fraction of 2-6% at a temperature of 65°C to 85°C to remove the damaged layer, and then polish it with a KOH or NaOH solution with a mass fraction of 10% to 30%;
[0025] S1.2: deposit a SiO2 layer or a SiONx mask layer on one polished surface of a selected silicon wafer by PECVD, and then remove the mask layer on the edge of the other polished surface by HF solution;
[0026] S1.3: The backlight surface of the silicon wafer is sequentially prepared by PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment to form a first tunneling oxide layer and a first doped polysilicon layer; at the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20nm is grown on the surface of the first doped polysilicon layer to serve as a back surface mask layer;
[0027] S1.4: Use chain equipment and trough wet cleaning equipment to remove the first doped polysilicon layer produced by the plating around the edge of the front surface and the SiO2 or SiONx mask layer grown in S1.2, so that the polished surface of the front surface of the silicon wafer is exposed.
[0028] S2 is specifically:
[0029] PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment are used to sequentially prepare the second tunneling oxide layer and the second doped polysilicon layer, and the doping types of the first doped polysilicon layer and the second doped polysilicon layer are opposite. At the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20nm is grown on the surface of the second doped polysilicon layer to serve as a front surface mask layer.
[0030] S3 is specifically as follows: using an ultraviolet picosecond laser to remove the mask layer on the front surface, retaining the second area, and then texturing the first area using a mixed solution of a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropyl alcohol or a texturing additive with a volume fraction of 0.5% to 1%, so that a velvet structure is formed in the first area, thereby obtaining a silicon wafer with a velvet structure.
[0031] Compared with the prior art, the present invention has the following beneficial effects:
[0032] (1) The light-absorbing surface point-contact TOPCon cell structure provided by the present invention, through ingenious cell structure design, applies the tunnel passivation contact structure to the front surface (light-absorbing surface) of the cell, greatly reducing the recombination of the front surface metal contact area, while minimizing the parasitic absorption of light by the front surface polysilicon layer. During the connection process of the front surface metal electrode, the point contact + line connection method is used to realize the production of the front surface metal electrode of the light-absorbing surface point-contact TOPCon cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 It is a schematic diagram of the structure of the first area and the second area of the present invention;
[0034] Figure 2 is a schematic structural diagram of the third region of the present invention;
[0035] Figure 3 yes Figure 2 Schematic diagram of the cross section of AA;
[0036] Figure 4 It is a schematic diagram of the connection between the metal gate line and the second metal contact electrode of the present invention.
[0037] In the figure, 1. first anti-reflection layer, 2. dielectric layer, 3. light-absorbing surface doped layer, 4. silicon substrate, 5. first tunneling oxide layer, 6. first doped polysilicon layer, 7. second anti-reflection layer, 8. first metal contact electrode, 9. second doped polysilicon layer, 10. second tunneling oxide layer, 11. second metal contact electrode, 12. metal gate line, 13. first region, 14. second region, 15. third region. DETAILED DESCRIPTION
[0038] The present invention will be further explained below in conjunction with the accompanying drawings and specific embodiments.
[0039] The present invention provides a light-absorbing surface point contact TOPCon battery structure, such as Figure 1 and Figure 2 As shown, it includes a silicon wafer, and the front surface of the silicon wafer is provided with a first area 13, a plurality of second areas 14 and a plurality of third areas 15; the surface of the first area 13 is set to a velvet structure, and the surfaces of the second area 14 and the third area 15 can be set to a velvet structure or a polished surface structure according to the needs of battery manufacturing; wherein the second area 14 is dispersed on the front surface of the battery in a rectangular, diamond, circular or elliptical structure, and the first area is between each rectangular, diamond, circular or elliptical structure; the inside of the second area 14 is set to an elliptical, rectangular, diamond or circular third area 15, and the third area 15 is filled with a second metal contact electrode 11.
[0040] Among them, Figure 3 As shown, the first region 13 is provided with a first anti-reflection layer 1, a dielectric layer 2, a light-absorbing surface doping layer 3, a silicon substrate 4, a first tunneling oxide layer 5, a first doped polysilicon layer 6, a second anti-reflection layer 7, and a first metal contact electrode 8 in order from top to bottom;
[0041] The second region 14 includes a second doped polysilicon layer 9 and a second tunneling oxide layer 10. The overall structure of the second region 14 and the first region is a first anti-reflection layer 1, a dielectric layer 2, a second doped polysilicon layer 9, a second tunneling oxide layer 10, a silicon substrate 4, a first tunneling oxide layer 5, a first doped polysilicon layer 6, an anti-reflection layer 7 and a first metal contact electrode 8 arranged in sequence from top to bottom; the second doped polysilicon layer 9 and the second tunneling oxide layer 10 are located between the dielectric layer 2 and the silicon substrate 4, the second doped polysilicon layer 9 is located on the lower surface of the dielectric layer 2, the second tunneling oxide layer 10 is located on the upper surface of the silicon substrate 4, and the first metal contact electrode 8 penetrates the first anti-reflection layer 1 and contacts the dielectric layer 2 and the first doped polysilicon layer 6;
[0042] The third region 15 is filled with a second metal contact electrode 11, and the overall structure is the second metal contact electrode 11, the first anti-reflection layer 1, the dielectric layer 2, the second doped polysilicon layer 9, the second tunneling oxide layer 10, the silicon substrate 4, the first tunneling oxide layer 5, the first doped polysilicon layer 6, the second anti-reflection layer 7, and the first metal contact electrode 8 arranged in sequence from top to bottom; the second metal contact electrode 11 is directly in contact with the second doped polysilicon layer 9; the first metal contact electrode 8 is distributed in strips; Figure 2 As shown, the second metal contact electrodes 11 are distributed in a rectangular, circular or elliptical shape, and the second metal contact electrodes 11 on the front surface of the battery are connected by metal grid lines 12, such as Figure 4 As shown, the metal grid lines 12 are distributed in strips and only contact the first anti-reflection layer 1 in the first area 13 .
[0043] Among them, the contact area of the second metal contact electrode 11 is smaller than the setting area of the second doped polysilicon layer 9, and the lateral width of the metal gate line 12 is smaller than the lateral width of the second doped polysilicon layer 9; the silicon substrate 4 can be selected from N-type or P-type silicon wafers, and the corresponding first doped polysilicon layer 6 is N-type or P-type doped, and the corresponding second doped polysilicon layer 9 is N-type or P-type doped.
[0044] The present invention also provides a method for manufacturing a light-absorbing surface point contact TOPCon battery, and the specific steps are as follows:
[0045] S1: polishing the silicon wafer and preparing a first tunneling oxide layer 5 and a first doped polysilicon layer 6;
[0046] S2: preparing a second doped polysilicon layer 9 and a second tunneling oxide layer 10;
[0047] S3: performing texturing treatment on the first region 13 using a mixed solution of a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropanol or a texturing additive with a volume fraction of 0.5% to 1%, to obtain a treated silicon wafer;
[0048] S4: loading the silicon wafer processed in S3 into a tubular low-pressure diffusion furnace, and then maintaining the temperature at 800° C. to 1050° C. for 20 to 100 minutes to complete the doping of the light-absorbing surface doping layer 3;
[0049] S5: The S4-doped silicon wafer is cleaned with HF solution, and a dielectric passivation layer, namely, a dielectric layer 2, is first grown on the surface of the light-absorbing surface doping layer 3 and the second doped polysilicon layer 9; and then a first anti-reflection layer 1 and a second anti-reflection layer 7 are grown on the front surface and the back surface respectively;
[0050] S6: Prepare and connect the first metal contact electrode 8, the second metal contact electrode 11 and the metal gate line 12 to complete the battery manufacturing.
[0051] S1 is specifically:
[0052] S1.1: Immerse the silicon wafer in a mixed solution of KOH or NaOH with a mass fraction of 2-5% and H2O2 with a mass fraction of 2-6% at a temperature of 65°C to 85°C to remove the damaged layer, and then polish it with a KOH or NaOH solution with a mass fraction of 10% to 30%;
[0053] S1.2: deposit a SiO2 layer or a SiONx mask layer on one polished surface of a selected silicon wafer by PECVD, and then remove the mask layer on the edge of the other polished surface by HF solution;
[0054] S1.3: The backlight surface of the silicon wafer is sequentially prepared by PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment to complete the preparation of the first tunneling oxide layer 5 and the first doped polysilicon layer 6; at the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20nm is grown on the surface of the first doped polysilicon layer 6 to serve as a back surface mask layer;
[0055] S1.4: Use chain equipment and trough wet cleaning equipment to remove the first doped polysilicon layer 6 produced by the plating around the edge of the front surface and the SiO2 or SiONx mask layer grown in S1.2, so that the polished surface of the front surface of the silicon wafer is exposed.
[0056] S2 is specifically:
[0057] PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment are used to sequentially prepare the second tunneling oxide layer 10 and the second doped polysilicon layer 9, and the doping types of the first doped polysilicon layer 6 and the second doped polysilicon layer 9 are opposite. At the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20nm is grown on the surface of the second doped polysilicon layer 9 to serve as a front surface mask layer.
[0058] S3 specifically comprises: using an ultraviolet picosecond laser to remove the mask layer on the front surface, retaining the second area 14, and then performing a texturing treatment on the first area 13 using a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropyl alcohol or a texturing additive mixed solution with a volume fraction of 0.5% to 1%, so that the first area 13 forms a velvet structure, and a silicon wafer with a velvet structure is obtained.
[0059] Example 1
[0060] This embodiment provides a light-absorbing surface point contact TOPCon cell structure, such as Figure 1-4As shown, it includes a silicon wafer, and the front surface of the silicon wafer is provided with a first area 13, a plurality of second areas 14 and a plurality of third areas 15; the surface of the first area 13 is set to a velvet structure, and the surfaces of the second area 14 and the third area 15 can be set to a velvet structure or a polished surface structure according to the needs of battery manufacturing; wherein the second area 14 is dispersed on the front surface of the battery in a rectangular, diamond, circular or elliptical structure, and the first area is between each rectangular, diamond, circular or elliptical structure; the inside of the second area 14 is set to an elliptical, rectangular, diamond or circular third area 15, and the third area 15 is filled with a second metal contact electrode 11.
[0061] The first region 13 is provided with a first anti-reflection layer 1, a dielectric layer 2, a light-absorbing surface doped layer 3, a silicon substrate 4, a first tunneling oxide layer 5, a first doped polysilicon layer 6, a second anti-reflection layer 7, and a first metal contact electrode 8 in sequence from top to bottom; the second region 14 includes a second doped polysilicon layer 9 and a second tunneling oxide layer 10, and the overall structure of the second region 14 and the first region is the first anti-reflection layer 1, the dielectric layer 2, the second doped polysilicon layer 9, the second tunneling oxide layer 10, the silicon substrate 4, the first tunneling oxide layer 5, the first doped polysilicon layer 6, the anti-reflection layer 7 and the first metal contact electrode 8 in sequence from top to bottom; the second doped polysilicon layer 9 and the second tunneling oxide layer 10 are located in the dielectric layer 2 Between the dielectric layer 2 and the silicon substrate 4, the second doped polysilicon layer 9 is located on the lower surface of the dielectric layer 2, the second tunneling oxide layer 10 is located on the upper surface of the silicon substrate 4, and the first doped polysilicon layer 6 is in contact with the first metal contact electrode 8; the third region 15 is filled with the second metal contact electrode 11, and the overall structure is the second metal contact electrode 11, the first anti-reflection layer 1, the dielectric layer 2, the second doped polysilicon layer 9, the second tunneling oxide layer 10, the silicon substrate 4, the first tunneling oxide layer 5, the first doped polysilicon layer 6, the second anti-reflection layer 7, and the first metal contact electrode 8 arranged in sequence from top to bottom; the second metal contact electrode 11 is directly in contact with the second doped polysilicon layer 9; the first metal contact electrode 8 is distributed in strips; Figure 2 As shown, the second metal contact electrodes 11 are distributed in a rectangular, circular or elliptical shape, and the second metal contact electrodes 11 on the front surface of the battery are connected by metal grid lines 12, such as Figure 4 As shown, the metal grid lines 12 are distributed in strips and only contact the first anti-reflection layer 1 in the first area 13 .
[0062] Among them, the contact area of the second metal contact electrode 11 is smaller than the setting area of the second doped polysilicon layer 9, and the lateral width of the metal gate line 12 is smaller than the lateral width of the second doped polysilicon layer 9; the silicon substrate 4 can be made of N-type silicon wafer, and the corresponding first doped polysilicon layer 6 is N-type doped, and the corresponding second doped polysilicon layer 9 is P-type doped.
[0063] Example 2
[0064] This embodiment provides a method for manufacturing a light-absorbing surface point contact TOPCon cell, and the specific steps are as follows:
[0065] S1: Select an N-type CZ original silicon wafer, first immerse the original silicon wafer in a mixed solution of KOH or NaOH with a mass fraction of 2-5% and H2O2 with a mass fraction of 2-6% at a temperature of 65°C to 85°C to remove the damaged layer, and then use a KOH or NaOH solution with a mass fraction of 10% to 30% to perform double-sided polishing;
[0066] Step 2: Deposit a SiO2 or SiONx mask layer with a thickness of 20nm to 100nm on one of the polished surfaces (defined as the front surface) by PECVD, and then remove the SiO2 or SiONx mask layer formed by plating around the edge of the other polished surface by chain equipment using a HF solution with a volume fraction of 20% to 50%;
[0067] Step 3: The first tunneling oxide layer 5 is grown on the back surface of the silicon wafer by PECVD, and then an in-situ phosphorus-doped N-type first doped polysilicon layer 6 is formed by PVD, and then the doping source is activated by annealing at a temperature of 840° C. to 900° C., oxygen is introduced during the annealing process, and a SiO2 layer with a thickness of ≥20 nm is grown on the surface of the N-type first doped polysilicon layer 6 to serve as a back surface mask layer;
[0068] Step 4: Use chain equipment and tank wet cleaning equipment, HF solution with a volume fraction of 20% to 50%, and KOH (or KOH mixed with a special polysilicon auxiliary cleaning additive) solution to remove the N-type first doped polysilicon layer 6 generated by the plating around the edge of the front surface and the SiO2 or SiONx mask layer grown in step S2, so that the polished surface of the front surface is exposed;
[0069] Step 5: On the front surface of the battery, the second tunneling oxide layer 10 and the P-type second doped polysilicon layer 9 are prepared in sequence by in-situ doping LPCVD, and oxygen is introduced during the annealing process to grow a SiO2 layer with a thickness of ≥20nm on the surface of the P-type second doped polysilicon layer 9 to serve as a front surface mask layer;
[0070] Step 6: Use a UV picosecond laser to selectively remove the SiO2 mask layer on the front surface, leaving the second area 14, and then Figure 1 The first region 13 is subjected to a texturing treatment using a KOH or NaOH solution having a mass fraction of 1% to 3% and a mixed solution of isopropyl alcohol or a texturing additive having a volume fraction of 0.5% to 1%, so that the first region 13 forms a velvet structure to increase the optical absorption of the light absorbing surface;
[0071] Step 7: Load the silicon wafer with a velvet structure in a local area of the light-absorbing surface obtained in the above step (in a back-to-back double-insertion manner) into a tubular low-pressure boron diffusion furnace tube, select a boron trichloride gas source as a doping source, and then complete the doping of the light-absorbing surface doping layer 3 at a high temperature of 850° C. to 1050° C. for 20 to 100 minutes. The light-absorbing surface doping layer 3 is a P-type doped emitter layer;
[0072] Step 8: Use HF solution with a volume fraction of 2% to 5% to clean and remove the SiO2 or SiONx mask layer on the front and back sides of the structure, and then grow a dielectric passivation layer of Al2O3, namely, dielectric layer 2, on the surface of the P-type doped layer on the light-absorbing surface and the P-type second doped polysilicon layer 9 by atomic layer deposition; finally, use PECVD to grow the first anti-reflection layer 1 and the second anti-reflection layer 7 on the front and back sides respectively, and both anti-reflection layers are SiNx:H film layers with different refractive indices. The first anti-reflection layer 1 is a SiNx:H film layer with a thickness of 70 to 80 nm, and the flow ratio of SiH4 to NH3 during the coating process is about 1:4, and the coating temperature is set to 450°C to 480°C; the second anti-reflection layer 7 is a SiNx:H film layer with a thickness of 80 to 100 nm, and the flow ratio of SiH4 to NH3 during the coating process is about 1:5. In order to improve the density of the SiNx film layer, the coating temperature is set to 490°C to 550°C;
[0073] Step nine: The first metal contact electrode 8, the second metal contact electrode 11 and the metal grid line 12 are respectively formed by screen printing and superimposed sintering. The first metal contact electrode 8 penetrates the second anti-reflection layer 7 and contacts the N-type first doped polysilicon layer 6; the second metal contact electrode 11 penetrates the first anti-reflection layer 1 and the Al2O3 dielectric passivation layer, that is, the dielectric layer 2, and finally forms a point contact with the P-type second doped polysilicon layer 9; the metal grid line 12 connects the point contact contact formed by the light-absorbing surface of the battery to the second metal contact electrode 11, and the metal grid line 12 only contacts the first anti-reflection layer 1 in the first area 13, completing the production of the battery structure.
[0074] Example 3
[0075] This embodiment provides a method for manufacturing a light-absorbing surface point contact TOPCon cell, and the specific steps are as follows:
[0076] Step 1: Select a P-type CZ original silicon wafer, first immerse the original silicon wafer in a mixed solution of KOH or NaOH with a mass fraction of 2-5% and H2O2 with a mass fraction of 2-6% at a temperature of 65°C to 85°C to remove the damaged layer, and then use a KOH or NaOH solution with a mass fraction of 10% to 30% for double-sided polishing;
[0077] Step 2: Deposit a SiO2 or SiONx mask layer with a thickness of 20nm to 100nm on one of the polished surfaces (defined as the front surface) by PECVD, and then remove the SiO2 or SiONx mask layer formed by plating around the edge of the other polished surface by chain equipment using a HF solution with a volume fraction of 20% to 50%;
[0078] Step 3: The back surface is thermally oxidized to grow the first tunneling oxide layer 5, and then the in-situ phosphorus-doped N-type first doped polysilicon layer 6 is formed by LPCVD, and then the passivated contact emitter layer is formed by annealing at a temperature of 850°C to 1000°C. At the same time, oxygen is introduced during the annealing process to grow a SiO2 layer with a thickness of ≥20nm on the surface of the N-type first doped polysilicon layer 6 to serve as a back surface mask layer;
[0079] Step 4: Use chain equipment and tank wet cleaning equipment, HF solution with a volume fraction of 20% to 50%, and KOH (or KOH mixed with a special polysilicon auxiliary cleaning additive) solution to remove the N-type first doped polysilicon layer 6 generated by the plating around the edge of the front surface and the SiO2 or SiONx mask layer grown in step S2, so that the polished surface of the front surface is exposed;
[0080] Step 5: A second tunnel oxide layer 10 is grown on the front surface of the battery by PECVD, followed by a single-sided growth of a P-type second doped polysilicon layer 9 by in-situ doping PVD, and oxygen is introduced during the subsequent annealing process to grow a SiO2 layer with a thickness of ≥20 nm on the surface of the P-type second doped polysilicon layer 9 to serve as a front surface mask layer;
[0081] Step 6: Use a UV picosecond laser to selectively remove the SiO2 mask layer on the front surface, leaving Figure 1 The second area 14 shown, and then Figure 1 The first region 13 is subjected to a texturing treatment using a KOH or NaOH solution having a mass fraction of 1% to 3% and a mixed solution of isopropyl alcohol or a texturing additive having a volume fraction of 0.5% to 1%, so that the first region 13 forms a velvet structure to increase the optical absorption of the light absorbing surface;
[0082] Step 7: Load the silicon wafer with a velvet (textured) structure in a local area of the light-absorbing surface obtained in the above step (in a back-to-back double-insertion manner) into a tubular low-pressure boron diffusion furnace tube, select a boron trichloride gas source as a doping source, and then complete the doping of the light-absorbing surface doping layer 3 at a high temperature of 850° C. to 1050° C. for 20 to 100 minutes. The light-absorbing surface doping layer 3 is a front surface field passivation doping layer;
[0083] Step 8: Use HF solution with a volume fraction of 2% to 5% to clean and remove the SiO2 or SiONx mask layer on the front and back sides of the structure, and then grow a dielectric passivation layer of Al2O3, that is, dielectric layer 2, on the surface of the P-type field passivation doping layer and the P-type second doped polysilicon layer 9 on the light-absorbing surface by atomic layer deposition; finally, use PECVD to grow the first anti-reflection layer 1 and the second anti-reflection layer 7 on the front and back sides respectively, and both anti-reflection layers are SiNx:H film layers with different refractive indices. The first anti-reflection layer 1 is a SiNx:H film layer with a thickness of 70 to 80 nm, and the flow ratio of SiH4 to NH3 during the coating process is about 1:4, and the coating temperature is set to 450°C to 480°C; the second anti-reflection layer 7 is a SiNx:H film layer with a thickness of 80 to 100 nm, and the flow ratio of SiH4 to NH3 during the coating process is about 1:5. In order to improve the density of the SiNx film layer, the coating temperature is set to 490°C to 550°C;
[0084] Step nine: The first metal contact electrode 8, the second metal contact electrode 11 and the metal grid line 12 are respectively formed by screen printing and superimposed sintering. The first metal contact electrode 8 penetrates the second anti-reflection layer 7 and contacts the N-type first doped polysilicon layer 6; the second metal contact electrode 11 penetrates the first anti-reflection layer 1 and the Al2O3 dielectric passivation layer, that is, the dielectric layer 2, and finally forms a point contact with the P-type second doped polysilicon layer 9; the metal grid line 12 connects the point contact contact formed by the light-absorbing surface of the battery to the second metal contact electrode 11, and the metal grid line 12 only contacts the first anti-reflection layer 1 in the first area 13, completing the production of the battery structure.
[0085] Example 4
[0086] This embodiment provides a method for manufacturing a light-absorbing surface point contact TOPCon cell, and the specific steps are as follows:
[0087] S1: polishing the silicon wafer and preparing a first tunneling oxide layer 5 and a first doped polysilicon layer 6;
[0088] S1 is specifically:
[0089] S1.1: Immerse the silicon wafer in a mixed solution of KOH or NaOH with a mass fraction of 2-5% and H2O2 with a mass fraction of 2-6% at a temperature of 65°C to 85°C to remove the damaged layer, and then polish it with a KOH or NaOH solution with a mass fraction of 10% to 30%;
[0090] S1.2: deposit a SiO2 layer or a SiONx mask layer on one polished surface of a selected silicon wafer by PECVD, and then remove the mask layer on the edge of the other polished surface by HF solution;
[0091] S1.3: The backlight surface of the silicon wafer is sequentially prepared by PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment to complete the preparation of the first tunneling oxide layer 5 and the first doped polysilicon layer 6; at the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20nm is grown on the surface of the first doped polysilicon layer 6 to serve as a back surface mask layer;
[0092] S1.4: Use chain equipment and trough wet cleaning equipment to remove the first doped polysilicon layer 6 produced by the plating around the edge of the front surface and the SiO2 or SiONx mask layer grown in S1.2, so that the polished surface of the front surface of the silicon wafer is exposed.
[0093] S2: preparing a second doped polysilicon layer 9 and a second tunneling oxide layer 10;
[0094] S2 is specifically:
[0095] PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment are used to sequentially prepare the second tunneling oxide layer 10 and the second doped polysilicon layer 9, and the doping types of the first doped polysilicon layer 6 and the second doped polysilicon layer 9 are opposite. At the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20nm is grown on the surface of the second doped polysilicon layer 9 to serve as a front surface mask layer.
[0096] S3: performing texturing treatment on the first region 13 using a mixed solution of a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropanol or a texturing additive with a volume fraction of 0.5% to 1%, to obtain a treated silicon wafer;
[0097] S3 specifically comprises: using an ultraviolet picosecond laser to remove the mask layer on the front surface, retaining the second area 14, and then performing a texturing treatment on the first area 13 using a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropyl alcohol or a texturing additive mixed solution with a volume fraction of 0.5% to 1%, so that the first area 13 forms a velvet structure, and a silicon wafer with a velvet structure is obtained.
[0098] S4: loading the silicon wafer processed in S3 into a tubular low-pressure diffusion furnace, and then maintaining the temperature at 800° C. to 1050° C. for 20 to 100 minutes to complete the doping of the light-absorbing surface doping layer 3;
[0099] S5: The S4-doped silicon wafer is cleaned with HF solution, and a dielectric passivation layer, namely, a dielectric layer 2, is first grown on the surfaces of the light-absorbing surface doped layer 3 and the second doped polysilicon layer 9; and then a first anti-reflection layer 1 and a second anti-reflection layer 7 are grown on the front surface and the back surface, respectively.
[0100] S6: Prepare and connect the first metal contact electrode 8, the second metal contact electrode 11 and the metal gate line 12 to complete the battery manufacturing.
[0101] The light-absorbing surface point contact TOPCon cell structure and its manufacturing method provided by the present invention skillfully apply the tunnel passivation contact structure to the front surface (light-absorbing surface) of the cell in a point contact manner, which not only reduces the metal composite on the front surface and improves the open circuit voltage of the solar cell, but also minimizes the optical parasitic absorption effect of the front surface polysilicon layer set on the light-absorbing surface.
Claims
1. The light-absorbing surface point contact TOPCon battery structure is characterized by: It comprises a silicon wafer, wherein the front surface of the silicon wafer is divided into a first area (13), a plurality of second areas (14) and a plurality of third areas (15); The first area (13) is configured as a suede structure, and the second areas (14) and the third areas (15) are respectively configured as suede structures or polished surface structures; The plurality of second regions (14) are evenly distributed in the first region (13), and the plurality of third regions (15) are arranged in a one-to-one correspondence in the plurality of second regions (14).
2. The light-absorbing surface point contact TOPCon cell structure according to claim 1, characterized in that: The first region (13) is provided with a first anti-reflection layer (1), a dielectric layer (2), a light-absorbing surface doping layer (3), a silicon substrate (4), a first tunneling oxide layer (5), a first doped polysilicon layer (6), a second anti-reflection layer (7) and a first metal contact electrode (8) in sequence from top to bottom; The second region (14) comprises a second doped polysilicon layer (9) and a second tunneling oxide layer (10), the second doped polysilicon layer (9) and the second tunneling oxide layer (10) being located between the dielectric layer (2) and the silicon substrate (4), the second doped polysilicon layer (9) being located on the lower surface of the dielectric layer (2), and the second tunneling oxide layer (10) being located on the upper surface of the silicon substrate (4); the first metal contact electrode (8) penetrates the first anti-reflection layer (1) and contacts the dielectric layer (2) and the first doped polysilicon layer (6); The third region (15) is filled with a second metal contact electrode (11), and a plurality of the second metal contact electrodes (11) are in contact with and connected to the second doped polysilicon layer (9).
3. The light-absorbing surface point contact TOPCon cell structure according to claim 2, characterized in that: The first metal contact electrodes (8) are distributed in strips, and the second metal contact electrodes (11) are distributed in a rectangular, circular or elliptical shape; a plurality of the second metal contact electrodes (11) are connected via metal grid lines (12), the metal grid lines (12) are distributed in strips, and the metal grid lines (12) are in contact with the first anti-reflection layer (1).
4. The light-absorbing surface point contact TOPCon cell structure according to claim 3, characterized in that: The contact area between the second metal contact electrode (11) and the first anti-reflection layer (1) is smaller than the area where the second doped polysilicon layer (9) is provided, and the lateral width of the metal gate line (12) is smaller than the lateral width of the second doped polysilicon layer (9).
5. The light-absorbing surface point contact TOPCon cell structure according to claim 4, characterized in that: The silicon substrate (4) is an N-type or P-type silicon wafer, the first doped polysilicon layer (6) is N-type or P-type doped, and the second doped polysilicon layer (9) is P-type or N-type doped.
6. The light-absorbing surface point contact TOPCon cell structure according to claim 5, characterized in that: The second doped polysilicon layer (9) is in any one of a rectangular, diamond, circular or elliptical shape.
7. A method for manufacturing a light-absorbing surface point contact TOPCon battery, characterized in that: The light-absorbing surface point contact TOPCon battery structure as claimed in claim 6 is adopted, and the specific steps are as follows: S1: polishing the silicon wafer and preparing the first tunneling oxide layer (5) and the first doped polysilicon layer (6); S2: preparing a second doped polysilicon layer (9) and a second tunneling oxide layer (10); S3: performing texturing treatment on the first region (13) using a mixed solution of a KOH or NaOH solution with a mass fraction of 1% to 3% and an isopropanol or a texturing additive with a volume fraction of 0.5% to 1%, to obtain a treated silicon wafer; S4: loading the silicon wafer treated in S3 into a tubular low-pressure diffusion furnace, and then maintaining the temperature at 800° C. to 1050° C. for 20 to 100 minutes to complete doping of the light-absorbing surface doping layer (3); S5: cleaning the S4-doped silicon wafer with an HF solution, first growing a dielectric layer (2) on the light-absorbing surface doping layer (3) and the surface of the second doped polysilicon layer (9); and then growing a first anti-reflection layer (1) and a second anti-reflection layer (7) on the front surface and the back surface respectively; S6: Prepare and connect the first metal contact electrode (8), the second metal contact electrode (11) and the metal grid line (12) to complete the battery manufacturing.
8. The method for manufacturing a light-absorbing surface point contact TOPCon cell according to claim 6, characterized in that: The S1 is specifically: S1.1: Immerse the silicon wafer in a mixed solution of KOH or NaOH with a mass fraction of 2 to 5% and H2O2 with a mass fraction of 2 to 6% at a temperature of 65°C to 85°C to remove the damaged layer, and then polish it with a KOH or NaOH solution with a mass fraction of 10% to 30%; S1.2: deposit a SiO2 layer or a SiONx mask layer on one polished surface of a selected silicon wafer by PECVD, and then remove the mask layer on the edge of the other polished surface by HF solution; S1.3: The backlight surface of the silicon wafer is sequentially prepared by PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment. At the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20 nm is grown on the surface of the first doped polysilicon layer (6) to serve as a back surface mask layer; S1.4: Use chain equipment and tank wet cleaning equipment to remove the first doped polysilicon layer (6) produced by plating around the edge of the front surface and the SiO2 or SiONx mask layer grown in S1.2, so that the polished surface of the front surface of the silicon wafer is exposed.
9. The method for manufacturing a light-absorbing surface point contact TOPCon cell according to claim 6, characterized in that: The S2 is specifically: The second tunneling oxide layer (10) and the second doped polysilicon layer (9) are prepared in sequence using PECVD, LPCVD, PVD or APCVD equipment and doping annealing equipment, and the doping types of the first doped polysilicon layer (6) and the second doped polysilicon layer (9) are opposite. At the same time, during the doping annealing process, a SiO2 layer with a thickness of not less than 20 nm is grown on the surface of the second doped polysilicon layer (9) to serve as a front surface mask layer.
10. The method for manufacturing a light-absorbing surface point contact TOPCon cell according to claim 8, characterized in that: The S3 specifically comprises: using an ultraviolet picosecond laser to remove the mask layer on the front surface, retaining the second area (14), and then performing a texturing treatment on the first area (13) using a KOH or NaOH solution with a mass fraction of 1% to 3% and a mixed solution of isopropyl alcohol or a texturing additive with a volume fraction of 0.5% to 1%, so that the first area (13) forms a velvet structure, thereby obtaining a silicon wafer with a velvet structure.