Manufacturing method of back contact battery

Abstract

The invention discloses a manufacturing method of a back contact battery, relates to the field of photovoltaic technology, and aims to improve the working performance of the back contact battery. The manufacturing method of the back contact battery comprises the following steps: providing a semiconductor substrate; and sequentially forming a first interface passivation layer and a first doped silicon layer which are stacked on the first surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. And forming an insulating mask pattern on a partial region of one side, deviating from the semiconductor substrate, of the first doped silicon layer. And removing the parts, exposed outside the insulating mask pattern, of the stacked first interface passivation layer and the first doped silicon layer. And texturing treatment is carried out on the surface of the area, exposed out of the insulating mask pattern, of the first surface and the second surface. A first passivation layer is formed on the second side of the semiconductor substrate. And sequentially forming a second interface passivation layer and a second doped silicon layer which are stacked on the first interface passivation layer and the first doped silicon layer which are stacked and the first surface. And selectively etching the stacked second interface passivation layer and second doped silicon layer.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a method for manufacturing a back-contact battery. Background Art

[0002] A solar cell is a device that can convert the above-mentioned solar light energy into electrical energy. Specifically, when the solar cell is in working state, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, the photogenerated holes flow to the p region, and the photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the battery is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for realizing high-efficiency crystalline silicon cells.

[0003] However, the existing manufacturing process of the back-contact battery is relatively complicated, which is not conducive to improving the manufacturing efficiency of the back-contact battery and reducing the manufacturing cost. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a back-contact battery, which can improve the manufacturing efficiency of the back-contact battery, reduce the manufacturing cost, and help improve the conversion efficiency of the back-contact battery.

[0005] In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a back-contact battery, which comprises: first, providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface opposite to each other. Next, a stacked first interface passivation layer and a first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. Next, an insulating mask pattern is formed on a partial area of ​​the first doped silicon layer away from the semiconductor substrate. Next, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern are removed. Next, the area of ​​the first surface exposed outside the insulating mask pattern and the second surface are subjected to a texturing treatment. Next, a first passivation layer is formed on the second surface of the semiconductor substrate. Next, a stacked second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate. The conductivity types of the second doped silicon layer and the first doped silicon layer are opposite. Next, a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer is removed to expose a portion of the first interface passivation layer and the first doped silicon layer.

[0006] In the case of adopting the above technical solution, the stacked first interface passivation layer and the first doped silicon layer, and the stacked second interface passivation layer and the second doped silicon layer can respectively constitute a passivation contact structure, which has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate of the first surface of the semiconductor substrate, and improve the conversion efficiency of the back contact battery. In addition, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the area of ​​the first surface where the first interface passivation layer and the first doped silicon layer are not formed is also exposed. At this time, the area of ​​the first surface exposed outside the insulating mask pattern and the second surface can be subjected to a texturing treatment at the same time, which improves the light trapping effect of the second surface. The second doped silicon layer formed on the area of ​​the first surface exposed outside the insulating mask pattern is also affected by the velvet surface and has roughly the same undulating morphology, which increases the specific surface area of ​​the second doped silicon layer on the side away from the semiconductor substrate. Therefore, it is also beneficial to increase the contact area between the second doped silicon layer and the conductive material (such as a transparent conductive layer or an electrode, etc.), reduce transmission loss, and further improve the conversion efficiency of the back contact battery. At the same time, since the area of ​​the first surface exposed outside the insulating mask pattern and the second surface can be subjected to a texturing treatment at the same time, the manufacturing efficiency of the back contact battery can also be improved. In addition, the second interface passivation layer and the second doped silicon layer also cover part of the first interface passivation layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, which can reduce the etching amount of the second interface passivation layer and the second doped silicon layer, and improve the etching capacity. At the same time, the edges of the first interface passivation layer and the first doped silicon layer are covered with the second interface passivation layer and the second doped silicon layer, which can prevent the etchant from affecting the edge portions of the first interface passivation layer and the first doped silicon layer, thereby improving the collection efficiency of the edge portions of the first interface passivation layer and the first doped silicon layer for carriers. In addition, no isolation groove is provided between the first interface passivation layer, the first doped silicon layer and the second interface passivation layer, the second doped silicon layer, so the contact area between the first interface passivation layer, the first doped silicon layer and the semiconductor substrate, and the contact area between the second interface passivation layer, the second doped silicon layer and the semiconductor substrate can be maximized, thereby improving the utilization rate of the semiconductor substrate, and further improving the photoelectric conversion efficiency.

[0007] As a possible implementation scheme, the texturing treatment of the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: while texturing the area of ​​the first surface exposed outside the insulating mask pattern and the second surface, removing the insulating mask pattern. Alternatively, the texturing treatment of the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: texturing the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; retaining the insulating mask pattern after the texturing treatment.

[0008] In the case of adopting the above technical solution, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the insulating mask pattern, the area exposed outside the insulating mask pattern in the first surface of the semiconductor substrate, and the second surface are all exposed. Based on this, when performing the above-mentioned texturing treatment, the texturing liquid will not only contact the area exposed outside the insulating mask pattern and the second surface of the first surface of the semiconductor substrate, but also contact the insulating mask pattern. At this time, in the manufacturing method provided by the present invention, the insulating mask pattern can be removed at the same time when performing the above-mentioned texturing treatment, or it can be removed after the texturing, and it can also be retained after the texturing treatment. It can be seen that after the texturing treatment, whether the insulating mask pattern is retained has two optional examples, which is conducive to reducing the material restrictions on the insulating mask pattern, and at the same time, it is also conducive to improving the applicability of the manufacturing method provided by the present invention in different application scenarios. Among them, when the insulating mask pattern is retained, it is conducive to separating the first doped silicon layer and the second doped silicon layer of the opposite conductivity type to itself, preventing leakage, and reducing the forward leakage loss of the back contact battery. When the insulating mask pattern is removed, a diode structure with a higher reverse breakdown voltage can be formed between the first doped silicon layer and the second doped silicon layer with opposite conductivity type, thereby reducing the risk of hot spots of the back-contact battery in an installation environment with many obstructions such as sand and dust.

[0009] As a possible implementation scheme, the first interfacial passivation layer and the first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate, including: while the first interfacial passivation layer and the first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate, a first doped silicon glass layer is formed on the side of the first doped silicon layer away from the semiconductor substrate; and the insulating mask pattern is formed on a partial area of ​​the first doped silicon layer away from the semiconductor substrate, including: patterning the first doped silicon glass layer to form an insulating mask pattern. In this case, the first doped silicon glass layer can be formed at the same time as the first doped silicon layer is formed, and there is no need to use an additional deposition process to form a corresponding insulating mask pattern in order to form the insulating mask pattern, which is conducive to simplifying the manufacturing process of the back contact battery and improving the manufacturing efficiency of the back contact battery.

[0010] As a possible implementation scheme, sequentially forming a stacked first interface passivation layer and a first doped silicon layer on a first surface of a semiconductor substrate includes: while sequentially forming a stacked first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on a side of the first doped silicon layer away from the semiconductor substrate; and forming an insulating mask pattern on a partial area of ​​the first doped silicon layer on a side away from the semiconductor substrate includes: forming an insulating layer on a side of the first doped silicon glass layer away from the semiconductor substrate; and patterning the first doped silicon glass layer and the insulating layer to form an insulating mask pattern.

[0011] In the case of adopting the above technical solution, compared with the insulating mask pattern of a single-layer structure, the insulating mask pattern in this case includes not only the first doped silicon glass layer after patterning, but also the insulating layer after patterning, which is conducive to improving the protection effect of the insulating mask pattern. Secondly, if the insulating mask pattern is retained after the texturing process, the insulating mask pattern including the first doped silicon glass layer and the insulating layer also has a high insulation isolation effect, which can further reduce the leakage risk of the overlapping part of the second doped silicon layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, and further improve the conversion efficiency of the back contact battery.

[0012] As a possible implementation scheme, sequentially forming a stacked first interface passivation layer and a first doped silicon layer on a first surface of a semiconductor substrate includes: while sequentially forming a stacked first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on a side of the first doped silicon layer away from the semiconductor substrate; and forming an insulating mask pattern on a partial area of ​​the first doped silicon layer on a side away from the semiconductor substrate includes: removing the first doped silicon glass layer; forming an insulating layer on a side of the first doped silicon layer away from the semiconductor substrate; and patterning the insulating layer to form an insulating mask pattern.

[0013] When the above technical solution is adopted, the insulating mask pattern can be directly formed on the side of the first doped silicon glass layer away from the semiconductor substrate. Since the insulating material (such as silicon oxide, aluminum oxide or silicon nitride, etc.) used to make the insulating mask pattern may have a passivation effect, it can not only play a mask protection and insulation role, but also directly passivate the side of the first doped silicon layer away from the semiconductor substrate, which is beneficial to reduce the surface defects of the first doped silicon layer away from the semiconductor substrate, and further improve the conversion efficiency of the back contact battery.

[0014] As a possible implementation scheme, forming a first passivation layer on the second surface of the semiconductor substrate includes: forming the first passivation layer on the second surface of the semiconductor substrate and forming the first passivation layer on the first surface of the semiconductor substrate at the same time. Next, annealing the first passivation layer. Next, removing the first passivation layer located on the first surface of the semiconductor substrate.

[0015] When the above technical solution is adopted, the first passivation layer is formed on the second surface of the semiconductor substrate while the first passivation layer is formed on the first surface. The presence of the first passivation layer on the first surface can passivate the side of the first doped silicon layer away from the semiconductor substrate during the annealing process, thereby reducing the surface defects of the first doped silicon layer away from the semiconductor substrate. It can also prevent the occurrence of problems such as hydrogen escape affecting the passivation effect of the first doped silicon layer due to the side of the first doped silicon layer away from the semiconductor substrate being exposed to the outside during the annealing process after the insulating mask pattern is removed, thereby ensuring that the back contact battery has a higher conversion efficiency.

[0016] As a possible implementation scheme, the first passivation layer includes an intrinsic silicon passivation layer. In this case, the intrinsic silicon passivation layer has a high hydrogen content, which can make the first passivation layer have a high passivation effect on the second surface of the semiconductor substrate, further improving the conversion efficiency of the manufactured back contact battery. During the annealing process, the first passivation layer can perform hydrogen injection into the first doped silicon layer, that is, replenish hydrogen, which can improve the passivation effect of the first doped silicon layer.

[0017] As a possible implementation scheme, after sequentially forming a stacked second interface passivation layer and a second doped silicon layer on the first surface, before removing a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the method for a back contact cell further includes: forming an anti-reflection layer on a side of the first passivation layer away from the semiconductor substrate. In this case, the reflectivity of the manufactured back contact cell on the second surface side is reduced, thereby further improving the conversion efficiency of the back contact cell.

[0018] As a possible implementation scheme, after the area of ​​the first surface exposed outside the insulating mask pattern and the second surface are textured, and before the first passivation layer is formed on the second surface of the semiconductor substrate, a stacked second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface.

[0019] In the case of adopting the above technical solution, the formation order of the stacked second interface passivation layer and the second doped silicon layer can not only be set after at least forming the first passivation layer, but also after the texturing treatment and before at least forming the first passivation layer, which adds another optional example to the manufacturing method provided by the present invention, which is conducive to improving the applicability of the manufacturing method provided by the present invention in different application scenarios. At the same time, when the first passivation layer is formed on the second surface of the semiconductor substrate, the first passivation layer may be plated around the side of the semiconductor substrate and at least part of the first surface. Based on this, when the formation order of the stacked second interface passivation layer and the second doped silicon layer is set after the texturing treatment and before at least forming the first passivation layer, it is no longer necessary to remove at least the part of the first passivation layer plated to one side of the first surface before forming the stacked second interface passivation layer and the second doped silicon layer, thereby reducing the process steps. It can be determined according to actual needs whether to remove the first passivation layer plated around one side of the first surface after at least forming the first passivation layer, thereby reducing manufacturing requirements. Moreover, in this case, the corresponding structure on the first side can be manufactured first, and then the corresponding film layer (first passivation layer and anti-reflection layer) on the second side can be manufactured, so as to reduce the number of flipping times and reduce the risk of damage.

[0020] As a possible implementation solution, the first passivation layer includes a second doped silicon glass layer, and the conductivity type of the dopant in the second doped silicon glass layer is the same as the conductivity type of the first doped silicon layer.

[0021] When the above technical solution is adopted, compared with the intrinsic silicon passivation layer, the second doped silicon glass layer has a higher light transmittance property. Therefore, compared with the first passivation layer including the intrinsic silicon passivation layer, when the first passivation layer includes the second doped silicon glass layer, the parasitic absorption of the first passivation layer can be reduced, which is beneficial to improve the utilization rate of light by the back contact battery. In addition, the second doped silicon glass layer is also doped with a dopant of the same conductivity type as the first doped silicon layer, so that the first passivation layer can not only chemically passivate the second side of the semiconductor substrate, but also field passivate the second side of the semiconductor substrate, which reduces the carrier recombination rate on the second side, and is also beneficial to improve the carrier collection efficiency of the first doped silicon layer and the second doped silicon layer. Compared with the need for separate deposition, the second doped silicon glass layer can be formed by a diffusion process, which simplifies the difficulty of making the first passivation layer.

[0022] As a possible implementation scheme, forming a first passivation layer on the second surface of the semiconductor substrate includes: forming a first passivation layer and an anti-reflection layer stacked in sequence along the thickness direction of the semiconductor substrate on the second surface of the semiconductor substrate. In this case, the reflectivity of the back contact cell on the second surface side is reduced, and the conversion efficiency of the back contact cell is further improved.

[0023] As a possible implementation scheme, after removing the part of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the manufacturing method of the back contact battery also includes: forming a transparent conductive layer covering the first doped silicon layer and the second doped silicon layer on the side away from the semiconductor substrate. An isolation groove is formed through the transparent conductive layer to disconnect the part of the transparent conductive layer corresponding to the first doped silicon layer from the part of the transparent conductive layer corresponding to the second doped silicon layer. Next, a first electrode is formed on the part of the transparent conductive layer corresponding to the first doped silicon layer, and a second electrode is formed on the part of the transparent conductive layer corresponding to the second doped silicon layer. In this case, the transparent conductive layer has a higher carrier transport characteristic, which is beneficial to improving the carrier collection efficiency. In addition, the transparent conductive layer is arranged between the metal electrode and the semiconductor layer, which is beneficial to reducing the contact barrier and reducing the contact resistance.

[0024] As a possible implementation scheme, the thickness of the edge portion of the transparent conductive layer adjacent to the isolation groove gradually decreases in the direction close to the isolation groove. In this case, the thickness of the transparent conductive layer close to both sides of the isolation groove is relatively small, and the thickness of the two parts of the transparent conductive layer used to transmit opposite-sex carriers is relatively small (the facing area is also relatively small), which is beneficial to reduce the risk of leakage and improve the electrical reliability of the back contact battery. In addition, such a setting is also conducive to the stress release between other structures in the back contact battery and the transparent conductive layer, avoiding the edge of the transparent conductive layer from being easily broken or falling off due to excessive stress during the formation process, thereby improving the structural reliability of the manufactured back contact battery.

[0025] As a possible implementation scheme, the second interface passivation layer and the second doped silicon layer stacked in sequence, and the transparent conductive layer disposed on the second doped silicon layer all cover a portion of the stacked first interface passivation layer and the first doped silicon layer away from the semiconductor substrate. And / or, the portion where the first interface passivation layer, the first doped silicon layer, the second interface passivation layer and the second doped silicon layer are stacked and disposed along the thickness direction of the semiconductor substrate is an overlapping region; at least a portion of the overlapping region is a reverse leakage region, and in the reverse leakage region, the second doped silicon layer is electrically connected to the first doped silicon layer through the second interface passivation layer.

[0026] When the above technical solution is adopted, in the reverse leakage region formed, the second doped silicon layer can be electrically connected to the first doped silicon layer with opposite conductivity type to its own through the second interface passivation layer to form a built-in diode structure with a lower reverse breakdown voltage, thereby reducing the risk of hot spots in the back-contact battery.

[0027] As a possible implementation solution, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm.

[0028] When the above technical solution is adopted, the presence of the transparent conductive layer can improve the carrier collection efficiency and leave room for thinning the first doped silicon layer. In other words, without reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is conducive to reducing its own parasitic absorption and further improving the working efficiency of the back contact battery. In addition, since the thickness of the first doped silicon layer is small, the formation time of the first doped silicon layer can be reduced, thereby improving the manufacturing efficiency.

[0029] As a possible implementation scheme, the width of the opening area of ​​the second interface passivation layer and the second doped silicon layer is greater than or equal to 250 μm and less than or equal to 400 μm.

[0030] In the case of adopting the above technical solution, it can be understood that the first doped silicon layer needs to be electrically connected to the corresponding conductive material through the opening area set in the second interface passivation layer and the second doped silicon layer, so as to lead out the carriers collected by itself. The carriers transmitted by the conductive material electrically connected to the first doped silicon layer are of the opposite conductivity type to that of the second doped silicon layer. Based on this, compared with the width of the opening area of ​​the second interface passivation layer and the second doped silicon layer in the existing back contact battery being less than 250μm, the back contact battery formed by the manufacturing method provided by the present invention has a larger width of the opening area for exposing the first doped silicon layer to the outside, which is beneficial to prevent short circuits. Under the premise, the corresponding conductive material electrically connected to the first doped silicon layer has a larger formable range, thereby facilitating the increase of the contact area between the first doped silicon layer and the corresponding conductive material, reducing transmission losses, and improving the electrical reliability of the manufactured back contact battery. Secondly, when the width of the above-mentioned opening area is less than or equal to 400μm, more parts of the second interface passivation layer and the second doped silicon layer are retained after the opening operation, which reduces the etching amount while ensuring that the second interface passivation layer and the second doped silicon layer have a certain area occupancy on one side of the first surface, ensuring that the second doped silicon layer has a higher current collection efficiency.

[0031] As a possible implementation scheme, in the first surface, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-like texture structure. Moreover, the thickness of the first interface passivation layer at the bottom surface of the tower-like texture structure is less than the thickness of the first interface passivation layer at the side wall of the tower-like texture structure.

[0032] In the case of adopting the above technical solution, it can be understood that the bottom surface of the tower-shaped texture structure and the side surface of the tower-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped texture structure is the

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-shaped texture structure is the

[111] crystal orientation, and the number of dangling bonds in the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial to make the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure have a relatively high passivation effect, meet the demand for high passivation effect on the side surface of the tower-shaped texture structure, reduce the carrier recombination rate on the side surface of the tower-shaped texture structure, and further improve the working efficiency of the back contact battery.

[0033] As a possible implementation scheme, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is greater than or equal to 0.5nm and less than or equal to 1.5nm. In this case, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is within the above range, which is conducive to preventing the first interface passivation layer from having a lower passivation effect on the semiconductor substrate due to the smaller thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure; in addition, it is also conducive to preventing the first interface passivation layer from having a higher tunneling resistance due to the larger thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure, and is conducive to achieving a balance between the passivation effect and tunneling resistance of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure, while ensuring that the first doped silicon layer has a higher carrier collection efficiency and reduces transmission loss.

[0034] As a possible implementation scheme, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is greater than or equal to 0.5nm and less than or equal to 2nm. In this case, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is within the above range, which is conducive to preventing the passivation effect of the first interface passivation layer from being low due to the small thickness of the part; in addition, it is also conducive to preventing the first interface passivation layer from being thicker on the side wall of the tower-shaped texture structure, which leads to a high tunneling resistance of the part, and is conducive to achieving a balance between the passivation effect and the tunneling resistance of the part of the first interface passivation layer located on the side wall of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure, while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0035] As a possible implementation scheme, the thickness of the second interface passivation layer is greater than or equal to 3nm and less than or equal to 16nm. In this case, the thickness of the second interface passivation layer is relatively large, which is conducive to enhancing the isolation effect of the second interface passivation layer on the first doped silicon layer and the second doped silicon layer, reducing the risk of leakage. In addition, it can also prevent the contact resistance from being large due to the excessive thickness of the second interface passivation layer, thereby reducing the transmission loss.

[0036] As a possible implementation scheme, the first doped silicon layer is a doped polycrystalline silicon layer. And the back contact cell also includes an amorphous silicon layer, which is arranged on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer can passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is less than the work function difference between the doped polycrystalline silicon layer and the transparent conductive layer, that is, the contact barrier between the amorphous silicon layer and the transparent conductive layer is less than the contact barrier between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is less than the contact resistance between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared with the first doped silicon layer directly contacting the transparent conductive layer, the amorphous silicon layer is arranged on the side of the first doped silicon layer away from the semiconductor substrate, which can achieve more reasonable energy band matching, reduce contact resistance, so that the back contact cell can effectively convert sunlight into electrical energy, and improve the photoelectric conversion efficiency of the back contact cell.

[0037] As a possible implementation scheme, removing a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer includes: using a laser to remove a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, and using a laser to process an edge portion of an opening area of ​​the second doped silicon layer so that a hole structure is formed in the edge portion of the second doped silicon layer.

[0038] In the case of adopting the above technical solution, it can be understood that the hole structure is a hollow structure, so when the hole structure is formed in the edge portion of the second doped silicon layer, the risk of leakage between the edge portion of the second doped silicon layer and the first doped silicon layer can be reduced, and the electrical reliability of the back contact battery can be improved. In addition, the presence of the hole structure can also increase the undulation of the edge portion of the stacked second interface passivation layer and the second doped silicon layer, thereby enhancing the light trapping effect of this portion, which is conducive to improving the bifaciality of the back contact battery.

[0039] As a possible implementation scheme, the first surface includes a first area and a second area. The second area includes a groove. The first interface passivation layer and the first doped silicon layer are located in the first area. The second interface passivation layer and the second doped silicon layer are located in the second area, and extend to the first area to cover part of the first interface passivation layer and the first doped silicon layer. The surface of the first area is a polished surface, and the bottom surface of the groove is a velvet surface. The thickness of the second doped silicon layer on the velvet surface is less than the thickness of the second doped silicon layer on the polished surface.

[0040] In the case of adopting the above technical solution, the presence of the groove makes the surface of the second area staggered with the surface of the first area along the thickness direction of the semiconductor substrate, thereby facilitating the second interface passivation layer and the second doped silicon layer located on the second area to be at least partially staggered with the first interface passivation layer and the first doped silicon layer located on the first area, thereby reducing the risk of leakage. In addition, compared with the polished surface, the specific surface area of ​​the velvet surface is larger. Within the same formation range, the contact area between the part of the second doped silicon layer located on the velvet surface and the semiconductor substrate is larger, while the contact area between the part of the second doped silicon layer located on the polished surface and the semiconductor substrate is smaller. Based on this, when the thickness of the second doped silicon layer located on the velvet surface is smaller, after ensuring that the part of the second doped silicon layer located on the velvet surface has sufficient contact area with the semiconductor substrate, a space that can be reduced can be reserved for setting the thickness of the part, and while ensuring a higher carrier collection efficiency, the amount of consumables used in manufacturing the part of the second doped silicon layer located on the velvet surface can also be reduced. In addition, the thickness of the second doped silicon layer located on the polished surface is larger, so that the part has a higher field passivation effect and reduces carrier recombination. In this case, the thickness difference between different parts of the second doped silicon layer can be set according to the surface roughness of the first region and the second region and actual needs, and is not specifically limited here.

[0041] As a possible implementation scheme, the first surface includes a first area and a second area. The second area includes a groove. The surface of the first area is a polished surface, and the bottom surface of the groove is a velvet surface. The first interface passivation layer and the first doped silicon layer are located in the first area. The second interface passivation layer and the second doped silicon layer are located in the second area, and extend from the second area to the first area to cover part of the first interface passivation layer and the first doped silicon layer. The distance from the surface of the semiconductor substrate located in the first area to the bottom surface of the groove is greater than or equal to 2μm and less than or equal to 8μm.

[0042] In the case of adopting the above technical solution, it is beneficial to prevent the first doped silicon layer and the second doped silicon layer from being staggered along the thickness direction of the semiconductor substrate due to the small distance from the surface of the semiconductor substrate located in the first area to the bottom surface of the groove of the groove, thereby ensuring that there is a low risk of leakage between the two; secondly, in the process of making the groove of the groove bottom surface, the semiconductor substrate needs to be corroded, so the distance from the surface of the semiconductor substrate located in the first area to the bottom surface of the groove of the groove will also affect the size of the velvet structure on the bottom surface of the groove. Based on this, the distance from the surface of the semiconductor substrate located in the first area to the bottom surface of the groove of the groove within the above range can also prevent the size of the groove bottom surface of the groove and the velvet structure formed on the second surface from being small due to the small distance, thereby ensuring that the second surface has a higher light trapping effect, and at the same time, it is beneficial to increase the specific surface area of ​​the second doped silicon layer away from the semiconductor substrate, further reducing the contact loss between the second doped silicon layer and the corresponding conductive material. In addition, it can also prevent the etching depth of the semiconductor substrate at the groove from being large due to the large distance from the surface of the semiconductor substrate located in the first area to the bottom surface of the groove of the groove, thereby ensuring that each part of the semiconductor substrate has a large light absorption depth, thereby making the back contact battery have a higher conversion efficiency.

[0043] As a possible implementation scheme, the first surface includes a first area and a second area; the second area includes a groove. The first interface passivation layer and the first doped silicon layer are located in the first area; the second interface passivation layer and the second doped silicon layer are located in the second area, and extend from the second area to the first area to cover part of the first interface passivation layer and the first doped silicon layer. The second doped silicon layer is a doped amorphous silicon layer. After the stacked second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact battery further includes: laser irradiating the second doped silicon layer located on the bottom surface of the groove to crystallize the second doped silicon layer.

[0044] In the case of adopting the above technical solution, the second doped silicon layer is a doped amorphous silicon layer, and the doped amorphous silicon layer is located in the second area including the groove. And the bottom surface of the groove is a velvet surface, and the velvet surface has a velvet structure that reflects the laser. When the second doped silicon layer located on the bottom surface of the groove is irradiated with a laser, the velvet structure reflects the laser, so that the second doped silicon layer is crystallized by heat, and the crystallization degree of the second doped silicon layer is improved, thereby improving the conductivity of the second doped silicon layer, reducing the contact resistance between the second doped silicon layer and the corresponding conductive material, and reducing the transmission loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0046] Figure 1 A flow chart of a method for manufacturing a back contact battery provided by an embodiment of the present invention;

[0047] Figure 2 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 1 ;

[0048] Figure 3 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 ;

[0049] Figure 4 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 ;

[0050] Figure 5 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4 ;

[0051] Figure 6 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 5 ;

[0052] Figure 7 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 6 ;

[0053] Figure 8 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 7 ;

[0054] Fig. 9 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 8 ;

[0055] Fig.10 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 9 ;

[0056] Fig.11 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 ;

[0057] Fig.12 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 one;

[0058] Fig.13 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 two;

[0059] Fig.14 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 three;

[0060] Fig.15 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 Four;

[0061] Fig.16 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 five;

[0062] Fig.17 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 six;

[0063] Fig.18 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 seven;

[0064] Fig.19 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 eight;

[0065] Fig. 20 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 10 Nine;

[0066] Fig.21 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 ten;

[0067] Fig. 22 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 eleven;

[0068] Fig.23 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2twelve;

[0069] Fig.24 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 Thirteen;

[0070] Fig.25 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 fourteen;

[0071] Fig.26 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 fifteen;

[0072] Fig. 27 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 sixteen;

[0073] Fig.28 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 XVII;

[0074] Fig.29 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 eighteen;

[0075] Fig.30 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 2 nineteen;

[0076] Fig.31 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 ten;

[0077] Fig.32 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 eleven;

[0078] Fig.33 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 twelve;

[0079] Fig.34 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3Thirteen;

[0080] Fig.35 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 fourteen;

[0081] Fig.36 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 fifteen;

[0082] Fig.37 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 sixteen;

[0083] Fig.38 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 XVII;

[0084] Fig.39 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 eighteen;

[0085] Fig.40 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 3 nineteen;

[0086] Fig.41 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4 ten;

[0087] Fig.42 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4 eleven;

[0088] Fig.43 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4 twelve;

[0089] Fig.44 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4 Thirteen;

[0090] Fig.45 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4fourteen;

[0091] Fig.46 Schematic diagram of the results of the back contact battery formed by the manufacturing method provided by the embodiment of the present invention during the manufacturing process Figure 4 fifteen.

[0092] Figure numerals: 11 is a semiconductor substrate, 12 is a first interface passivation layer, 13 is a first doped silicon layer, 14 is a first doped silicon glass layer, 15 is an insulating mask pattern, 16 is an insulating layer, 17 is a first passivation layer, 18 is an anti-reflection layer, 19 is a second interface passivation layer, 20 is a second doped silicon layer, 21 is a transparent conductive layer, 22 is an isolation groove, 23 is a first region, and 24 is a second region. DETAILED DESCRIPTION

[0093] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0094] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0095] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0096] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0097] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0098] A solar cell is a device that can convert sunlight into electrical energy. Specifically, when the solar cell is in operation, sunlight shines on the semiconductor pn junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field of the pn junction, photogenerated holes flow to the p region, and photogenerated electrons flow to the n region. When the circuit is connected, current can be generated. Among them, a solar cell in which both the positive electrode and the negative electrode are on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front of the back-contact cell is not blocked by a metal electrode, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0099] However, the existing manufacturing process of the back-contact battery is relatively complicated, which is not conducive to improving the manufacturing efficiency of the back-contact battery and reducing the manufacturing cost.

[0100] In order to solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a back contact battery. Figure 1As shown, the manufacturing method of the back contact battery provided by the embodiment of the present invention includes the following steps: First, a semiconductor substrate is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. Next, a stacked first interface passivation layer and a first doped silicon layer are sequentially formed on the first surface of the semiconductor substrate along the thickness direction of the semiconductor substrate. Next, an insulating mask pattern is formed on a partial area of ​​the first doped silicon layer away from the semiconductor substrate. Next, the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern are removed. Next, the area of ​​the first surface not covered by the insulating mask pattern and the second surface are subjected to a texturing treatment. Next, a first passivation layer is formed on the second surface of the semiconductor substrate. Next, a stacked second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate. The conductivity types of the second doped silicon layer and the first doped silicon layer are opposite. Next, a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer is removed to expose a portion of the first interface passivation layer and the first doped silicon layer.

[0101] It should be noted that the manufacturing method provided in the embodiment of the present invention does not specifically limit the order of execution of the above-mentioned operation steps of forming the first passivation layer on the second surface of the semiconductor substrate, and the operation steps of sequentially forming the stacked second interface passivation layer and the second doped silicon layer on the first surface along the thickness direction of the semiconductor substrate. It can be that the first passivation layer is first formed on the second surface of the semiconductor substrate, and then the stacked second interface passivation layer and the second doped silicon layer are sequentially formed on the first surface; or it can be that the stacked second interface passivation layer and the second doped silicon layer are first formed sequentially on the first surface, and then the first passivation layer is formed on the second surface of the semiconductor substrate.

[0102] In the case of adopting the above technical solution, the stacked first interface passivation layer and the first doped silicon layer, and the stacked second interface passivation layer and the second doped silicon layer can respectively constitute a passivation contact structure, which has an excellent interface passivation effect, and can realize the selective collection of carriers, reduce the carrier recombination rate of the first surface of the semiconductor substrate, and improve the conversion efficiency of the back contact battery. In addition, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the area of ​​the first surface where the first interface passivation layer and the first doped silicon layer are not formed is also exposed. At this time, the area of ​​the first surface exposed outside the insulating mask pattern and the second surface can be subjected to a texturing treatment at the same time, which improves the light trapping effect of the second surface. The second doped silicon layer formed on the area of ​​the first surface exposed outside the insulating mask pattern is also affected by the velvet surface and has roughly the same undulating morphology, which increases the specific surface area of ​​the second doped silicon layer on the side away from the semiconductor substrate. Therefore, it is also beneficial to increase the contact area between the second doped silicon layer and the conductive material (such as a transparent conductive layer or an electrode, etc.), reduce transmission loss, and further improve the conversion efficiency of the back contact battery. At the same time, since the area of ​​the first surface exposed outside the insulating mask pattern and the second surface can be subjected to a texturing treatment at the same time, the manufacturing efficiency of the back contact battery can also be improved. In addition, the second interface passivation layer and the second doped silicon layer also cover part of the first interface passivation layer and the first doped silicon layer along the thickness direction of the semiconductor substrate, which can reduce the etching amount of the second interface passivation layer and the second doped silicon layer, and improve the etching capacity. At the same time, the edges of the first interface passivation layer and the first doped silicon layer are covered with the second interface passivation layer and the second doped silicon layer, which can prevent the etchant from affecting the edge portions of the first interface passivation layer and the first doped silicon layer, thereby improving the collection efficiency of the edge portions of the first interface passivation layer and the first doped silicon layer for carriers. In addition, no isolation groove is provided between the first interface passivation layer, the first doped silicon layer and the second interface passivation layer, the second doped silicon layer, so the contact area between the first interface passivation layer, the first doped silicon layer and the semiconductor substrate, and the contact area between the second interface passivation layer, the second doped silicon layer and the semiconductor substrate can be maximized, thereby improving the utilization rate of the semiconductor substrate, and further improving the photoelectric conversion efficiency.

[0103] The following will be based on Figures 2 to 38 The cross-sectional view of the operation is shown, and the manufacturing process of the back contact battery provided by the present invention is described in various embodiments:

[0104] Embodiment 1

[0105] The first step is to provide a semiconductor substrate having a first surface and a second surface opposite to each other.

[0106] Specifically, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate, and the semiconductor substrate can be a substrate of any semiconductor material such as a silicon substrate, a silicon germanium substrate, a germanium substrate, or a gallium arsenide substrate. In addition, the conductivity type of the semiconductor substrate can be N-type or P-type.

[0107] In the actual manufacturing process, after providing the semiconductor substrate, in some examples, the semiconductor substrate can be pre-cleaned to remove cutting damage on the surface of the semiconductor substrate, as well as organic matter and other contaminants generated during transportation, to improve the yield of the manufactured back-contact battery.

[0108] Step 2: If Figure 2 As shown, along the thickness direction of the semiconductor substrate 11 , a stacked first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11 .

[0109] Specifically, the embodiment of the present invention does not specifically limit the materials of the first interface passivation layer and the first doped silicon layer, and they can be set according to actual needs.

[0110] Exemplarily, the first interface passivation layer may be an intrinsic silicon layer, and the first interface passivation layer and the first doped silicon layer may form a heterogeneous contact structure, in which case the first interface passivation layer and the first doped silicon layer have a high passivation effect on the surface of the corresponding region in the semiconductor substrate, further reducing the carrier recombination rate on the surface of the region, and improving the conversion efficiency of the manufactured back contact battery. The material of the first interface passivation layer and / or the first doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon.

[0111] Exemplarily, the first interface passivation layer may be a tunneling passivation layer, and the material of the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. Secondly, in the case where the first interface passivation layer is a tunneling passivation layer, the first doped silicon layer includes a doped crystalline silicon layer. Specifically, the first doped silicon layer may include a doped polysilicon layer and / or a doped single crystal silicon layer. In this case, since amorphous silicon, nanocrystalline silicon and microcrystalline silicon are easy to form polycrystalline silicon or single crystal silicon at high temperature, and the chemical properties of the tunnel passivation layer and the doped crystalline silicon layer are relatively stable at high temperature, when the first interface passivation layer and the first doped silicon layer with high thermal stability are first formed on the first side of the semiconductor substrate, the influence of the laser radiation heat on the first interface passivation layer and the first doped silicon layer when the stacked second interface passivation layer and the second doped silicon layer are selectively etched by the subsequent laser processing process can be reduced or even avoided, thereby improving the yield of the back contact battery. At the same time, the first interface passivation layer and the first doped silicon layer are less sensitive to high-temperature laser thermal damage, which can reduce the influence on their own passivation effect during the laser processing process, further increasing the process window and reducing the process difficulty.

[0112] In the case where the first interface passivation layer is a tunnel passivation layer and the first doped silicon layer includes a doped crystalline silicon layer, in the actual manufacturing process, a process such as low-pressure chemical vapor deposition or thermal oxidation can be used to form the first interface passivation layer on the first surface of the semiconductor substrate. Next, in some examples, a process such as chemical vapor deposition can be used to form an intrinsic silicon layer on the first interface passivation layer, and then a process such as diffusion, ion implantation, or doping source coating can be used to dope the intrinsic silicon layer so that the intrinsic silicon layer forms a first doped polysilicon layer.

[0113] In some other examples, a doped amorphous silicon layer may be formed on the first interface passivation layer by using a process such as chemical vapor deposition; then, the doped amorphous silicon layer is annealed to form a doped polysilicon layer. In some other examples, a first doped silicon layer including at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon may be directly formed on the first interface passivation layer by using a process such as chemical vapor deposition.

[0114] It should be noted that if Figure 2 As shown, when the first interface passivation layer 12 and the first doped silicon layer 13 are formed, a stacked first interface passivation layer 12 and a first doped silicon layer 13 will be formed on the side of the semiconductor substrate 11 and at least a portion of the second surface due to the winding plating. In the process of forming the first doped silicon layer 13, if the semiconductor substrate 11 adopts a double insertion method, the first doped silicon layer 13 will be formed in the edge area of ​​the second surface of the semiconductor substrate 11; if the semiconductor substrate 11 adopts a single insertion method, Figure 2 As shown, a first doped silicon layer 13 is formed on the entire second surface of the semiconductor substrate 11 .

[0115] In addition, if Figure 2 As shown, when the intrinsic silicon layer is doped by a diffusion process, a first doped silicon glass layer 14 is formed on a side of the first doped silicon layer 13 away from the semiconductor substrate 11 while the first doped silicon layer 13 is formed.

[0116] Specifically, the embodiment of the present invention does not specifically limit the thickness of the first interface passivation layer and the first doped silicon layer, and they can be set according to actual needs.

[0117] Exemplarily, the thickness of the first doped silicon layer may be greater than or equal to 30 nm and less than or equal to 150 nm. For example, the thickness of the first doped silicon layer may be 30 nm, 40 nm, 50 nm, 80 nm, 100 nm, 120 nm or 150 nm.

[0118] Exemplarily, when the first interface passivation layer is a tunneling passivation layer, the thickness of the first interface passivation layer may be greater than or equal to 0.5 nm and less than or equal to 2.5 nm; or, when the first interface passivation layer is an intrinsic silicon layer, the thickness of the first interface passivation layer may be greater than or equal to 4 nm and less than or equal to 18 nm.

[0119] In the actual application process, the thickness of each part of the first interface passivation layer may be the same or different. In the case where the thickness of each part of the first interface passivation layer is different, in some examples, in the first surface, when the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-shaped texture structure, the thickness of the first interface passivation layer located at the bottom surface of the tower-shaped texture structure may be less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure. In this case, it can be understood that the bottom surface of the tower-shaped texture structure and the side surface of the tower-shaped texture structure have different crystal orientations. Specifically, the bottom surface of the tower-shaped texture structure is a

[110] crystal orientation, and the number of dangling bonds on the surface of the

[110] crystal orientation is relatively small; while the side surface of the tower-shaped texture structure is a

[111] crystal orientation, and the number of dangling bonds on the

[111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located on one side of the bottom surface of the tower-shaped texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure, it is beneficial for the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure to have a relatively high passivation effect, meet the demand for high passivation effect on the side of the tower-shaped texture structure, reduce the carrier recombination rate on the side of the tower-shaped texture structure, and further improve the working efficiency of the manufactured back contact battery.

[0120] The thickness of the first interface passivation layer at the bottom surface of the tower-shaped texture structure and the thickness of the first interface passivation layer on the side wall of the tower-shaped texture structure can be determined according to the requirements for the passivation effect of different areas of the tower-shaped texture structure and the actual manufacturing process, and are not specifically limited here.

[0121] Exemplarily, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure can be greater than or equal to 0.5nm and less than or equal to 1.5nm. For example, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure can be 0.5nm, 0.6nm, 0.8nm, 1nm, 1.2nm, 1.3nm or 1.5nm, etc. In this case, the thickness of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure is within the above range, which is conducive to preventing the first interface passivation layer from having a low passivation effect on the semiconductor substrate due to the small thickness of the bottom surface of the tower-shaped texture structure; in addition, it is also conducive to preventing the first interface passivation layer from having a high tunneling resistance due to the large thickness of the bottom surface of the tower-shaped texture structure, and is conducive to achieving a balance between the passivation effect and the tunneling resistance of the first interface passivation layer located on the bottom surface of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure, while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0122] Exemplarily, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure can be greater than or equal to 0.5nm and less than or equal to 2nm. For example, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure can be 0.5nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm, etc. In this case, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is within the above range, which is conducive to preventing the passivation effect of the first interface passivation layer from being low due to the small thickness of the part; in addition, it is also conducive to preventing the tunneling resistance of the first interface passivation layer from being high due to the large thickness of the side wall of the tower-shaped texture structure, which is conducive to achieving a balance between the passivation effect and the tunneling resistance of the part of the first interface passivation layer located on the side wall of the tower-shaped texture structure, thereby reducing the carrier recombination rate on the side of the tower-shaped texture structure, while ensuring that the first doped silicon layer has a high carrier collection efficiency and reduces transmission loss.

[0123] Step 3: If Figure 3 As shown, the first doped silicon glass layer is removed. Specifically, in actual application, the first doped silicon glass layer can be removed by wet etching (such as using a hydrofluoric acid solution) or other processes.

[0124] It should be noted that, in the case where the first interface passivation layer formed in the second step is an intrinsic silicon layer, and the first interface passivation layer and the first doped silicon layer constitute a heterogeneous contact structure, in some examples, the third step may also be omitted.

[0125] Step 4: If Figure 4 As shown, an insulating layer 16 is formed on the side of the first doped silicon layer 13 away from the semiconductor substrate 11. Specifically, the insulating layer 16 can be formed on the side of the first doped silicon layer away from the semiconductor substrate 11 by using a process such as chemical vapor deposition. The material of the insulating layer 16 may include any insulating material with a mask protection function, such as aluminum oxide and / or silicon nitride, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention. As for the thickness of the insulating layer 16, it can be set according to actual needs.

[0126] It is worth noting that the insulating layer can be directly formed on the side of the first doped silicon layer away from the semiconductor substrate. Since the insulating material (such as aluminum oxide or silicon nitride, etc.) used to make the insulating layer may have a passivation effect, it can not only play a mask protection and insulation role, but also directly passivate the side of the first doped silicon layer away from the semiconductor substrate, which is beneficial to reduce the surface defects of the first doped silicon layer away from the semiconductor substrate, and further improve the conversion efficiency of the back contact battery. The insulating layer can also select some materials with hydrogen replenishment function, such as at least one of aluminum oxide and silicon nitride, for hydrogen injection into the first doped silicon layer, especially when the material of the first doped silicon layer is doped polysilicon, to improve the passivation effect of the first doped silicon layer.

[0127] In addition, it should be noted that if Figure 4 and Figure 5 As shown, while the insulating layer 16 is formed on one side of the first surface of the semiconductor substrate 11, an insulating layer 16 is also formed on the side of the semiconductor substrate 11 and at least a portion of the second surface. In this case, in some examples, after the insulating layer 16 is formed and before the subsequent texturing process, at least the insulating layer 16 formed on one side of the second surface of the semiconductor substrate 11 can be removed. Among them, the insulating layer 16 formed on the side of the semiconductor substrate 11 can be retained in its entirety, can be retained in part, and of course can be removed in its entirety.

[0128] Step 5: If Figure 6 As shown, the insulating layer is patterned to form an insulating mask pattern 15. Specifically, the insulating layer can be patterned by photolithography combined with etching, laser irradiation or chemical slurry etching. After the patterning, the remaining portion of the insulating layer forms the insulating mask pattern 15.

[0129] Step 6: If Figure 7As shown, the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed.

[0130] In the actual manufacturing process, other processes such as laser or wet etching can be used to remove the first interface passivation layer and the first doped silicon layer that are not covered by the insulating mask pattern. After the removal operation, in the semiconductor substrate, at least the first surface is exposed outside the insulating mask pattern, and the second surface is exposed to the outside (it can be understood that when the insulating layer formed on one side of the second surface of the semiconductor substrate is removed, the insulating layer formed on at least part of the side surface of the semiconductor substrate is also removed, and the area on the side surface that does not correspond to the insulating layer is also exposed to the outside). The etchant and etching conditions used in the wet etching process can be determined according to the actual application scenario, and are not specifically limited here.

[0131] It should be noted that after forming the insulating mask pattern, the first interface passivation layer and the first doped silicon layer that are not covered by the insulating mask pattern can be removed by a corresponding etching process. Alternatively, the first interface passivation layer and the first doped silicon layer that are not covered by the insulating mask pattern can be removed while the insulating layer is patterned to form the insulating mask pattern. This can simplify the process and improve the production efficiency of the back contact solar cell. For example, a laser can be used to simultaneously remove part of the insulating layer and part of the first interface passivation layer and the first doped silicon layer to finally form the insulating mask pattern and the first interface passivation layer and the first doped silicon layer covered by the insulating mask pattern.

[0132] In addition, the above-mentioned first surface may include a first region and a second region. Furthermore, the region covered with the first interface passivation layer and the first doped silicon layer in the first surface is defined as the first region, and the region not covered with the first interface passivation layer and the first doped silicon layer is defined as the second region. Based on this, after removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern, the surface of the first region in the first surface can be flush with the surface of the second region. At this time, along the thickness direction of the semiconductor substrate, the portion of the semiconductor substrate corresponding to the second region also has a larger light absorption depth, which is beneficial to improving the conversion efficiency of the semiconductor substrate. Or, as Figure 7As shown, the second region 24 may also include a groove, which indicates that when removing the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15, the first interface passivation layer 12 and the first doped silicon layer 13 located on the second region 24 have been completely removed to prevent short circuit. At the same time, the presence of the groove makes the surface of the second region 24 and the surface of the first region 23 staggered along the thickness direction of the semiconductor substrate 11, which is conducive to at least partially staggering the second interface passivation layer and the second doped silicon layer located on the second region 24 with the first interface passivation layer 12 and the first doped silicon layer 13 located on the first region 23, thereby reducing the risk of leakage. Specifically, the embodiment of the present invention does not specifically limit the depth of the groove, which can be determined according to the actual manufacturing process.

[0133] Step 7: Figure 8 and Fig. 9 As shown, the surface of the area of ​​the first surface exposed outside the insulating mask pattern 15 and the second surface are subjected to texturing treatment.

[0134] Specifically, the above-mentioned texturing treatment can be performed by wet etching or other processes, and the processing solution and processing conditions of the texturing treatment can be determined according to the actual application scenario, and are not specifically limited here. Figure 8 As shown, after the texturing treatment, at least the surface of the first surface exposed outside the insulating mask pattern 15 and the second surface form a textured surface. Figure 8 As shown, if the insulating mask pattern 15 covers various areas on the side of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11, the surface of the area of ​​the first surface exposed outside the insulating mask pattern 15 and the second surface after the above-mentioned texturing process form a textured surface. Fig. 9 As shown, if the insulating mask pattern 15 does not cover the side of the semiconductor substrate 11, or only covers a partial area of ​​the side of the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11, then after the above-mentioned texturing treatment, not only the surface of the first surface exposed outside the insulating mask pattern 15 and the second surface will form a velvet surface, but the surface of the area on the side of the semiconductor substrate 11 not covered by the insulating mask pattern 15 will also form a velvet surface.

[0135] In the actual manufacturing process, in some examples, the exposed surface of the semiconductor substrate can be polished and cleaned by an alkaline solution. The alkaline solution can be sodium hydroxide or potassium hydroxide, etc. The concentration of the alkaline solution can be 0.1% to 3%. Next, it is cleaned in a mixed solution including KOH, H2O2 and H2O. Among them, the ratio of KOH, H2O2 and H2O in the mixed solution is (1:2:5), the cleaning temperature is 65°C, and the cleaning time is 360s. Then, the area of ​​the first surface of the semiconductor substrate exposed outside the insulating mask pattern and the second surface are subjected to a texturing treatment, and the texturing treatment uses, for example, a solution system of TS53V01:KOH:DIW. Among them, the mass percentage concentration of TS53V01 is 0.2% to 1.5%, the mass percentage concentration of KOH is 1% to 3%, and the temperature of the texturing treatment is 75°C to 85°C. Optionally, the mass percentage concentration of TS53V01 is 0.5% to 1%, and the mass percentage concentration of KOH is 1.5% to 2%. Then, the substrate was cleaned again in a mixed solution of KOH, H2O2 and H2O at a temperature of 65°C and a cleaning time of 300 seconds.

[0136] It should be noted that in the above-mentioned first surface, the depth of the groove included in the second area will also be affected by the above-mentioned texturing treatment. Optionally, when the surface of the first area is a polished surface, and the bottom surface of the groove is a velvet surface, the distance from the surface of the semiconductor substrate in the first area to the bottom surface of the groove can be greater than or equal to 2μm and less than or equal to 8μm. Specifically, the distance refers to the distance between the surface of the semiconductor substrate in the first area and the bottom of the pyramid of the velvet structure in the bottom surface of the groove. For example: the distance from the surface of the semiconductor substrate in the first area to the bottom surface of the groove can be 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 5μm, 6μm, 7μm or 8μm, etc. In this case, it is helpful to prevent the first doped silicon layer and the second doped silicon layer from being staggered along the thickness direction of the semiconductor substrate due to the small distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove of the groove, thereby ensuring a low risk of leakage between the two. Secondly, in the process of making the groove of the groove bottom surface, the semiconductor substrate needs to be corroded, so the distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove of the groove will also affect the size of the velvet structure on the bottom surface of the groove. Based on this, the distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove of the groove within the above range can also prevent the size of the bottom surface of the groove of the groove and the velvet structure formed on the second surface from being small due to the small distance, thereby ensuring that the second surface has a higher light trapping effect, and at the same time, it is helpful to increase the specific surface area of ​​the second doped silicon layer away from the semiconductor substrate, further reducing the contact loss between the second doped silicon layer and the corresponding conductive material. In addition, it can also prevent the etching depth of the semiconductor substrate at the groove from being large due to the large distance from the surface of the semiconductor substrate in the first region to the bottom surface of the groove of the groove, thereby ensuring that each part of the semiconductor substrate has a large light absorption depth, thereby making the back contact battery have a higher conversion efficiency.

[0137] Step 8: Fig.10 and Fig.11 As shown, the insulating mask pattern is removed. Specifically, the insulating mask pattern can be removed by wet etching or other processes. The etchant used to remove the insulating mask pattern can be determined according to the material of the insulating mask pattern and actual needs, and is not specifically limited here.

[0138] For example, when the material of the insulating mask pattern is silicon nitride, hydrofluoric acid with a concentration of 5% wt to 10% wt may be used to remove the insulating mask pattern. The removal time may be, for example, 600 seconds.

[0139] It should be noted that, in some examples, the seventh step may be performed first and then the eighth step; in another example, the seventh step and the eighth step may be performed simultaneously, that is, the insulating mask pattern may be removed while the texturing process is being performed.

[0140] Step 9: Fig.12As shown, while the first passivation layer 17 is formed on the second surface of the semiconductor substrate 11 , the first passivation layer 17 is formed on the first surface of the semiconductor substrate 11 .

[0141] In the actual manufacturing process, chemical vapor deposition (such as low pressure chemical vapor deposition LPCVD or plasma enhanced chemical vapor deposition PECVD, etc.) or atomic layer deposition (ALD) process can be used to form the first passivation layer. The material of the first passivation layer can be set according to actual needs and is not specifically limited here. For example, the first passivation layer may include aluminum oxide (Al x In addition, Fig.12 As shown, while the first passivation layer 17 is formed on the second surface and the first surface of the semiconductor substrate 11 , the first passivation layer 17 may also be formed on the side surface of the semiconductor substrate 11 .

[0142] Step 10: If Fig.13 As shown, an anti-reflection layer is formed on the second surface of the semiconductor substrate 11 to reduce the reflectivity of the back contact battery on one side of the second surface, thereby further improving the conversion efficiency of the back contact battery. The material of the anti-reflection layer 18 can be determined according to the actual application scenario and is not specifically limited here. Exemplarily, the anti-reflection layer 18 may include a silicon nitride layer. Secondly, when the anti-reflection layer 18 is formed on the second surface of the semiconductor substrate 11, the anti-reflection layer 18 may also be formed on the side of the semiconductor substrate 11 and on at least a portion of the first surface of the semiconductor substrate 11 due to coating.

[0143] Step 11: Annealing the first passivation layer to activate the passivation effect of the first passivation layer. During the annealing process, the presence of the first passivation layer is beneficial to preventing the hydrogen in the first doped silicon layer from escaping, and the hydrogen in the first passivation layer can also be injected into the first doped silicon layer, reducing the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, ensuring that the side of the first doped silicon layer away from the semiconductor substrate has a higher passivation effect.

[0144] Step 12: After annealing and before forming the stacked second interface passivation layer and the second doped silicon layer, as Fig.13 and Fig.14 As shown, the anti-reflection layer 18 plated around one side of the first surface and the first passivation layer 17 formed on one side of the first surface need to be removed in sequence. At this time, the first passivation layer 17 and the anti-reflection layer 18 plated around the side of the semiconductor substrate 11 can be retained in full or in part. The above-mentioned removal operation can be performed in a chain cleaning device, and then after the above-mentioned removal operation and before performing subsequent operations, the semiconductor substrate 11 can be cleaned with metal ions (i.e., RCA cleaning) to remove contamination and slight scratches caused by the semiconductor substrate 11 in the chain cleaning device. In some embodiments, the cleaning operation may not be performed.

[0145] In some embodiments, step 12 may not be performed.

[0146] Step 13: If Fig.15 As shown, along the thickness direction of the semiconductor substrate 11, a second interface passivation layer 19 and a second doped silicon layer 20 are sequentially stacked on the first surface. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0147] In the actual manufacturing process, a plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition process can be used to form a second interface passivation layer and a second doped silicon layer stacked in sequence on the first surface. The materials of the second interface passivation layer and the second doped silicon layer can be set according to actual needs.

[0148] Exemplarily, the second interface passivation layer may be a tunneling passivation layer, and the material of the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide. Secondly, in the case where the second interface passivation layer is a tunneling passivation layer, the second doped silicon layer includes a doped crystalline silicon layer. Specifically, the second doped silicon layer may include a doped polysilicon layer and / or a doped single crystal silicon layer.

[0149] Exemplarily, the second interface passivation layer may be an intrinsic silicon layer, and the second interface passivation layer and the second doped silicon layer may form a heterogeneous contact structure, in which case the second interface passivation layer and the second doped silicon layer have a high passivation effect on the surface of the corresponding region in the semiconductor substrate, further reducing the carrier recombination rate on the surface of the region, and improving the conversion efficiency of the manufactured back contact battery. The material of the second interface passivation layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon.

[0150] It should be noted that if Fig.15 and Fig.16 As shown, when the second interface passivation layer 19 and the second doped silicon layer 20 are formed, a stacked second interface passivation layer 19 and the second doped silicon layer 20 will also be formed on the side of the semiconductor substrate 11 and at least a portion of the second surface due to the coating. In some examples, such as Fig.19 As shown, a process such as wet etching can be used to remove at least the portion of the second interface passivation layer 19 and the second doped silicon layer 20 that is plated around the second surface of the semiconductor substrate 11. The portion of the second interface passivation layer 19 and the second doped silicon layer 20 that is plated around the side of the semiconductor substrate 11 can be retained in its entirety or in part, and can also be removed in its entirety.

[0151] As for the conductivity type of the second doped silicon layer, it can be set according to actual needs, as long as the conductivity types of the first doped silicon layer and the second doped silicon layer are opposite.

[0152] Optionally, when the first interface passivation layer is a tunneling passivation layer, the first doped silicon layer is doped polysilicon, the second interface passivation layer is an intrinsic silicon layer, and the second interface passivation layer and the second doped silicon layer constitute a heterogeneous contact structure, the conductivity type of the first doped silicon layer may be N-type, and the conductivity type of the second doped silicon layer may be P-type. In this case, compared with P-type doped amorphous silicon, P-type doped microcrystalline silicon or P-type nanocrystalline silicon materials, the contact resistance between the P-type doped polycrystalline silicon material and the electrode is higher and the field passivation effect is poorer. Therefore, when the conductivity type of the first doped silicon layer is set to N-type and the conductivity type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, and at the same time, the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the manufactured back contact battery.

[0153] The thickness of the second interface passivation layer and the second doped silicon layer can be set according to actual needs and is not specifically limited here.

[0154] Exemplarily, the thickness of the second interface passivation layer may be greater than or equal to 3nm and less than or equal to 16nm. For example, the thickness of the second interface passivation layer may be 3nm, 5nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm or 16nm. In this case, it can be understood that after the texturing process or at the same time as the texturing process, the insulating mask pattern is removed, and the second surface passivation layer and the second doped silicon layer formed on the first surface are directly formed on the semiconductor substrate and the first doped silicon layer. At this time, the overlapping parts of the second doped silicon layer and the first doped silicon layer are separated only by the second interface passivation layer. Based on this, when the thickness of the second interface passivation layer is within the above range, the thickness of the second interface passivation layer is large, which is conducive to enhancing the isolation effect of the second interface passivation layer on the first doped silicon layer and the second doped silicon layer overlapping along the thickness direction of the semiconductor substrate, reducing the risk of forward leakage, and improving the conversion efficiency of the manufactured back contact battery. In addition, it can also prevent the contact resistance from being large due to the excessive thickness of the second interface passivation layer, and reduce the transmission loss.

[0155] In addition, the thickness of each part of the second interface passivation layer can be the same. In this case, each part of the second interface passivation layer has a high passivation effect.

[0156] Or, if Fig.17As shown, the first surface may include a first area 23 and a second area 24. The second area 24 includes a groove. The first interface passivation layer 12 and the first doped silicon layer 13 are located in the first area 23. The second interface passivation layer 19 and the second doped silicon layer 20 are located in the second area 24, and extend to the first area 23 to cover part of the first interface passivation layer 12 and the first doped silicon layer 13. The surface of the first area 23 is a polished surface, and the bottom surface of the groove is a velvet surface. In addition, the thickness of the second interface passivation layer 19 located on the velvet surface may be less than the thickness of the second interface passivation layer 19 located on the polished surface. In this case, the presence of the groove causes the surface of the second area 24 to be offset from the surface of the first area 23 along the thickness direction of the semiconductor substrate 11, thereby facilitating the second interface passivation layer 19 and the second doped silicon layer 20 located on the second area 24 to be at least partially offset from the first interface passivation layer 12 and the first doped silicon layer 13 located on the first area 23, thereby reducing the risk of leakage. In addition, when the thickness of the second interface passivation layer 19 on the velvet surface is relatively small, this part has a lower transmission resistance, which is beneficial to reducing transmission loss. The thickness of the second interface passivation layer 19 on the polished surface is relatively large, which is beneficial to improving the passivation and insulation effect of the part on the polished surface, reducing forward leakage, and improving the conversion efficiency of the manufactured back contact battery. In this case, the thickness difference between different parts of the second interface passivation layer 19 can be set according to the surface roughness of the first area 23 and the second area 24, as well as actual needs, and is not specifically limited here.

[0157] As for the second doped silicon layer, optionally, the thickness of the second doped silicon layer may be greater than or equal to 3 nm and less than or equal to 50 nm. For example, the thickness of the second doped silicon layer may be 3 nm, 5 nm, 8 nm, 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.

[0158] The thickness of each part of the second doped silicon layer may be the same. In this case, each part of the second doped silicon layer has a high field passivation effect.

[0159] Or, if Fig.16As shown, in the case where the first surface includes the above-mentioned first area 23 and the above-mentioned second area 24, the thickness of the second doped silicon layer 20 on the velvet surface can also be less than the thickness of the second doped silicon layer 20 on the polished surface. In this case, compared with the polished surface, the specific surface area of ​​the velvet surface is larger, and within the same formation range, the contact area between the portion of the second doped silicon layer 20 on the velvet surface and the semiconductor substrate 11 is larger, while the contact area between the portion of the second doped silicon layer 20 on the polished surface and the semiconductor substrate 11 is smaller. Based on this, when the thickness of the second doped silicon layer 20 on the velvet surface is smaller, after ensuring that the portion of the second doped silicon layer 20 on the velvet surface has sufficient contact area with the semiconductor substrate 11, a space that can be reduced can be reserved for setting the thickness of the portion, and while ensuring a high carrier collection efficiency, the amount of consumables used in manufacturing the portion of the second doped silicon layer 20 on the velvet surface can also be reduced. In addition, the second doped silicon layer 20 on the polished surface has a larger thickness, so that the portion has a higher field passivation effect and reduces carrier recombination. In this case, the thickness difference between different parts of the second doped silicon layer 20 can be set according to the surface roughness of the first area 23 and the second area 24 and actual needs, and is not specifically limited here.

[0160] In addition, in some examples, in actual application processes, when the first surface includes the above-mentioned first region and the above-mentioned second region, the second region includes a groove, and the second doped silicon layer is a doped amorphous silicon layer, after a second interface passivation layer and a second doped silicon layer are stacked in sequence on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact battery may further include a fourteenth step: laser irradiating the second doped silicon layer located on the bottom surface of the groove to crystallize the second doped silicon layer.

[0161] In the case of adopting the above technical solution, the second doped silicon layer located on the bottom surface of the groove is irradiated with laser. Under the irradiation of high-temperature laser, the degree of crystallization of at least part of the second doped silicon layer located on the bottom surface of the groove is increased. In addition, it can be understood that when the degree of crystallization of the semiconductor layer is smaller, the grains in the semiconductor layer are smaller, and even the disorder of amorphous silicon material is presented. The smaller the grains in the semiconductor layer, the fewer interfaces between the grains in the semiconductor layer, so the resistance of the grain interface will be larger. Based on this, when the degree of crystallization of at least part of the second doped silicon layer located on the bottom surface of the groove is increased, it is beneficial to improve the conductive properties of at least part of the second doped silicon layer located on the bottom surface of the groove, reduce the transmission loss between the second doped silicon layer and the corresponding conductive material (such as a transparent conductive layer or a conductive electrode, etc.), and improve the conversion efficiency of the manufactured back contact battery.

[0162] It should be noted that the greater the degree of crystallization referred to in the embodiments of the present invention may refer to a greater crystallization rate, a larger grain size and / or a greater number of grains. For example, when the second doped silicon layer is a doped amorphous silicon layer (the amorphous silicon layer may contain a small amount of nanocrystalline silicon, but the content of the nanocrystalline silicon is very small, for example, less than 5%, which is known in the art), the second doped silicon layer located at least partially inside the bottom surface of the groove of the groove will generate lattice-ordered grains, so that its degree of crystallization is increased. The degree of crystallization of the portion of the second doped silicon layer corresponding to the first region is smaller, and at this time, the portion with a smaller degree of crystallization is still an amorphous silicon material, and there are no grains generated after laser treatment. In this case, the conductivity of at least the portion of the second doped silicon layer located at the bottom surface of the groove will be greater, which is conducive to reducing the transmission loss of at least the portion of the second doped silicon layer located at the bottom surface of the groove, and reducing the contact resistance between at least the portion of the second doped silicon layer located at the bottom surface of the groove and the transparent conductive layer. The crystallization degree of the portion of the second doped silicon layer corresponding to the first region is relatively low. At this time, the conductivity of the portion of the second doped silicon layer corresponding to the first region is relatively low, which is beneficial to reduce the magnitude of the forward leakage current between the portion of the second doped silicon layer corresponding to the first region and the first doped silicon layer, and further improve the conversion efficiency of the back contact battery. Specifically, after the second doped silicon layer is crystallized, the crystal type of the second doped silicon layer may remain unchanged, and the degree of crystallization increases; for example: before and after the above crystallization treatment, the crystal type of the second doped silicon layer may be microcrystalline silicon, and the degree of crystallization increases from 20% before the crystallization treatment to 80% after the crystallization treatment. Alternatively, after the second doped silicon layer is crystallized, the crystal type of the second doped silicon layer may also change; for example: before the above crystallization treatment, the crystal type of the second doped silicon layer may be amorphous silicon, and after the crystallization treatment, the crystal type of the second doped silicon layer is converted to nanocrystalline silicon or microcrystalline silicon.

[0163] In addition, in the actual manufacturing process, the above-mentioned fourteenth step operation may not be performed.

[0164] Step 15: If Fig.17 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 is removed to expose a portion of the first interface passivation layer 1212 and the first doped silicon layer 13 .

[0165] In the actual manufacturing process, laser etching, etching with a corrosive slurry, or etching methods such as a combination of photolithography and wet etching processes can be used to selectively etch the stacked second interface passivation layer and the second doped silicon layer. It can be understood that after selective etching, the remaining portion of the second interface passivation layer and the second doped silicon layer will affect the carrier collection efficiency of the second doped silicon layer. In addition, the first doped silicon layer needs to be electrically connected to the corresponding conductive material through an opening area provided in the second interface passivation layer and the second doped silicon layer, so as to lead out the carriers collected by itself. The carriers transmitted by the conductive material electrically connected to the first doped silicon layer are opposite to the conductivity type of the second doped silicon layer. Therefore, the width of the opening area of ​​the second interface passivation layer and the second doped silicon layer will also affect the formation of the conductive material electrically connected to the first doped silicon layer. Therefore, the size of the opening area can be determined according to the requirements of the carrier collection efficiency of the second doped silicon layer in the actual application scenario, and the manufacturing accuracy and range of the conductive material electrically connected to the first doped silicon layer, and no specific limitation is made here.

[0166] Exemplarily, the width of the opening area of ​​the second interface passivation layer and the second doped silicon layer may be greater than or equal to 250 μm and less than or equal to 400 μm. For example, the width of the opening area may be 250 μm, 260 μm, 280 μm, 300 μm, 320 μm, 340 μm, 360 μm, 380 μm or 400 μm, etc. In this case, compared with the width of the opening area of ​​the second interface passivation layer and the second doped silicon layer in the existing back contact battery being less than 250 μm, the width of the opening area for exposing the first doped silicon layer to the outside is larger in the back contact battery formed by the manufacturing method provided by the present invention, which is beneficial to prevent short circuits, so that the corresponding conductive material electrically connected to the first doped silicon layer has a larger formable range, thereby facilitating the increase of the contact area between the first doped silicon layer and the corresponding conductive material, reducing transmission losses, and improving the electrical reliability of the manufactured back contact battery. Secondly, when the width of the above-mentioned opening area is less than or equal to 400μm, more parts of the second interface passivation layer and the second doped silicon layer are retained after the opening operation, which reduces the etching amount while ensuring that the second interface passivation layer and the second doped silicon layer have a certain area occupancy on one side of the first surface, ensuring that the second doped silicon layer has a higher current collection efficiency.

[0167] In addition, in some examples, in the actual manufacturing process, when the laser is used to remove the part of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the edge portion of the opening area of ​​the second doped silicon layer can be processed by laser so that a hole structure is formed in the edge portion of the second doped silicon layer. Specifically, the laser etching parameters can be adjusted so that the edge portion of the second doped silicon layer close to the opening area is heated under the action of the high-temperature laser, so that after selective etching, a hole structure is formed in the edge portion of the second doped silicon layer. In this case, it can be understood that the hole structure is a hollow structure, so when the hole structure is formed in the edge portion of the second doped silicon layer, the edge structure of the second doped silicon layer is loose, which can reduce the risk of leakage between the edge portion of the second doped silicon layer and the first doped silicon layer, and improve the electrical reliability of the back contact battery. In addition, the presence of the hole structure can also increase the undulation of the edge portion of the stacked second interface passivation layer and the second doped silicon layer, thereby enhancing the light trapping effect of this portion, which is conducive to improving the bifaciality of the back contact battery. Specifically, the distribution and size of the holes in the hole structure can be determined according to the actual manufacturing process and are not specifically limited here.

[0168] Exemplarily, the width of the portion having the hole structure in the second doped silicon layer may be greater than or equal to 0.1 μm and less than or equal to 20 μm. For example, the width of the portion having the hole structure in the second doped silicon layer may be 0.1 μm, 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 10 μm, 15 μm or 20 μm, etc. In this case, when the width of the portion having the hole structure in the second doped silicon layer is within the above range, the flow of carriers between the first doped silicon layer and the second doped silicon layer can be effectively reduced, thereby reducing leakage.

[0169] Exemplarily, in a top view of the back contact battery, the hole structure may be in at least one of a circular, elliptical, and irregular shape. Furthermore, when the hole structure is in at least one of a circular, elliptical, and irregular shape, the hole structure may enhance insulation and reduce leakage.

[0170] Step 16: Fig.18As shown, a transparent conductive layer 21 is formed covering the first doped silicon layer 13 and the second doped silicon layer 20 on the side away from the semiconductor substrate 11. An isolation groove 22 is formed through the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20. Specifically, the embodiment of the present invention does not specifically limit the material and thickness of the transparent conductive layer 21, and the width of the isolation groove 22, as long as they can be applied to the manufacturing method provided in the embodiment of the present invention. Secondly, the second doped silicon layer and the second interface passivation layer corresponding to the isolation groove can be removed or not. Among them, in the case of removing the second doped silicon layer and the second interface passivation layer corresponding to the isolation groove, the portion of the second doped silicon layer close to the opening area can also be provided with the above-mentioned hole structure. The beneficial effects can be referred to the foregoing, and will not be repeated here.

[0171] Among them, the above-mentioned transparent conductive layer can be formed by a process such as physical vapor deposition, and then an isolation groove can be opened in the transparent conductive layer by a process such as laser etching or etching slurry. Specifically, when etching is performed by etching slurry, the etching slurry can be printed first, and then the etching slurry is cured and etched. Next, the etching slurry needs to be cleaned. In addition, the location of the above-mentioned isolation groove can be determined according to actual needs and manufacturing accuracy. Optionally, the isolation groove can be set in the area where the first doped silicon layer and the second doped silicon layer overlap along the thickness direction of the semiconductor substrate.

[0172] In addition, if Fig.18 As shown, the thickness of each part of the transparent conductive layer 21 can be substantially the same. Alternatively, the thickness of the edge portion of the transparent conductive layer adjacent to the isolation groove 22 can also gradually decrease in the direction close to the isolation groove 22. In this case, the thickness of the transparent conductive layer near both sides of the isolation groove 22 is relatively small, and the thickness of the two parts of the transparent conductive layer used to transmit opposite carriers is relatively small (the facing area is also relatively small), which is conducive to reducing the risk of leakage and improving the electrical reliability of the back contact battery. Among them, the width of the area where the thickness gradually decreases in the transparent conductive layer and the amplitude of the gradual decrease in thickness can be determined according to the etching parameters when the isolation groove 22 is opened in the transparent conductive layer during the actual manufacturing process, and are not specifically limited here. In addition, such a setting is also conducive to the stress release between other structures in the back contact battery and the transparent conductive layer, avoiding the edge of the transparent conductive layer in the formation process due to excessive stress, which is easy to cause the edge to collapse or fall off, and improves the structural reliability of the manufactured back contact battery.

[0173] Furthermore, when the back contact cell further includes a transparent conductive layer, and the first doped silicon layer includes a doped crystalline silicon layer, the thickness of the first doped silicon layer can be adjusted to reduce the amount of consumables used in the first doped silicon layer.

[0174] Optionally, when the back contact battery further includes a transparent conductive layer, and the first doped silicon layer includes a doped crystalline silicon layer, the thickness of the first doped silicon layer may be greater than or equal to 30 nm and less than or equal to 140 nm. For example, the thickness of the first doped silicon layer may be 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, 130 nm or 140 nm, etc. In this way, when the back contact battery includes a transparent conductive layer, and the first doped silicon layer includes a doped crystalline silicon layer, because the transparent conductive layer can be responsible for collecting and conducting carriers, the thickness requirement of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer without reducing the carrier collection efficiency. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is conducive to reducing its own parasitic absorption and further improving the working efficiency of the manufactured back contact battery. In addition, since the thickness of the first doped silicon layer is small, the formation time of the first doped silicon layer can be reduced, thereby improving the manufacturing efficiency.

[0175] Of course, when the manufactured back-contact battery does not include the above-mentioned transparent conductive layer, or when the back-contact battery includes a transparent conductive layer, the thickness of the first doped silicon layer can also be set to other appropriate values ​​according to different application scenarios.

[0176] In addition, in some examples, such as Fig.18 As shown, the second interface passivation layer 19 and the second doped silicon layer 20 stacked in sequence, and the transparent conductive layer 21 arranged on the second doped silicon layer 20 all cover the partial area of ​​the stacked first interface passivation layer 12 and the first doped silicon layer 13 away from the semiconductor substrate 11. And / or, the portion where the first interface passivation layer 12, the first doped silicon layer 13, the second interface passivation layer 19 and the second doped silicon layer 20 are stacked and arranged along the thickness direction of the semiconductor substrate 11 is an overlapping area. In the overlapping area, the second interface passivation layer 19 is in direct contact with the first doped silicon layer 13. Among them, in the overlapping area, the second doped silicon layer 20 can be electrically isolated from the first doped silicon layer 13 by the second interface passivation layer 19. Alternatively, at least part of the overlapping area can also be a reverse leakage area, and in the reverse leakage area, the second doped silicon layer 20 is electrically connected to the first doped silicon layer 13 through the second interface passivation layer 19. In this case, in the reverse leakage region, the second doped silicon layer 20 can be electrically connected to the first doped silicon layer 13 with a conductivity type opposite to its own through the second interface passivation layer 19 to form a built-in diode structure with a lower reverse breakdown voltage, thereby reducing the risk of hot spots in the back-contact battery.

[0177] Specifically, along the length extension direction of the overlapping area, the reverse leakage area can be distributed continuously or discontinuously. It can be understood that the width of the reverse leakage area along the width direction of the overlapping area and the length of the continuous distribution of the reverse leakage area along the length direction of the overlapping area will affect the size of the leakage current. Specifically, the larger the width of the reverse leakage area, and / or the longer the length of the continuous distribution of the reverse leakage area, the larger the leakage current, the lower the hot spot risk, but the forward leakage current will also be larger. Based on this, the width of the reverse leakage area and the length of the continuous distribution of the reverse leakage area can be determined according to the hot spot risk and conversion efficiency requirements of the back contact battery in the actual application scenario, and no specific limitation is made here.

[0178] Step 17: Fig.19 As shown, a first electrode is formed on a portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 , and a second electrode is formed on a portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20 .

[0179] Exemplarily, the first electrode and the second electrode may be formed by screen printing, electroplating, etc. Specifically, the material of the first electrode and the second electrode may include any conductive material such as silver, aluminum, copper, nickel or titanium, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0180] It should be noted that, in addition to forming the insulating mask pattern in the manner described above, the insulating mask pattern in Embodiment 1 of the present invention may also be formed in at least the following two ways:

[0181] The first method is to form a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate while forming the first doped silicon layer. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may include: Fig. 20 and Fig.21 As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third and fourth steps can be omitted in the first method. The fifth step described above is replaced by patterning the first doped silicon glass layer.

[0182] Specifically, Fig. 20 and Fig.21As shown, the first doped silicon glass layer 14 can be patterned by laser irradiation. The density of the area where the first doped silicon glass layer 14 is irradiated by the laser becomes poor and is easily etched and removed. The density of the area where the first doped silicon glass layer 14 is not irradiated by the laser is higher, and it has a mask protection effect. Of course, other methods can also be used to pattern the first doped silicon glass layer 14. In this case, the above-mentioned first doped silicon glass layer 14 can be formed at the same time as the first doped silicon layer 13 is formed, and there is no need to use an additional deposition process to form a corresponding insulating layer in order to form the insulating mask pattern 15, which is conducive to simplifying the manufacturing process of the back contact battery and improving the manufacturing efficiency of the back contact battery.

[0183] Second, while forming the first doped silicon layer, a first doped silicon glass layer is formed on a portion of the first doped silicon layer away from the semiconductor substrate. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may also include: Figure 22 to Figure 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third step can be omitted in the second method. In addition, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0184] Specifically, Figure 22 to Figure 24 As shown, a process such as chemical vapor deposition can be used to form an insulating layer on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11. The material of the insulating layer may include insulating materials with mask protection such as aluminum oxide and / or silicon nitride. As for the thickness of the insulating layer, it can be set according to actual needs. Next, the patterning of the first doped silicon glass layer 14 and the insulating layer can be achieved by processes such as photolithography combined with etching, laser irradiation or chemical slurry corrosion. In this case, compared with the insulating mask pattern 15 of a single-layer structure, the insulating mask pattern 15 in this case not only includes the patterned first doped silicon glass layer 14, but also includes the patterned insulating layer, which is beneficial to improve the protection of the insulating mask pattern 15.

[0185] In addition, in some embodiments, in the actual manufacturing process, the eighth step may not be performed. Fig.25As shown, after removing the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15, and before forming the stacked second interface passivation layer 19 and the second doped silicon layer 20, the insulating mask pattern 15 is not removed. At this time, the existence of the insulating mask pattern 15 can separate the first doped silicon layer 13 and the second doped silicon layer 20 along the thickness direction of the semiconductor substrate 11, which can suppress forward leakage while reducing the thickness requirement of the second interface passivation layer 19, reducing the transmission resistance of the second interface passivation layer 19, reducing transmission losses, and helping to improve the carrier collection efficiency of the second doped silicon layer 20 and improve the conversion efficiency of the back contact battery.

[0186] Wherein, when the eighth step is not performed, in the ninth step, the first passivation layer may be formed only on the second surface of the semiconductor substrate, or the first passivation layer may be formed on both the first surface and the second surface of the semiconductor substrate.

[0187] In addition, in some examples, when the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer, which is disposed on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer may passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. Secondly, the presence of the amorphous silicon layer may also prevent the etchant for etching the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than the work function difference between the doped polycrystalline silicon layer and the transparent conductive layer, that is, the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact barrier between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared with the first doped silicon layer directly contacting the transparent conductive layer, arranging the amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable energy band matching, reduce contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0188] Specifically, the amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are laser removed, and the high temperature laser modifies the surface of the first doped silicon layer. In addition, the amorphous silicon layer can be located on a portion of the bottom of the opening area of ​​the second interface passivation layer and the second doped silicon layer, or can cover all areas of the bottom of the opening area.

[0189] In addition, the amorphous silicon layer can be continuously distributed in the opening area of ​​the second interface passivation layer and the second doped silicon layer and arranged on the side of the first doped silicon layer away from the semiconductor substrate; it can also be distributed intermittently, for example, in dispersed point distribution.

[0190] Example 2

[0191] This embodiment 2 only describes in detail the steps that are different from the embodiment 1. The same steps can refer to the explanation of the above embodiment 1, and will not be repeated in the embodiment 2. The difference between the embodiment 2 and the embodiment 1 is that the first passivation layer formed in the embodiment 2 in the eighth step includes an intrinsic silicon passivation layer, and the anti-reflection layer is formed after the stacked second interface passivation layer and the second doped silicon layer are formed. The embodiment 2 is described in detail below:

[0192] The first step is to provide a semiconductor substrate having a first surface and a second surface opposite to each other.

[0193] Step 2: If Figure 2 As shown, along the thickness direction of the semiconductor substrate 11 , a stacked first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11 .

[0194] Step 3: If Figure 3 As shown, the first doped silicon glass layer is removed.

[0195] Step 4: If Figure 4 and Figure 5 As shown, an insulating layer 16 is formed on a side of the first doped silicon layer 13 facing away from the semiconductor substrate 11 .

[0196] Step 5: If Figure 6 As shown, the insulating layer is patterned to form an insulating mask pattern 15 .

[0197] Step 6: If Figure 7 As shown, the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed.

[0198] Step 7: Figure 8 and Fig. 9 As shown, the surface of the area of ​​the first surface exposed outside the insulating mask pattern 15 and the second surface are subjected to texturing treatment.

[0199] The operations in the first to seventh steps of the manufacturing method provided in Example 2 are the same as the operations in the first to seventh steps of the manufacturing method provided in Example 1. The description in the above-mentioned Example 1 can be referred to and will not be repeated here. After the texturing treatment, the insulating mask pattern 15 in the manufacturing method provided in Example 2 is retained and is not removed.

[0200] Step 8: Fig.26 As shown, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11. The first passivation layer 17 includes an intrinsic silicon passivation layer. In this case, the intrinsic silicon passivation layer has a higher hydrogen content, which can make the first passivation layer 17 have a higher passivation effect on the second surface of the semiconductor substrate 11, further improving the conversion efficiency of the manufactured back contact battery. During the annealing treatment, the first passivation layer can inject hydrogen into the first doped silicon layer, that is, replenish hydrogen, which can improve the passivation effect of the first doped silicon layer. In addition, the manufacturing temperature of the intrinsic silicon passivation layer is relatively low, and it does not need to be activated by high-temperature annealing treatment, which is conducive to reducing the manufacturing cost of the back contact battery.

[0201] In addition, in the eighth step of the manufacturing method provided in Embodiment 2, the first passivation layer may be formed only on the second surface. Alternatively, the first passivation layer may be formed on one side of the second surface while the first passivation layer is plated around the side of the semiconductor substrate and at least a portion of the area on one side of the first surface.

[0202] Step 9: Fig. 27 As shown, a second interface passivation layer 19 and a second doped silicon layer 20 are sequentially stacked on the first surface along the thickness direction of the semiconductor substrate 11. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0203] The operation of the ninth step in the manufacturing method provided in Example 2 is the same as the operation of the ninth step in the manufacturing method provided in Example 1, and the description in the above-mentioned Example 1 can be referred to, and will not be repeated here. In addition, when the first passivation layer is an intrinsic silicon passivation layer and the second interface passivation layer is an intrinsic silicon layer, the manufacturing method provided in the embodiment of the present invention does not specifically limit the formation order of the first passivation layer and the second interface passivation layer. It can be that the first passivation layer is formed first, and then the second interface passivation layer is formed; it can also be that the second interface passivation layer is formed first, and then the first passivation layer is formed.

[0204] Step 10: If Fig.28 As shown, an anti-reflection layer is formed on the second surface of the semiconductor substrate 11 to reduce the reflectivity of the back contact battery on the side of the second surface, and further improve the conversion efficiency of the back contact battery. The material of the anti-reflection layer 18 can be determined according to the actual application scenario, and is not specifically limited here. Exemplarily, the anti-reflection layer 18 may include a silicon nitride layer. Secondly, when the anti-reflection layer 18 is formed on the second surface of the semiconductor substrate 11, the anti-reflection layer 18 may also be formed on the side of the semiconductor substrate 11 and on at least part of the first surface of the semiconductor substrate 11 due to winding. Therefore, before performing the operation step, a process such as wet etching can be used to remove the anti-reflection layer 18 that is wound around at least part of the first surface of the semiconductor substrate 11. After de-winding, the anti-reflection layer 18 on the side of the semiconductor substrate 11 can be retained in its entirety or in part.

[0205] In addition, in the actual application process, in some examples, in the manufacturing method provided in Example 2, the first surface may also include the above-mentioned first area and the above-mentioned second area, and the second area includes a groove. In this case, when the second doped silicon layer is a doped amorphous silicon layer, after the second interface passivation layer and the second doped silicon layer are stacked in sequence on the first surface along the thickness direction of the semiconductor substrate, the manufacturing method of the back contact battery may also include an eleventh step: laser irradiating the second doped silicon layer located on the bottom surface of the groove to crystallize the second doped silicon layer. The method, degree of treatment and treatment effect of the crystallization treatment can also be referred to the previous text and will not be repeated here. In addition, the above-mentioned eleventh step operation may also be omitted.

[0206] Step 12: Fig.29 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 is removed to expose a portion of the first interface passivation layer 1212 and the first doped silicon layer 13 .

[0207] Step 13: If Fig.30 and Fig.31 As shown, a transparent conductive layer 21 is formed to cover the first doped silicon layer 13 and the second doped silicon layer 20 on the side away from the semiconductor substrate 11. An isolation groove 22 is formed through the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0208] Step 14: If Fig.32 As shown, a first electrode is formed on a portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 , and a second electrode is formed on a portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20 .

[0209] Among them, the operations of steps 12 to 14 in the manufacturing method provided in Example 2 are the same as the operations of steps 15 to 17 in the manufacturing method provided in Example 1 where the insulating mask pattern is retained after the texturing treatment. Please refer to the description in the above Example 1 and no further details will be given here.

[0210] It should be noted that, in addition to forming the insulating mask pattern in the manner described above, the insulating mask pattern in Embodiment 2 of the present invention may also be formed in at least the following two ways:

[0211] The first method is to form a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate while forming the first doped silicon layer. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may include: Fig. 20 and Fig.21 As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third and fourth steps can be omitted in the first method. The fifth step described above is replaced by patterning the first doped silicon glass layer.

[0212] Second, while forming the first doped silicon layer, a first doped silicon glass layer is formed on a portion of the first doped silicon layer away from the semiconductor substrate. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may also include: Figure 22 to Figure 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third step can be omitted in the second method. In addition, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0213] The specific forming process of the first and second insulating mask patterns mentioned above can refer to the specific forming process of the first and second insulating mask patterns in Embodiment 1, which will not be described in detail here.

[0214] In addition, in the actual manufacturing process, the insulating mask pattern may be removed while performing the seventh step, or after performing the seventh step and before performing the eighth step.

[0215] In addition, in some embodiments, when the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer, which is disposed on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer may passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. Secondly, the presence of the amorphous silicon layer may also prevent the etchant for etching the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than the work function difference between the doped polycrystalline silicon layer and the transparent conductive layer, that is, the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact barrier between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared with the first doped silicon layer directly contacting the transparent conductive layer, arranging the amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable energy band matching, reduce contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0216] Specifically, the amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are laser removed, and the high temperature laser modifies the surface of the first doped silicon layer. In addition, the amorphous silicon layer can be located on a portion of the bottom of the opening area of ​​the second interface passivation layer and the second doped silicon layer, or can cover all areas of the bottom of the opening area.

[0217] In addition, the amorphous silicon layer can be continuously distributed in the opening area of ​​the second interface passivation layer and the second doped silicon layer and arranged on the side of the first doped silicon layer away from the semiconductor substrate; it can also be distributed intermittently, for example, in dispersed point distribution.

[0218] Example 3

[0219] This embodiment 3 only describes in detail the steps that are different from the embodiment 1. The same steps can refer to the explanation of the above embodiment 1, and will not be repeated in the embodiment 3. The difference between the embodiment 3 and the embodiment 1 is that the embodiment 3 first forms a stacked second interface passivation layer and a second doped silicon layer, and then forms a first passivation layer and an anti-reflection layer. The following is a detailed description of the embodiment 3:

[0220] The first step is to provide a semiconductor substrate having a first surface and a second surface opposite to each other.

[0221] Step 2: If Figure 2As shown, along the thickness direction of the semiconductor substrate 11 , a stacked first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11 .

[0222] Step 3: If Figure 3 As shown, the first doped silicon glass layer is removed.

[0223] Step 4: If Figure 4 and Figure 5 As shown, an insulating layer 16 is formed on a side of the first doped silicon layer 13 facing away from the semiconductor substrate 11 .

[0224] Step 5: If Figure 6 As shown, the insulating layer 16 is patterned to form an insulating mask pattern 15 .

[0225] Step 6: If Figure 7 As shown, the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed.

[0226] Step 7: Fig.11 and Fig.12 As shown, the surface of the area of ​​the first surface exposed outside the insulating mask pattern 15 and the second surface are subjected to texturing treatment.

[0227] Step 8: Figure 8 and Fig. 9 As shown, the insulating mask pattern is removed.

[0228] The operations from the first step to the eighth step in the manufacturing method provided in Example 3 are the same as the operations from the first step to the eighth step in the manufacturing method provided in Example 1, and will not be repeated here.

[0229] Step 9: Fig.33 As shown, a second interface passivation layer 19 and a second doped silicon layer 20 are sequentially stacked on the first surface along the thickness direction of the semiconductor substrate 11. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0230] Step 10: If Fig.34 As shown, while the first passivation layer 17 is formed on the second surface of the semiconductor substrate 11 , the first passivation layer 17 is formed on the first surface of the semiconductor substrate 11 .

[0231] Step 11: Fig.35 As shown, an anti-reflection layer is formed on the second surface of the semiconductor substrate 11 .

[0232] Among them, the methods of forming the corresponding structures in the ninth to eleventh steps of the manufacturing method provided in Example 3 are the same as the manufacturing methods of the corresponding structures formed in the ninth, tenth and twelfth steps of the manufacturing method provided in Example 1, and will not be repeated here.

[0233] Step 12: Using laser annealing, the first passivation layer disposed on the second surface of the semiconductor substrate is processed to activate the passivation performance of the first passivation layer.

[0234] It should be noted that in the manufacturing method provided in Example 1, annealing treatment is required after forming the first passivation layer (or forming the first passivation layer and the anti-reflection layer) to activate the passivation performance. In the manufacturing method provided in Example 3, after forming the first passivation layer (or forming the first passivation layer and the anti-reflection layer), the passivation performance of the first passivation layer is activated by laser treatment. The processing temperature of the laser annealing is relatively low, which can reduce the influence of high temperature on the formed structure and help reduce the manufacturing cost.

[0235] Step 13: If Fig.36 As shown, the anti-reflection layer 18 plated around one side of the first surface and the first passivation layer 17 formed on one side of the first surface need to be removed in sequence. At this time, the first passivation layer 17 and the anti-reflection layer 18 plated around the side of the semiconductor substrate 11 can be retained in full or in part. The above-mentioned removal operation can be performed in a chain cleaning device, and then after the above-mentioned removal operation and before performing subsequent operations, the semiconductor substrate 11 can be cleaned with metal ions (i.e., RCA cleaning) to remove contamination and slight scratches caused by the semiconductor substrate 11 in the chain cleaning device. In some embodiments, the cleaning operation may not be performed.

[0236] In some examples, step 13 may not be performed.

[0237] Step 14: If Fig.37 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 is removed to expose a portion of the first interface passivation layer 12 and the first doped silicon layer 13 .

[0238] Step 15: If Fig.38 As shown, a transparent conductive layer 21 is formed to cover the first doped silicon layer 13 and the second doped silicon layer 20 on the side away from the semiconductor substrate 11. An isolation groove 22 is formed through the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0239] Step 16: Fig.39 As shown, a first electrode is formed on a portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 , and a second electrode is formed on a portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20 .

[0240] The operations of steps 14 to 16 in the manufacturing method provided in Example 3 are the same as the operations of steps 15 to 17 in the manufacturing method provided in Example 1, and are not described again here.

[0241] It is worth noting that, unlike the manufacturing method provided in Example 1, the manufacturing method provided in Example 3 is to form a stacked second interface passivation layer and a second doped silicon layer on the first surface after the surface of the area exposed outside the insulating mask pattern on the first surface and the second surface are subjected to a texturing treatment, and before the first passivation layer is formed on the second surface of the semiconductor substrate. In this case, another optional example can be added to the manufacturing method provided in the embodiment of the present invention, which is conducive to improving the applicability of the manufacturing method provided in the embodiment of the present invention in different application scenarios. At the same time, when the first passivation layer is formed on the second surface of the semiconductor substrate, the first passivation layer may be plated around the side of the semiconductor substrate and at least part of the area of ​​the first surface. Based on this, when the formation sequence of the stacked second interface passivation layer and the second doped silicon layer is set after the texturing treatment and before at least the first passivation layer is formed, it is no longer necessary to remove at least the portion of the first passivation layer plated around the first surface before forming the stacked second interface passivation layer and the second doped silicon layer, thereby reducing the process steps. It can be determined according to actual needs whether to remove the first passivation layer plated around the first surface after at least the first passivation layer is formed, thereby reducing manufacturing requirements. Moreover, in this case, the corresponding structure on one side of the first surface can be made first, and then the corresponding film layer (first passivation layer and anti-reflection layer) on the second side can be made, so as to reduce the number of flipping and reduce the risk of damage. In addition, when the material of the second doped silicon layer includes at least one of amorphous silicon, microcrystalline silicon and nanocrystalline silicon, since the structure on the first side is made first, and then the structure on the second side is made. And the thermal stability of amorphous silicon, microcrystalline silicon and nanocrystalline silicon is poorer than that of polycrystalline silicon and single crystal silicon, only laser annealing that can be processed locally can be used, and rapid annealing cannot be used.

[0242] It should be noted that, in addition to forming the insulating mask pattern in the manner described above, the insulating mask pattern in Embodiment 3 of the present invention may also be formed in at least the following two ways:

[0243] The first method is to form a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate while forming the first doped silicon layer. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may include: Fig. 20 and Fig.21As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third and fourth steps can be omitted in the first method. The fifth step described above is replaced by patterning the first doped silicon glass layer.

[0244] Second, while forming the first doped silicon layer, a first doped silicon glass layer is formed on a portion of the first doped silicon layer away from the semiconductor substrate. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may also include: Figure 22 to Figure 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third step can be omitted in the second method. In addition, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0245] The specific forming process of the first and second insulating mask patterns mentioned above can refer to the specific forming process of the first and second insulating mask patterns in Embodiment 1, which will not be described in detail here.

[0246] In addition, in the actual manufacturing process, the eighth step may not be performed. Fig.39 As shown, after removing the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15, and before forming the stacked second interface passivation layer 19 and the second doped silicon layer 20, the insulating mask pattern 15 is not removed. At this time, the existence of the insulating mask pattern 15 can separate the first doped silicon layer 13 and the second doped silicon layer 20 along the thickness direction of the semiconductor substrate 11, which can suppress forward leakage while reducing the thickness requirement of the second interface passivation layer 19, reducing the transmission resistance of the second interface passivation layer 19, reducing transmission losses, and helping to improve the carrier collection efficiency of the second doped silicon layer 20 and improve the conversion efficiency of the back contact battery.

[0247] Wherein, when the eighth step is not performed, in the tenth step, the first passivation layer may be formed only on the second surface of the semiconductor substrate. Alternatively, the first passivation layer may be formed on both the first surface and the second surface of the semiconductor substrate.

[0248] In addition, in some embodiments, when the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer, which is disposed on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer may passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. Secondly, the presence of the amorphous silicon layer may also prevent the etchant for etching the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than the work function difference between the doped polycrystalline silicon layer and the transparent conductive layer, that is, the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact barrier between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared with the first doped silicon layer directly contacting the transparent conductive layer, arranging the amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable energy band matching, reduce contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0249] Specifically, the amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are laser removed, and the high temperature laser modifies the surface of the first doped silicon layer. In addition, the amorphous silicon layer can be located on a portion of the bottom of the opening area of ​​the second interface passivation layer and the second doped silicon layer, or can cover all areas of the bottom of the opening area.

[0250] In addition, the amorphous silicon layer can be continuously distributed in the opening area of ​​the second interface passivation layer and the second doped silicon layer and arranged on the side of the first doped silicon layer away from the semiconductor substrate; it can also be distributed intermittently, for example, in dispersed point distribution.

[0251] Example 4

[0252] This embodiment 4 only describes in detail the steps that are different from the embodiment 1. The same steps can refer to the explanation of the above embodiment 1, and will not be repeated in the embodiment 4. The difference between the embodiment 4 and the embodiment 1 is that the first passivation layer formed in the embodiment 4 in the eighth step includes a second doped silicon glass layer and / or an aluminum oxide layer. The embodiment 4 is described in detail below:

[0253] The first step is to provide a semiconductor substrate having a first surface and a second surface opposite to each other.

[0254] Step 2: If Figure 2As shown, along the thickness direction of the semiconductor substrate 11 , a stacked first interface passivation layer 12 and a first doped silicon layer 13 are sequentially formed on the first surface of the semiconductor substrate 11 .

[0255] Step 3: If Figure 3 As shown, the first doped silicon glass layer is removed.

[0256] Step 4: If Figure 4 and Figure 5 As shown, an insulating layer 16 is formed on a side of the first doped silicon layer 13 facing away from the semiconductor substrate 11 .

[0257] Step 5: If Figure 6 As shown, the insulating layer 16 is patterned to form an insulating mask pattern 15 .

[0258] Step 6: If Figure 7 As shown, the first interface passivation layer 12 and the first doped silicon layer 13 not covered by the insulating mask pattern 15 are removed.

[0259] Step 7: Figure 8 and Fig. 9 As shown, the surface of the area of ​​the first surface exposed outside the insulating mask pattern 15 and the second surface are subjected to texturing treatment.

[0260] Step 8: Fig.26 As shown, a first passivation layer 17 is formed on the second surface of the semiconductor substrate 11 .

[0261] Wherein, the first passivation layer may include any film layer with a passivation effect, such as a second doped silicon glass layer and / or an aluminum oxide layer, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention. Wherein, the conductivity type of the dopant in the second doped silicon glass layer is the same as the conductivity type of the first doped silicon layer. In this case, compared with the intrinsic silicon passivation layer, the second doped silicon glass layer and the aluminum oxide layer have higher light transmittance characteristics. Therefore, compared with the first passivation layer including the intrinsic silicon passivation layer, when the first passivation layer includes the second doped silicon glass layer and / or the aluminum oxide layer, the parasitic absorption of the first passivation layer can be reduced, which is beneficial to improve the utilization rate of light by the back contact battery. In addition, the second doped silicon glass layer is also doped with a dopant of the same conductivity type as the first doped silicon layer, so that the first passivation layer can not only chemically passivate the second side of the semiconductor substrate, but also field passivate the second side of the semiconductor substrate, reducing the carrier recombination rate on the second side, while also helping to improve the carrier collection efficiency of the first doped silicon layer and the second doped silicon layer. Compared with the need for separate deposition, the second doped silicon glass layer can be formed by a diffusion process, which simplifies the difficulty of manufacturing the first passivation layer.

[0262] In addition, when the first passivation layer is a second doped silicon glass layer, the first passivation layer can be formed on the second surface of the semiconductor substrate and also on the first surface. When the first passivation layer is an aluminum oxide layer, the first passivation layer can be formed only on the second surface without forming the first passivation layer on the first surface.

[0263] Step 9: Fig.40 As shown, an anti-reflection layer is formed on the second surface of the semiconductor substrate 11 .

[0264] Step 10: Using laser annealing, the first passivation layer disposed on the second surface of the semiconductor substrate is processed to activate the passivation performance.

[0265] Step 11: Fig.41 As shown, the anti-reflection layer 18 coated on one side of the first surface and the first passivation layer 17 formed on one side of the first surface are removed in sequence.

[0266] Step 12: Fig.42 and Fig.43 As shown, along the thickness direction of the semiconductor substrate 11, a second interface passivation layer 19 and a second doped silicon layer 20 are sequentially stacked on the first surface. The second doped silicon layer 20 and the first doped silicon layer 13 have opposite conductivity types.

[0267] Step 13: If Fig.44 As shown, a portion of the second interface passivation layer 19 and the second doped silicon layer 20 located on the first interface passivation layer 12 and the first doped silicon layer 13 is removed to expose a portion of the first interface passivation layer 12 and the first doped silicon layer 13 .

[0268] Step 14: If Fig.45 As shown, a transparent conductive layer 21 is formed to cover the first doped silicon layer 13 and the second doped silicon layer 20 on the side away from the semiconductor substrate 11. An isolation groove 22 is formed through the transparent conductive layer 21 to disconnect the portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 from the portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20.

[0269] Step 15: If Fig.46 As shown, a first electrode is formed on a portion of the transparent conductive layer 21 corresponding to the first doped silicon layer 13 , and a second electrode is formed on a portion of the transparent conductive layer 21 corresponding to the second doped silicon layer 20 .

[0270] Among them, except that the insulating mask pattern is retained after the seventh step operation, and the first passivation layer may also include a second doped silicon glass layer, the operations of the first to fifteenth steps in the manufacturing method provided in Example 4 are the same as the operations of the first to seventh steps and the ninth to seventeenth steps in the manufacturing method provided in Example 1, and will not be repeated here.

[0271] It should be noted that, in addition to forming the insulating mask pattern in the manner described above, the insulating mask pattern in Embodiment 4 of the present invention may also be formed in at least the following two ways:

[0272] The first method is to form a first doped silicon glass layer on a portion of the first doped silicon layer away from the semiconductor substrate while forming the first doped silicon layer. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may include: Fig. 20 and Fig.21 As shown, the first doped silicon glass layer 14 is patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third and fourth steps can be omitted in the first method. The fifth step described above is replaced by patterning the first doped silicon glass layer.

[0273] Second, while forming the first doped silicon layer, a first doped silicon glass layer is formed on a portion of the first doped silicon layer away from the semiconductor substrate. Based on this, forming an insulating mask pattern on a portion of the first doped silicon layer away from the semiconductor substrate may also include: Figure 22 to Figure 24 As shown, an insulating layer 16 is formed on the side of the first doped silicon glass layer 14 away from the semiconductor substrate 11; and the first doped silicon glass layer 14 and the insulating layer 16 are patterned to form an insulating mask pattern 15. At this time, relative to the formation process of the insulating mask pattern described above, the third step can be omitted in the second method. In addition, the fifth step described above needs to be replaced by patterning the first doped silicon glass layer and the insulating layer.

[0274] The specific forming process of the first and second insulating mask patterns mentioned above can refer to the specific forming process of the first and second insulating mask patterns in Embodiment 1, which will not be described in detail here.

[0275] In addition, in the actual manufacturing process, the insulating mask pattern may be removed while performing the seventh step, or after performing the seventh step and before performing the eighth step. At this time, in the eighth step, while forming the first passivation layer on the second surface of the semiconductor substrate, the first passivation layer may also be formed on the first surface, so as to perform hydrogen implantation into the first doped silicon layer through the first passivation layer, thereby reducing the number of defects on the side of the first doped silicon layer away from the semiconductor substrate.

[0276] In addition, in some embodiments, when the first doped silicon layer is a doped polycrystalline silicon layer, the back contact cell may further include an amorphous silicon layer, which is disposed on the side of the first doped silicon layer away from the semiconductor substrate. In this case, the amorphous silicon layer may passivate the side of the first doped silicon layer away from the semiconductor substrate, reduce the number of surface defects on the side of the first doped silicon layer away from the semiconductor substrate, and improve the conversion efficiency of the back contact cell. Secondly, the presence of the amorphous silicon layer may also prevent the etchant for etching the second interface passivation layer and the second doped silicon layer from affecting the first doped silicon layer, further improving the formation quality of the first doped silicon layer. In addition, since the work function difference between the amorphous silicon layer and the transparent conductive layer is smaller than the work function difference between the doped polycrystalline silicon layer and the transparent conductive layer, that is, the contact barrier between the amorphous silicon layer and the transparent conductive layer is smaller than the contact barrier between the doped polycrystalline silicon layer and the transparent conductive layer, the contact resistance between the amorphous silicon layer and the transparent conductive layer is smaller than the contact resistance between the doped polycrystalline silicon layer and the transparent conductive layer. Therefore, compared with the first doped silicon layer directly contacting the transparent conductive layer, arranging the amorphous silicon layer on the side of the first doped silicon layer away from the semiconductor substrate can achieve more reasonable energy band matching, reduce contact resistance, and enable the back contact cell to effectively convert sunlight into electrical energy, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0277] Specifically, the amorphous silicon layer is formed when the second interface passivation layer and the second doped silicon layer are laser removed, and the high temperature laser modifies the surface of the first doped silicon layer. In addition, the amorphous silicon layer can be located on a portion of the bottom of the opening area of ​​the second interface passivation layer and the second doped silicon layer, or can cover all areas of the bottom of the opening area.

[0278] In addition, the amorphous silicon layer can be continuously distributed in the opening area of ​​the second interface passivation layer and the second doped silicon layer and arranged on the side of the first doped silicon layer away from the semiconductor substrate; it can also be distributed intermittently, for example, in dispersed point distribution.

[0279] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0280] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for manufacturing a back contact battery, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; Forming a stacked first interface passivation layer and a first doped silicon layer in sequence on a first surface of the semiconductor substrate along a thickness direction of the semiconductor substrate; forming an insulating mask pattern on a partial region of the first doped silicon layer facing away from the semiconductor substrate; removing the first interface passivation layer and the first doped silicon layer not covered by the insulating mask pattern; Performing a texturing process on the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; forming a first passivation layer on the second surface of the semiconductor substrate; A second interface passivation layer and a second doped silicon layer are sequentially formed on the first surface along the thickness direction of the semiconductor substrate; the second doped silicon layer and the first doped silicon layer have opposite conductivity types; Portions of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer are removed to expose portions of the first interface passivation layer and the first doped silicon layer.

2. The method for manufacturing a back contact battery according to claim 1, characterized in that: The texturing treatment of the area of ​​the first surface exposed outside the insulating mask pattern and the second surface comprises: performing the texturing treatment on the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; removing the insulating mask pattern; Alternatively, the texturing treatment of the area of ​​the first surface exposed outside the insulating mask pattern and the second surface includes: performing the texturing treatment on the area of ​​the first surface exposed outside the insulating mask pattern and the second surface; and retaining the insulating mask pattern after the texturing treatment.

3. The method for manufacturing a back contact battery according to claim 1 or 2, characterized in that: The sequentially forming a stacked first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate comprises: while sequentially forming the stacked first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on a side of the first doped silicon layer away from the semiconductor substrate; The forming of the insulating mask pattern on a partial region of the first doped silicon layer away from the semiconductor substrate comprises: patterning the first doped silicon glass layer to form the insulating mask pattern; Or, the sequentially forming a stacked first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate comprises: while sequentially forming the stacked first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on a side of the first doped silicon layer away from the semiconductor substrate; The step of forming an insulating mask pattern on a partial region of the first doped silicon layer away from the semiconductor substrate comprises: forming an insulating layer on a side of the first doped silicon glass layer away from the semiconductor substrate; and patterning the first doped silicon glass layer and the insulating layer to form the insulating mask pattern; Or, the sequentially forming a stacked first interface passivation layer and a first doped silicon layer on the first surface of the semiconductor substrate comprises: while sequentially forming the stacked first interface passivation layer and the first doped silicon layer on the first surface of the semiconductor substrate, forming a first doped silicon glass layer on a side of the first doped silicon layer away from the semiconductor substrate; The forming of the insulating mask pattern on a partial area of ​​the first doped silicon layer away from the semiconductor substrate comprises: removing the first doped silicon glass layer; forming an insulating layer on the side of the first doped silicon layer away from the semiconductor substrate; and patterning the insulating layer to form the insulating mask pattern.

4. The method for manufacturing a back contact battery according to claim 1, characterized in that: The forming of a first passivation layer on the second surface of the semiconductor substrate comprises: forming the first passivation layer on the first surface of the semiconductor substrate while forming the first passivation layer on the second surface of the semiconductor substrate; performing annealing treatment on the first passivation layer; The first passivation layer located on the first surface of the semiconductor substrate is removed.

5. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first passivation layer comprises an intrinsic amorphous silicon layer; And / or, after a second interface passivation layer and a second doped silicon layer are stacked in sequence on the first surface, before removing a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the method for the back contact battery further includes: forming an anti-reflection layer on a side of the first passivation layer away from the semiconductor substrate.

6. The method for manufacturing a back contact battery according to claim 1, characterized in that: After the area of ​​the first surface exposed outside the insulating mask pattern and the second surface are textured, and before the first passivation layer is formed on the second surface of the semiconductor substrate, the second interface passivation layer and the second doped silicon layer are stacked in sequence on the first surface.

7. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first passivation layer includes a second doped silicon glass layer, and the conductivity type of the dopant in the second doped silicon glass layer is the same as the conductivity type of the first doped silicon layer; And / or, forming the first passivation layer on the second surface of the semiconductor substrate comprises: forming the first passivation layer and the anti-reflection layer sequentially stacked along the thickness direction of the semiconductor substrate on the second surface of the semiconductor substrate.

8. The method for manufacturing a back contact battery according to claim 1, characterized in that: After removing the portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, the method for manufacturing the back contact cell further includes: forming a transparent conductive layer covering the first doped silicon layer and the second doped silicon layer on a side away from the semiconductor substrate; forming a penetrating isolation groove in the transparent conductive layer to disconnect a portion of the transparent conductive layer corresponding to the first doped silicon layer from a portion of the transparent conductive layer corresponding to the second doped silicon layer; A first electrode is formed on a portion of the transparent conductive layer corresponding to the first doped silicon layer, and a second electrode is formed on a portion of the transparent conductive layer corresponding to the second doped silicon layer.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: The thickness of the edge portion of the transparent conductive layer adjacent to the isolation groove gradually decreases along a direction approaching the isolation groove.

10. The method for manufacturing a back contact battery according to claim 8 or 9, characterized in that: The second interface passivation layer and the second doped silicon layer stacked in sequence, and the transparent conductive layer disposed on the second doped silicon layer all cover a partial area of ​​the stacked first interface passivation layer and the first doped silicon layer away from the semiconductor substrate.

11. The method for manufacturing a back contact battery according to claim 1, characterized in that: The thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm; And / or, the width of the opening area of ​​the second interface passivation layer and the second doped silicon layer is greater than or equal to 250 μm and less than or equal to 400 μm.

12. The method for manufacturing a back contact battery according to claim 1, characterized in that: In the first surface, a region where the first interface passivation layer and the first doped silicon layer are provided has a tower base-shaped texture structure; The thickness of the first interface passivation layer at the bottom surface of the tower base-shaped texture structure is smaller than the thickness of the first interface passivation layer at the side wall of the tower base-shaped texture structure.

13. The method for manufacturing a back contact battery according to claim 1, characterized in that: The thickness of the second interface passivation layer is greater than or equal to 3 nm and less than or equal to 16 nm.

14. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first doped silicon layer is a doped polysilicon layer; The back contact cell further comprises an amorphous silicon layer, which is located in the opening region between the second interface passivation layer and the second doped silicon layer and is arranged on a side of the first doped silicon layer away from the semiconductor substrate.

15. The method for manufacturing a back contact battery according to claim 1, characterized in that: The removing a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer comprises: A laser is used to remove a portion of the second interface passivation layer and the second doped silicon layer located on the first interface passivation layer and the first doped silicon layer, and a laser is used to process an edge portion of an opening area of ​​the second doped silicon layer so that a hole structure is formed in the edge portion of the opening area of ​​the second doped silicon layer.

16. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first surface includes a first area and a second area; the second area includes a groove; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region and extend to the first region to cover a portion of the first interface passivation layer and the first doped silicon layer; The surface of the first region is a polished surface, and the bottom surface of the groove is a velvet surface; the thickness of the second doped silicon layer on the velvet surface is less than the thickness of the second doped silicon layer on the polished surface.

17. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first surface includes a first area and a second area; the second area includes a groove; the surface of the first area is a polished surface, and the bottom surface of the groove is a velvet surface; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region, and extend from the second region to the first region to cover a portion of the first interface passivation layer and the first doped silicon layer; The distance from the surface of the semiconductor substrate located in the first region to the bottom surface of the groove is greater than or equal to 2 μm and less than or equal to 8 μm.

18. The method for manufacturing a back-contact battery according to claim 1, wherein the first surface comprises a first region and a second region; the second region comprises a groove; The first interface passivation layer and the first doped silicon layer are located in the first region; the second interface passivation layer and the second doped silicon layer are located in the second region, and extend from the second region to the first region to cover a portion of the first interface passivation layer and the first doped silicon layer; The second doped silicon layer is a doped amorphous silicon layer; After sequentially forming a stacked second interface passivation layer and a second doped silicon layer on the first surface along the thickness direction of the semiconductor substrate, the method for manufacturing a back contact battery further includes: The second doped silicon layer located on the bottom surface of the groove is irradiated with laser to crystallize the second doped silicon layer.

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