Soft start circuit and DC / DC converter

Abstract

The present invention provides a soft start circuit and a DC / DC converter, wherein the soft start circuit comprises a ramp voltage circuit, a differential input circuit, a load amplifier circuit, a switching circuit and a positive feedback hysteresis circuit. When the soft start circuit is powered on, the ramp voltage circuit outputs a ramp voltage that changes and rises, and when the voltage difference between a reference voltage and the rising ramp voltage reaches a preset difference, the differential input circuit outputs a second current signal, and outputs a second switching signal after being amplified by the load amplifier circuit. The positive feedback hysteresis circuit increases the flipping speed of the second switching signal, so that the second switching signal quickly reaches the switching threshold of the switching circuit. Since the ramp voltage is less than the reference voltage at this time, during the signal output delay period, even if the ramp voltage continues to rise, the soft start circuit can be adjusted according to the signal delay time and the rising speed of the ramp voltage to ensure that the ramp voltage is less than the reference voltage when the switching circuit is switched, thereby avoiding output overshoot during switching.

Description

Technical Field

[0001] The invention belongs to the technical field of soft starting, and in particular relates to a soft starting circuit and a DC / DC converter. Background Art

[0002] The DC / DC converter is used to realize the conversion of DC voltage and provide DC working power for the load. During the power-on startup phase of the DC / DC converter, the internal reference voltage is established quickly, while the external output voltage is established slowly due to the load and loop. The feedback voltage of the feedback pin of the error amplifier circuit is much lower than the reference voltage, causing the power tube of the switching circuit to open with the maximum duty cycle, so that a large amount of surge current is output to the load, resulting in excessive output voltage and increased possibility of device damage. In order to solve this problem, Figure 1 As shown, a soft start circuit is usually used to achieve a slow rise in the output voltage of the DC / DC converter to reduce voltage overshoot.

[0003] During the power-on startup phase of the DC / DC converter, the soft start circuit generates a slowly rising ramp voltage and outputs it to the reference voltage terminal of the error amplifier circuit. When the ramp voltage reaches the reference voltage, it switches the output reference voltage to the reference voltage terminal of the error amplifier circuit to achieve the purpose of soft start.

[0004] The switching signal of the output voltage of a common soft start circuit is output by a comparator. When the ramp voltage is the same as the reference voltage, the comparator switches to output a switching signal. There is a delay from the issuance of the switching signal to the completion of the switching. During this delay period, if the ramp voltage continues to rise, it is easy to cause the output of the ramp voltage to overshoot. Summary of the invention

[0005] The purpose of the present invention is to provide a soft start circuit, aiming to solve the problem of ramp voltage output overshoot in traditional soft start circuits.

[0006] A first aspect of an embodiment of the present invention provides a soft start circuit, comprising:

[0007] A ramp voltage circuit, configured to output a ramp voltage that increases when receiving a first switching signal;

[0008] A comparator circuit, the comparator circuit comprising a differential input circuit and a load amplifier circuit;

[0009] The differential input terminals of the differential input circuit are respectively input with the ramp voltage and the reference voltage, and the differential input circuit is used to compare the ramp voltage with the reference voltage, and output a first current signal when the voltage difference between the reference voltage and the ramp voltage does not reach a preset difference, and switch to output a second current signal when the voltage difference between the reference voltage and the ramp voltage reaches a preset difference;

[0010] The load amplifier circuit is connected to the differential input circuit and the ramp voltage circuit, and is used to amplify the first current signal and output a first switching signal, and to amplify the second current signal and output a second switching signal;

[0011] a switching circuit, wherein the ramp voltage and the reference voltage are input to two voltage input terminals of the switching circuit respectively, the control terminal of the switching circuit is connected to the output terminal of the load amplifier circuit, and the switching circuit is used to switch to output the ramp voltage when the first switching signal is received or when the voltage of the second switching signal does not reach a preset voltage, and to switch to output the reference voltage when the voltage of the second switching signal reaches a preset voltage;

[0012] A positive feedback hysteresis circuit is connected to the load amplifier circuit, and is used to obtain the second switching signal and positively feedback to increase the flipping speed of the second switching signal and provide a hysteresis amount to change the flipping threshold of the load amplifier circuit when the ramp voltage rises and falls.

[0013] Optionally, the ramp voltage circuit includes a first transistor, a second transistor, a third transistor and a capacitor;

[0014] The first transistor, the second transistor and the capacitor are connected in series in sequence and connected between a positive power supply terminal and a ground terminal, the third transistor is connected in parallel to both ends of the capacitor, a first bias voltage is input to the control terminal of the first transistor, the control terminal of the second transistor is connected to the output terminal of the load amplifier circuit, and a second enable signal is input to the control terminal of the third transistor.

[0015] Optionally, the load amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor;

[0016] The fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are sequentially connected in series and connected between the positive power supply terminal and the ground terminal. The eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are sequentially connected in series and connected between the positive power supply terminal and the ground terminal. The connection node of the fourth transistor and the fifth transistor constitutes the first input terminal of the load amplifier circuit. The connection node of the eighth transistor and the ninth transistor constitutes the second input terminal of the load amplifier circuit. The connection node of the ninth transistor and the tenth transistor constitutes the output terminal of the load amplifier circuit. The connection node of the sixth transistor and the seventh transistor constitutes the third input terminal of the load amplifier circuit. The connection node of the tenth transistor and the eleventh transistor constitutes the fourth input terminal of the load amplifier circuit. The control terminal of the fourth transistor and the control terminal of the eighth transistor are used to input a first bias voltage. The control terminal of the fifth transistor and the control terminal of the ninth transistor are used to input a second bias voltage. The control terminal of the sixth transistor and the control terminal of the tenth transistor are used to input a third bias voltage. The connection node of the fifth transistor and the sixth transistor is also connected to the control terminal of the seventh transistor and the control terminal of the eleventh transistor.

[0017] Optionally, the differential input circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor;

[0018] The first end of the twelfth transistor is connected to the positive power supply terminal, the second end of the twelfth transistor, the first end of the thirteenth transistor and the first end of the fourteenth transistor are connected, the second end of the thirteenth transistor is connected to the third input terminal of the load amplifier circuit, the second end of the fourteenth transistor is connected to the fourth input terminal of the load amplifier circuit, the first end of the fifteenth transistor is connected to the first input terminal of the load amplifier circuit, the second end of the sixteenth transistor is connected to the second input terminal of the load amplifier circuit, the second end of the fifteenth transistor, the second end of the sixteenth transistor and the first end of the seventeenth transistor are connected, the second end of the seventeenth transistor is connected to the ground terminal, the control end of the twelfth transistor is used to input the first bias voltage, the control end of the thirteenth transistor and the control end of the fifteenth transistor are used to input the reference voltage, the control end of the fourteenth transistor and the control end of the sixteenth transistor are connected to the output end of the ramp voltage circuit, and the control end of the seventeenth transistor is used to input the fourth bias voltage;

[0019] The width-to-length ratio of the thirteenth transistor is greater than the width-to-length ratio of the fourteenth transistor, and the width-to-length ratio of the fifteenth transistor is smaller than the width-to-length ratio of the sixteenth transistor.

[0020] Optionally, the switching circuit includes a first inverter, a second inverter and a transmission gate;

[0021] The input end of the first inverter is connected to the output end of the load amplifier circuit, the output end of the first inverter is connected to the input end of the second inverter, the input end of the transmission gate is used to input the reference voltage, the first control end of the transmission gate is connected to the output end of the first inverter, the second control end of the transmission gate is connected to the output end of the second inverter, and the output end of the transmission gate is connected to the output end of the ramp voltage circuit.

[0022] Optionally, the positive feedback hysteresis circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor;

[0023] The first end of the eighteenth transistor is connected to the positive power supply end, the second end of the eighteenth transistor, the control end of the nineteenth transistor and the first end of the twenty-third transistor are connected, the control end of the eighteenth transistor and the first end of the nineteenth transistor are connected to the output end of the load amplifier circuit, the second end of the nineteenth transistor is connected to the first end of the twentieth transistor, the second end of the twentieth transistor is connected to the first end of the twenty-first transistor, the second end of the twenty-first transistor is connected to the first end of the twenty-second transistor, the second end of the twenty-second transistor and the second end of the twenty-third transistor are connected to the ground end, and the control ends of the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-third transistor are used to input a fourth bias voltage.

[0024] Optionally, the soft start circuit further includes:

[0025] A bias circuit, connected to the ramp voltage circuit, the differential input circuit, the load amplifier circuit and the positive feedback hysteresis circuit respectively, for providing a corresponding bias voltage;

[0026] The enabling circuit is connected to the ramp voltage circuit, the differential input circuit and the load amplifier circuit respectively, and is used to control the soft start circuit to start or shut down according to a first enabling signal.

[0027] Optionally, the bias circuit includes a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor and a current source;

[0028] The first end of the twenty-fourth transistor, the first end of the twenty-fifth transistor, the first end of the twenty-sixth transistor and the first end of the twenty-seventh transistor are connected to the positive power supply terminal, the second end of the twenty-fourth transistor, the control end of the twenty-fourth transistor, the control end of the twenty-fifth transistor and the first end of the current source are connected to form a first voltage output end of the bias circuit and are used to output a first bias voltage, the second end of the current source is connected to the ground terminal, the second end of the twenty-fifth transistor, the first end of the twenty-ninth transistor, the control end of the twenty-ninth transistor and the control end of the thirtieth transistor are connected to form a fourth voltage output end of the bias circuit and are used to output a fourth bias voltage, the control end of the twenty-seventh transistor, the second end of the twenty-seventh transistor and the first end of the thirtieth transistor are connected to form a second voltage output end of the bias voltage and are used to output a second bias voltage, the second end of the twenty-sixth transistor, the first end of the twenty-eighth transistor and the control end of the twenty-eighth transistor constitute a third voltage output end of the bias circuit and are used to output a third bias voltage, and the second end of the twenty-eighth transistor, the second end of the twenty-ninth transistor and the thirtieth transistor are connected to the ground terminal.

[0029] Optionally, the enabling circuit includes a thirty-first transistor, a thirty-second transistor, a thirty-third transistor and a third inverter;

[0030] The first end of the thirty-first transistor and the first end of the thirty-second transistor are connected to the positive power supply end, the second end of the thirty-first transistor is connected to the first voltage output end of the bias circuit, the second end of the thirty-second transistor is connected to the output end of the load amplifier circuit, the control end of the thirty-first transistor and the control end of the thirty-second transistor are connected to the input end of the third inverter and are used to input the first enable signal, the first end of the thirty-third transistor is connected to the fourth voltage output end of the bias circuit, the control end of the thirty-third transistor and the control end of the third transistor are connected to the output end of the third inverter and are used to input the second enable signal, and the second end of the thirty-third transistor is connected to the ground end.

[0031] A second aspect of an embodiment of the present invention provides a DC / DC converter, comprising an error amplifier circuit, a PWM generation circuit, a switch circuit and the soft start circuit as described above, wherein the output end of the soft start circuit is connected to the non-phase input end of the error amplifier circuit, the inverting input end of the error amplifier circuit is connected to the output end of the switch circuit, the output end of the error amplifier circuit is connected to the input end of the PWM generation circuit, the output end of the PWM generation circuit is connected to the control end of the switch circuit, and the input end of the switch circuit is used to input a positive voltage.

[0032] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the above-mentioned soft start circuit includes a ramp voltage circuit, a differential input circuit, a load amplifier circuit, a switching circuit and a positive feedback hysteresis circuit. When the soft start circuit is powered on, the differential input circuit outputs a first current signal, the load amplifier circuit converts and outputs a first switching signal, the ramp voltage circuit outputs a ramp voltage that changes and rises, and when the voltage difference between the reference voltage and the rising ramp voltage reaches a preset difference, the differential input circuit outputs a second current signal, the load amplifier circuit converts and outputs a second switching signal to the switching circuit and the positive feedback hysteresis circuit, the positive feedback hysteresis circuit increases the flipping speed of the second switching signal, so that the second switching signal quickly reaches the switching threshold of the switching circuit, and because the ramp voltage is less than the reference voltage at this time, during the signal output delay period, even if the ramp voltage continues to rise, the soft start circuit can be adjusted according to the signal delay time and the rising speed of the ramp voltage to ensure that the ramp voltage is less than the reference voltage when the switching circuit switches, thereby avoiding output overshoot during switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 A schematic diagram of the structure of a DC / DC converter provided in an embodiment of the present invention;

[0035] Figure 2 A first structural schematic diagram of a soft start circuit provided by an embodiment of the present invention;

[0036] Figure 3 A circuit diagram of a soft start circuit provided by an embodiment of the present invention;

[0037] Figure 4 A second structural schematic diagram of a soft start circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0040] A first aspect of an embodiment of the present invention provides a soft start circuit 100 .

[0041] like Figure 2 As shown, in this embodiment, the soft start circuit 100 includes:

[0042] The ramp voltage circuit 10 is used to output a ramp voltage that changes and increases when receiving a first switching signal;

[0043] A comparator circuit 20, the comparator circuit 20 includes a differential input circuit 21 and a load amplifier circuit 22;

[0044] The differential input terminals of the differential input circuit 21 are respectively input with the ramp voltage and the reference voltage VREF0, and the differential input circuit 21 is used to compare the ramp voltage and the reference voltage VREF0, and output a first current signal when the voltage difference between the reference voltage VREF0 and the ramp voltage does not reach a preset difference, and output a second current signal when the voltage difference between the reference voltage VREF0 and the ramp voltage reaches a preset difference;

[0045] The load amplifier circuit 22 is connected to the differential input circuit 21 and the ramp voltage circuit 10, and is used to amplify the first current signal and output a first switching signal, and to amplify the second current signal and output a second switching signal;

[0046] A switching circuit 30, wherein the two voltage input terminals of the switching circuit 30 are respectively input with the ramp voltage and the reference voltage VREF0, and the control terminal of the switching circuit 30 is connected with the output terminal of the load amplifier circuit 22, and the switching circuit 30 is used to switch the output ramp voltage when receiving the first switching signal or when the voltage of the second switching signal does not reach the preset voltage, and to switch the output reference voltage VREF0 when the voltage of the second switching signal reaches the preset voltage;

[0047] The positive feedback hysteresis circuit 40 is connected to the load amplifier circuit 22, and is used to obtain the second switching signal and positively feedback to increase the flipping speed of the second switching signal and provide hysteresis to change the flipping threshold of the load amplifier circuit 22 when the ramp voltage rises and falls.

[0048] In this embodiment, VOUT represents the output voltage of the ramp voltage circuit 10. When the soft start circuit 100 is initially powered on, the initial value of the ramp voltage output by the ramp voltage circuit 10 is zero. At this time, the ramp voltage is much smaller than the reference voltage VREF0. The differential input circuit 21 compares and outputs a first current signal. The load amplifier circuit 22 receives the first current signal and amplifies it into a first switching signal through an internal load. The first switching signal can be a high level or a low level, and is output to the switching circuit 30 and the positive feedback hysteresis circuit 40. At this time, the positive feedback hysteresis circuit 40 does not work. The ramp voltage circuit 10 receives the first switching signal to start and output a changing and rising ramp voltage. The ramp voltage continues to rise. The switching circuit 30 outputs the current ramp voltage as the reference voltage VREF of the back-end circuit to prevent the DC / DC converter from having an output overshoot.

[0049] When the ramp voltage is close to the reference voltage VREF0, that is, the voltage difference between the reference voltage VREF0 and the ramp voltage is within the preset difference, for example, the reference voltage VREF0 is 5V, when the ramp voltage rises to 4.5V, the output of the differential input circuit 21 begins to flip, the differential input circuit 21 switches to output the second current signal, the load amplifier circuit 22 receives the second current signal and amplifies it through the internal load into a second switching signal, the second switching signal is at an opposite level to the first switching signal, in an optional embodiment, the first switching signal is at a high level, the second switching signal is at a low level, and at the same time, the positive feedback hysteresis circuit 40 starts to work and accelerates the second switching signal. The flipping speed of the switching signal speeds up the output flipping speed of the comparator circuit 20. During the period from the initial switching of the second switching signal to the drop to the preset voltage, the ramp voltage continues to rise, and when the voltage of the second switching signal drops to the preset voltage, the switching circuit 30 switches the output reference voltage VREF0. The soft start circuit 100 can be based on the rising speed of the ramp voltage, the output delay setting of the second switching signal, and the structure of the positive feedback hysteresis circuit 40, so that when the ramp voltage approaches and does not exceed the reference voltage VREF0, the switching circuit 30 switches the output reference voltage VREF0 as the reference voltage VREF of the back-end circuit to prevent output overshoot.

[0050] In order to prevent the comparator circuit 20 from frequently flipping at the flipping threshold, which may cause the soft start circuit 100 to misjudge, the positive feedback hysteresis circuit 40 also provides a hysteresis amount to change the flipping threshold of the comparator circuit 20 when the ramp voltage rises and falls. When the ramp voltage decreases, the flipping threshold of the comparator circuit 20 decreases, thereby preventing the comparator circuit 20 from frequently flipping and ensuring the output reliability of the comparator circuit 20.

[0051] Among them, the differential input circuit 21 can adopt other structures such as an asymmetric rail-to-rail structure, the ramp voltage circuit 10 can adopt structures such as a signal generator and an energy storage module, the load amplifier circuit 22 can adopt a common source and common gate structure, etc., and the positive feedback hysteresis circuit 40 can adopt a corresponding feedback adjustment circuit.

[0052] like Figure 3 As shown, in an optional embodiment, the ramp voltage circuit 10 includes a first transistor M1, a second transistor M2, a third transistor M3 and a capacitor C1;

[0053] The first transistor M1, the second transistor M2 and the capacitor C1 are connected in series in sequence and connected between the positive power supply terminal VDD and the ground terminal GND. The third transistor M3 is connected in parallel to both ends of the capacitor C1. The control end of the first transistor M1 inputs the first bias voltage, the control end of the second transistor M2 is connected to the output end of the load amplifier circuit 22, and the control end of the third transistor M3 inputs the second enable signal ENN.

[0054] The load amplifier circuit 22 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and an eleventh transistor M11;

[0055] The fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are sequentially connected in series and connected between the positive power supply terminal VDD and the ground terminal GND, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 are sequentially connected in series and connected between the positive power supply terminal VDD and the ground terminal GND, the connection node of the fourth transistor M4 and the fifth transistor M5 constitutes the first input terminal of the load amplifier circuit 22, the connection node of the eighth transistor M8 and the ninth transistor M9 constitutes the second input terminal of the load amplifier circuit 22, the connection node of the ninth transistor M10 and the tenth transistor M10 constitutes the output terminal of the load amplifier circuit 22, and the connection node of the eighth transistor M8 and the ninth transistor M9 constitutes the output terminal of the load amplifier circuit 22. The connection node of the sixth transistor M6 and the seventh transistor M7 constitutes the third input terminal of the load amplifier circuit 22, the connection node of the tenth transistor M10 and the eleventh transistor M11 constitutes the fourth input terminal of the load amplifier circuit 22, the control terminal of the fourth transistor M4 and the control terminal of the eighth transistor M8 are used to input the first bias voltage, the control terminal of the fifth transistor and the control terminal of the ninth transistor M9 are used to input the second bias voltage, the control terminal of the sixth transistor M6 and the control terminal of the tenth transistor M10 are used to input the third bias voltage, and the connection node of the fifth transistor and the sixth transistor M6 is also connected to the control terminal of the seventh transistor M7 and the control terminal of the eleventh transistor M11.

[0056] The differential input circuit 21 includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a sixteenth transistor M16 and a seventeenth transistor M17;

[0057] A first end of the twelfth transistor M12 is connected to the positive power supply terminal VDD, a second end of the twelfth transistor M12, a first end of the thirteenth transistor M13 and a first end of the fourteenth transistor M14 are connected, a second end of the thirteenth transistor M13 is connected to the third input terminal of the load amplifier circuit 22, a second end of the fourteenth transistor M14 is connected to the fourth input terminal of the load amplifier circuit 22, a first end of the fifteenth transistor M15 is connected to the first input terminal of the load amplifier circuit 22, a second end of the sixteenth transistor M16 is connected to the second input terminal of the load amplifier circuit 22, and a second end of the fifteenth transistor M15 is connected to the first input terminal of the load amplifier circuit 22. The second end of the transistor M15, the second end of the sixteenth transistor M16 and the first end of the seventeenth transistor M17 are connected, the second end of the seventeenth transistor M17 is connected to the ground terminal GND, the control end of the twelfth transistor M12 is used to input the first bias voltage, the control end of the thirteenth transistor M13 and the control end of the fifteenth transistor M15 are used to input the reference voltage VREF0, the control end of the fourteenth transistor M14 and the control end of the sixteenth transistor M16 are connected to the output end of the ramp voltage circuit 10, and the control end of the seventeenth transistor M17 is used to input the fourth bias voltage;

[0058] The width-to-length ratio of the thirteenth transistor M13 is greater than that of the fourteenth transistor M14 , and the width-to-length ratio of the fifteenth transistor M15 is less than that of the sixteenth transistor M16 .

[0059] The switching circuit 30 includes a first inverter INV1, a second inverter INV2 and a transmission gate T1;

[0060] The input end of the first inverter INV1 is connected to the output end of the load amplifier circuit 22, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the input end of the transmission gate T1 is used to input the reference voltage VREF0, the first control end of the transmission gate T1 is connected to the output end of the first inverter INV1, the second control end of the transmission gate T1 is connected to the output end of the second inverter INV2, and the output end of the transmission gate T1 is connected to the output end of the ramp voltage circuit 10.

[0061] The positive feedback hysteresis circuit 40 includes an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22 and a twenty-third transistor M23;

[0062] A first end of the eighteenth transistor M18 is connected to the positive power supply terminal VDD, a second end of the eighteenth transistor M18, a control end of the nineteenth transistor M19 and a first end of the twenty-third transistor M23 are connected, the control end of the eighteenth transistor M18 and the first end of the nineteenth transistor M19 are connected to the output end of the load amplifier circuit 22, a second end of the nineteenth transistor M19 is connected to a first end of the twenty-th transistor M20, a second end of the twentieth transistor M20 is connected to a first end of the twenty-first transistor M21, a second end of the twenty-first transistor M21 is connected to a first end of the twenty-second transistor M22, a second end of the twenty-second transistor M22 and a second end of the twenty-third transistor M23 are connected to the ground terminal GND, and the control ends of the twentieth transistor M20, the twenty-first transistor M21, the twenty-second transistor M22 and the twenty-third transistor M23 are used to input a fourth bias voltage.

[0063] In this embodiment, the output voltage V1 of the load amplifier circuit 22 is set as the output voltage of the comparator circuit 20, the terminal voltage of the capacitor C1 is the voltage output terminal of the ramp voltage circuit 10, and when initially powered on, the terminal voltage of the capacitor C1 is zero, the thirteenth transistor M13 and the fifteenth transistor M15 receive the reference voltage VREF0, the fourteenth transistor M14 and the sixteenth transistor M16 receive an initial value of zero, the fifteenth transistor M15 is turned on, the sixteenth transistor M16 is turned off, the current flowing through the fifteenth transistor M15 is greater than the current of the sixteenth transistor M16, the current flowing through the ninth transistor M9 is greater than the current of the tenth transistor M10, and the output voltage V1 of the load amplifier circuit 22 is a high level. At this time, the first inverter INV1 outputs a low level, the second inverter INV2 outputs a high level, the transmission gate T1 is turned off, the reference voltage VREF0 stops outputting, and the output voltage of the switching circuit 30 is the terminal voltage of the capacitor C1, that is, the ramp voltage.

[0064] The second transistor M2 is triggered to turn on by receiving a high level signal, and the third transistor M3 is triggered to turn off by receiving a low level second enable signal ENN. The capacitor C1 starts to charge, and the switching circuit 30 switches to output a rising ramp voltage.

[0065] Among them, the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 constitute a differential input circuit 21 of an unbalanced differential pair, the width-to-length ratio of the thirteenth transistor M13 is greater than the width-to-length ratio of the fourteenth transistor M14, and the width-to-length ratio of the fifteenth transistor M15 is less than the width-to-length ratio of the sixteenth transistor M16.

[0066] When the thirteenth transistor M13 and the fourteenth transistor M14 receive gate voltages of the same magnitude, the current flowing through the fourteenth transistor M14 is less than the current flowing through the thirteenth transistor M13. Therefore, when the gate voltage of the fourteenth transistor M14 is less than the gate voltage of the thirteenth transistor M13, the currents flowing through the thirteenth transistor M13 and the fourteenth transistor M14 are balanced.

[0067] Similarly, when the fifteenth transistor M15 and the sixteenth transistor M16 receive gate voltages of the same magnitude, the current flowing through the sixteenth transistor M16 is greater than the current flowing through the fifteenth transistor M15, that is, when the gate voltage of the sixteenth transistor M16 is less than the gate voltage of the fifteenth transistor M15, the currents flowing through the fifteenth transistor M15 and the sixteenth transistor M16 are balanced.

[0068] By properly setting the width-to-length ratio of the input differential pairs on both sides, when the ramp voltage is slightly lower than the reference voltage VREF0 , the output of the load amplifier circuit 22 is reversed, thereby completing the output voltage switching of the soft start circuit 100 .

[0069] When the ramp voltage approaches the reference voltage VREF0, and the voltage difference between the two reaches a preset difference, the current flowing through the ninth transistor M9 is less than the current flowing through the tenth transistor M10, the load amplifier circuit 22 starts to flip, the load amplifier circuit 22 switches to output the second switching signal, the output voltage V1 of the load amplifier circuit 22 is a low level, the eighteenth transistor M18 is triggered to turn on, the nineteenth transistor M19 is triggered to turn on, the current of the nineteenth transistor M19 increases, the second switching signal is further pulled down, and the second switching signal again causes the gate voltage of the nineteenth transistor M19 to become higher, thereby achieving positive feedback, accelerating the flipping speed of the second switching signal, and ultimately accelerating the flipping speed of the output voltage V1 of the load amplifier circuit 22, the second switching signal quickly reaches the preset voltage, and triggers the switching circuit 30 to switch the output reference voltage VREF0, the reference voltage VREF0 is output as the reference voltage VREF to prevent voltage output overshoot.

[0070] At the same time, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, the twenty-first transistor M21 and the twenty-first transistor M21 form a hysteresis unit, and are connected in parallel with the branch formed by the tenth transistor M10 and the eleventh transistor M11 when turned on, providing an additional current loop, thereby changing the flip threshold of the comparator circuit 20 when the ramp voltage rises and falls, and preventing misjudgment when the ramp voltage rises to near the flip threshold of the comparator circuit 20.

[0071] When the ramp voltage approaches and is slightly lower than the reference voltage VREF0, the comparator circuit 20 flips, the second transistor M2 is turned off, the capacitor C1 stops charging, the output level of the first inverter INV1 is high, and the level of the second inverter INV2 is low. At this time, the transmission gate T1 is turned on, and the reference voltage VREF of the soft start circuit 100 is switched to the reference voltage VREF0, completing the soft start.

[0072] Furthermore, if Figure 4 As shown, in order to complete the biasing work and enabling of each circuit, in an optional embodiment, the soft start circuit 100 further includes:

[0073] The bias circuit 50 is respectively connected to the ramp voltage circuit 10, the differential input circuit 21, the load amplifier circuit 22 and the positive feedback hysteresis circuit 40 to provide a corresponding bias voltage;

[0074] The enabling circuit 60 is connected to the ramp voltage circuit 10 , the differential input circuit 21 and the load amplifier circuit 22 respectively, and is used to control the soft start circuit 100 to start or shut down according to the first enabling signal EN.

[0075] In this embodiment, the bias circuit 50 is used to provide a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage to the corresponding ramp generating circuit, the differential input circuit 21, the load amplifier circuit 22, and the positive feedback hysteresis circuit 40. After the soft start circuit 100 is enabled, each circuit operates normally with bias.

[0076] At the same time, the enabling circuit 60 is used to implement the working state control of the soft start. When the enabling circuit 60 receives the first enabling signal EN in the first level state, the soft start circuit 100 stops working. When receiving the first enabling signal EN in the second level state, the soft start circuit 100 works normally.

[0077] In an alternative embodiment, if Figure 3 As shown, the bias circuit 50 includes a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, a twenty-ninth transistor M29, a thirtieth transistor M30 and a current source IBIAS;

[0078] The first end of the twenty-fourth transistor M24, the first end of the twenty-fifth transistor M25, the first end of the twenty-sixth transistor M26 and the first end of the twenty-seventh transistor M27 are connected to the positive power supply terminal VDD, the second end of the twenty-fourth transistor M24, the control end of the twenty-fourth transistor M24, the control end of the twenty-fifth transistor M25 and the first end of the current source IBIAS are connected to form a first voltage output end of the bias circuit 50 and are used to output a first bias voltage, the second end of the current source IBIAS is connected to the ground terminal GND, the second end of the twenty-fifth transistor M25, the first end of the twenty-ninth transistor M29, the control end of the twenty-ninth transistor M29 and the first end of the thirtieth transistor The control end of the transistor M30 is connected to form a fourth voltage output end of the bias circuit 50 and is used to output a fourth bias voltage. The control end of the twenty-seventh transistor M27, the second end of the twenty-seventh transistor M27 and the first end of the thirtieth transistor M30 are connected to form a second voltage output end of the bias voltage and are used to output a second bias voltage. The second end of the twenty-sixth transistor M26, the first end of the twenty-eighth transistor M28 and the control end of the twenty-eighth transistor M28 form a third voltage output end of the bias circuit 50 and are used to output a third bias voltage. The second end of the twenty-eighth transistor M28, the second end of the twenty-ninth transistor M29, the thirtieth transistor M30 and the ground terminal GND are connected.

[0079] The enabling circuit 60 includes a thirty-first transistor M31, a thirty-second transistor M32, a thirty-third transistor M33 and a third inverter INV3;

[0080] A first end of the thirty-first transistor M31 and a first end of the thirty-second transistor M32 are connected to the positive power supply terminal VDD, a second end of the thirty-first transistor M31 is connected to the first voltage output terminal of the bias circuit 50, a second end of the thirty-second transistor M32 is connected to the output terminal of the load amplifier circuit 22, a control end of the thirty-first transistor M31 and a control end of the thirty-second transistor M32 are connected to the input terminal of the third inverter INV3 and are used to input a first enable signal EN, a first end of the thirty-third transistor M33 is connected to the fourth voltage output terminal of the bias circuit 50, a control end of the thirty-third transistor M33 and a control end of the third transistor M3 are connected to the output terminal of the third inverter INV3 and are used to input a second enable signal ENN, and a second end of the thirty-third transistor M33 is connected to the ground terminal GND.

[0081] In this embodiment, when the soft start circuit 100 stops working, the enable circuit 60 receives a low-level first enable signal EN, the third inverter INV3 outputs a high-level second enable signal ENN, the thirty-first transistor M31, the thirty-second transistor M32, the thirty-third transistor M33 and the third transistor M3 are turned on, the soft start circuit 100 is in an off state, and no current flows through the circuit.

[0082] When the soft start circuit 100 is triggered to work, when the first enable signal EN is at a high level, the third inverter INV3 outputs a second enable signal ENN at a low level, the thirty-first transistor M31, the thirty-second transistor M32, the thirty-third transistor M33 and the third transistor M3 are turned off, the soft start circuit 100 is in a working state, current flows through the soft start circuit 100, and the soft start circuit 100 starts to work.

[0083] At the same time, the twenty-fourth transistor M24, the twenty-fifth transistor M25 and the twenty-sixth transistor M26 are biased on and provide a first bias voltage, the twenty-seventh transistor M27 is biased on and provides a second bias voltage, the twenty-eighth transistor M28 is biased on and provides a third bias voltage, and the twenty-ninth transistor M29 and the thirtieth transistor M30 are biased on and provide a fourth bias voltage.

[0084] Among them, based on the conduction state of each transistor at different levels, in an optional embodiment, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, the eighteenth transistor M18, the twenty-fourth transistor M24, the twenty-fifth transistor M25, the twenty-sixth transistor M26, the twenty-seventh transistor M27, the thirty-first transistor M31, and the thirty-second transistor M32 are PMOS transistors, and the remaining transistors are NMOS transistors.

[0085] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: the soft start circuit 100 includes a ramp voltage circuit 10, a differential input circuit 21, a load amplifier circuit 22, a switching circuit 30 and a positive feedback hysteresis circuit 40. When the soft start circuit 100 is powered on, the differential input circuit 21 outputs a first current signal, the load amplifier circuit 22 converts and outputs a first switching signal, the ramp voltage circuit 10 outputs a ramp voltage that changes and rises, and when the voltage difference between the reference voltage VREF0 and the rising ramp voltage reaches a preset difference, the differential input circuit 21 outputs a second current signal, and the negative feedback hysteresis circuit 40 outputs a first current signal. The load amplifier circuit 22 converts and outputs the second switching signal, and outputs it to the switching circuit 30 and the positive feedback hysteresis circuit 40. The positive feedback hysteresis circuit 40 increases the flipping speed of the second switching signal, so that the second switching signal quickly reaches the switching threshold of the switching circuit 30. Since the ramp voltage is less than the reference voltage VREF0 at this time, during the signal output delay period, even if the ramp voltage continues to rise, the soft start circuit 100 can be adjusted according to the signal delay time and the rising speed of the ramp voltage to ensure that the ramp voltage is less than the reference voltage VREF0 when the switching circuit 30 switches, thereby avoiding output overshoot during switching.

[0086] The present invention also provides a DC / DC converter, such as Figure 1 As shown, the DC / DC converter includes an error amplifier circuit 200, a PWM generation circuit 300, a switch circuit 400 and a soft start circuit 100. The specific structure of the soft start circuit 100 refers to the above embodiment. Since the DC / DC converter adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0087] Among them, the output end of the soft start circuit 100 is connected to the non-inverting input end of the error amplifier circuit 200, the inverting input end of the error amplifier circuit 200 is connected to the output end of the switch circuit 400, the output end of the error amplifier circuit 200 is connected to the input end of the PWM generation circuit 300, the output end of the PWM generation circuit 300 is connected to the control end of the switch circuit 400, and the input end of the switch circuit 400 is used to input the positive voltage VIN.

[0088] In this embodiment, VOUT1 represents the output voltage of the switching circuit 400. The error amplifier circuit 200 outputs a comparison signal based on the ratio of the feedback voltage Vfb to the received reference voltage VREF, and adjusts the duty cycle of the PWM modulation signal of the PMW generating circuit, thereby changing the on and off time of the switching circuit 400, thereby changing the output voltage VOUT1 of the switching circuit 400 to achieve DC conversion.

[0089] The error amplifier circuit 200 is an error amplifier, the non-inverting input terminal of the error amplifier is connected to the output terminal of the soft start circuit 100 , the inverting input terminal of the error amplifier is connected to the output terminal of the switch circuit 400 , and the output terminal of the error amplifier is connected to the input terminal of the PWM generation circuit 300 .

[0090] The PWM generation circuit 300 may adopt a signal generator, a clock circuit, etc., and output a PWM modulation signal with relevant changes based on the received comparison signal.

[0091] The switch circuit 400 may use a switch tube, such as a MOS tube, a triode, etc., and change the output voltage VOUT1 of the switch circuit 400 based on the received PWM modulation signal.

[0092] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A soft start circuit, characterized in that: include: A ramp voltage circuit, configured to output a ramp voltage that increases when receiving a first switching signal; A comparator circuit, the comparator circuit comprising a differential input circuit and a load amplifier circuit; The differential input terminals of the differential input circuit are respectively input with the ramp voltage and the reference voltage, and the differential input circuit is used to compare the ramp voltage with the reference voltage, and output a first current signal when the voltage difference between the reference voltage and the ramp voltage does not reach a preset difference, and switch to output a second current signal when the voltage difference between the reference voltage and the ramp voltage reaches a preset difference; The load amplifier circuit is connected to the differential input circuit and the ramp voltage circuit, and is used to amplify the first current signal and output a first switching signal, and to amplify the second current signal and output a second switching signal; a switching circuit, wherein the ramp voltage and the reference voltage are input to two voltage input terminals of the switching circuit respectively, the control terminal of the switching circuit is connected to the output terminal of the load amplifier circuit, and the switching circuit is used to switch to output the ramp voltage when the first switching signal is received or when the voltage of the second switching signal does not reach a preset voltage, and to switch to output the reference voltage when the voltage of the second switching signal reaches a preset voltage; A positive feedback hysteresis circuit is connected to the load amplifier circuit, and is used to obtain the second switching signal and positively feedback to increase the flipping speed of the second switching signal and provide a hysteresis amount to change the flipping threshold of the load amplifier circuit when the ramp voltage rises and falls.

2. The soft start circuit according to claim 1, characterized in that: The ramp voltage circuit includes a first transistor, a second transistor, a third transistor and a capacitor; The first transistor, the second transistor and the capacitor are connected in series in sequence and connected between a positive power supply terminal and a ground terminal, the third transistor is connected in parallel to both ends of the capacitor, a first bias voltage is input to the control terminal of the first transistor, the control terminal of the second transistor is connected to the output terminal of the load amplifier circuit, and a second enable signal is input to the control terminal of the third transistor.

3. The soft start circuit according to claim 2, characterized in that: The load amplifier circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor; The fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are sequentially connected in series and connected between the positive power supply terminal and the ground terminal. The eighth transistor, the ninth transistor, the tenth transistor and the eleventh transistor are sequentially connected in series and connected between the positive power supply terminal and the ground terminal. The connection node of the fourth transistor and the fifth transistor constitutes the first input terminal of the load amplifier circuit. The connection node of the eighth transistor and the ninth transistor constitutes the second input terminal of the load amplifier circuit. The connection node of the ninth transistor and the tenth transistor constitutes the output terminal of the load amplifier circuit. The connection node of the sixth transistor and the seventh transistor constitutes the third input terminal of the load amplifier circuit. The connection node of the tenth transistor and the eleventh transistor constitutes the fourth input terminal of the load amplifier circuit. The control terminal of the fourth transistor and the control terminal of the eighth transistor are used to input a first bias voltage. The control terminal of the fifth transistor and the control terminal of the ninth transistor are used to input a second bias voltage. The control terminal of the sixth transistor and the control terminal of the tenth transistor are used to input a third bias voltage. The connection node of the fifth transistor and the sixth transistor is also connected to the control terminal of the seventh transistor and the control terminal of the eleventh transistor.

4. The soft start circuit according to claim 3, characterized in that: The differential input circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor; The first end of the twelfth transistor is connected to the positive power supply terminal, the second end of the twelfth transistor, the first end of the thirteenth transistor and the first end of the fourteenth transistor are connected, the second end of the thirteenth transistor is connected to the third input terminal of the load amplifier circuit, the second end of the fourteenth transistor is connected to the fourth input terminal of the load amplifier circuit, the first end of the fifteenth transistor is connected to the first input terminal of the load amplifier circuit, the second end of the sixteenth transistor is connected to the second input terminal of the load amplifier circuit, the second end of the fifteenth transistor, the second end of the sixteenth transistor and the first end of the seventeenth transistor are connected, the second end of the seventeenth transistor is connected to the ground terminal, the control end of the twelfth transistor is used to input the first bias voltage, the control end of the thirteenth transistor and the control end of the fifteenth transistor are used to input the reference voltage, the control end of the fourteenth transistor and the control end of the sixteenth transistor are connected to the output end of the ramp voltage circuit, and the control end of the seventeenth transistor is used to input the fourth bias voltage; The width-to-length ratio of the thirteenth transistor is greater than the width-to-length ratio of the fourteenth transistor, and the width-to-length ratio of the fifteenth transistor is smaller than the width-to-length ratio of the sixteenth transistor.

5. The soft start circuit according to claim 3, characterized in that: The switching circuit includes a first inverter, a second inverter and a transmission gate; The input end of the first inverter is connected to the output end of the load amplifier circuit, the output end of the first inverter is connected to the input end of the second inverter, the input end of the transmission gate is used to input the reference voltage, the first control end of the transmission gate is connected to the output end of the first inverter, the second control end of the transmission gate is connected to the output end of the second inverter, and the output end of the transmission gate is connected to the output end of the ramp voltage circuit.

6. The soft start circuit according to claim 3, characterized in that: The positive feedback hysteresis circuit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor; The first end of the eighteenth transistor is connected to the positive power supply end, the second end of the eighteenth transistor, the control end of the nineteenth transistor and the first end of the twenty-third transistor are connected, the control end of the eighteenth transistor and the first end of the nineteenth transistor are connected to the output end of the load amplifier circuit, the second end of the nineteenth transistor is connected to the first end of the twentieth transistor, the second end of the twentieth transistor is connected to the first end of the twenty-first transistor, the second end of the twenty-first transistor is connected to the first end of the twenty-second transistor, the second end of the twenty-second transistor and the second end of the twenty-third transistor are connected to the ground end, and the control ends of the twentieth transistor, the twenty-first transistor, the twenty-second transistor and the twenty-third transistor are used to input a fourth bias voltage.

7. The soft start circuit according to claim 3, characterized in that: The soft start circuit also includes: A bias circuit, connected to the ramp voltage circuit, the differential input circuit, the load amplifier circuit and the positive feedback hysteresis circuit respectively, for providing a corresponding bias voltage; The enabling circuit is connected to the ramp voltage circuit, the differential input circuit and the load amplifier circuit respectively, and is used to control the soft start circuit to start or shut down according to a first enabling signal.

8. The soft start circuit according to claim 7, characterized in that: The bias circuit includes a twenty-fourth transistor, a twenty-fifth transistor, a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor and a current source; The first end of the twenty-fourth transistor, the first end of the twenty-fifth transistor, the first end of the twenty-sixth transistor and the first end of the twenty-seventh transistor are connected to the positive power supply terminal, the second end of the twenty-fourth transistor, the control end of the twenty-fourth transistor, the control end of the twenty-fifth transistor and the first end of the current source are connected to form a first voltage output end of the bias circuit and are used to output a first bias voltage, the second end of the current source is connected to the ground terminal, the second end of the twenty-fifth transistor, the first end of the twenty-ninth transistor, the control end of the twenty-ninth transistor and the control end of the thirtieth transistor are connected to form a fourth voltage output end of the bias circuit and are used to output a fourth bias voltage, the control end of the twenty-seventh transistor, the second end of the twenty-seventh transistor and the first end of the thirtieth transistor are connected to form a second voltage output end of the bias voltage and are used to output a second bias voltage, the second end of the twenty-sixth transistor, the first end of the twenty-eighth transistor and the control end of the twenty-eighth transistor constitute a third voltage output end of the bias circuit and are used to output a third bias voltage, and the second end of the twenty-eighth transistor, the second end of the twenty-ninth transistor and the thirtieth transistor are connected to the ground terminal.

9. The soft start circuit according to claim 8, characterized in that: The enabling circuit includes a thirty-first transistor, a thirty-second transistor, a thirty-third transistor and a third inverter; The first end of the thirty-first transistor and the first end of the thirty-second transistor are connected to the positive power supply end, the second end of the thirty-first transistor is connected to the first voltage output end of the bias circuit, the second end of the thirty-second transistor is connected to the output end of the load amplifier circuit, the control end of the thirty-first transistor and the control end of the thirty-second transistor are connected to the input end of the third inverter and are used to input the first enable signal, the first end of the thirty-third transistor is connected to the fourth voltage output end of the bias circuit, the control end of the thirty-third transistor and the control end of the third transistor are connected to the output end of the third inverter and are used to input the second enable signal, and the second end of the thirty-third transistor is connected to the ground end.

10. A DC / DC converter, characterized in that: The invention comprises an error amplifier circuit, a PWM generation circuit, a switch circuit and a soft start circuit as claimed in any one of claims 1 to 9, wherein the output end of the soft start circuit is connected to the non-phase input end of the error amplifier circuit, the inverting input end of the error amplifier circuit is connected to the output end of the switch circuit, the output end of the error amplifier circuit is connected to the input end of the PWM generation circuit, the output end of the PWM generation circuit is connected to the control end of the switch circuit, and the input end of the switch circuit is used to input a positive voltage.

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