Digital DC-DC controller, time domain modulator and analog-to-digital converter

Abstract

The invention discloses an all-digital multiphase DC-DC controller, a time domain modulator and an analog-to-digital converter. The digital DC-DC controller includes a time domain analog-to-digital converter for converting an analog domain signal into a digital domain signal so as to benefit from miniaturization of process progress without being limited by low voltage swings. In addition, the DC-DC controller also comprises a digital control circuit and a time domain modulator. The digital control circuit may control the time domain modulator in the digital domain, thereby reducing the effects caused by process, voltage, and temperature deviations. In addition, the time domain modulator can adjust the time sequence of a plurality of pulse width modulation signals, avoid circuit mismatching and further improve efficiency. Because the digital control circuit can be synthesized by a program language, the digital control circuit can be applied to any digital semiconductor process for implementation to reduce chip area.

Description

Technical Field

[0001] The present invention relates to a direct current-direct current (DC-DC) controller, and in particular to a fully digital multi-phase DC-DC controller. Background Art

[0002] Multiphase DC-DC converters that meet low voltage and high load current requirements have the following advantages: small size, high converter bandwidth, fast transient response, and low ripple. However, it is difficult to improve the efficiency of multiphase converters. Therefore, how to develop a DC-DC converter with higher efficiency has become a problem that needs to be solved.

[0003] This "Background" section provides background information only. Statements in this "Background" are not an admission that the subject matter disclosed in the "Background" of the present invention constitutes prior art to the present invention, and no part of the "Background" of the present invention is an admission that any part of this specification (including the discussion in the "Background") constitutes prior art to the present invention. Summary of the invention

[0004] One aspect of the present invention discloses a DC-DC controller, which is configured to generate N pulse width modulation (PWM) signals for converting an input voltage into an output voltage calibrated to a reference voltage, wherein N is an integer greater than 1. The DC-DC controller includes a first voltage-to-time converter (VTC), a second VTC, a third VTC, a digital control circuit, a sequential phase signal generator (SPSG), and a time domain modulator. The first VTC is configured to generate a first time domain signal corresponding to the input voltage. The second VTC is configured to generate a second time domain signal corresponding to the output voltage. The third VTC is configured to generate a third time domain signal corresponding to the reference voltage. The digital control circuit includes a multiplexer, a first time-to-digital converter (TDC), a second TDC, a symbol extractor, and a first successive approximation register (SAR) controller. The multiplexer is configured to determine the voltage segment of the reference voltage according to the first time domain signal and the third time domain signal, and generate N time period indication signals to indicate the time period of the falling edge of each PWM signal in the N PWM signals. The first TDC is coupled to the second VTC and configured to generate a first digital domain signal corresponding to the second time domain signal. The second TDC is coupled to the third VTC and configured to generate a second digital domain signal corresponding to the third time domain signal. The symbol extractor is configured to generate a comparison code indicating the relationship between the output voltage and the reference voltage according to the first digital domain signal and the second digital domain signal. The first SAR controller is configured to generate a first control code according to the comparison code. The sequence phase signal generator is configured to generate N phase signals, and the N phase signals have a duty cycle of the same width, and the frequency of the N phase signals is 1 / N times the frequency of the third time domain signal. The time domain modulator is configured to adjust the duty cycle of the N phase signals according to the N time period indication signals and the first control code to generate N PWM signals.

[0005] Another aspect of the present invention provides a time domain modulator for adjusting the duty cycle of N phase signals to generate N pulse width modulation (PWM) signals, wherein N is an integer greater than 1, and the duty cycles of the N phase signals have the same width. The time domain modulator includes an input duty cycle selector, at least one digital-to-time converter (DTC), and an output duty cycle selector. The input duty cycle selector is configured to generate N pulse signals according to the N phase signals and N time period indication signals, and combine the N pulse signals into a first combined pulse signal. The at least one DTC is coupled to the input duty cycle selector and configured to adjust the timing of the first combined pulse signal according to at least one control code to generate a second combined pulse signal. The output duty cycle selector is coupled to the at least one DTC and configured to generate N PWM signals according to the second combined pulse signal and the N time period indication signals. The N rising edges of the N PWM signals are determined by the N phase signals, and the N falling edges of the N PWM signals are determined by the second combined pulse signal generated by the at least one DTC.

[0006] Another aspect of the present invention provides an analog-to-digital converter (ADC) for converting a voltage domain signal into a digital domain signal. The ADC includes a voltage-to-time converter (VTC) and a time-to-digital converter (TDC). The VTC is configured to receive the voltage domain signal and generate a time domain signal corresponding to the voltage domain signal. The TDC is coupled to the VTC and configured to generate a digital domain signal related to the time domain signal received from the VTC.

[0007] The features and technical advantages of the present invention have been summarized in a fairly general manner above so that the following embodiments of the present invention can be better understood. Other features and technical advantages of the present invention will be described later and form the subject of the claims of this application. It should be understood by those skilled in the art that the disclosed concepts and specific embodiments can be used as a basis for modifying or designing other structures or processes for implementing the purposes of the present invention. It should also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the present invention as set forth in the claims. . BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the present invention may be obtained by referring to the embodiments and claims. In addition, the present invention may be understood in conjunction with the component symbols of the drawings, where the component symbols of the same drawings represent similar / same components throughout the specification.

[0009] Figure 1 is a schematic diagram of a DC-DC controller according to some embodiments of the present invention.

[0010] Figure 2 According to some embodiments of the present invention Figure 1 The timing diagram of the sequence phase signal generator is shown in FIG.

[0011] Figure 3 According to some embodiments of the present invention Figure 1 Schematic diagram of the sequence phase signal generator described herein.

[0012] Figure 4 The present invention provides a process for obtaining a PWM signal according to some embodiments of the present invention.

[0013] Figure 5 According to some embodiments of the present invention Figure 1 Schematic diagram of the internal time domain modulator.

[0014] Figure 6 According to some embodiments of the present invention Figure 1 Timing diagram of the internal time domain modulator.

[0015] Figure 7 FIG. 4 is a schematic diagram of an ADC according to some embodiments of the present invention.

[0016] Figure 8 FIG. 1 is a schematic diagram of a voltage-controlled oscillator (VCO) according to some embodiments of the present invention.

[0017] Fig. 9 According to some embodiments of the present invention Figure 8 Schematic diagram of each delay circuit in the circuit. DETAILED DESCRIPTION

[0018] This application claims priority to U.S. Patent No. 18 / 341,237, filed on June 26, 2023.

[0019] Specific language will now be used to describe the embodiments or examples of the invention illustrated in the accompanying drawings. It should be understood that no limitation of the scope of the invention is intended herein. Any changes or modifications to the described embodiments, and any further application of the principles described in this document, should be considered as would normally occur to one skilled in the art. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same component symbol.

[0020] It should be understood that although the words first, second, third, etc. are used herein to describe many components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited to these words. Instead, these words are only used to distinguish one component, part, region, layer, or section from other components, parts, regions, layers, or sections. Thus, without departing from the teachings of the present invention, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section.

[0021] The terms used herein are only used to illustrate the purpose of specific exemplary embodiments and are not intended to limit the inventive concept. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" also include plural forms. It should be understood that the terms "comprises" and "comprising" used in the specification indicate the presence of the stated features, wholes, steps, operations, components or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or groups thereof.

[0022] See also Figure 1 . Figure 1 1 is a schematic diagram of a DC-DC controller 100 according to some embodiments of the present invention. In this embodiment, the DC-DC controller 100 may be applied to an N-phase DC-DC converter 10, where N is an integer greater than 1. In the following, for the sake of simplicity, N may be 4; however, the present invention is not limited thereto. In this case, the DC-DC converter 10 includes output channels OC1 to OC4 and an output capacitor C OUT Each output channel OC1 to OC4 includes a driver, a switch, and an inductor. The DC-DC controller 100 may generate a pulse-width modulation (PWM) signal SIG PWM1 To SIG PWM4 , to control the different phases of the output channels OC1 to OC4, thereby converting the input voltage V in Converted to reference voltage V ref The target output voltage V out .

[0023] In some embodiments, the DC-DC controller 100 may be a buck controller, a boost controller, or a buck-boost controller. However, the present invention is not limited thereto. In addition, in some embodiments, the target reference voltage V refAccording to system requirements, the output voltage V out Can also change accordingly.

[0024] The DC-DC controller 100 may include a first voltage-to-time converter (VTC) 101 , a second VTC 102 , a third VTC 103 , a digital control circuit 110 , a sequential phased signal generator (SPSG) 130 , and a time-domain modulator 140 .

[0025] like Figure 1 As shown, the first VTC 101 can generate a voltage corresponding to the input voltage V in The time domain signal SIG vtin The second VTC 102 can generate an output voltage corresponding to V out The time domain signal SIG vtout The third VTC 103 can generate a voltage corresponding to the reference voltage V ref The time domain signal SIG vtref .

[0026] In some embodiments, VTCs 101, 102, and 103 can convert voltage domain signals (eg, input voltage V in , output voltage V out and reference voltage V ref ) is converted into a time domain signal (eg, a time domain signal SIG) having a frequency corresponding to the voltage domain signal. vtin , SIG vtout and SIG vtref ). For example, as the voltage domain signal becomes larger, VTCs 101, 102, and 103 may correspondingly generate time domain signals with higher frequencies. However, the present invention is not limited thereto.

[0027] The digital control circuit 110 can also convert the time domain signal into a digital domain signal so that the DC-DC controller 100 can generate an output voltage V out With reference voltage V ref ) performs signal processing and controls the PWM signal SIG accordingly PWM1 To SIG PWM4 Since the DC-DC controller 100 can be operated in the digital domain, it can benefit more from the trend of process scaling compared to conventional analog DC-DC controllers.

[0028] It is also worth noting that, with the trend of process advancement and miniaturization, the voltage value of the power supply will generally have a lower signal swing, which will also cause the signal-to-noise ratio (SNR) of the traditional analog-to-digital converter (ADC) to decrease. In particular, when the supply voltage drops below 1V or even lower, it becomes more challenging to improve the performance of the ADC. In addition, the low voltage makes the circuit design of the ADC complicated because it requires a finer sampling resolution. In order to avoid the difficulties encountered by the traditional ADC, the DC-DC controller 100 uses VTCs 101, 102 and 103 to convert the voltage domain signal into a time domain signal because the VTCs 101, 102 and 103 can improve the time resolution even at low supply voltages. In this case, the time domain signal can be easily further converted into a digital domain signal by the time digital converter, so that time domain analog-to-digital conversion can be achieved without being limited by the low voltage swing.

[0029] In this embodiment, the third VTC 103 can be used to generate a voltage according to the reference voltage V ref The generated time domain signal SIG vtref , as the PWM signal SIG PWM1 To SIG PWM4 Specifically, the sequence phase signal generator 130 can generate a basic signal according to the time domain signal SIG vtref Four phase signals PH1 to PH4 are generated. The phase signals PH1 to PH4 have the same frequency, which is the frequency of the time domain signal SIG. vtref 1 / N times the frequency of the time domain signal SIG vtref 1 / 4 of the frequency) and have a duty cycle of the same width.

[0030] Figure 2 is a timing diagram of the sequence phase signal generator 130 according to some embodiments of the present invention. In this embodiment, the sequence phase signal generator 130 may be based on a reference voltage V ref The generated time domain signal SIG vtref , to generate four phase signals PH1, PH2, PH3 and PH4.

[0031] Figure 3 FIG. 1 is a schematic diagram of a sequence phase signal generator 130 according to some embodiments of the present invention. Figure 3As shown, the sequence phase signal generator 130 may include a phase signal generator (PSG) 131 and N D flip-flops (DFFs) 132 (i.e., four DFFs 132 for N=4). The phase signal generator 131 may include (N-1) DFFs 133 (i.e., three DFFs 133 for N=4) and a NOR gate 134.

[0032] In the phase signal generator 131, each DFF 133 includes a clock terminal, a data terminal and an output terminal, and the clock terminal of each DFF 133 can be configured to receive the time domain signal SIG vtref The output terminal of the Mth DFF 133 is coupled to the data terminal of the (M+1)th DFF 133, where M is an integer less than (N-1). For example, the output terminal of the first DFF 133 is coupled to the data terminal of the second DFF 133, and the output terminal of the second DFF 133 is coupled to the data terminal of the third DFF 133.

[0033] The NOR gate 134 in the phase signal generator 131 may include an (N-1) input terminal coupled to the (N-1) output terminals of the (N-1) DFFs 133 and an output terminal coupled to the data terminal of the first DFF 133 (ie, the leftmost DFF 133).

[0034] In addition, the sequence phase signal generator 130 further includes N DFFs 132, which are used to prevent combinational logic errors caused by noise. The N DFFs 132 are configured to output phase signals PH1 to PH4. Each of the N DFFs 132 may include a clock terminal, a data terminal, and an output terminal, wherein the clock terminal of each DFF may be configured to receive the time domain signal SIG vtref .

[0035] like Figure 3 As shown, the data terminal of the Kth DFF 132 is coupled to the data terminal of the Kth DFF 133 in the phase signal generator 131, where K is an integer less than N. For example, the data terminal of the 1st DFF 132 is coupled to the data terminal of the 1st DFF 133, and the data terminal of the 2nd DFF 132 is coupled to the data terminal of the 2nd DFF 133. Moreover, the data terminal of the Nth DFF 132 (i.e., the last DFF 132) is coupled to the output terminal of the (N-1)th DFF 133 (i.e., the last DFF 133) in the phase signal generator 131. The output terminals of the N DFFs 132 can output phase signals PH1 to PH4, respectively.

[0036] In this embodiment, when N=4, each of the four phase signals PH1 to PH4 has a time domain signal SIG vtref Frequency F ref In other words, if T represents the time domain signal SIG vtref The complete cycle (i.e. T = 1 / F ref ), the phase signal PH1 will have a logic high voltage during the duration from 0 to T / 4, the phase signal PH2 will have a logic high voltage during the duration from T / 4 to T / 2, the phase signal PH3 will have a logic high voltage during the duration from T / 2 to 3T / 4, and the last phase signal PH4 will have a logic high voltage during the duration from 3T / 4 to T. That is, Figure 2 As shown, each of the phase signals PH1 to PH4 has a duty cycle of 25%.

[0037] In this embodiment, the timing of the rising edges of the phase signals PH1 to PH4 can be used to determine the PWM signals SIG. PWM1 To SIG PWM4 The rising edge timing of the PWM signal SIG PWM1 To SIG PWM4 The timing of the falling edge of the output voltage V can be determined by the time domain modulator 140 according to the pulse signal corresponding to the phase signals PH1 to PH4. That is, in this embodiment, by determining the timing of the rising edge and the falling edge, the output voltage V out Close to the reference voltage V ref The PWM signal SIG PWM1 To SIG PWM4 waveform.

[0038] Figure 4 According to some embodiments of the present invention, a PWM signal SIG is obtained. PWM1 To SIG PWM4 Process 20. Figure 4 As shown, the process 20 may include four procedures 200 , 202 , 204 , and 206 .

[0039] In this embodiment, the multiplexer selector (MUX selector) 114 can determine the reference voltage V in the process 200. ref Compared to the input voltage V in Therefore, in process 202, the time domain modulator 140 can further determine the PWM signal SIG PWM1 To SIG PWM4 The period of time where the falling edge of

[0040] like Figure 2 As shown, each cycle of the phase signals PH1 to PH4 can be divided into four equal time periods. For example, there are four time periods in the cycle of the phase signal PH1: 0 to T / 4, T / 4 to 2T / 4, 2T / 4 to 3T / 4, 3T / 4 to T. Therefore, the input voltage V in Can be divided into four equal voltage sections. At this time, if the input voltage V in If the voltage is 3.3V, the four voltage segments between 0V and 3.3V can be defined by using voltages of 0.825V, 1.65V and 2.475V.

[0041] For example, if the reference voltage V ref If it is greater than 2.475V (3 / 4 of 3.3V), it means the reference voltage V ref is quite close to the input voltage Vin, so the PWM signal SIG PWM1 To SIG PWM4 The duty cycle of the PWM signal SIG should also be greater than 75% to maintain the inductor charging for a longer time. PWM1 The falling edge of should be located at a certain time point in the fourth period between 3T / 4 and T. Alternatively, if the reference voltage V ref is less than 0.825V, it means that the reference voltage V ref is less than one quarter of the input voltage Vin, so the PWM signal SIG PWM1 The falling edge of should be located at a certain time point in the first period between 0 and T / 4. ref The same principle can also be applied to determine the PWM signal SIG when the voltage is between 0.825V and 1.65V or between 1.65V and 2.475V. PWM1 The period of time where the falling edge of

[0042] like Figure 1 As shown, the digital control circuit 110 includes a first divider 121 and a multiplexer selector 114. The first divider 121 may be coupled to the first VTC 101, and may be configured to convert the time domain signal SIG vtin Divided by a first number (eg, 64) to generate a first clock signal SIG CLK1 In some embodiments, the first divider 121 may be implemented by a counter. However, the present invention is not limited thereto.

[0043] The multiplexer 114 may receive the time domain signal SIG vtref and the first clock signal SIG CLK1 To determine the reference voltage V refThe voltage segment of the PWM signal SIG is generated to generate interval indication signals S1 to SN (N=4) to indicate the voltage segment of the PWM signal SIG. PWM1 To SIG PWMN The period of time where the falling edge of

[0044] In some embodiments, the first clock signal SIG CLK1 Estimate a fixed time and use a counter to count how many time domain signals SIG have passed within the fixed time. vtref The third VTC 103 has set the reference voltage V ref Converted into time domain signal SIG vtref , and make the time domain signal SIG vtref The frequency and reference voltage V ref proportional to, therefore, the time domain signal SIG vtref The number of pulses that pass during a fixed time period can reflect the reference voltage V ref , which can be used to determine the voltage segment. For example, the numbers 128, 256, and 384 can be used to determine the reference voltage V ref In this case, when the number of pulses is less than 128, the multiplexer selector 114 may determine the reference voltage V ref The voltage segment is the first quarter interval, so the PWM signal SIG PWM1 The falling edge of should be located at the period between 0 and T / 4. When the number of pulses is greater than 128 and less than 256, the multiplexer 114 can determine the reference voltage V ref The voltage segment is the second quarter interval, so the PWM signal SIG PWM1 The falling edge of should be located at the period between T / 4 and 2T / 4. In addition, when the number of pulses is greater than 256 and less than 384, the multiplexer selector 114 can determine the reference voltage V ref The voltage segment is the third quarter interval, so the PWM signal SIG PWM1 The falling edge of should be located at the period between 2T / 4 and 3T / 4. When the number of pulses is greater than 384, the multiplexer 114 can determine the reference voltage V ref The voltage segment is the fourth quarter interval, so the PWM signal SIG PWM1 The falling edge of SIG should be located at the time period between 3T / 4 and T. However, the present invention is not limited thereto. In some other embodiments, the multiplexer selector 114 can also determine the PWM signal SIG in other ways. PWM1 To SIG PWM4 The period in which the falling edge of each PWM signal lies.

[0045] In addition, in order to allow the time domain modulator 140 to select the voltage segment in a simpler manner, the multiplexer selector 114 can generate four PWM signals SIG corresponding to the pulse number counted within a fixed time. PWM1 To SIG PWM4 The time period indication signals S1 to S4.

[0046] In this embodiment, each of the time period indication signals S1 to S4 can be represented by 2 bits. ref The voltage segment represents the PWM signal SIG PWM1 The falling edge of the reference voltage V ref The voltage segment represents the PWM signal SIG PWM1 If the falling edge of is located at an interval between T / 4 and 2T / 4 (overlapping with the pulse of the phase signal PH2), the period indication signal S1 may be "01", and so on.

[0047] In addition, since the PWM signal SIG PWM1 To SIG PWM4 have the same pulse width, so once the reference voltage V is determined ref The voltage segment of the time period indication signal S1 can be determined, and the remaining time period indication signals S2 to S4 can also be determined accordingly. In this embodiment, the time period indication signals S1 to S4 can be generated in a sequence. For example, if the time period indication signal S1 is "00", the time period indication signals S2, S3 and S4 will be "01", "10" and "11" respectively. Similarly, if the time period indication signal S1 is "10", the time period indication signals S2, S3 and S4 will be "11", "00" and "01" respectively.

[0048] According to the time period indication signal generated by the multiplexer selector 114, the time domain modulator 140 can roughly locate the PWM signal SIG PWM1 To SIG PWM4 The falling edge of

[0049] Then, in process 202, the PWM signal SIG can be further accurately located. PWM1 To SIG PWM4 The falling edge of the output voltage V out Can approach the reference voltage V ref , thereby achieving an output voltage V out Following the reference voltage V ref goal.

[0050] That is, in process 202, the purpose of the DC-DC controller 100 is to adjust the output voltage V out To match the reference voltage V ref , so that the output voltage V out Finally, it can be equal to or close enough to the reference voltage V ref To achieve this goal, the digital control circuit 110 may include a first time-to-digital converter (TDC) 111 , a second TDC 112 , a sign extractor 113 , and a first successive approximate register (SAR) controller 115 .

[0051] In this embodiment, the first SAR controller 115 can output the voltage V out and reference voltage V ref The control code is used to adjust (for example, advance or delay) the PWM signal SIG. PWM1 To SIG PWM4 The falling edge of the out With reference voltage V ref match.

[0052] In this embodiment, the first TDC 111 is coupled to the second VTC 102 and is configured to generate a time domain signal SIG corresponding to the time domain signal generated by the second VTC 102. vtout Digital domain signal DV out The second TDC 112 is coupled to the third VTC 103 and is configured to generate a time domain signal SIG corresponding to the time domain signal generated by the third VTC 103. vtref Digital domain signal DV ref .

[0053] In this embodiment, the first TDC 111 may include a counter, and may be configured to generate a counter by processing the time domain signal SIG vtout The number of pulses is counted to obtain the digital domain signal DV out , and does not need to refer to any clock signal. Similarly, the second TDC 112 may include a counter, and may vtref The number of pulses is counted to obtain the digital domain signal DV ref , without reference to any clock signal. That is, in this embodiment, the first TDC 111 together with the second VTC 102 (or the second TDC 112 together with the third VTC 103) can be regarded as a time domain analog-to-digital converter. In this case, the digital domain signal DV out and DVref The value of the output voltage V out and reference voltage V ref , which can be used to indicate the reference voltage V ref and output voltage V out The relationship between.

[0054] The symbol extractor 113 is configured to extract the digital signal DV out and DV ref The value of the output voltage V out and reference voltage V ref The comparison code e[k] may include only a single bit whose value is 0 or 1, and the single bit may also be a digital domain signal DV. ref The value of the digital domain signal DV is subtracted out The value of the sign bit is generated to indicate the output voltage V out and reference voltage V ref The size relationship.

[0055] The first SAR controller 115 is configured to generate a first control code SAR according to the comparison code e[k] C [k], to adjust the PWM signal SIG PWM1 To SIG PWM4 More specifically, when the reference voltage V ref Higher than the output voltage V out The digital domain signal DV ref The value is greater than the digital domain signal DV out When the value of (for example but not limited to e[k]=0), the first SAR controller 115 may generate a SAR control code SAR C [k], to increase the duty cycle of the PWM signal, when the reference voltage V ref Lower than the output voltage V out The digital domain signal DV ref The value is less than the digital domain signal DV out When the value of (for example but not limited to e[k] = 1), another SAR control code SAR is generated C [k] to reduce the duty cycle of the PWM signal.

[0056] In some embodiments, the digital control circuit 110 may further include a second divider 122. The second divider 122 may be coupled to the first VTC 101 and may be configured to generate a second divider 122 according to the time domain signal SIG. vtin Generate a second clock signal SIG CLK2 In this embodiment, the second divider 122 may be implemented by a counter, and may be configured to divide the time domain signal SIG by vtin Frequency Fin Divide by a second number (eg, 512) to generate a second clock signal SIG CLK2 That is, the second clock signal SIG CLK2 The frequency of the time domain signal SIG vtin 1 / 512 of the clock signal SIG, and the first SAR controller 115 may receive the second clock signal SIG CLK2 In some embodiments, the first divider 121 can be reused to generate the clock signal SIG CLK1 and SIG CLK2 In this case, the second divider 122 may be omitted to reduce the hardware components required for the DC-DC controller 100 .

[0057] In some embodiments, the digital control circuit 110 may further include a second SAR controller 116. The second SAR controller 116 may generate a more refined SAR control code SAR according to the comparison code e[k]. F [k], to further adjust the PWM signal SIG in a more refined manner PWM1 To SIG PWM4 The falling edge of the PWM signal SIG is adjusted more accurately. PWM1 To SIG PWM4 That is, the digital control circuit 110 can adjust the PWM signal SIG through two-stage adjustment. PWM1 To SIG PWM4 The duty cycle of the SAR controller 115 is roughly adjusted in the first stage and the second SAR controller 116 is finely adjusted in the second stage.

[0058] For example, when the first SAR controller 115 obtains the coarse SAR control code SAR C [k], the SAR control code SAR C [k] is fed into the time domain modulator 140 to adjust the PWM signal SIG PWM1 To SIG PWM4 , so adjust the output voltage V out After that, in order to further obtain the fine-tuning SAR control code SAR F [k], the SAR control code SAR C [k] minus one unit, that is, one least significant bit (LSB). For example, if the control code SAR C [k] corresponds to the value 53, then the control code SAR C The updated SAR code after [k]-1 (i.e., 52) is fed into the time domain modulator 140. In this case, the output voltage V outwill be reduced accordingly, and the second SAR controller 116 can receive the updated comparison code e[k] and generate the fine adjustment control code SAR according to the updated comparison code e[k]. F [k] In this embodiment, the coarse control code SAR C [k] The time adjustment unit that can be adjusted is greater than the fine-tuning control code SAR F [k] The time adjustment unit that can be adjusted. In addition, in some embodiments, the coarse adjustment control code SAR C [k] The time adjustment unit that can be adjusted can be less than or equal to the fine-tuning control code SAR F [k] controllable full adjustment time. Therefore, by using fine-tuning control code SAR F [k], the output voltage V can be adjusted with higher resolution out Since the second SAR controller 116 can provide a higher resolution, the limit-cycling condition of the ADC can be avoided.

[0059] Although the digital control circuit 110 includes two SAR controllers 115 and 116, respectively, for adjusting the PWM signal SIG with different resolutions. PWM1 To SIG PWM4 In some other embodiments, two-stage adjustment can be implemented by repeatedly using one SAR controller 115 or 116. In addition, in some embodiments, only one-stage adjustment can be performed according to system requirements. In addition, the control code SAR C [k] and control code SAR F [k] may include the same number of bits. For example, the control code SAR C [k] and control code SAR F [k] may include 6 bits. However, the present embodiment is not limited thereto. In some embodiments, the control code SAR C The number of bits of [k] can be compared with the control code SAR F The number of digits of [k] may be the same or different.

[0060] Figure 5 is a schematic diagram of a time domain modulator 140 according to some embodiments of the present invention, and Figure 6 FIG. 1 is a timing diagram of the time domain modulator 140 according to some embodiments of the present invention. The time domain modulator 140 may include an input duty selector 141, digital-to-time converters (DTCs) 142C and 142F, and an output duty selector 143.

[0061] The input duty ratio selector 141 may include N input channel units, namely, input channel units 1411 to 1414. Each of the input channel units 1411 to 1414 includes a multiplexer MUX1, a multiplexer MUX2, a pulse generator PG1, and a buffer BF1.

[0062] In this embodiment, after the multiplexer 114 determines the voltage segment and generates the corresponding period indication signals S1 to S4, the period indication signals S1 to S4 are respectively output to the multiplexers MUX1 and MUX2 of the input channel units 1411 to 1414, thereby generating a transparent window that facilitates the reuse of the DTCs 142C and 142F. In some embodiments, if only one-stage SAR control is used for adjustment (i.e., only the coarse SAR controller 115 is used), the DTC 142F can be omitted. In this case, the time domain modulator 140 can include only one DTC.

[0063] In this embodiment, if the time period indication signals S1 to S4 are "10", "11", "00" and "01", the multiplexer MUX1 of the input channel unit 1411 will select the phase signal PH3, the multiplexer MUX1 of the input channel unit 1412 will select the phase signal PH4, the multiplexer MUX1 of the input channel unit 1413 will select the phase signal PH1, and the multiplexer MUX1 of the input channel unit 1414 will select the phase signal PH2.

[0064] The pulse generators PG1 in the input channel units 1411 to 1414 are respectively coupled to the multiplexers MUX1 in the input channel units 1411 to 1414, and are configured to generate pulse signals PL1 to PL4 corresponding to the phase signals PH1 to PH4. The pulse widths of the pulse signals PL1 to PL4 are shorter than the pulse widths of the phase signals PH1 to PH4. That is, the pulse generator PG1 can shorten the pulse widths of the phase signals PH1 to PH4. Since the pulse signals PL1 to PL4 have shorter pulses and are maintained at a logic high voltage only for a shorter period of time, the power consumption of the time domain modulator 140 can be reduced.

[0065] Each buffer BF1 includes an input terminal configured to receive a pulse signal from a corresponding pulse generator PG1 , a control terminal configured to receive a phase signal selected by a corresponding multiplexer MUX2 , and an output terminal coupled to an input terminal of the DTC 142C.

[0066] In this embodiment, the multiplexer MUX2 can receive the same period indication signals S1 to S4 as the multiplexer MUX1, and thus can generate corresponding windows for the pulse signals PL1 to PL4 to pass through the buffer BF1. Figure 6 As shown, the buffer BF1 of the input channel unit 1411 can output the pulse signal PL1 during the conduction time of the phase signal PH3. Similarly, the buffer BF1 of the input channel unit 1412 can output the pulse signal PL2 during the conduction time of the phase signal PH4, the buffer BF1 of the input channel unit 1413 can output the pulse signal PL3 during the conduction time of the phase signal PH1, and the buffer BF1 of the input channel unit 1414 can output the pulse signal PL4 during the conduction time of the phase signal PH2. In this embodiment, the conduction time of a signal refers to the time during which the signal remains at a logic high voltage.

[0067] In this way, the pulse signals PL1 to PL4 can be combined into a combined pulse signal SIG CP1 , and processed by DTC142C and 142F. Figure 6 As shown, according to the combined pulse signal SIG received by DTC 142C CP1 , the DTC 142C may receive a pulse corresponding to the pulse signal PL1 during the on-time of the phase signal PH3. Similarly, the DTC 142C may receive a pulse corresponding to the pulse signal PL2 during the on-time of the phase signal PH4, a pulse corresponding to the pulse signal PL3 during the on-time of the phase signal PH1, and a pulse corresponding to the pulse signal PL4 during the on-time of the phase signal PH2.

[0068] DTC 142C adjustable combined pulse signal SIG CP1 The waveform timing is used to generate another combined pulse signal SIG CPA For example, DTC 142C may adjust the SAR control code SAR according to the coarse SAR control code SAR C [k] Adjust the combined pulse signal SIG CP1 Therefore, the combined pulse signal SIG CP1 The pulse timing of the DTC 142C can be adjusted to generate a combined pulse signal SIG CPA Similarly, DTC 142F can adjust the SAR control code SAR according to the fine adjustment SAR F [k] Adjust the combined pulse signal SIG CPA Therefore, the combined pulse signal SIG CPA The pulse timing of the DTC 142F can be further adjusted to generate a combined pulse signal SIG CP2In this case, the DTCs 142C and 142F can be reused at different time periods to adjust different pulse signals PL1 to PL4, thereby reducing the hardware required for the time domain modulator 140 and ensuring that the phase signals PH1 to PH4 are adjusted equally.

[0069] The DTCs 142C and 142F adjust the pulses of the phase signals PH1 to PH4 and generate a combined pulse signal SIG CP2 Afterwards, the output duty cycle selector 143 can convert the combined pulse signal SIG CP2 Divided into four PWM signals SIG PWM1 To SIG PWM4 .

[0070] The output duty cycle selector 143 includes N output channel units, namely, output channel units 1431 to 1434, which are respectively used to generate PWM signals SIG PWM1 To SIG PWM4 Each of the output channel units 1431 to 1434 includes a multiplexer MUX3, a buffer BF2, and a D-type flip-flop (D flip-flop, DFF) DF1.

[0071] Each multiplexer MUX3 is configured to select a phase signal from the phase signals PH1 to PH4 according to a corresponding one of the period indication signals S1 to S4.

[0072] Each buffer BF2 includes an input terminal, a control terminal, and an output terminal, wherein the input terminal is configured to receive the combined pulse signal SIG generated by the DTCs 142C and 142F. CP2 The control end is configured to receive the phase signal selected by the multiplexer MUX3, and the output end is configured to output the combined pulse signal SIG during the conduction time of the phase signal selected by the multiplexer MUX3. CP2 as a part of the DFF DF1 reset signal.

[0073] For example, the multiplexer MUX3 of the output channel unit 1431 may select the third phase signal PH3 according to the period indication signal S1. In this case, the combined pulse signal SIG CP2 The buffer BF2 can only be passed during the conduction period of the third phase signal PH3 in the output channel unit 1431. Similarly, the multiplexer MUX3 of the output channel unit 1432 can select the fourth phase signal PH4 according to the period indication signal S2, so that the combined pulse signal SIG CP2The buffer BF2 can only be passed during the on-time of the fourth phase signal PH4 in the output channel unit 1432. That is, the multiplexer MUX3 and the buffer BF2 in the output channel units 1431 to 1434 can be used to select the pulses of the corresponding phase signals PH1 to PH4 after adjustment.

[0074] The DFF DF1 in each output channel unit 1431 to 1434 includes a data terminal, a clock terminal, a reset terminal and an output terminal, wherein the data terminal is coupled to a logic high potential VDD, the clock terminal is configured to receive a corresponding phase signal, the reset terminal is configured to receive a reset signal output by a buffer BF2, and the output terminal is configured to output a PWM signal.

[0075] In this case, DFF DF1 can generate a PWM signal SIG PWM1 To SIG PWM4 , which has a rising edge determined by the clock signal (i.e., a corresponding phase signal among the phase signals PH1 to PH4) and a falling edge determined by the reset signal output by the buffer BF2. Figure 6 As shown, the PWM signal SIG generated by the DFF DF1 of the output channel unit 1431 PWM1 The rising edge of the phase signal PH1 may be triggered. In addition, in the present embodiment, since the reset terminal of the DFF DF1 is active low, an inverter may be added to invert the reset signal output by the buffer BF2. In this case, when the reset signal (i.e., the combined pulse signal SIG CP2 When the phase signal PH3 is at a logic high voltage during the on-time, the DFF DF1 of the output channel unit 1431 will be transmitted and will pull down the PWM signal SIG. PWM1 , thereby generating a PWM signal SIG PWM1 However, the present invention is not limited thereto. In some other embodiments, according to the design and system requirements, the reset terminal of DFF DF1 may be active high, and the inverter may be omitted.

[0076] In this embodiment, the time domain modulator 140 can generate four phase PWM signals SIG by using the same loop instead of four independent loops. PWM1 To SIG PWM4 , thus avoiding the problem caused by circuit mismatch between different loop circuits. In addition, by using digital control to control the PWM signal SIG PWM1 To SIG PWM4, and can also eliminate the adverse effects caused by process, voltage and temperature variations (PVT variations).

[0077] Furthermore, in some embodiments, the time domain modulator 140 may also be used by other applications to perform signal modulation.

[0078] When the output voltage V out Close to the reference voltage V ref Afterwards, the DC-DC controller 100 may execute a program 204 to calibrate the time domain signal SIG through a frequency-locked loop (FLL) technique between the second VTC 102 and the third VTC 103. vtout Frequency F out With the time domain signal SIG vtref Frequency F ref In this embodiment, the digital control circuit 110 may further include a third SAR controller 117, which is used to generate a control code according to the comparison code e[k] obtained by the symbol extractor 113. The control code may be output to the second VTC 102 to control the capacitor bank in the second VTC 102. By adjusting the capacitor bank, the frequency of the second VTC 102 can be adjusted. In this way, a frequency locked loop can be implemented, and the output voltage V out Equal to the reference voltage V ref When the frequency F out Can be equal to frequency F ref .

[0079] In this embodiment, the third SAR controller 117 can be used to generate a control code for controlling at least one capacitor bank of the second VTC 102; however, the embodiment is not limited thereto. In some embodiments, the first SAR controller 115 can be reused to perform frequency offset calibration, so that the third SAR controller 117 can be omitted to reduce the hardware components required for the DC-DC controller 100.

[0080] When the frequency offset calibration is completed, that is, when the frequency F out Equal to frequency F ref , the process 206 can be performed to perform background calibration, so that the output voltage V out It can also adjust the output voltage V in transient state. outIn this embodiment, the digital control circuit 110 can adjust the control code input to the DTC 142C and 142F of the time domain modulator 140 to perform background calibration, thereby achieving fast transient response and load regulation.

[0081] like Figure 1 As shown, the digital control circuit 110 may further include an adder 123 and a code modification unit (CMU) 124. The adder 123 may be coupled to the first TDC 111 and the second TDC 112, and may be configured to convert the digital domain signal DV ref The value of the digital domain signal DV is subtracted out The value of D is used to generate the digital code e [k], and CMU 124 can be based on the digital code D e [k] to perform background calibration, modifying the control code received by the DTCs 142C and 142F of the time domain modulator 140 to adjust the output voltage V in steady state and / or transient state out It is worth noting that the CMU 124 can be configured to generate a digital signal according to the digital code D in a steady state and / or transient state. e [k], control code SAR C [k] and control code SAR F [k] to perform background calibration and control the control codes received by DTCs 142C and 142F.

[0082] In addition, the control code SAR is obtained in steady state and / or transient state C [k] and SAR F [k] After that, if CMU124 detects the digital code D e [k] is greater than a first critical value (e.g., 2), which means that the reference voltage V ref Higher than the output voltage V out , then CMU 124 can e [k] Added to control code SAR C [k] and / or control code SAR F [k], to increase the control code received by the time domain modulator 140, so that the DTC 142C and / or 142F will further increase the PWM signal SIG PWM1 To SIG PWM4 duty cycle in order to increase the output voltage V out In addition, if the digital code D e [k] is less than the second critical value (e.g. -2), which means that the reference voltage V ref Lower than the output voltage V out , then CMU 124 cane [k] Added to control code SAR C [k] and / or SAR F [k] (i.e., from the control code SAR C [k] and / or SAR F Subtract the digital code D from [k] e [k] absolute value), to reduce the control code received by the time domain modulator 140, thus reducing the PWM signal SIG PWM1 To SIG PWM4 duty cycle, thereby reducing the output voltage V out .

[0083] In addition, as described above, the combination of the second VTC 102 and the first TDC 111 and the combination of the third VTC 103 and the second TDC 112 can be regarded as a time domain ADC. In some embodiments, in addition to the DC-DC controller 100, this time domain ADC can also be used in other low voltage applications. The structure of the time domain ADC is further described below.

[0084] Figure 7 3 is a schematic diagram of an ADC 30 according to some embodiments of the present invention. The ADC 30 includes a VTC 32 and a TDC 34 coupled to the VTC 32. In some embodiments, the VTC 32 may be the same as the second VTC 102 (or the third VTC 103) of the DC-DC controller 100, and the TDC 34 may be the same as the first TDC 111 (or the second TDC 112) of the DC-DC controller 100. The VTC 32 is configured to convert the voltage domain signal SIG V Convert to time domain signal SIG T , and TDC 34 is configured to convert the time domain signal SIG T Convert to digital domain signal SIG D .

[0085] In some embodiments, the VTC 32 may include a voltage controlled oscillator (VCO) for generating a voltage-controlled oscillator according to the received voltage domain signal SIG. V To adjust the time domain signal SIG T frequency. Figure 8 3 is a schematic diagram of a VCO 320 according to some embodiments of the present invention. In this embodiment, the VTC 32 may include the VCO 320, and the VCO 320 may include a plurality of delay stages 3301 to 3304 and a plurality of capacitor groups 3401 to 3403. The plurality of capacitor groups 3401 to 3403 are coupled between the plurality of delay stages 3301 to 3304, and may be configured to generate a plurality of capacitor groups according to the SAR code C. e[k] Adjust the frequency of VCO 320. In the present embodiment, VCO 320 is a ring oscillator including four differential delay circuits, however, the present invention is not limited thereto. For example, in some embodiments, VCO 320 may omit delay circuit 3301 and capacitor group 3401. In this case, the positive input terminal of delay circuit 3302 may be coupled to the negative output terminal of delay circuit 3304, and the negative input terminal of delay circuit 3302 may be coupled to the positive output terminal of delay circuit 3304. In addition, in some embodiments, depending on the needs of the system, if one capacitor group is sufficient for frequency adjustment, VCO 320 may also include only one capacitor group without including multiple capacitor groups. It should be noted that the above-mentioned architecture of VCO 320 is for illustrative purposes only and is not intended to limit the scope of the present invention. That is, other VCO circuit structures may be used to implement Figure 7 The VTC 32 shown may be modified without departing from the spirit of the present invention.

[0086] Fig. 9 FIG. 3 is a schematic diagram of a delay circuit 3301 according to some embodiments of the present invention. In this embodiment, the delay circuits 3302 to 3304 may have the same structure as the delay circuit 3301. Fig. 9 As shown, the delay circuit 3301 may include transistors M1, M2, M3, M4, M5 and M6.

[0087] The transistor M1 includes a first terminal coupled to the current source 332 and configured to output a first output voltage V out- to the second terminal of the next delay circuit 3302, and is configured to receive an input voltage V in+ The transistor M2 includes a first terminal coupled to the current source 332 and configured to output a second output voltage V out+ to the second terminal of the next delay circuit 3302, and is configured to receive an input voltage V in- In this embodiment, the current source 332 may be included in the delay circuit 3301 and may be coupled to the supply voltage VDD of the VCO. However, in some other embodiments, the current source 332 may be disposed outside the delay circuit 3301.

[0088] The transistor M3 includes a first terminal coupled to the second terminal of the transistor M1, a second terminal configured to receive a ground voltage (ie, coupled to ground), and a second terminal configured to receive the voltage domain signal SIG. V The transistor M4 includes a first terminal coupled to the second terminal of the transistor M2, a second terminal configured to receive a ground voltage, and a second terminal configured to receive a voltage domain signal SIG. V control terminal.

[0089] The transistor M5 includes a first terminal coupled to the second terminal of the transistor M1, a second terminal configured to receive a ground voltage, and a control terminal configured to be coupled to the second terminal of the transistor M2. The transistor M6 includes a first terminal coupled to the second terminal of the transistor M2, a second terminal configured to receive a ground voltage, and a control terminal coupled to the second terminal of the transistor M1.

[0090] In this embodiment, transistors M3 and M4 allow the voltage domain signal SIG V Has a wider voltage range, such as the voltage domain signal SIG V The voltage swing of the voltage domain signal SIG may be higher than the supply voltage VDD of the VCO. In some embodiments, the transistors M3 and M4 may be high-voltage transistors with thicker gate oxides to withstand higher voltages. In this case, although the supply voltage VDD of the VCO may be 1.8V, the voltage domain signal SIG V The voltage of can be in the range of 0V to 3.3V. In this way, the supply voltage VDD of the VCO can be maintained at a lower voltage to reduce power consumption.

[0091] In this embodiment, the capacitance value of each capacitor group in the plurality of capacitor groups 340 can be adjusted. When the VCO 320 is used in the second VTC 102 of the DC-DC controller 100, the capacitor group 340 can be controlled by the SAR code C generated by the third SAR controller 117. e [k] Control. By adjusting the capacitance of capacitor bank 340, the frequency of VCO 320 can also be adjusted.

[0092] In some embodiments, TDC 34 may include a counter. The counter may be configured to calculate the time domain signal SIG without reference to any clock signal. T The number of pulses is counted to convert the time domain signal SIG T Convert to digital domain signal SIG D In this case, the number of pulses reflects the time domain signal SIG T frequency, and can also reflect the voltage domain signal SIG V The voltage value of the TDC 34 is thus obtained. Thus, the present embodiment provides a time domain ADC 30 capable of converting a low voltage domain signal into a digital domain signal. It should be noted that the architecture of the counter described above is only for illustrative purposes and is not intended to limit the scope of the present invention. In other words, other circuit structures may be used to implement the counter included in the TDC 34 without departing from the spirit of the present invention.

[0093] In summary, the DC-DC controller provided by the embodiment of the present invention can use the time domain ADC to convert the analog domain signal into a digital domain signal, so it can benefit from the miniaturization of process advancement without being limited by the low voltage swing. In addition, since the DC-DC controller can use the same control loop to adjust the timing of the PWM signal in the digital domain, it can reduce the impact caused by process, voltage, and temperature changes, and prevent performance degradation caused by circuit mismatch. In addition, the digital control circuit provided by the embodiment of the present invention can be fully synthesizable in a programming language, so it can be implemented with a smaller chip area in various digital processes.

[0094] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and modifications may be made thereto without departing from the spirit and scope of the present invention as defined in the appended claims. For example, many of the processes discussed above may be implemented in different ways, by replacing or combining other processes.

[0095] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, components, methods and steps described in the specification. From the disclosure of the present invention, it will be readily apparent to those skilled in the art that existing or later developed processes, machines, manufactures, compositions of matter, components, methods or steps may be utilized in accordance with the present invention to perform substantially the same functions or obtain substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, components, methods and steps within their scope.

Claims

1. A DC-DC controller, characterized in that The DC-DC controller is configured to generate N pulse width modulation signals for converting an input voltage into an output voltage targeting a reference voltage, wherein N is an integer greater than 1, and the DC-DC controller comprises: a first voltage-to-time converter configured to generate a first time domain signal corresponding to the input voltage; a second voltage-to-time converter configured to generate a second time domain signal corresponding to the output voltage; a third voltage-to-time converter configured to generate a third time domain signal corresponding to the reference voltage; Digital control circuit, including: a multiplexer configured to determine a voltage segment of the reference voltage according to the first time domain signal and the third time domain signal, and to generate N time segment indication signals to indicate a time segment in which a falling edge of each of the N pulse width modulation signals is located; a first time-to-digital converter coupled to the second voltage-to-time converter and configured to generate a first digital domain signal corresponding to the second time domain signal; a second time-to-digital converter coupled to the third voltage-to-time converter and configured to generate a second digital domain signal corresponding to the third time domain signal; a sign extractor configured to generate a comparison code indicating a magnitude relationship between the output voltage and the reference voltage according to the first digital domain signal and the second digital domain signal; and a first successive approximation register controller configured to generate a first control code according to the comparison code; a sequence phase signal generator configured to generate N phase signals, wherein the N phase signals have duty cycles of the same width, and frequencies of the N phase signals are 1 / N times the frequency of the third time domain signal; and The time domain modulator is configured to adjust the duty ratios of the N phase signals according to the N time period indication signals and the first control code to generate the N pulse width modulation signals.

2. The DC-DC controller according to claim 1, characterized in that: The digital control circuit further includes a first divider coupled to the first voltage-to-time converter and configured to generate a first clock signal by dividing the frequency of the first time domain signal by a first number; as well as The multiplexer receives the third time domain signal and the first clock signal, and uses the fixed time measured by the first clock signal to generate the N time period indication signals according to the number of pulses of the third time domain signal that pass within the fixed time.

3. The DC-DC controller according to claim 2, characterized in that: The first divider is further configured to generate a second clock signal by dividing the frequency of the first time domain signal by a second number; The first successive approximation register controller receives the second clock signal as a clock signal; as well as The first number is equal to or not equal to the second number.

4. The DC-DC controller according to claim 2, characterized in that: The digital control circuit further includes a second divider coupled to the first voltage-to-time converter and configured to generate a second clock signal by dividing the frequency of the first time domain signal by a second number; The first successive approximation register controller receives the second clock signal as a clock signal; as well as The first number is equal to or not equal to the second number.

5. The DC-DC controller according to claim 1, characterized in that: After the first successive approximation register controller generates the first control code, subtracting a least significant bit of the first control code from the first control code; The first SAR controller is further configured to generate a second control code according to the comparison code to adjust the timing of the falling edge of each of the N PWM signals; The time adjustment unit that can be adjusted by the first control code is greater than the time adjustment unit that can be adjusted by the second control code; as well as The number of bits of the first control code is the same as or different from the number of bits of the second control code.

6. The DC-DC controller according to claim 1, characterized in that: The first SAR controller is further configured to generate a third control code for controlling at least one capacitor bank of the second voltage-to-time converter to calibrate a frequency offset between frequencies of the second time domain signal and the third time domain signal.

7. The DC-DC controller according to claim 1, characterized in that: The digital control circuit further comprises: a second successive approximation register controller configured to generate a second control code according to the comparison code to adjust the timing of a falling edge of each of the N pulse width modulation signals; wherein after the first successive approximation register controller generates the first control code and before the second successive approximation register controller is started, the first control code is subtracted from a least significant bit of the first control code; The time adjustment unit that can be adjusted by the first control code is greater than the time adjustment unit that can be adjusted by the second control code; The number of bits of the first control code is the same as or different from the number of bits of the second control code.

8. The DC-DC controller according to claim 1, characterized in that: The digital control circuit further comprises: A third SAR controller is configured to generate a third control code for controlling at least one capacitor bank of the second voltage-to-time converter to calibrate a frequency offset between frequencies of the second time domain signal and the third time domain signal.

9. The DC-DC controller according to claim 1, characterized in that: The digital control circuit further comprises: an adder coupled to the first time-to-digital converter and the second time-to-digital converter, and configured to generate a digital code according to the first digital domain signal and the second digital domain signal; and A code modification unit is configured to modify a control code received by the time domain modulator according to the digital code to adjust the output voltage in at least one of a steady state and a transient state.

10. The DC-DC controller according to claim 9, characterized in that: If the digital code is greater than a first critical value, the code modification unit increases the control code received by the time domain modulator to increase the duty cycle of the N pulse width modulation signals, thereby increasing the output voltage in at least one of a steady state and a transient state; as well as If the digital code is less than a second critical value, the code modification unit reduces the control code received by the time domain modulator to reduce the duty cycle of the N pulse width modulation signals, thereby reducing the output voltage in at least one of a steady state and a transient state.

11. The DC-DC controller according to claim 1, characterized in that: The sequence phase signal generator comprises: A phase signal generator, comprising: N-1 D-type flip-flops, wherein each of the N-1 D-type flip-flops comprises a clock terminal, a data terminal, and an output terminal configured to receive the third time domain signal, wherein the output terminal of the Mth D-type flip-flop among the N-1 D-type flip-flops is coupled to the data terminal of the M+1th D-type flip-flop among the N-1 D-type flip-flops, and M is an integer less than N-1; and a NOR gate having N-1 input terminals coupled to the output terminals of the N-1 D-type flip-flops, and an output terminal coupled to the data terminal of a first D-type flip-flop among the N-1 D-type flip-flops; and N D-type flip-flops are configured to output the N phase signals, wherein each of the N D-type flip-flops includes a clock terminal, a data terminal and an output terminal configured to receive the third time domain signal, wherein the data terminal of the Kth D-type flip-flop among the N D-type flip-flops is coupled to the data terminal of the Kth D-type flip-flop among the N-1 D-type flip-flops in the phase signal generator, K is an integer less than N, and the data terminal of the Nth D-type flip-flop among the N D-type flip-flops is coupled to the output terminal of the N-1th D-type flip-flop among the N-1 D-type flip-flops in the phase signal generator, and the output terminal of each D-type flip-flop among the N D-type flip-flops outputs a corresponding one of the N phase signals.

12. A time domain modulator, characterized in that The invention is used for adjusting the duty cycle of N phase signals to generate N pulse width modulation signals, wherein N is an integer greater than 1, and the duty cycles of the N phase signals have the same width, and the time domain modulator comprises: an input duty cycle selector configured to generate N pulse signals according to the N phase signals and the N time period indication signals, and combine the N pulse signals into a first combined pulse signal; at least one digital-to-time converter connected to the input duty cycle selector and configured to adjust the timing of the first combined pulse signal to generate a second combined pulse signal according to at least one control code; and an output duty cycle selector connected to the at least one digital-to-time converter and configured to generate the N pulse width modulation signals according to the second combined pulse signal and the N time period indication signals; The N rising edges of the N pulse width modulation signals are determined by the N phase signals, and the N falling edges of the N pulse width modulation signals are determined by the second combined pulse signal generated by the at least one digital-to-time converter.

13. The time domain modulator according to claim 12, characterized in that The input duty cycle selector comprises N input channel units, and a first input channel unit of the N input channel units comprises: a first multiplexer configured to select a selected phase signal from the N phase signals according to a first period indication signal of the N period indication signals; a second multiplexer configured to select the selected phase signal from the N phase signals according to the first period indication signal; a pulse generator coupled to the first multiplexer and configured to generate a pulse signal corresponding to the selected phase signal, wherein a pulse width of the pulse signal is smaller than a pulse width of the selected phase signal; and A buffer having an input terminal configured to receive the pulse signal, a control terminal configured to receive the selected phase signal, and an output terminal configured to output the pulse signal during the conduction time of the selected phase signal; the output terminal of the buffer is coupled to the input terminal of the at least one digital-to-time converter.

14. The time domain modulator according to claim 12, characterized in that: The output duty cycle selector comprises N output channel units, a first output channel unit among the N output channel units generates a first pulse width modulation signal among the N pulse width modulation signals, and the first output channel unit comprises: a multiplexer configured to select a selected phase signal from the N phase signals according to a first period indication signal of the N period indication signals; a buffer having an input terminal configured to receive the second combined pulse signal generated by the at least one digital-to-time converter, a control terminal configured to receive the selected phase signal, and an output terminal configured to output a portion of the second combined pulse signal as a reset signal during the on-time of the selected phase signal; and A D-type flip-flop having a data terminal coupled to a logic high voltage, a clock terminal configured to receive a corresponding phase signal among the N phase signals, a reset terminal configured to receive the reset signal, and an output terminal configured to output the first pulse width modulation signal.

15. An analog-to-digital converter, used for converting a voltage domain signal into a digital domain signal, the analog-to-digital converter comprising: a voltage-to-time converter configured to receive the voltage domain signal and generate a time domain signal corresponding to the voltage domain signal; as well as A time-to-digital converter is coupled to the voltage-to-time converter and is configured to generate the digital domain signal related to the time domain signal received from the voltage-to-time converter.

16. The analog-to-digital converter according to claim 15, characterized in that: The voltage-to-time converter includes a voltage-controlled oscillator.

17. The analog-to-digital converter according to claim 16, characterized in that: The voltage controlled oscillator comprises: A multi-stage delay circuit; and At least one capacitor group is coupled between the plurality of delay circuits and configured to adjust the frequency of the voltage controlled oscillator.

18. The analog-to-digital converter according to claim 17, characterized in that: Each of the plurality of delay circuits comprises: A first transistor having a first terminal coupled to a current source, a second terminal configured to generate a first output voltage for a next stage delay circuit, and a control terminal configured to receive a first input voltage; a second transistor having a first terminal coupled to the current source, a second terminal configured to generate a second output voltage for the next stage delay circuit, and a control terminal configured to receive a second input voltage; a third transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal configured to receive a ground voltage, and a control terminal configured to receive the voltage domain signal; a fourth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal configured to receive the ground voltage, and a control terminal configured to receive the voltage domain signal; a fifth transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal configured to receive the ground voltage, and a control terminal configured to be coupled to the second terminal of the second transistor; and a sixth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal configured to receive the ground voltage, and a control terminal configured to be coupled to the second terminal of the first transistor; The voltage domain signal has a voltage swing higher than a power supply voltage swing.

19. The analog-to-digital converter according to claim 18, characterized in that: The third transistor and the fourth transistor are both high voltage resistant transistors.

20. The analog-to-digital converter according to claim 15, characterized in that The time-to-digital converter includes a counter configured to generate the digital domain signal by counting the number of pulses of the time domain signal.

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