Multi-model implementation method of digital predistorter
By generating and configuring model files and optimizing lookup table resources, the problems of limited complexity and poor scalability of the DPD model are solved, and the flexible configuration of the DPD model on different FPGA platforms are realized.
Patent Information
- Application Number
- CN202411227110.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-03
- Publication Date
- 2024-12-27
AI Technical Summary
The complexity of the existing digital predistorter (DPD) model is limited, cannot be flexibly configured, and cannot be ported on different FPGA hardware platforms, resulting in poor scalability.
By obtaining the predistorter expression, generating model files, parsing and configuring the lookup table number and number of usage, optimizing FPGA hardware resources based on model parameters, and using a general FPGA language design to adapt to all models of FPGAs.
It realizes flexible configuration of DPD models, optimizes the use of FPGA hardware resources, ensures that the design of FPGAs suitable for all models, and avoids the dependence of specific FPGA IPs.
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Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of wireless communications, and in particular to a multi-model implementation method of a digital predistorter. Background Art
[0002] In modern wireless communication systems, it is necessary to perform necessary linearization processing on the power amplifier at the end of the transmitter RF. The most common linearization technology is digital pre-distortion technology (DPD). DPD performs pre-distortion processing on the signal at the baseband, which can effectively compensate for the memory nonlinear effect of the power amplifier, thereby linearizing it. Digital pre-distortion technology can not only ensure the transmission quality of the signal, but also significantly reduce the power consumption of the base station.
[0003] like Figure 1 The figure shows a typical DPD application scenario. The baseband signal u(n) is first input to the digital predistorter. The predistorted signal x(n) is output after digital / analog conversion, and then the power amplifier PA outputs the signal y(n). The digital predistortion system consists of two parts: the predistorter and the model training. The predistorter contains a model with the opposite behavior characteristics of the power amplifier, which performs real-time predistortion on the baseband signal. The model training part is used to update the predistorter coefficients. It contains complex matrix operations and does not require high real-time performance. It is usually implemented in software.
[0004] Taking GMP DPD as an example, its model expression is as follows:
[0005]
[0006] Where d(n) represents the predistorter input signal, x GMP (n) represents the output signal of the predistorter, i represents the memory term, j represents the cross-memory term, k represents the nonlinear order, c ijk Represents the model coefficients.
[0007] Digital predistortion can be implemented by direct calculation and table lookup. Since formula (1) includes a large number of multiplication and addition operations, direct calculation will consume too many DSP resources and will produce a large delay. Therefore, FPGA-based predistortion is generally implemented by table lookup (LUT). At present, mainstream foreign FPGA manufacturers provide commercial DPD IP, but it is a black box design for users. It not only has certain restrictions on the complexity of the DPD model, but can only be applied to specified models of FPGA. Therefore, when implementing a digital predistortion system, customers will have the following difficulties:
[0008] (1) The complexity of the DPD model is limited, such as limiting the number of model coefficients, limiting the memory depth and nonlinear order.
[0009] (2) The existing DPD IP has poor scalability and cannot be ported to different FPGA hardware platforms. Summary of the invention
[0010] The purpose of the present invention is to provide a multi-model implementation method of a digital predistorter, which supports customers to flexibly configure DPD models. The method is not only applicable to all types of FPGAs, but also can optimize the hardware resources used by the FPGA according to the model configuration parameters.
[0011] In order to achieve the above object, a multi-model implementation method of a digital predistorter is provided, comprising the following steps:
[0012] S1. Obtain a model file according to a predistorter expression; specifically, save all value combinations of (i, j, k) in the predistorter expression as a text file according to a set format, and the text file is defined as a model file;
[0013] S2. Parse the model file to obtain the lookup table number and the number of lookup tables to be used;
[0014] S3, configuring model parameters to the FPGA top-level design module, and selectively instantiating the effective lookup table in the FPGA top-level design module according to different model configuration parameters to optimize the hardware resources used by the FPGA; the model configuration parameters include data bit width, lookup table depth and lookup table mask; the lookup table mask is an array whose size is expressed as the number of lookup tables, indicating whether the corresponding lookup table will be instantiated as a BRAM in the tool during FPGA synthesis; the lookup table mask is calculated according to the lookup table number of the lookup table;
[0015] S4. Using FPGA synthesis tools, the pre-distorter input signal is multiplied with the output of the corresponding lookup table instantiated as BRAM after different time delays, and then the output is accumulated to obtain a hardware pre-distorter. In the process of implementing the pre-distorter, no specific FPGA primitives or IPs are called, and a synthesizable general FPGA language is used to encapsulate the design into an IP with a general bus interface.
[0016] Further, the calculation formula for the lookup table number in step S2 is as follows:
[0017] lutID=i+j×N
[0018] Among them, i represents a memory item, j represents a cross memory item, and N is the maximum value of the user-defined cross memory item j.
[0019] Furthermore, the following transformation is performed based on the GMP digital pre-distortion model:
[0020]
[0021] Among them, d(n) represents the input signal of the predistorter, and x GMP (n) represents the output signal of the predistorter, i represents the memory term, j represents the cross-memory term, and lut(i, j) is the output signal of the lookup table related to i and j. Its expression is as follows:
[0022]
[0023] Among them, c ijk represents the model coefficient.
[0024] Furthermore, in step S3, the FPGA top-level design module performs FPGA module partitioning. The partitioning steps are as follows:
[0025] Perform FPGA module partitioning from top to bottom, including the top-level module DPD Actuator and several DPD LutRow modules. Each DPD Lut Row module contains several sub-modules lut(i, j). The several sub-modules lut(i, j) in the DPD Lut Row module represent a group of lookup tables with the same cross-memory term j.
[0026] Furthermore, the steps for analyzing whether the lookup table will be instantiated as a BRAM in step S3 are as follows:
[0027] S301: Read the lookup table mask lutIdMask[lutId] in the configuration parameters and initialize the lookup table number lutID;
[0028] S302: Determine whether the lookup table mask is greater than 0, that is, lutIdMask[lutId]>0. If it is greater than 0, execute step S303; otherwise, execute step S304;
[0029] S303: Instantiate the lookup table corresponding to the lookup table number lutID as a BRAM, and then execute step S304;
[0030] S304: lutID = lutID + 1;
[0031] S305: Determine whether the lookup table number lutID is less than M*N, that is, lutID<M*N; if so, jump to execute step S302; otherwise, perform signal connection on the instantiated sub-module lut(i, j).
[0032] Principle and advantages:
[0033] 1. This solution does not limit the complexity of the DPD model, for example, it does not limit the number of model coefficients, memory depth, and nonlinear order. Moreover, one DPD model corresponds to one file, and loading different model files is to configure different DPD models. Through the steps, customers can flexibly configure the DPD model.
[0034] 2. This solution can selectively instantiate the active lookup table according to different model configuration parameters, thereby optimizing the hardware resources used by the FPGA. In addition, in the process of implementing the predistorter, no specific FPGA primitives or IPs are called, but the design is encapsulated into an IP with a universal bus interface using a synthesizable general FPGA language, thereby ensuring that the design is applicable to all types of FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 This is a schematic diagram of a typical DPD application scenario;
[0036] Figure 2 A flowchart of a multi-model implementation method of a digital predistorter according to an embodiment of the present invention;
[0037] Figure 3 This is a schematic diagram of the FPGA design structure corresponding to the pre-distorter;
[0038] Figure 4 For submodule ∑ i Schematic diagram of the structure of lut(i,0);
[0039] Figure 5 A flowchart of a lookup table that works for instantiation;
[0040] Figure 6 This is a schematic diagram of the structure of the top-level module. DETAILED DESCRIPTION
[0041] The following is further described in detail through specific implementation methods:
[0042] Example
[0043] A multi-model implementation method for a digital predistorter is basically as follows Figure 2 As shown, the following steps are included:
[0044] S1. Obtain a model file according to a predistorter expression; specifically, save all value combinations of (i, j, k) in the predistorter expression as a text file according to a set format, and the text file is defined as a model file; since different models will be instantiated as different FPGA resources, this model file will be used as input for subsequent steps.
[0045] The GMP digital pre-distortion model is transformed as follows:
[0046]
[0047] Where d(n) represents the predistorter input signal, x GMP (n) represents the predistorter output signal, i represents the memory item, j represents the cross memory item, lut(i,j) is the lookup table output signal associated with i and j, and its expression is as follows:
[0048]
[0049] Among them, c ijk Represents the model coefficients.
[0050] S2. Parse the model file to obtain the lookup table number and the number of lookup tables to be used; the number of lookup tables to be used and the lookup table number depend only on the (i, j) combination.
[0051] The calculation formula for the lookup table number in step S2 is as follows:
[0052] lutID=i+j×N
[0053] Among them, i represents a memory item, j represents a cross memory item, and N is the maximum value of the user-defined cross memory item j.
[0054] S3. Configure the model parameters to the FPGA top-level design module. In the FPGA top-level design module, according to different model configuration parameters, selectively instantiate the effective lookup table to optimize the hardware resources used by the FPGA; the model configuration parameters include data bit width, lookup table depth and lookup table mask; data bit width and lookup table depth affect the calculation accuracy of the model and can be adjusted according to the application scenario. The lookup table mask is an array whose size is expressed as the number of lookup tables, indicating whether the corresponding lookup table will be instantiated as BRAM in the tool during FPGA synthesis; the lookup table mask is calculated based on the lookup table number of the lookup table; such as lutIdMask = 0x0001, indicating that only Lut0 will be instantiated, and the rest of the Lut will be ignored. The hardware resources actually used by the model are a BRAM (block ram) occupied by a Lut.
[0055] lutIdMask can be calculated based on lutId in step S2. If lutIdMask[lutId] is not 0, the corresponding lookup table will be instantiated as BRAM in the FPGA synthesis tool, otherwise it will be ignored and will not occupy any hardware resources.
[0056] like Figure 5 As shown, the steps of analyzing whether the lookup table will be instantiated as BRAM in step S3 are as follows:
[0057] S301. Read the lookup table mask lutIdMask[lutId] in the configuration parameters and initialize the lookup table number lutID;
[0058] S302. Determine whether the lookup table mask is greater than 0, that is, lutIdMask[lutId]>0. If it is greater than 0, execute step S303; otherwise, execute step S304;
[0059] S303. Instantiate the lookup table corresponding to the lookup table number lutID as a BRAM, and then execute step S304;
[0060] S304. lutID = lutID + 1;
[0061] S305. Determine whether the lookup table number lutID is less than M*N, that is, lutID<M*N; if so, jump to execute step S302; otherwise, perform signal connection on the instantiated sub-module lut(i,j). The signal connection is as Figure 3 shown.
[0062] In the above S3, the FPGA top-level design module performs FPGA module division; the division steps are as follows:
[0063] Perform FPGA module division from top to bottom, including the top-level module DPD Actuator and several DPD LutRow modules. Each DPD Lut Row module contains several sub-modules lut(i,j). The several sub-modules lut(i,j) in the DPD Lut Row module represent a group of lookup tables with the same cross memory item j, as Figure 6 shown.
[0064] S4. Use the FPGA synthesis tool to multiply the input signal of the predistorter after different time delays by the output of the lookup table instantiated as a BRAM, and then perform accumulation and output to obtain the hardware predistorter. The input of the lookup table is the modulus value of the input signal of the distorter after different time delays. In addition, during the implementation of the predistorter, specific FPGA primitives or IPs are not called, but a general FPGA language (VerilogHDL or VHDL) that can be synthesized is used to encapsulate the design into an IP with a general bus interface, so as to ensure that the design can be adapted to FPGAs of different manufacturers. The FPGA synthesis tool is vivado or synopsys, etc.
[0065] Assume M = 8, N = 8, the schematic diagram of the FPGA design structure corresponding to the predistorter Figure 3 shown; where, d(n) represents the input signal of the predistorter, and the sub-module ∑ ilut(i,j) represents the sum of the outputs of a set of lookup tables with the same cross-memory item j. Its schematic diagram is as follows Figure 4 As shown (taking j=0, M=8 as an example).
[0066] For example:
[0067] According to step S1, a simple model file is obtained, as shown in Table 2 below:
[0068] Table 2: Model files
[0069]
[0070]
[0071] It can be seen that the only lookup tables that need hardware instantiation are LUT9, LUT10, LUT18, and LUT26.
[0072] Among them, the lookup table LUT9 is equivalent to the following expression:
[0073] lut(1,1)=c 112 |d(n-1)| 2 +c 113 |d(n-1)| 3
[0074] The lookup table LUT10 is equivalent to the following expression:
[0075] lut(2,1)=c 211 |d(n-2)| 1 +c 215 |d(n-2)| 5
[0076] The lookup table LUT18 is equivalent to the following expression:
[0077] lut(2,2)=c 221 |d(n-2)| 1 +c 223 |d(n-2)| 3
[0078] The lookup table LUT26 is equivalent to the following expression:
[0079] lut(2,3)=c 233 |d(n-2)| 3 +c 235 |d(n-2)| 5 +c 237 |d(n-2)| 7
[0080] The output of the DPD model is:
[0081] x GMP (n)=lut(1,1)d(n-1)+lut(2,1)d(n-1)+lut(2,2)d(n-2)+lut(2,3)d(n-3)
[0082] The above is only an embodiment of the present invention. The common sense such as the known specific structure and characteristics in the scheme is not described in detail here. The ordinary technicians in the relevant field know all the common technical knowledge in the technical field of the invention before the application date or priority date, can obtain all the existing technologies in the field, and have the ability to apply the conventional experimental means before that date. The ordinary technicians in the relevant field can improve and implement this scheme in combination with their own abilities under the enlightenment given by this application. Some typical known structures or known methods should not become obstacles for ordinary technicians in the relevant field to implement this application. It should be pointed out that for those skilled in the art, without departing from the structure of the present invention, several deformations and improvements can be made, which should also be regarded as the protection scope of the present invention, which will not affect the effect of the implementation of the present invention and the practicality of the patent. The protection scope required by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to interpret the content of the claims.
Claims
1. A multi-model implementation method for a digital predistorter, characterized in that: The following steps are involved: S1. Obtain a model file according to a predistorter expression; specifically, save all value combinations of (i, j, k) in the predistorter expression as a text file according to a set format, and the text file is defined as a model file; S2. Parse the model file to obtain the lookup table number and the number of lookup tables to be used; S3, configuring model parameters to the FPGA top-level design module, and selectively instantiating the effective lookup table in the FPGA top-level design module according to different model configuration parameters to optimize the hardware resources used by the FPGA; the model configuration parameters include data bit width, lookup table depth and lookup table mask; the lookup table mask is an array whose size is expressed as the number of lookup tables, indicating whether the corresponding lookup table will be instantiated as BRAM in the tool during FPGA synthesis; The lookup table mask is calculated based on the lookup table number of the lookup table; S4. Using FPGA synthesis tools, the pre-distorter input signal is multiplied with the output of the corresponding lookup table instantiated as BRAM after different time delays, and then the output is accumulated to obtain a hardware pre-distorter. In the process of implementing the pre-distorter, no specific FPGA primitives or IPs are called, and a synthesizable general FPGA language is used to encapsulate the design into an IP with a general bus interface.
2. The multi-model implementation method of a digital predistorter according to claim 1, characterized in that: The calculation formula for the lookup table number in step S2 is as follows: lutID=i+j×N Among them, i represents a memory item, j represents a cross memory item, and N is the maximum value of the user-defined cross memory item j.
3. The multi-model implementation method of a digital predistorter according to claim 2, characterized in that: The GMP digital pre-distortion model is transformed as follows: Where d(n) represents the predistorter input signal, x GMP (n) represents the predistorter output signal, i represents the memory item, j represents the cross memory item, lut(i,j) is the lookup table output signal associated with i and j, and its expression is as follows: Among them, c ijk Represents the model coefficients.
4. The multi-model implementation method of a digital predistorter according to claim 3, characterized in that: The FPGA top-level design module in S3 is divided into FPGA modules; the division steps are as follows: The FPGA module is divided from top to bottom, including the top-level module DPD Actuator and several DPD Lut Row modules. Each DPD Lut Row module contains several sub-modules lut(i,j). The several sub-modules lut(i,j) in the DPD Lut Row module represent a set of lookup tables with the same cross-memory item j.
5. The multi-model implementation method of a digital predistorter according to claim 4, characterized in that: The steps of analyzing whether the lookup table will be instantiated as BRAM in step S3 are as follows: S301, read the lookup table mask lutIdMask[lutId] in the configuration parameters, and initialize the lookup table number lutID; S302, determine whether the lookup table mask is greater than 0, that is, lutIdMask[lutId]>0, if it is greater than 0, execute step S303, otherwise execute step S304; S303, instantiate the lookup table corresponding to the lookup table number lutID into BRAM, and then execute step S304; S304, lutID=lutID+1; S305, determine whether the lookup table number lutID is less than M*N, that is, lutID <M*N; If yes, jump to step S302, otherwise, perform signal connection on the instantiated submodule lut(i,j).