ADC error compensation using power of ADC output

Abstract

An apparatus may include an input configured to receive an analog input signal. An apparatus may include an output configured to output a digital signal x, wherein the digital signal x includes a digital approximation of the analog input signal. For example, an apparatus may include an error correction system connected to an ADC, the error correction system including a first input configured to receive an N-power version of the digital signal x, where N is an integer equal to or greater than two, where the error correction system is configured to: determine a correction value using the N-power version of the digital signal x; and modifying the digital signal x to produce a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors present within the ADC.

Description

Technical Field

[0001] Errors in the analog-to-digital converter (ADC) are compensated using an error correction system, which may implement a machine learning engine. The error correction system is configured to compensate for those errors by analyzing the power of the ADC output. Background Art

[0002] In electronics, an analog-to-digital converter ("ADC") is a system that converts an analog signal, such as sound picked up by a microphone or light entering a digital camera, into a digital signal. An ADC can also provide isolated measurements when implemented as an electronic device that converts an input analog voltage or current into a digital number representing the voltage or current magnitude.

[0003] More specifically, an ADC converts an analog signal of continuous time and continuous amplitude into a digital signal of discrete time and discrete amplitude. The conversion involves quantization of the input, so the process necessarily introduces a small amount of error or noise. In addition, rather than performing conversions continuously, the ADC performs conversions periodically, sampling the input signal at a certain sampling rate, which limits the allowable bandwidth of the input signal.

[0004] ADCs can suffer from signal degradation due to circuit nonlinearity, which can appear as errors in the ADC output. Such nonlinearity can degrade the signal by introducing harmonic distortion (i.e., noise spurs at multiples of the input signal frequency) and intermodulation products.

[0005] Circuit nonlinearities can be detrimental in a delta-sigma (ΣΔ) modulator, where the noise is shaped so that most of the quantization noise is shifted to higher frequencies within the modulator spectrum. Since the intermodulation portion of the high-frequency quantization noise cancels the effect of the noise shaping, these nonlinearities can fold the carefully shaped noise back into the baseband of the ADC. Summary of the invention

[0006] In some aspects, the technology described herein relates to a system comprising: an analog-to-digital converter (ADC) comprising an input terminal configured to receive an analog input signal and an output terminal configured to output a digital signal x, wherein the digital signal x comprises a digital approximation of the analog input signal; and an error correction system connected to the ADC, the error correction system comprising a first input terminal configured to receive an Nth-power version of the digital signal x, wherein N is an integer equal to or greater than two, wherein the error correction system is configured to: determine a correction value using the Nth-power version of the digital signal x; and modify the digital signal x to produce a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors present within the ADC.

[0007] According to one or more embodiments, the ADC is a sigma-delta ADC.

[0008] According to one or more embodiments,

[0009] The delta-sigma ADC is a multi-bit delta-sigma ADC;

[0010] The error correction system includes a second terminal configured to receive an M-th power version of the digital signal x, where M is an integer equal to or greater than two; and

[0011] The error correction system is configured to determine the correction value using the M-th power version of the digital signal x.

[0012] According to one or more embodiments, N is equal to two, and M is equal to three.

[0013] According to one or more embodiments, the error correction system includes a neural network configured to determine the correction value.

[0014] According to one or more embodiments, the system further comprises a sensor configured to provide a parameter to the error correction system, wherein the output of the ADC varies with a value of the parameter, and the parameter comprises at least one of semiconductor manufacturing related process variations, voltage, and temperature.

[0015] According to one or more embodiments, the neural network has been configured through a training phase using the parameters to compensate for variations in the output of the ADC.

[0016] According to one or more embodiments, the ADC has a first bandwidth and further includes a filter connected between the first input of the error correction system and the error correction system, wherein the filter is configured to attenuate signals having frequencies outside a second bandwidth.

[0017] According to one or more embodiments, the first bandwidth is equal to the second bandwidth.

[0018] In some aspects, the technology described herein relates to a system comprising: an analog-to-digital converter (ADC) comprising an input terminal configured to receive an analog input signal, a summing node connected to the input terminal, and an output terminal configured to output a digital signal x, wherein the digital signal x comprises a digital approximation of the analog input signal; a digital-to-analog converter electrically connected between the output terminal and the summing node, wherein the digital-to-analog converter is configured to: receive the digital signal from the output terminal; and convert the digital signal into a second analog signal, wherein the digital signal x comprises an error signal having the form of ax2+bx3+...; and an error correction system connected to the ADC, the error correction system comprising a first input terminal configured to receive a quadratic version of the digital signal x and a neural network configured to: determine a correction value using the quadratic version of the digital signal x; and modify the digital signal x to produce a corrected digital signal by applying the correction value to the digital signal x to compensate for the polynomial error signal generated by the digital-to-analog converter.

[0019] According to one or more embodiments, the system further comprises a sensor configured to provide a parameter to the neural network, wherein the output of the ADC varies with a value of the parameter, and the parameter comprises at least one of a process parameter, a voltage parameter, and a temperature parameter.

[0020] According to one or more embodiments, the neural network has been configured through a training phase using the parameters to compensate for variations in the output of the ADC.

[0021] According to one or more embodiments, the ADC has a first bandwidth and further includes a filter connected between the first input of the error correction system and the neural network, wherein the filter is configured to attenuate signals having frequencies outside a second bandwidth.

[0022] According to one or more embodiments, the first bandwidth is equal to the second bandwidth.

[0023] In some aspects, the technology described herein relates to a method comprising: receiving a digital signal x from an analog-to-digital converter (ADC) configured to receive an analog input signal and output a digital signal x, wherein the digital signal x comprises a digital approximation of the analog input signal; receiving an Nth-power version of the digital signal x, wherein N is an integer equal to or greater than two; determining a correction value using the Nth-power version of the digital signal x; and modifying the digital signal x to produce a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors present within the ADC.

[0024] According to one or more embodiments, the ADC is a sigma-delta ADC.

[0025] According to one or more embodiments, the delta-sigma ADC is a multi-bit delta-sigma ADC, and the method further comprises:

[0026] receiving an M-th power version of the digital signal x, where M is an integer equal to or greater than two; and

[0027] The correction value is determined using the M-th power version of the digital signal x.

[0028] According to one or more embodiments, N is equal to two, and M is equal to three.

[0029] According to one or more embodiments, the method further comprises:

[0030] receiving a parameter from a sensor, wherein the parameter comprises at least one of semiconductor manufacturing related process variation, voltage, and temperature; and

[0031] The correction value is determined using the parameter, wherein the output of the ADC is a function of the value of the parameter.

[0032] According to one or more embodiments, the ADC has a first bandwidth, and the method further comprises attenuating signals from the Nth-power version of the digital signal x having frequencies outside the first bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] A more complete understanding of the subject matter may be obtained by referring to the detailed description and claims when considered in conjunction with the following drawings, in which like reference numerals refer to similar elements throughout the various figures.

[0034] Figure 1 is a block diagram depicting the components of a sigma-delta modulator analog-to-digital converter (ADC).

[0035] Figure 2 is a graph depicting the FFT of the output bit stream produced by an ideal sigma-delta modulator when the input to the sigma-delta modulator is a sine wave.

[0036] Figure 3 Depicts a non-ideal sigma-delta modulator ADC where the non-ideality resides in the feedback digital-to-analog converter (DAC).

[0037] Figure 4 is a graph depicting the FFT of an output bit stream produced by a non-ideal sigma-delta modulator when the input to the non-ideal sigma-delta modulator is a sine wave.

[0038] Figure 5 An ADC system including an error correction system configured to correct or minimize an error generated by the ADC, wherein the error is in the form of a polynomial error, is described.

[0039] Figure 6 An ADC system is depicted that includes an error correction system that includes a neural network configured to correct or minimize an error produced by the ADC, the error being in the form of a polynomial error.

[0040] Figure 7 Describes the implementation Figure 6 The neural network is the function of the neural network.

[0041] Figure 8 Methods that may be implemented by an error correction system to provide error correction to an output signal of an ADC are described.

[0042] Fig. 9 Depicted is the low-pass filtered frequency-domain output signal of an ideal sigma-delta ADC without error correction.

[0043] Fig.10 Depicted is the low-pass filtered frequency domain output signal of a delta-sigma ADC, where second-order and third-order circuit nonlinearities produce a distorted and noisy output signal.

[0044] Fig.11 Depicted is a low pass filtered frequency domain output signal of a delta-sigma ADC containing second and third order circuit nonlinearities having performed error correction according to the present disclosure. DETAILED DESCRIPTION

[0045] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter of the present application and the uses of such embodiments. As used herein, the words "exemplary" and "exemplary" mean "serving as an example, instance, or illustration". Any embodiment or embodiment described herein as exemplary or exemplary is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any express or implied theory presented in the aforementioned technical field, background technology, or the following detailed description.

[0046] Like all circuits, analog-to-digital converters (ADCs) can suffer from signal degradation due to circuit nonlinearities. Nonlinearities can introduce harmonic distortion and intermodulation (IM) products to the ADC's output signal. The degradative effects of this nonlinearity can be evident in an ADC configured as a delta-sigma (ΣΔ) modulator in the form of an increased noise floor within the bandwidth of interest. In a delta-sigma modulator, the output noise is shaped so that most of the quantization noise is moved to the higher frequencies of the modulator spectrum. This nonlinearity folds the shaped noise back to baseband due to intermodulation of the high-frequency quantization noise, which can eliminate the benefits of noise shaping in those types of ADCs, negatively affecting modulator performance.

[0047] A sigma-delta modulator is an ADC configured to produce a digital output bit stream, where the average magnitude of the digital output bit stream is equal or identical to the magnitude of the analog input signal to the sigma-delta modulator. Figure 1 is a block diagram depicting the components of a delta-sigma modulator 100. The delta-sigma modulator 100 includes an input terminal 102 configured to receive an analog input signal. The input signal is passed through a summing node 104 to a loop filter 106 having a transfer function H1, where the transfer function H1 can be a discrete or continuous time analog filter. The output of the loop filter 106 is supplied to a quantizer 108, which is configured to convert the output of the integration stage into an amplitude and time discrete (i.e., digital) value, which is output as a digital bit stream at an output terminal 110.

[0048] The digital bit stream output by the delta-sigma modulator 100 at the output 110 is also passed back through the digital-to-analog converter 112, which is configured to convert the output digital bit stream back into a corresponding analog signal. Ideally, the analog signal produced by the digital-to-analog converter 112 exactly matches the input signal originally received at the input 102.

[0049] The analog output of the digital-to-analog converter 112 is supplied to the negative input of the summing node 104. In this configuration, the digital-to-analog converter 112 provides a feedback loop that causes the analog signal output by the digital-to-analog converter 112 to be subtracted from the analog input signal received at the input 102. The result of the subtraction is supplied to the loop filter 106. In this manner, the sigma-delta modulator 100 is configured to produce a digital output bit stream having an average power level that matches the power level of the analog input signal to the modulator.

[0050] Figure 2 150 is a graph depicting the FFT of the output bit stream produced by the sigma delta modulator when the input to the ideal sigma delta modulator 100 is a sine wave. In FIG. 150 , the horizontal axis represents frequency (on a logarithmic scale) and the vertical axis represents amplitude in decibels (dB). As shown in FIG. 150 , the sigma delta modulator implementation shifts most of the noise (shown by line 152) to frequencies significantly higher than the frequency of the signal (indicated by arrow 154) produced by the sigma delta modulator 100 (i.e., the frequency containing valid information). This characteristic of the sigma delta modulator (i.e., pushing the quantization noise to a higher frequency of the modulator's output signal) can be useful because the characteristic enables a low-pass filter to be applied to the output of the sigma delta modulator (e.g., a low-pass filter having a cutoff frequency just higher than the frequency of the signal in the modulator output) to remove most of the quantization noise from the modulator output signal while maintaining the useful portion of the modulator output signal.

[0051] However, in a non-ideal sigma-delta modulator, nonlinearities in the modulator components can cause noise and harmonic distortion to be introduced into the output of the sigma-delta modulator 100. For example, Figure 3 A non-ideal sigma-delta modulator 200 is depicted. Like the sigma-delta modulator 100, the non-ideal sigma-delta modulator 200 includes an input 202, a summing node 204, a loop filter 206, a quantizer 208, and an output 210. The sigma-delta modulator 200 includes a feedback loop that includes a digital-to-analog converter 212. However, in the non-ideal sigma-delta modulator 200, the digital-to-analog converter 212 exhibits some non-linearity such that the output of the digital-to-analog converter 212 includes distortion. Specifically, as shown in FIG. Figure 3 As shown in FIG. 1 , the output signal of the digital / analog converter 212 includes a signal in the form of ax 2 +bx 3 + polynomial nonlinear components of ... These additional distortion components can fold high frequency spectral components back to baseband due to intermodulation, reduce the noise shaping benefits of the delta-sigma modulator implementation, and increase the noise level at frequencies near the frequency of the signal output by the modulator.

[0052] To illustrate, Figure 4 250 is a graph depicting the FFT of the output bit stream produced by the non-ideal sigma-delta modulator 200 when the input to the non-ideal sigma-delta modulator is a sine wave. In graph 250, the horizontal axis represents frequency (on a logarithmic scale) and the vertical axis represents amplitude in decibels (dB). As shown in graph 250, the quantization noise generated by the non-ideal digital-to-analog converter 212 causes IM products 252 to be produced at frequencies close to the frequency of the true signal 254 being output by the modulator. This in turn reduces the signal-to-noise ratio (SNR) of the modulator, thereby reducing its accuracy and effectiveness. This is reflected as the foldback noise (N ) shown by line 256 in graph 250. foldback ) levels.

[0053] To avoid these problems, care should be taken when designing the circuit components (e.g., amplifiers and / or feedback digital / analog converters) inside the feedback loop of the ΣΔ modulator to minimize circuit nonlinearities. Of course, this can be difficult and is usually done at the expense of additional silicon area (i.e., larger circuit design) and power requirements.

[0054] To mitigate these deficiencies, post-processing can be performed on the output signal of the non-ideal delta-sigma converter to remove unwanted spectral components from the output signal. Although intermodulation products that reduce the modulator SNR are called "noise," they are still associated with quantization noise and loop nonlinearity. Therefore, post-processing can reduce the impact of intermodulation products to improve the modulator's SNR.

[0055] The present disclosure provides a system and method for compensating for ADC nonlinearity by providing a scaled version of the power of an ADC (e.g., a delta-sigma modulator or a Nyquist ADC) output signal to a properly configured error correction system. The error correction system can be implemented as a numerical optimizer or a neural network, where the applied error correction scheme can be learned by the error correction system. By training the error correction system for the power of the scaled bit stream, the process of removing distortion and folded noise components due to component nonlinearity can be simplified. Although the error correction system and method of the present disclosure can be used in conjunction with any type of ADC or modulator, performance improvements can be observed when used in conjunction with specific types of ADCs, including oversampled ADCs, where nonlinearities can produce IM products (from low-frequency and high-frequency noise components) that fall back to the frequency band of interest (the frequency band of interest is fs / 2*1 / OSR, where OSR is the oversampling rate), and other types of noise shaping ADCs, where the noise is "shaped" to be outside the frequency band of interest. In a noise shaping ADC, since most of the noise in an ideal noise shaping ADC is outside the band of interest, the IM products of the noise components may fold back into the band of interest with significant signal degradation. A sigma-delta modulator is an ADC that uses both oversampling and noise shaping, and thus significant performance improvements may be observed when used in conjunction with the systems and methods of the present disclosure.

[0056] When the error correction system is implemented using machine learning, any suitable structure and / or implementation scheme can be utilized (e.g., artificial neural networks, deep neural networks, convolutional neural networks, recurrent neural networks, autoencoders, reinforcement learning, etc.), fuzzy logic, artificial intelligence ("AI"), deep learning algorithms, deep structured learning hierarchical learning algorithms, support vector machines ("SVM") (e.g., linear SVM, nonlinear SVM, SVM regression, etc.), decision tree learning (e.g., classification and regression trees ("CART"), ensemble methods (e.g., ensemble learning, random forests, sampling with replacement and without replacement (Bagging and Pasting), patches and subspaces (Patches and Subspaces), boosting (Boosting), stacking (Stacking), etc.), dimensionality reduction (e.g., projection, manifold learning (Manifold Learning), principal component analysis, etc.) and / or deep machine learning algorithms. Non-limiting examples of publicly available machine learning algorithms, software, and libraries that can be utilized within embodiments of the present disclosure include Python, OpenCV, Inception, Theano, Torch, PyTorch, Pylearn2, Numpy, Blocks, TensorFlow, MXNet, Caffe, Lasagne, Keras, Chainer, Matlab Deep Learning, CNTK, MatConvNet (MATLAB toolbox for implementing convolutional neural networks for computer vision applications), DeepLearnToolbox (Matlab toolbox for deep learning (from Rasmus Berg Palm)), BigDL, Cuda-Convnet (fast C++ / CUDA implementation of convolutional (or more generally, feedforward) neural networks), Deep Belief Networks (Deep Belief Networks), RNNLM, RNNLIB-RNNLIB, matrbm, deeplearning4j, Eblearn.lsh, deepmat, MShadow, Matplotlib, SciPy, CXXNET, Nengo-Nengo, Eblearn, cudamat, Gnumpy, 3-way factored RBM and mcRBM, mPoT, ConvNet, Elektronn, OpenNN, NeuralDesigner, Theano Generalized HebbianLearning, Apache Singa, Lightnet, and SimpleDNN.

[0057] Various embodiments disclosed herein are described with respect to the use of artificial neural networks (also referred to herein simply as "neural networks"), but one of ordinary skill in the art will be able to implement any suitable machine learning system or other error correction logic network in a delta-sigma modulator or Nyquist ADC according to the embodiments of the present disclosure.

[0058] Neural networks are typically based on a collection of connected units or nodes called artificial neurons, which loosely model neurons in biological brains. Each connection, like a synapse in a biological brain, can transmit signals to other neurons. The artificial neuron that receives the signal then processes it and can send signals to the neurons connected to it. In a neural network implementation, the "signal" at the connection is a real number, and the output of each neuron is calculated by a nonlinear function of the sum of its inputs (e.g., S-shaped activation). Connections are called edges. Neurons and edges typically have weights that are adjusted as the training of the neural network proceeds. The weight increases or decreases the signal strength at the connection. Neurons can have a threshold so that a signal is sent only when the aggregate signal exceeds the threshold. Typically, neurons are aggregated into layers. Different layers can perform different transformations on their inputs. The signal travels from the first layer (input layer) to the last layer (output layer), possibly after traversing these layers multiple times. The neural network architecture can be configured as a feedforward network with one or more hidden layers and a back-propagation learning algorithm. The implementation of a neural network can involve three stages: a training or learning stage; a verification stage; and an inference or generation stage. In the training phase, the neural network essentially learns by comparing its actual output to known correct outputs (or at least outputs that are closer to the desired output) to find errors. The model is then modified accordingly. In the validation phase, the trained neural network is tested against data (the "validation set"), which may be different from the data used in the training phase. In the inference or production phase, the trained and validated neural network is now configured and able to provide outputs corresponding to any input.

[0059] The result of the above is an ADC device that utilizes an error correction system (e.g., a neural network) that has been trained to "know" the form of the ADC's analog-to-digital conversion error (e.g., the form ax 2 +bx 3 +…) and also “knows” how to compensate for these nonlinearities by applying specific error corrections.

[0060] When the error correction system is implemented as a neural network, the neural network can be implemented in any type of hardware and / or software (as will be disclosed elsewhere herein), such as within a set of appropriate digital circuit systems suitable for implementing a neural network or other type of machine learning system. The neural networks shown in the figures do not limit the scope of the embodiments of the present disclosure. In each figure, "(A)" indicates that the signal is an analog signal, and "(D)" indicates that the signal is a digital signal.

[0061] Figure 5 An ADC system 300 is depicted that includes an error correction system 302 configured to correct or minimize errors in the form of polynomial errors produced by an ADC 304. The system 300 includes an input 306 configured to receive an analog input signal. The system 300 is configured to convert the analog input signal into an output digital stream (e.g., which may include a stream of digital bit values ​​or digital words or multi-bit values) at an output 308. The magnitude of the values ​​of the output digital data stream is equivalent to the corresponding magnitude of the analog input signal.

[0062] In system 300, ADC 304 is configured to periodically (eg, at a sampling rate and with a frequency f s ) measures or samples the magnitude of the analog input signal and converts the analog value into a corresponding digital value that is output at the output terminal 310 of the ADC 304. If the ADC 304 is an ideal ADC device, the magnitude of the output digital value 'x' will be the same as the analog input signal x. a or x analog However, in practice, as described above, ADC 304 may generate errors, so that the size of the digital output value is not exactly equal to the sampled size of the analog input signal. Specifically, ADC 304 introduces polynomial nonlinearity or distortion to the output digital value at the output terminal, so that the output value is not equal to x, but equal to x+ax 2 +bx 3 + ... (that is, the output contains the form ax 2 +bx 3 + ... distortion). Therefore, it is necessary to provide a method that can introduce a distortion equal to -ax to the output of ADC 304. 2 +-bx 3 + Error correction of ... Error correction system.

[0063] Thus, system 300 includes an error correction system 302. In the depicted embodiment, error correction system 302 is configured to provide error correction to correct for quadratic errors (ie, x) contained in the output of ADC 304. 2 ) and the cubic (i.e., x 3 ) error signal, but it should be understood that Figure 5The error correction method depicted in can be used to provide correction for higher-order errors, such as those of the form cx 4 、dx 5 or higher error.

[0064] The error correction system 302 includes a multiplier 312 (which may be implemented as a quadratic function performed with respect to a single copy of the signal received from the ADC 304). The multiplier 312 is configured to receive as input two copies of the output signal of the ADC 304. The multiplier 312 is configured to multiply the two copies to produce a signal equivalent to (x+ax 2 +bx 3 …) 2 =x 2 +ax 3 +bx 4 +a 2 x 4 The output signal is the same as that of x+ax. 2 +ax 3 In the case of , the term 'x' dominates), after the quadratic, the term x 2 Next, if the optimizer finds a coefficient '-a', it can generate a -ax that includes the dominant 2 component and much smaller output of other components, which can be used as the correction ax 2 However, in various embodiments, multiplier 312 may be configured to output a signal that is an Nth-power version of the digital signal output by ADC 304, where the Nth-power version of digital signal x is equal to the digital signal multiplied by itself N times, where N is an integer equal to or greater than 2.

[0065] The error correction system 302 includes a multiplier 314 (which may be implemented as a cubic function performed with respect to a single copy of the signal received from the ADC 304). The multiplier 314 is configured to receive as input three copies of the output signal of the ADC 304. The multiplier 314 is configured to multiply the three copies to produce a cubic error signal bx equivalent to the output of the ADC 304. 3 However, in various embodiments, the multiplier 314 may be configured to output a signal that is an Nth-power version of the digital signal output by the ADC 304, where the Nth-power version of the digital signal x is equal to the digital signal multiplied by itself N times, where N is an integer equal to or greater than 2.

[0066] The error correction system 302 is configured to process the two input signals (e.g., by applying a suitably configured loss function) to determine the values ​​of the coefficients a and b in the input error signal. The error correction system 302 outputs the additive inverses (inverse solutions) of those values ​​(i.e., -a and -b) at output terminals 316 and 318, respectively. The output at terminal 316 (i.e., -a) is multiplied by multiplier 320 with the quadratic input signal to produce the product represented by the term -ax 2 The dominant output signal is added to the output of ADC 304 via summing node 322 to correct or remove the quadratic error term in the output of ADC 304.

[0067] Similarly, the output at terminal 318 is multiplied by the cubic input signal via multiplier 324 to produce the term -bx 3 The dominant output signal is summed with the output of ADC 304 via summing node 322 to correct or remove the cubic error term in the output of ADC 304.

[0068] By providing the quadratic and cubic outputs of ADC 304 to error correction system 302, error correction coefficients may be calculated using a numerical optimizer or a neural network. Specifically, because error correction system 302 knows the form of the polynomial error generated by ADC 304 (i.e., the polynomial function), the process of determining the values ​​of the error correction coefficients and thereby removing nonlinearities may be simpler because the relationship between the quadratic and cubic inputs to error correction system 302 and the outputs of error correction system 302 (i.e., the error correction coefficient values) is relatively simple to determine.

[0069] exist Figure 5 In the example presented, only the 2nd and 3rd order components are provided to the input of the error correction system 302, but the same principles can be used to provide error correction for higher order error signals. Within the system 300, the various multiplication operations performed by blocks 312, 314, 320, and 324 can be performed by a mathematical processor, or, where the number of potential values ​​in the output signal of the ADC 304 is relatively low, the multiplication can be achieved via a lookup operation that does not perform a multiplication operation but rather accesses a data table that maps input values ​​to multiplication results.

[0070] Figure 6An ADC system 400 is depicted that includes an error correction system 402 configured to correct or minimize errors in the form of polynomial errors generated by a delta-sigma ADC 404. Specifically, the delta-sigma ADC 404 includes an input 452 configured to receive an analog input signal. The input signal is passed through a summing node 454 to an integrator 456 having a transfer function H1. The output of the integrator 456 is supplied to a quantizer 458 that is configured to convert the summed analog input signal into digital values ​​that are output as a digital bit stream at an output 460. In an ideal delta-sigma ADC 404, the output digital bit stream contains values ​​equal to the corresponding magnitude of the analog input signal.

[0071] The digital bit stream output by the delta-sigma ADC 404 at the output 460 is also passed back through the digital-to-analog converter 462, which is configured to convert the digital bit stream into a corresponding analog signal. Ideally, the analog signal produced by the digital-to-analog converter 462 accurately matches the input signal originally received at the input 406.

[0072] The analog output of the digital / analog converter 462 is supplied to the negative input of the summing node 454, so that the analog signal output by the digital / analog converter 462 is subtracted from the analog input signal. The result of the subtraction is supplied to the analog integrator 456. In this way, the delta-sigma ADC 404 is configured to generate a digital output bit stream having an average power level that matches the power level of the analog input signal of the modulator. However, in real-world applications of the delta-sigma ADC 404, nonlinearities in the modulator components can cause distortion to be introduced into the output of the delta-sigma ADC 404.

[0073] In one example, the D / A converter 462 exhibits some nonlinearity, such that the output of the D / A converter 462 includes some distortion. Figure 6 As shown in FIG. 4 , the output signal of the digital / analog converter 462 includes a signal in the form of ax 2 +bx 3 + polynomial nonlinear components of ... These additional distortion components can fold high frequency spectral components back to baseband due to intermodulation, reduce the noise shaping benefits of the delta-sigma modulator implementation, and increase the noise level at frequencies near the frequency of the signal output by the modulator.

[0074] The system 400 includes an input 406 configured to receive an analog input signal. The system 400 is configured to convert the analog input signal into an output digital bit stream at an output 408. The magnitude of the values ​​in the output digital data stream is equivalent to the corresponding magnitude of the analog input signal.

[0075] In system 400, sigma-delta ADC 404 is configured to periodically (eg, at a sampling rate and with a frequency f s ) or continuously measures or samples the magnitude of the analog input signal and converts the analog value into a corresponding digital value that is output as a bit stream (BS) (also referred to as signal x) at the output terminal 410 of the delta-sigma ADC 404. The output bit stream BS is filtered by a digital filter 411 and is output as a filtered output bit stream signal BS. F Output. Filter 411 is typically configured as a low pass filter, but may also be a high pass filter or a band pass filter. In some embodiments, filter 411 may be configured to include a delay element configured to compensate for signal delays present within error correction system 402 (or a separate delay element may be positioned between filter 411 and summing node 470).

[0076] To correct errors generated by the sigma-delta ADC 404 (e.g., due to nonlinear errors introduced by the converter 462 of the sigma-delta ADC 404), the system 400 includes an error correction system 402. In the depicted embodiment, the error correction system 402 is configured to provide error correction to correct for quadratic errors (i.e., x) generated by the components of the sigma-delta ADC 404. 2 ) and the cubic (i.e., x 3 ) error signal, but it should be understood that Figure 6 The error correction method described in can be used to correct higher-order errors, such as fourth-order errors of the form (cx 4 ), fifth-order error (dx 5 ) or higher.

[0077] To approximate those quadratic and cubic error signals, the error correction system 402 includes a multiplier 412. The multiplier 412 is configured to receive as input two copies of the output signal bit stream BS of the delta-sigma ADC 404. The multiplier 412 is configured to multiply the two copies to generate an output signal BS 2 , which is equivalent to the quadratic error signal ax that may be generated by the components of the delta-sigma ADC 404 2. Next, the output signal of the multiplier 412 passes through a filter 464 configured to filter out unwanted frequencies in the output of the multiplier 412. In a typical application, the filter 464 is configured as a low pass filter, but in other embodiments, the filter 464 may be implemented as a band pass filter. In various embodiments, the filter 464 has a cutoff frequency to block signals having a frequency greater than the frequency of the decimation filter contained within the delta-sigma ADC 404. Thus, the filter 464 may be configured to filter or attenuate (i.e., reduce the size of) signals having frequencies outside the target bandwidth of the delta-sigma ADC 404. However, in various embodiments, the multiplier 412 may be configured to output a signal that is an Nth power version of the digital signal output by the delta-sigma ADC 404, where the Nth power version of the digital signal x is equal to the digital signal multiplied by itself N times, where N is an integer equal to or greater than 2.

[0078] The error correction system 402 includes a multiplier 414. The multiplier 414 is configured to receive as input three copies of the output signal bit stream BS of the delta-sigma ADC 404. The multiplier 414 is configured to multiply the three copies to generate an output signal BS. 3 , which is equivalent to the cubic error signal ax that may be generated by the components of the delta-sigma ADC 404 3 . The output signal of multiplier 414 then passes through a filter 466 configured to filter out unwanted frequencies in the output of multiplier 412. In a typical application, filter 466 is configured as a low pass filter, but in other embodiments, filter 466 may be implemented as a band pass filter. In various embodiments, filter 466 has a cutoff frequency to block signals having a frequency greater than the frequency of a decimation filter contained within sigma delta ADC 404. Thus, filter 466 may be configured to filter or attenuate frequencies outside of the target bandwidth of sigma delta ADC 404. Within system 400, the various multiplication operations performed by multipliers 412 and 414 may be performed by a mathematical processor, or because the potential values ​​in the output signal of sigma delta ADC 404 are relatively low, the multiplication may be implemented via a lookup operation that does not directly perform the multiplication operation but rather accesses a data table that maps input values ​​to multiplication results. However, in various embodiments, the multiplier 414 can be configured to output a signal that is an Nth-power version of the digital signal output by the delta-sigma ADC 404, where the Nth-power version of the digital signal x is equal to the digital signal multiplied by itself N times (i.e., the signal raised to the Nth power), where N is an integer equal to or greater than 2.

[0079] The filtered outputs of filter 464 and filter 466 are supplied as inputs to neural network 468 as filtered signals BS 2 F and BS 3F The neural network 468 is configured to determine corresponding correction values ​​to minimize the loss function of the network so that nonlinear components contained in the output of the delta-sigma ADC 404 can be offset by the correction signal. In a specific embodiment (e.g., where the neural network 468 is extremely simple and does not compensate for PVT nonlinearities), the neural network 468 can be configured to process the two input signals (e.g., by applying a suitably configured loss function) to directly determine the values ​​of the coefficients a and b in the input error signal and output a suitable error correction signal ε at the output terminal 416.

[0080] The output of the neural network 468 at terminal 416 (ie, the error correction signal ε) is obtained from the filtered output bit stream BS of the sigma-delta ADC 404 at the summing node 470. F The polynomial error term in the output of the delta-sigma ADC 404 is subtracted from the output of the delta-sigma ADC 404, thereby correcting or removing the polynomial error term.

[0081] The corrected signal is output at output 408 of system 400 .

[0082] Depend on Figure 6 The correction provided by the neural network 468 depicted in FIG. 4 is configured to correct the 2nd and 3rd order distortion components present in the output bit stream BS of the delta-sigma ADC 404. Specifically, the output of the delta-sigma ADC 404, which is affected by the distortion generated by the digital-to-analog converter 462 and is in the form of polynomial distortion, is quadratically and cubically transformed and passed through filters 464 and 466 to filter out frequency bands of no interest in the quadratic and cubic signals. The neural network 468 then uses the filtered quadratic and filtered cubic bit stream inputs (i.e., BS2 F and BS3 F ) to predict the filtered bit stream (BS F ) within a polynomial error (or at least quadratic and cubic error signals) and applying corresponding error compensation at the output of system 400 to provide a corrected output signal.

[0083] In various embodiments, neural network 468 may be trained to provide additional error correction for other sources of error that may exist within sigma-delta ADC 404 or other components of system 400 .

[0084] For example, the performance and accuracy of the sigma-delta ADC 404 may be affected by process-voltage-temperature (PVT) factors that affect the output of the sigma-delta ADC 404. Among these types of variations, process variations account for deviations in the semiconductor manufacturing process of the components of the sigma-delta ADC 404. Process variations may be due to changes in manufacturing conditions such as temperature, pressure, and dopant concentration. The various voltages utilized within the various ICs that make up the system 400 (e.g., supply voltages, reference voltages, bias conditions on the device) may vary from established design values ​​during daily operation and over their lifetime, which may affect the operation of the circuit components of the sigma-delta ADC 404. Similarly, temperature fluctuations may affect the operating parameters of the various circuit components while the device is operating.

[0085] Thus, one or more sensors 418 measuring one or more PVT variables may optionally be incorporated into the system 400 to provide PVT parameters to the neural network 468 so that the neural network 468 can adjust the value of the error correction signal ε to correct for PVT variations. Thus, the neural network 468 may be trained with a cost function that takes into account the effect of PVT on the errors caused by such processing inputs for use in adjusting weights and / or biases within the nodes of the neural network 468.

[0086] According to various embodiments of the present disclosure, any type of process-related information may be added as PVT input to the neural network 468, such as various technology parameters (e.g., electron mobility, transistor parameters (e.g., Vt, fT, β, doping), resistor parameters (e.g., nominal resistor value, voltage dependency), or capacitor parameters (e.g., nominal capacitor value, voltage dependency). As long as there is a way to measure the process-related parameters, the output of this measurement may be provided as the PVT input to the neural network 468.

[0087] During operation of the system 400, the neural network 468 is configured to generate a signal based on the quadratic and cubic input bit streams (BS 2 F and BS 3 F) to determine an error correction signal ε configured to compensate for nonlinearities in the output of the delta-sigma ADC 404. Given this relatively straightforward mathematical operation, it may not be necessary to use a neural network 468 to implement the error correction system 402, and the neural network 468 may be replaced by a more conventional mathematical function. However, when multiple sources of distortion are present simultaneously, such as when the system 400 includes one or more PVT sensors 418 configured to provide PVT parameters to the error correction system 402 so as to enable correction of PVT-induced errors or other types of complex errors (e.g., inter-symbol interference, imperfect stability in the circuit, mismatch of circuit components, etc.), those errors may be more complex in form, requiring a more complex solution, such as a neural network.

[0088] The neural network 468 of the system 400 can be trained by using known training data according to known techniques for training neural networks. For example, according to certain embodiments of the present disclosure, a known analog input signal can be supplied at the input 406 of the system 400. The known analog input signal, when processed by the ideal ADC, causes the ideal ADC to produce a known output bit stream. In the configuration, the neural network 468 can then be trained by an error signal, which is equivalent to the difference between the output digital bit stream produced by the delta-sigma ADC 404 and the known output bit stream. The error signal generated is passed through a cost function that can be used to train the neural network 468 (e.g., using a Levenberg-Marquardt algorithm, a back propagation (gradient descent) algorithm, or a similar algorithm). In the method, back propagation calculates the gradient of the weight space of the feedforward neural network with respect to the loss function. Using back propagation, the computational parameters (e.g., weights and / or biases) of the neural network 468 are adjusted (e.g., following the steepest descent method, also known as gradient descent).

[0089] However, it will be apparent to one of ordinary skill in the art that any suitable cost function and training algorithm may be used to train the neural network 468. The training phase may be performed continuously or repeatedly until the output bit stream of the delta-sigma ADC 404 has minimal error (or at least desirably a set of fewer errors) compared to the known output bit stream after the training phase is completed.

[0090] Figure 7 Describes the implementation Figure 6 The neural network 500 is a functional neural network 468. The neural network 500 includes an input 502 configured to receive a signal transmitted by an ADC (e.g., Figure 6 The delta-sigma ADC 404 or Figure 5 The ADC 304 generates a filtered quadratic version of the bit stream BS 2 FNeural network 500 includes an input 504 configured to be fed by an ADC (e.g., Figure 6 The delta-sigma ADC 404 or Figure 5 The ADC 304 generates a filtered cubic version of the bit stream BS 3 F .

[0091] Inputs 502 and 504 are connected to a first layer 506 having neurons 508, 510, and 512. Each neuron 508, 510, and 512 is configured to implement an activation function such that when the input signal to the neuron falls below a certain threshold, the output of the neuron is a default value. However, when the input to the neuron exceeds the threshold or activation level, the output of the neuron is a linear function of the input value. In some embodiments, the linear function is configured to cause the neuron to output a copy of the input signal if the input signal exceeds the activation threshold. Thus, neurons 508, 510, and 512 can be implemented as rectified linear units (ReLUs), but it will be clear to one of ordinary skill in the art that other neuron configurations can be utilized.

[0092] Each neuron 508, 510, and 512 receives and sums weighted versions of the quadratic and cubic signals received at inputs 502 and 504. Based on those summed values ​​and the neuron's respective activation function, the neurons 508, 510, and 512 generate output values. In some cases, the neurons 508, 510, and 512 can be configured to implement biases that can modify the output of each neuron 508, 510, and 512.

[0093] The second layer 514 of the neural network 500 includes neurons 516 and 518. Each neuron 516 and 518 is configured to implement an activation function so that when the input signal of the neuron falls below a certain threshold, the output of the neuron is a default value. However, when the input of the neuron exceeds the threshold or activation level, the output of the neuron is a linear function of the input value. In some embodiments, the linear function is configured to cause the neuron to output a copy of the input signal if the input signal exceeds the activation threshold. In some cases, the neurons 516 and 518 can be configured to implement biases that can modify the output of each neuron 516 and 518.

[0094] Thus, neurons 516 and 518 may be implemented as rectified linear units (ReLUs), although it will be apparent to one of ordinary skill in the art that other neuron configurations may be utilized.

[0095] Each neuron 516 and 518 receives and sums the weighted outputs of each neuron 508, 510, and 512 in the previous layer 506. Based on those summed values ​​and the neuron's respective activation function, the neurons 516 and 518 generate output values.

[0096] The output node 520 of the neural network 500 is a neuron configured to implement a linear activation function so that the output of the output node 520 is the sum of the two input signals. Therefore, the output node 520 receives the weighted outputs of each neuron 516 and 518 in the layer 514 and sums them, and based on the summed value, generates an output equivalent to the error correction signal ε. As described herein, the error correction signal can be used to correct the ADC output BS that can be generated by nonlinearity in the ADC F The error in .

[0097] Although neural network 500 is described as being implemented by ReLU neurons, it should be clear to one of ordinary skill in the art that different neural network configurations may be utilized. Therefore, it is expressly contemplated that neural network 500 may be implemented using other neural network or machine learning structures, such as perceptron networks, feedforward neural networks, convolutional neural networks, recurrent neural networks, and the like. One or more neurons of network 500 may be configured to perform any suitable activation, such as a hyperbolic tangent activation function, depending on the system implementation.

[0098] exist Figure 5 In the depicted configuration, neural network 500 is configured to process quadratic and cubic input bit streams to determine appropriate error correction values ​​ε. Given this goal of the neural network, in some embodiments, the functionality of neural network 500 may be provided by other circuit structures or computational models, where a specific neural network implementation may not be required, i.e., a simpler solution may suffice. However, when multiple sources of distortion are simultaneously present in the ADC output (e.g., inter-symbol interference, imperfect stability in the circuit, mismatch of circuit components, etc.), these relationships become much more complex, and such simpler solutions will no longer suffice. Furthermore, given a circuit implementation in which the ADC error is at least partially determined by PVT parameters, there may be extremely complex dependencies between nonlinear distortion sources in the ADC output that may be difficult to determine and correct through purely mathematical (i.e., non-machine learning) methods.

[0099] Figure 8 Describing the error correction system (e.g., Figure 5 The error correction system 302 or Figure 6 The error correction system 402 is implemented to provide an ADC (eg, Figure 5 ADC 304 or Figure 6The invention provides a method for error correction of the output signal of the delta-sigma ADC 404. In step 610, the output signal x of the ADC is received. As described above, the signal x is generally in the form of an output digital bit or code stream generated by the ADC. At step 620, a quadratic version of the output signal x is determined. Optionally, step 620 may also include receiving a cubic version of the output signal x. In yet another embodiment, step 620 may include receiving a high-order version (e.g., fourth order, fifth order, or higher order) of the output signal x of the ADC.

[0100] The received signal at step 620 is supplied to a neural network (e.g., Figure 6 A neural network 468) or another processing system can be used to determine, in step 630, a correction value configured to cancel the error signal present in the signal received in step 620 using the techniques described herein.

[0101] In step 640, the correction value is applied to the digital signal x to generate a corrected digital signal to compensate for the analog-to-digital conversion error present in the ADC. The corrected signal can then be output at an appropriate device output (e.g., Figure 5 The output terminal 308 or Figure 6 The output is output at the output terminal 408).

[0102] To illustrate the noise reduction benefits of the present disclosure, Fig. 9 Describe the frequency domain output signal of an ideal delta-sigma ADC. Fig. 9 As shown in , the output signal includes a region of noise 702 that has high frequencies and can be filtered from the output signal of an ideal ADC as described herein. In addition, the noise floor on the portion of the output signal 704 that contains the actual output of the ideal ADC is relatively low and does not include IM or noise products. In contrast, Fig.10 Figure 1 depicts the frequency domain output signal of a non-ideal delta-sigma ADC where no error correction is performed. Fig.10 As depicted in , there is still a lot of noise in the high frequency range 706 of the non-ideal sigma-delta ADC, but the noise has been folded back into the spectrum of interest, resulting in several large IM products and other noise artifacts 708.

[0103] In order to Fig.10 The uncorrected output signal is compared to the one depicted in Fig.11 1 depicts the frequency domain output signal of a delta-sigma ADC in which error correction according to the present disclosure has been performed. Fig.11 As shown in FIG, the output signal includes high frequency noise 710. However, after correction, Fig.10 The IM products and noise artifacts observed in the uncorrected output signal have been removed and are not present in the portion 712 of the output signal containing the data output of the ADC.

[0104] As described herein, various embodiments of the present disclosure implement error correction systems configured to compensate for ADC errors in ADC devices, such as Nyquist and delta-sigma ADC devices. Such error correction systems may include neural networks implemented in hardware and / or software, such as implemented in one or more data processing systems. However, the functionality described herein is not limited to implementation into any particular hardware / software platform.

[0105] Those skilled in the art will appreciate that aspects of the present disclosure may be embodied as systems, processes, methods, and / or program products. Thus, aspects of the present disclosure (e.g., a machine learning system) may take the form of an all-hardware embodiment, an all-software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may generally be referred to herein as a "circuit," "circuitry," "module," or "system." Additionally, aspects of the present disclosure may take the form of a program product embodied in one or more computer-readable storage media having computer-readable program code embodied thereon. (However, any combination of one or more computer-readable media may be utilized. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium.)

[0106] A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, biological, atomic or semiconductor system, device, controller or apparatus, or any suitable combination of the above, wherein the computer-readable storage medium is not a transient signal itself. More specific examples of computer-readable storage media (a non-exhaustive list) may include the following: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory ("RAM"), a read-only memory ("ROM"), an erasable programmable read-only memory ("EPROM" or flash memory), an optical fiber, a portable compact disc read-only memory ("CD-ROM"), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the context of this article, a computer-readable storage medium may be any tangible medium in which a program for use by or in conjunction with an instruction execution system, device, controller or apparatus may be contained or stored. The program code embodied on a computer-readable signal medium may be transmitted using any appropriate medium, including but not limited to wireless, wires, fiber optic cables, RF, etc., or any suitable combination of the above.

[0107] A computer readable signal medium may include a propagated data signal in which a computer readable program code is embodied, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, device, controller, or apparatus.

[0108] The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of circuit systems, systems, methods, processes, and program products according to various embodiments of the present disclosure. In this regard, certain blocks in the block diagrams (e.g., error correction system 302, neural network 468, and / or neural network 500) may represent modules, segments, or portions of code, including one or more executable program instructions for implementing a specified logic function. It should also be noted that in some embodiments, the functions shown in the blocks may not appear in the order shown in the figures. For example, in fact, two blocks shown in succession may be executed substantially in parallel, or the blocks may sometimes be executed in reverse order, depending on the functions involved.

[0109] The module implemented in software for being executed by various types of processors may, for example, include one or more physical or logical blocks of computer instructions, which may, for example, be organized as objects, processes or functions. However, the executable program of the identified module does not need to be physically located together, but may include different instructions stored in different locations, which include the module and realize the purpose of the module when logically connected together. In fact, the module of executable code may be a single instruction or multiple instructions, and may even be distributed on several different code segments, between different programs and between several memory devices. Similarly, operational data (e.g., the knowledge base of adaptive weights and / or biases described herein) may be identified in the module and shown herein, and may be embodied and organized in any suitable type of data structure in any suitable form. Operational data may be collected as a single data set, or may be distributed in different locations, including on different storage devices. Data may provide electronic signals on a system or network.

[0110] These program instructions may be provided to a general purpose computer, one or more processors and / or controllers of a special purpose computer or other programmable data processing devices (e.g., a controller) to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices create a circuit system or method for implementing the functions / actions specified in one or more blocks of the block diagram.

[0111] It should also be noted that each block of the block diagram and combinations of blocks in the block diagram can be implemented by a dedicated hardware-based system (e.g., which may include one or more graphics processing units) or a combination of dedicated hardware and computer instructions that performs the specified functions or actions. For example, the modules (e.g., error correction system 302, neural network 468, and / or neural network 500) can be implemented as hardware circuits, including custom VLSI circuits or gate arrays, off-the-shelf semiconductors (e.g., logic chips, transistors, controllers, or other discrete components). The modules (e.g., error correction system 302, neural network 468, and / or neural network 500) can also be implemented in programmable hardware devices, such as field programmable gate arrays, programmable array logic, programmable logic devices, dedicated ICs, microcontrollers, systems on chips, general-purpose processors, microprocessors, etc.

[0112] Computer program code, i.e., instructions, for performing operations of various aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, Python, C++, conventional procedural programming languages ​​such as the "C" programming language or similar programming languages, or any of the machine learning software disclosed herein.

[0113] These program instructions may also be stored in a computer-readable storage medium, which may direct a computer system, other programmable data processing device, controller or other apparatus to function in a specific manner so that the instructions stored in the computer-readable medium produce an article of manufacture, which includes instructions for implementing the functions / actions specified in one or more blocks of the block diagram.

[0114] The program instructions may also be loaded onto a computer, other programmable data processing device, controller or other apparatus to cause a series of operating steps to be executed on the computer, other programmable device or other apparatus to produce a computer-implemented process, so that the instructions executed on the computer, other programmable device or other apparatus provide a process for implementing the functions / actions specified in one or more blocks of the block diagram.

[0115] The preceding detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments.

[0116] As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or detailed description.

[0117] The connecting lines shown in each figure contained herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in the embodiments of this theme. In addition, some terms may also be used only for reference purposes in this article, and are therefore not intended to be restrictive, and the terms "first", "second" and other such numerical terms referring to structures do not mean order or sequence, unless the context clearly indicates.

[0118] As used herein, a "node" refers to any internal or external reference point, connection point, junction, signal line, conductive element, etc. at which a given signal, logic level, voltage, data pattern, current or quantity exists. In addition, two or more nodes may be implemented by one physical element (and two or more signals may be multiplexed, modulated, or otherwise distinguished, even if received or output at a common node).

[0119] The above description refers to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" refers to an element being directly connected (or directly communicating) with another element, and not necessarily being mechanically connected. Similarly, unless otherwise expressly stated, "coupling" refers to an element being directly or indirectly connected (or directly or indirectly communicating, electrically or otherwise) with another element, and not necessarily being mechanically connected. Therefore, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or assemblies may be present in the embodiments of the depicted subject matter.

[0120] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability or configuration of the claimed subject matter in any way. On the contrary, the foregoing detailed description will provide a convenient roadmap for implementing the one or more embodiments described to those skilled in the art. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the scope defined by the claims, and the claims include equivalents and foreseeable equivalents known at the time of filing this patent application.

Claims

1. A system, characterized in that: include: An analog-to-digital converter (ADC), comprising: an input terminal configured to receive an analog input signal, and an output terminal configured to output a digital signal x, wherein the digital signal x comprises a digital approximation of the analog input signal; as well as an error correction system connected to the ADC, the error correction system comprising a first input terminal configured to receive an N-th power version of the digital signal x, where N is an integer equal to or greater than two, wherein the error correction system is configured to: determining a correction value using the Nth-power version of the digital signal x; and The digital signal x is modified by applying the correction value to compensate for analog-to-digital conversion errors present in the ADC to generate a corrected digital signal.

2. The system according to claim 1, characterized in that The ADC is a sigma-delta ADC.

3. The system according to claim 2, characterized in that: The delta-sigma ADC is a multi-bit delta-sigma ADC; The error correction system includes a second terminal configured to receive an M-th power version of the digital signal x, where M is an integer equal to or greater than two; and The error correction system is configured to determine the correction value using the M-th power version of the digital signal x.

4. The system according to claim 1, characterized in that The error correction system includes a neural network configured to determine the correction value.

5. A system, characterized in that: include: An analog-to-digital converter (ADC), comprising: an input terminal configured to receive an analog input signal, The summing node is connected to the input terminal, an output terminal configured to output a digital signal x, wherein the digital signal x comprises a digital approximation of the analog input signal, and a digital-to-analog converter electrically connected between the output terminal and the summing node, wherein the digital-to-analog converter is configured to: receiving the digital signal from the output terminal; and The digital signal is converted into a second analog signal, wherein the digital signal x comprises a 2 +bx 3 + a polynomial error signal of the form ...; and an error correction system connected to the ADC, the error correction system comprising: a first input terminal configured to receive a quadratic version of the digital signal x, and A neural network configured as: determining a correction value using the quadratic version of the digital signal x; and The digital signal x is modified to generate a corrected digital signal by applying the correction value to the digital signal x to compensate for the polynomial error signal generated by the digital-to-analog converter.

6. The system according to claim 5, characterized in that Also included is a sensor configured to provide a parameter to the neural network, wherein the output of the ADC varies as a function of a value of the parameter, and the parameter includes at least one of a process parameter, a voltage parameter, and a temperature parameter.

7. The system according to claim 5, characterized in that The ADC has a first bandwidth and further includes a filter connected between the first input of the error correction system and the neural network, wherein the filter is configured to attenuate signals having frequencies outside a second bandwidth.

8. A method, characterized in that include: receiving a digital signal x from an analog-to-digital converter (ADC) configured to receive an analog input signal and output a digital signal x, wherein the digital signal x comprises a digital approximation of the analog input signal; receiving an Nth-power version of the digital signal x, where N is an integer equal to or greater than two; determining a correction value using the Nth-power version of the digital signal x; as well as The digital signal x is modified by applying the correction value to compensate for analog-to-digital conversion errors present in the ADC to generate a corrected digital signal.

9. The method according to claim 8, characterized in that The ADC is a sigma-delta ADC.

10. The method according to claim 9, characterized in that The delta-sigma ADC is a multi-bit delta-sigma ADC, and the method further comprises: receiving an M-th power version of the digital signal x, where M is an integer equal to or greater than two; and The correction value is determined using the M-th power version of the digital signal x.

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