Input signal processing device and method, and test system
By delaying the signal first and then sampling it, the problem of high design complexity in traditional technology is solved, and the input signal processing is realized using a general-purpose chip to dynamically adjust the sampling time, reducing the design complexity and improving the Efficiency.
Patent Information
- Application Number
- CN202310713038.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-27
AI Technical Summary
The traditional Timing Generator controls the sampling time of the input signal in chip testing, which requires a dedicated IC, resulting in high design complexity and inability to implement it using a general-purpose chip.
The comparison signal is delayed first and then sampled. The input signal delay module delays the comparison signal, and then the input signal sampling module samples according to the set sampling time. Finally, the comparison processing module analyzes and determines the actual sampling value and combines the Preset value comparison realizes signal processing function without changing the driving clock phase.
It reduces the design complexity, enables the use of a general-purpose chip to implement input signal processing, dynamically adjusts sampling time, and improves design flexibility and efficiency.
Smart Images
Figure CN119210445A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of signal processing technology, and in particular to an input signal processing device, method and test system. Background Art
[0002] Timing Generator (TG) is an important component of the tester, responsible for synthesizing the output waveform according to the user's requirements and sampling the input signal according to the sampling time configured by the user. When the traditional Timing Generator is testing the chip, the control of the sampling time of the input signal is achieved by adjusting the clock phase, and a dedicated IC (Integrated Circuit) must be used, and the implementation structure is complex, which has the disadvantage of high design complexity. Summary of the invention
[0003] Based on this, it is necessary to provide an input signal processing device, method and test system that can reduce the design complexity in order to address the above problems.
[0004] An input signal processing device, comprising:
[0005] An input signal delay module, connected to the PE module, for delaying the comparison signal output by the PE module to obtain a delayed comparison signal;
[0006] An input signal sampling module, connected to the input signal delay module, for sampling the delayed comparison signal according to a set sampling time to obtain a sampling signal;
[0007] The comparison processing module is connected to the input signal sampling module and is used to determine the actual sampling value according to the sampling signal analysis, and to compare and judge the actual sampling value with a preset expected value to obtain a comparison result.
[0008] In one embodiment, the input signal processing device further comprises:
[0009] An input configuration module is connected to the input signal delay module and is used to set the delay time of the input signal delay module according to a set sampling time.
[0010] In one embodiment, the comparison signal output by the PE module includes two output signals; the input signal delay module includes a first delay unit and a second delay unit, and the input signal sampling module includes a first signal sampling unit and a second signal sampling unit;
[0011] Among them, the set sampling time of the first signal sampling unit and the second signal sampling unit is the same, the first delay unit is connected to the PE module, the first signal sampling unit and the input configuration module, the second delay unit is connected to the PE module, the second signal sampling unit and the input configuration module, and the comparison processing module is connected to the first signal sampling unit and the second signal sampling unit.
[0012] In one embodiment, the first delay unit and the second delay unit are CARRY modules, which include a CARRY unit, a data selector and a tap setting unit. The number of the CARRY units is at least two, and the CARRY units are connected in series in sequence. The CARRY unit at the head end is connected to the PE module, and the CARRY unit at the end is correspondingly connected to the first signal sampling unit / the second signal sampling unit; the data selector is connected to the taps of the CARRY units and the tap setting unit.
[0013] In one embodiment, the first delay unit and the second delay unit are IODELAY modules, and the IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit at the head end is connected to the PE module, and the ODELAY unit at the tail end is correspondingly connected to the first signal sampling unit / the second signal sampling unit, and the tap configuration unit connects the IDELAY unit and the ODELAY unit.
[0014] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and a preset expected value to obtain a comparison result and output it.
[0015] In one of the embodiments, the input signal delay module includes at least one of a CARRY module, an IDELAY, an ODELAY and a digital control delay chain chip.
[0016] A method for processing an input signal, comprising:
[0017] The input signal delay module delays the comparison signal output by the PE module to obtain a delayed comparison signal;
[0018] The input signal sampling module samples the delayed comparison signal according to the set sampling time to obtain a sampling signal;
[0019] The comparison processing module determines the actual sampling value according to the sampling signal analysis, and compares and judges the actual sampling value with a preset expected value to obtain a comparison result.
[0020] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges based on the actual sampling value and a preset expected value to obtain a comparison result, including: performing a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performing a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain and output the comparison result.
[0021] In one embodiment, the input signal delay module delays the comparison signal output by the PE module, and before obtaining the delayed comparison signal, it also includes:
[0022] The input configuration module sets the delay time of the input signal delay module according to the set sampling time.
[0023] A test system comprises a PE module and the above-mentioned input signal processing device.
[0024] In one of the embodiments, the PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the input signal delay module.
[0025] The above-mentioned input signal processing device, method and test system first delay the comparison signal output by the PE module through the input signal delay module to obtain the delayed comparison signal, and then sample the delayed comparison signal according to the set sampling time through the input signal sampling module to obtain the sampling signal. Finally, the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain the comparison result. By adopting the method of delaying the signal first and then sampling the signal, the sampling time of the input signal can be adjusted without changing the driving clock phase, and a general chip can be used to implement the input signal processing function, reducing the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 is a structural block diagram of a test system in one embodiment;
[0027] Figure 2 is a structural block diagram of an input signal delay module and an input signal sampling module in one embodiment;
[0028] Figure 3 is a flow chart for implementing input signal delayed sampling control in one embodiment;
[0029] Figure 4A schematic diagram of signal conversion of a PE module in one embodiment;
[0030] Figure 5 A schematic diagram of the timing sequence of input signal delay control sampling position in one embodiment;
[0031] Figure 6 A comparison truth table and a comparison processing principle diagram in one embodiment. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0034] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.
[0036] The current Timing Generator controls the sampling time of the input signal by adjusting the clock phase. If you want to sample the chip output signal at different positions, you usually adjust the sampling clock phase first, and then sample the chip output signal. You must design a dedicated chip to implement it, and you cannot use a general FPGA to implement it. In addition, the dedicated chip has a complex structure. Based on this, in order to solve the problem of dynamically switching the sampling position of the input signal, the present application provides an input signal processing device, which first delays the comparison signal output by the PE module through the input signal delay module to obtain the delayed comparison signal, and then samples the delayed comparison signal according to the set sampling time through the input signal sampling module to obtain the sampling signal. Finally, the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain the comparison result. By adopting the method of first signal delay and then signal sampling, there is no need to switch the clock phase, and a general chip can be used to implement the input signal processing function, which reduces the design complexity.
[0037] In one embodiment, Figure 1 As shown, an input signal processing device is provided, including an input signal delay module 220, an input signal sampling module 230 and a comparison processing module 240, the input signal delay module 220 is connected to the PE (Pin Electronics Driver / Comparator) module 210 and the input signal sampling module 230, and the input signal sampling module 230 is connected to the comparison processing module 240.
[0038] Among them, the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value, and outputs the comparison signal to the input signal delay module 220. The device under test DUT can be a chip under test or other devices. The input signal delay module 220 is used to delay the comparison signal output by the PE module 210 to obtain the delayed comparison signal; the input signal sampling module 230 is used to sample the delayed comparison signal according to the set sampling time to obtain the sampling signal; the comparison processing module 240 is used to determine the actual sampling value according to the sampling signal analysis, and compare and judge according to the actual sampling value and the preset expected value to obtain the comparison result. Specifically, the delay time of the input signal delay module 220 is not unique, and can be set according to the sampling time of the input signal sampling module 230. Further, the input signal processing device also includes an input configuration module 250, which is connected to the input signal delay module 220 and is used to set the delay time of the input signal delay module 220 according to the set sampling time. The input configuration module 250 determines the actually required delay time according to the set sampling time, determines the input delay value and configures the input signal delay module 220 according to the actually required delay time and the correspondence between the delay time and the delay value.
[0039] It can be understood that the specific structure of the input signal delay module 220 is not unique, and can be a combination of one or more of the IDELAY (input delay unit), ODELAY (output delay unit) and CARRY modules. Specifically, the signal delay function of the input signal delay module 220 can be implemented through dedicated resources such as IDELAY, ODELAY, and CARRY inside the FPGA. In other embodiments, the input signal delay module 220 can also use general resources, such as a lookup table to implement signal delay, or use a CNC delay chain chip to implement signal delay. When the input signal delay module 220 uses IDELAY, ODELAY or CARRY, the input delay value configured by the input signal delay module 220 is specifically a tap value.
[0040] The way in which the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value is not unique. In one embodiment, the preset level threshold value includes a threshold value VOH and a threshold value VOL. The values of the threshold value VOH and the threshold value VOL are not unique and can be set according to actual needs, as long as the threshold value VOH is greater than the threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. The output signal of the PE module 210 is delayed by the input signal delay module 220, and the delayed signal is sent to the input signal sampling module 230. The input signal sampling module 230 samples the two input signals based on the main sampling clock frequency according to the set sampling time, and obtains the sampling signal and sends it to the comparison processing module 240. Among them, the delay span of the input signal delay module 220 can cover the clock cycle range, ensuring that any position within the clock cycle can be sampled.
[0041] The above-mentioned input signal processing device first delays the comparison signal output by the PE module 210 through the input signal delay module 220 to obtain the delayed comparison signal, and then samples the delayed comparison signal according to the set sampling time through the input signal sampling module 230 to obtain the sampling signal. Finally, the comparison processing module 240 determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain the comparison result. By adopting the method of delaying the signal first and then sampling the signal, the sampling time of the input signal can be adjusted without changing the driving clock phase, and a general chip can be used to implement the input signal processing function, which reduces the design complexity.
[0042] In one embodiment, Figure 2 As shown, the comparison signal output by the PE module 210 includes two output signals, the input signal delay module 220 includes a first delay unit 222 and a second delay unit 224, and the input signal sampling module 230 includes a first signal sampling unit 232 and a second signal sampling unit 234. The first delay unit 222 is connected to the PE module 210, the first signal sampling unit 232 and the input configuration module 250, the second delay unit 224 is connected to the PE module 210, the second signal sampling unit 234 and the input configuration module 250, and the comparison processing module 240 is connected to the first signal sampling unit 232 and the second signal sampling unit 234.
[0043] The first signal sampling unit 232 and the second signal sampling unit 234 have the same set sampling time, and synchronously perform signal delay and sampling on the two output signals of the PE module 210. Further, the sampling signal includes the first signal and the second signal, and the comparison processing module 240 performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain the comparison result and output it.
[0044] Specifically, the output signal CA and the output signal CB of the PE module 210 are delayed by the first delay unit 222 and the second delay unit 224, respectively. The two delayed signals are sampled by the first signal sampling unit 232 and the second signal sampling unit 234, respectively, and the two sampling signals are sent to the comparison processing module 240. The comparison processing module 240 can analyze the two sampling signals according to the set comparison truth table to determine the actual sampling value, and then compare and judge according to the actual sampling value and the preset expected value, and output the comparison result after obtaining it for data storage or analysis.
[0045] In one embodiment, the first delay unit 222 and the second delay unit 224 may adopt a CARRY module. Specifically, the CARRY module includes a CARRY unit, a data selector and a tap setting unit. The number of CARRY units is at least two, and the cumulative delay span of each CARRY unit covers the clock cycle range. Each CARRY unit is connected in series in sequence, the CARRY unit at the head end is connected to the PE module 210, and the CARRY unit at the end is correspondingly connected to the first signal sampling unit 232 / the second signal sampling unit 234; the data selector connects the taps of each CARRY unit and the tap setting unit, and the tap setting unit is connected to the input configuration module 250. Among them, the CARRY unit can be a CARRY8 unit, which leads to 8 taps connected to the data selector, and the tap setting unit performs delay control on the connected signal according to the tap value configured by the input configuration module 250, and the delayed signal is output through the data selector MUX.
[0046] In one embodiment, the first delay unit 222 and the second delay unit 224 may adopt an IODELAY module. Specifically, the IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit. The number of the IDELAY unit and the ODELAY unit is at least two. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit at the head end is connected to the PE module 210, and the ODELAY unit at the tail end is correspondingly connected to the first signal sampling unit 232 / the second signal sampling unit 234, and the tap configuration unit is connected to the IDELAY unit, the ODELAY unit and the input configuration module 250. The tap configuration unit performs delay control on the connected signal according to the IDELAY tap value and the ODELAY tap value configured by the input configuration module 250, and the delayed signal is output through the ODELAY unit at the tail end.
[0047] It should be noted that in this embodiment, at least two IDELAY units and ODELAY units are alternately connected in sequence, so that the IDELAY unit\ODELAY unit alternately updates the tap value. In other embodiments, if the sampling position does not need to be adjusted for each sampling process, or the interval between sampling position changes is greater than or equal to 3 clock cycles, it is only necessary for the delay span of the IDELAY unit and the ODELAY unit to cover the clock cycle, and the specific number does not need to be limited.
[0048] In one embodiment, an input signal processing method is also provided, including: an input signal delay module delays the comparison signal output by the PE module to obtain a delayed comparison signal; an input signal sampling module samples the delayed comparison signal according to a set sampling time to obtain a sampling signal; a comparison processing module determines an actual sampling value based on sampling signal analysis, and compares and judges the actual sampling value with a preset expected value to obtain a comparison result.
[0049] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges based on the actual sampling value and a preset expected value to obtain a comparison result, including: performing a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performing a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain and output the comparison result.
[0050] In one embodiment, the input signal delay module delays the comparison signal output by the PE module, and before obtaining the delayed comparison signal, it also includes: the input configuration module sets the delay time of the input signal delay module according to the set sampling time.
[0051] In one embodiment, the input configuration module sets the delay time of the input signal delay module according to the set sampling time, including: determining the actually required delay time according to the set sampling time, determining the input delay value and configuring the input signal delay module according to the actually required delay time and the correspondence between the delay time and the delay value.
[0052] It can be understood that the specific implementation of the above-mentioned input signal processing method has been explained in detail in the above-mentioned input signal processing device, and will not be repeated here.
[0053] In one embodiment, continue to refer to Figure 1 , a test system is also provided, including a PE module 210 and the above-mentioned input signal processing device. Among them, the PE module 210 compares and judges the input signal fed back by the device to be tested according to the preset level threshold value, and outputs the comparison signal to the input signal delay module 220. Further, the preset level threshold value includes a threshold value VOH and a threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB.
[0054] Specifically, Figure 3 As shown, the execution process of delayed sampling of the input signal is as follows:
[0055] 1. The device under test (DUT) generates a signal and feeds it into the PE module 210 .
[0056] 2. The PE module 210 compares and judges the input signal according to the two set comparison threshold values (VOH\VOL), and outputs the required comparison results after comparison: output signal CA and output signal CB. Output signal CA\output signal CB are standard high and low level digital signals, such as Figure 4 When the input signal is less than the threshold value VOL, the output signal CA is low level, and the output signal CB is low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is low level, and the output signal CB is high level; when the input signal is greater than the threshold value VOH, the output signal CA is high level, and the output signal CB is high level.
[0057] 3. According to the set sampling position information, the input configuration module 250 configures the signal delay time.
[0058] 4. The input signal delay module 220 performs delay processing on the signal to ensure that the sampling time of the input signal sampling module 230 is the set time.
[0059] 5. The output signals CA and CB of the PE module 210 are fed into the input signal sampling module 230 after delay. The input signal sampling module 230 samples the two delayed signals according to the set sampling time and transmits the sampling results to the comparison processing module 240. The sampling principle is as follows Figure 5 As shown, Clock is the clock signal, DataIn is the original input signal before signal delay, Sample_Position is the sampling position, DataIn_Delay is the signal after delay, and DataIn_Sample is the sampling signal.
[0060] 6. The sampling signal is input to the comparison processing module 240, which first uses the comparison truth table to determine the actual sampling value according to the state value of the output signal CA\output signal CB, and then uses the actual sampling value to perform parallel comparison and judgment with the expected value, and outputs the corresponding comparison result. The principle of comparison is as follows Figure 6 , and give the corresponding comparison result according to the actual sampling value of the output signal CA\output signal CB.
[0061] By delaying the input signal fed back by the device under test DUT before sampling the signal, the dynamic control signal sampling position is realized. The signal delay does not require the clock phase switching, which reduces the complexity of the design. In addition, the parallel matching truth table method is used to realize the parallel comparison and judgment processing of the signal. It is not necessary to decompose the output signal CA\output signal CB to gradually judge whether the output signal CA is consistent with the expected value, and then judge whether the output signal CB is consistent with the expected value. Instead, the actual value is directly determined by matching and comparing through the table lookup method, and then the actual value and the expected value are matched and compared to analyze whether the output result is consistent with the expectation, and the detection efficiency is high.
[0062] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0063] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. An input signal processing device, characterized in that: include: An input signal delay module, connected to the PE module, for delaying the comparison signal output by the PE module to obtain a delayed comparison signal; An input signal sampling module, connected to the input signal delay module, for sampling the delayed comparison signal according to a set sampling time to obtain a sampling signal; The comparison processing module is connected to the input signal sampling module and is used to determine the actual sampling value according to the sampling signal analysis, and to compare and judge the actual sampling value with a preset expected value to obtain a comparison result.
2. The input signal processing device according to claim 1, characterized in that: Also includes: An input configuration module is connected to the input signal delay module and is used to set the delay time of the input signal delay module according to a set sampling time.
3. The input signal processing device according to claim 1, characterized in that: The comparison signal output by the PE module includes two output signals; the input signal delay module includes a first delay unit and a second delay unit, and the input signal sampling module includes a first signal sampling unit and a second signal sampling unit; Among them, the set sampling time of the first signal sampling unit and the second signal sampling unit is the same, the first delay unit is connected to the PE module, the first signal sampling unit and the input configuration module, the second delay unit is connected to the PE module, the second signal sampling unit and the input configuration module, and the comparison processing module is connected to the first signal sampling unit and the second signal sampling unit.
4. The input signal processing device according to claim 3, characterized in that: The first delay unit and the second delay unit are CARRY modules, which include a CARRY unit, a data selector and a tap setting unit. The number of the CARRY units is at least two, and the CARRY units are connected in series in sequence. The CARRY unit located at the head end is connected to the PE module, and the CARRY unit located at the end is correspondingly connected to the first signal sampling unit / the second signal sampling unit; the data selector is connected to the taps of each CARRY unit and the tap setting unit.
5. The input signal processing device according to claim 3, characterized in that: The first delay unit and the second delay unit are IODELAY modules, and the IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit located at the head end is connected to the PE module, and the ODELAY unit located at the tail end is correspondingly connected to the first signal sampling unit / the second signal sampling unit, and the tap configuration unit connects the IDELAY unit and the ODELAY unit.
6. The input signal processing device according to claim 1, characterized in that: The sampling signal includes a first signal and a second signal. The comparison processing module performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and a preset expected value to obtain and output a comparison result.
7. The input signal processing device according to claim 1, characterized in that: The input signal delay module includes at least one of a CARRY module, an IDELAY, an ODELAY and a digital control delay chain chip.
8. A method for processing an input signal, characterized in that: include: The input signal delay module delays the comparison signal output by the PE module to obtain a delayed comparison signal; The input signal sampling module samples the delayed comparison signal according to the set sampling time to obtain a sampling signal; The comparison processing module determines the actual sampling value according to the sampling signal analysis, and compares and judges the actual sampling value with a preset expected value to obtain a comparison result.
9. The method according to claim 8, characterized in that The sampling signal includes a first signal and a second signal. The comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges based on the actual sampling value and a preset expected value to obtain a comparison result, including: performing a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performing a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain and output the comparison result.
10. The method according to claim 8 or 9, characterized in that: The input signal delay module delays the comparison signal output by the PE module to obtain the delayed comparison signal, and also includes: The input configuration module sets the delay time of the input signal delay module according to the set sampling time.
11. A testing system, characterized in that: It comprises a PE module and the input signal processing device according to any one of claims 1 to 7.
12. The test system according to claim 11, characterized in that: The PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the input signal delay module.