Input signal sampling control device and method, test device and test system

Abstract

The invention relates to an input signal sampling control device and method, a test device and a test system, and the device comprises a signal delay parallel sampling module which is used for carrying out the delay sampling of a signal fed back by a to-be-tested device according to a configured delay parameter, and obtaining a sampling signal; the selection output module is connected with the signal delay parallel sampling module and is used for selectively outputting the sampling signals according to the configured sampling time; and the input configuration module is connected with the signal delay parallel sampling module and the selection output module and is used for setting delay parameters of the signal delay parallel sampling module according to the sampling time. By adopting a mode of first signal delay and then signal sampling selection output, phase switching of a clock is not needed, the signal sampling position can be dynamically changed in a more universal chip, and the design complexity is reduced.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an input signal sampling control device, method, test device and test system. Background Art

[0002] Timing Generator (TG) is an important component of the tester, responsible for synthesizing the output waveform according to the user's requirements and sampling the input signal according to the sampling time configured by the user. When the traditional Timing Generator is testing the chip, the control of the sampling time of the input signal is achieved by adjusting the clock phase, and a dedicated IC (Integrated Circuit) must be used, and the implementation structure is complex, which has the disadvantage of high design complexity. Summary of the invention

[0003] Based on this, it is necessary to provide an input signal sampling control device, method, test device and test system that can reduce the high design complexity in order to address the above problems.

[0004] An input signal sampling control device, comprising:

[0005] A signal delay parallel sampling module is used to perform delay sampling on the signal fed back by the device to be tested according to the configured delay parameters to obtain a sampling signal;

[0006] A selection output module is connected to the signal delay parallel sampling module and is used to select and output the sampling signal according to the configured sampling time;

[0007] An input configuration module is connected to the signal delay parallel sampling module and the selection output module, and is used to set the delay parameter of the signal delay parallel sampling module according to the sampling time.

[0008] In one embodiment, the signal delay parallel sampling module includes a CARRY carry chain and a D-type flip-flop, and the selection output module includes a multiplexer; the CARRY carry chain is connected to the D-type flip-flop, the D-type flip-flop is connected to the multiplexer, and the input configuration module is connected to the CARRY carry chain and the multiplexer.

[0009] In one of the embodiments, the CARRY carry chain includes at least two CARRY units, the number of the D-type flip-flops is the same as the number of the CARRY units, the CARRY units are connected in sequence, each of the D-type flip-flops is respectively connected to a tap of the corresponding CARRY unit, and each of the D-type flip-flops is connected to the multiplexer.

[0010] An input signal sampling control method, comprising:

[0011] The input configuration module sets the delay parameters of the signal delay parallel sampling module according to the sampling time;

[0012] The signal delay parallel sampling module performs delay sampling on the signal fed back by the device to be tested according to the configured delay parameters to obtain a sampling signal;

[0013] The selection output module selects and outputs the sampling signal according to the configured sampling time.

[0014] In one embodiment, the signal delay parallel sampling module includes a CARRY carry chain and a D-type flip-flop, and the selection output module includes a multiplexer; the CARRY carry chain is connected to the D-type flip-flop, the D-type flip-flop is connected to the multiplexer, and the input configuration module is connected to the CARRY carry chain and the multiplexer;

[0015] The selection output module selects and outputs the sampling signal according to the configured sampling time, including: the multiplexer determines the sampling output beat and the corresponding target tap according to the configured sampling time, selects the sampling signal of the target tap in the CARRY carry chain from the D-type trigger, and outputs the sampling signal of the target tap according to the sampling output beat; wherein the sampling signal is obtained by the D-type trigger sampling and caching the output signal of the corresponding tap in the CARRY carry chain according to the clock signal.

[0016] In one of the embodiments, the signal delay parallel sampling module performs delayed sampling on the signal fed back from the device to be tested according to the configured delay parameters, including: utilizing the propagation delay of the CARRY carry chain to cache the signal fed back from the device to be tested, and sampling the signal in the CARRY carry chain according to the clock signal through the D-type trigger.

[0017] A testing device comprises a waveform synthesis module, an output signal delay module and the above-mentioned input signal sampling control device, wherein the waveform synthesis module is connected to the output signal delay module, and the output signal delay module is used to connect to a device to be tested.

[0018] In one of the embodiments, the testing device further comprises an output data source module connected to the waveform synthesis module.

[0019] In one of the embodiments, the testing device further includes an output configuration module, wherein the output configuration module is connected to the waveform synthesis module and the output signal delay module.

[0020] A test system comprises a PE module and the above-mentioned test device, wherein the output signal delay module is connected to the PE module, the PE module is connected to a device to be tested, and the signal delay parallel sampling module is connected to the PE module.

[0021] In one of the embodiments, the PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the signal delay parallel sampling module.

[0022] In one embodiment, the test system also includes a comparison processing module connected to the selection output module, and the comparison processing module is used to determine the actual sampling value based on the sampling signal analysis output by the selection output module, and to compare and judge the actual sampling value with a preset expected value to obtain a comparison result.

[0023] In one embodiment, the comparison processing module performs a table lookup analysis based on the two received sampling signals to determine the actual sampling value, performs a parallel comparison and judgment based on the actual sampling value and a preset expected value, obtains a comparison result and outputs it.

[0024] In the above-mentioned input signal sampling control device, method, test device and test system, the input configuration module sets the delay parameter of the signal delay parallel sampling module according to the sampling time, the signal delay parallel sampling module performs delayed sampling on the signal fed back by the device to be tested according to the configured delay parameter to obtain the sampling signal, and the selection output module selects and outputs the sampling signal according to the configured sampling time. By adopting the method of first delaying the signal and then sampling and selecting the output of the signal, there is no need to switch the phase of the clock, and the signal sampling position can be dynamically changed in a more general chip, reducing the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a structural block diagram of an input signal sampling control device in one embodiment;

[0026] Figure 2 A schematic diagram of the structure of a signal delay parallel sampling module and a selection output module in one embodiment;

[0027] Figure 3 A schematic diagram of a delayed dynamic switching sampling position configuration process in one embodiment;

[0028] Figure 4 is a structural block diagram of a test system in one embodiment;

[0029] Figure 5 A schematic diagram of signal conversion of a PE module in one embodiment;

[0030] Figure 6A comparison truth table and a comparison processing principle diagram in one embodiment. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.

[0035] When the current Timing Generator samples the input signal, it is necessary to dynamically adjust the sampling position according to the sampling result, and the control of the input signal sampling time is achieved by adjusting the clock phase. If you want to sample the chip output signal at different positions, you usually adjust the sampling clock phase first, and then sample the chip output signal. You must design a dedicated chip to implement it. It is impossible to use a general FPGA (Field Programmable Gate Array, Field Programmable Logic Array) to implement it, and the dedicated chip implementation structure is complex. Based on this, the present application provides an input signal sampling control device, in which the input configuration module sets the delay parameter of the signal delay parallel sampling module according to the sampling time, and the signal delay parallel sampling module performs delayed sampling on the signal fed back by the device to be tested according to the configured delay parameter to obtain the sampling signal, and the selection output module selects the sampling signal for output according to the configured sampling time. By adopting the method of first signal delay and then signal sampling and output selection, there is no need to switch the clock phase, and the dynamic change of the signal sampling position can be realized in a more general chip, reducing the design complexity.

[0036] In one embodiment, Figure 1As shown, an input signal sampling control device is provided, including a signal delay parallel sampling module 220, a selection output module 230 and an input configuration module 240, wherein the selection output module 230 is connected to the signal delay parallel sampling module 220, and the input configuration module 240 is connected to the signal delay parallel sampling module 220 and the selection output module 230. The signal delay parallel sampling module 220 is used to perform delay sampling on the signal fed back by the device under test DUT according to the configured delay parameters to obtain a sampling signal; the selection output module 230 is used to select and output the sampling signal according to the configured sampling time; and the input configuration module 240 is used to set the delay parameter of the signal delay parallel sampling module 220 according to the sampling time.

[0037] The device under test DUT may be a chip under test or other devices. It is understood that the structure of the signal delay parallel sampling module 220 is not unique and can be implemented by dedicated resources such as a CARRY carry chain inside the FPGA. Correspondingly, the delay parameter configured by the signal delay parallel sampling module 220 is specifically a tap value. In one embodiment, Figure 2 As shown, the signal delay parallel sampling module 220 includes a CARRY carry chain and a D-type flip-flop DFF (D-type flip-flop), the delay span of the CARRY carry chain needs to cover the clock cycle, and the selection output module 230 includes a multiplexer MUX; the CARRY carry chain is connected to the D-type flip-flop DFF, the D-type flip-flop DFF is connected to the multiplexer MUX, and the input configuration module 240 is connected to the CARRY carry chain and the multiplexer MUX. Among them, the D-type flip-flop DFF is an internal resource of the FPGA, which is used to store digital signals, and each logic block has a total of 8 registers A, B, ..., H. The multiplexer MUX is an internal resource of the FPGA, which is used to select and output multiple signals.

[0038] The CARRY carry chain performs signal delay according to the configured tap value, and the D-type flip-flop DFF samples and caches the output signal of the corresponding tap in the CARRY carry chain according to the clock signal to obtain a sampled signal. The multiplexer MUX determines the sampling output beat and the corresponding target tap according to the configured sampling moment, selects the sampling signal of the target tap in the CARRY carry chain from the D-type flip-flop DFF, and outputs the sampling signal of the target tap according to the sampling output beat. In one embodiment, the CARRY carry chain includes at least two CARRY units 222, the number of D-type flip-flops DFF is the same as the number of CARRY units 222, each CARRY unit 222 is connected in sequence, each D-type flip-flop DFF is respectively connected to the tap of the corresponding CARRY unit 222, and each D-type flip-flop DFF is connected to the multiplexer MUX. The CARRY unit 222 can be a CARRY8 unit, which leads to 8 taps connected to the D-type flip-flop DFF.

[0039] Among them, the propagation delay of the CARRY carry chain can be used to cache the signal fed back by the device under test DUT, and the signal in the CARRY carry chain is sampled according to the clock signal through the D-type flip-flop DFF. Specifically, the signal delay parallel sampling module 220 feeds the signal into the CARRY carry chain, caches the signal of a certain time length into the CARRY carry chain by using the propagation delay of the CARRY, and then uses the D-type flip-flop DFF to sample the signal in the CARRY, and the D-type flip-flop DFF works according to the main frequency clock signal. The series length N of the CARRY carry chain is related to the working main frequency (f) of the D-type flip-flop DFF. Assuming that the propagation delay of each level of the CARRY tap in a group of CARRY8 units is d, it is necessary to ensure that the corresponding time of the signal length cached in the CARRY carry chain is greater than the working cycle of the D-type flip-flop DFF. The principle is equivalent to using the propagation delay of CARRY to increase the sampling frequency. The sampling interval is equivalent to the propagation delay d of each level of CARRY tap. Then, the D-type flip-flop DFF is used to latch the data, and then the multiplexer MUX and the clock beat are used to sample and output the latched sampled data. The D-type flip-flop DFF samples the signal cached in the CARRY carry chain according to the working main frequency. The sampling rate of the sampled registered data stream is equivalent to 1 / d. The multiplexer MUX selects data according to the set sampling time. The data selection is divided into two parts. One part is to directly select the CARRY tap captured by the specific D-type flip-flop DFF in the current clock beat through the multiplexer MUX, and the other part is to output the sampled data according to the beat corresponding to the sampling time.

[0040] Specifically, Figure 3 As shown, the specific execution process of input signal sampling control is as follows:

[0041] 1) The device under test (DUT) outputs the signal to be sampled.

[0042] 2) The signal to be sampled is fed into the CARRY carry chain for buffering. The tap interval time of each CARRY unit determines the maximum sampling rate of the device.

[0043] 3) The D-type flip-flop samples and caches the data cached in the CARRY unit.

[0044] 4) The input configuration module determines the beat of the output sampling signal and the corresponding CARRY tap according to the set sampling time, configures the multiplexer to select the specified CARRY tap output, and outputs the sampling value according to the sampling output beat.

[0045] The above-mentioned input signal sampling control device uses CARRY in the FPGA chip to increase the sampling rate of the signal, and then performs sampling output, thereby adjusting the signal sampling position, and the resolution of adjusting the signal sampling position can reach picoseconds at most. The more common and general FPGA chip is used to realize the function of dynamically changing the signal sampling position, which is no longer limited by the dedicated chip. In addition, a single FPGA chip realizes both the signal sampling position adjustment function and the logic control, and can also save printed circuit board space.

[0046] In one embodiment, an input signal sampling control method is provided, comprising: an input configuration module sets a delay parameter of a signal delay parallel sampling module according to a sampling time; the signal delay parallel sampling module performs delay sampling on a signal fed back by a device to be tested according to the configured delay parameter to obtain a sampling signal; and a selection output module selects and outputs the sampling signal according to the configured sampling time.

[0047] In one embodiment, the signal delay parallel sampling module includes a CARRY carry chain and a D-type flip-flop, and the selection output module includes a multiplexer; the CARRY carry chain is connected to the D-type flip-flop, the D-type flip-flop is connected to the multiplexer, and the input configuration module is connected to the CARRY carry chain and the multiplexer. The selection output module selects and outputs the sampling signal according to the configured sampling time, including: the multiplexer determines the sampling output beat and the corresponding target tap according to the configured sampling time, selects the sampling signal of the target tap in the CARRY carry chain from the D-type flip-flop, and outputs the sampling signal of the target tap according to the sampling output beat. Among them, the sampling signal is obtained by the D-type flip-flop sampling and caching the output signal of the corresponding tap in the CARRY carry chain according to the clock signal.

[0048] In one embodiment, the signal delay parallel sampling module performs delayed sampling on the signal fed back from the device to be tested according to the configured delay parameters, including: utilizing the propagation delay of the CARRY carry chain to cache the signal fed back from the device to be tested, and sampling the signal in the CARRY carry chain according to the clock signal through a D-type trigger.

[0049] It can be understood that the specific implementation of the above-mentioned input signal sampling control method has been explained in detail in the above-mentioned input signal sampling control device, and will not be repeated here.

[0050] In one embodiment, Figure 4As shown, a test device is also provided, including a waveform synthesis module 120, an output signal delay module 130 and the above-mentioned input signal sampling control device, the waveform synthesis module 120 is connected to the output signal delay module 130, and the output signal delay module 130 is used to connect to the device under test DUT. The waveform synthesis module 120 performs waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform; the output signal delay module 130 performs delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform. Further, the test device also includes an output data source module 110 connected to the waveform synthesis module 120, and the output data source module 110 is used to output the original data stream.

[0051] Among them, according to the different output waveforms actually required, the waveform format configured by the waveform synthesis module 120 and the output delay value configured by the output signal delay module 130 will also be different, and can be adjusted according to the actual situation. In one embodiment, the test device also includes an output configuration module 140, which connects the waveform synthesis module 120 and the output signal delay module 130 to configure the waveform format and the output delay value. The tester can configure the waveform format and the output delay value through the output configuration module 140 according to the actual test needs, so that the output waveform control device generates the corresponding output waveform according to the actual needs. After the waveform synthesis module 120 synthesizes the waveform format of the original data stream output by the output data source module 110 according to the configured waveform format, it outputs the synthesized waveform to the output signal delay module 130. The output signal delay module 130 delays the synthesized waveform according to the configured output delay value and the internal clock to obtain the output waveform. The output waveform is used to be transmitted to the device under test DUT to test the device under test DUT. The type of waveform format is not unique, for example, it may include NRZ, RZ, XORBC and other formats.

[0052] It is understandable that the specific structure of the output signal delay module 130 is not unique, and can be a combination of one or more of the IDELAY (input delay unit), ODELAY (output delay unit) and CARRY modules. The delay width of the output signal delay module 130 covers the clock cycle, and the signal delay can be achieved through dedicated resources such as IDELAY, ODELAY, and CARRY inside the FPGA.

[0053] In one embodiment, the output signal delay module 130 includes a CARRY module or an IDELAY\ODELAY module. The CARRY module may include a CARRY unit, a data selector, and a tap setting unit, wherein the delay span of the CARRY unit covers the clock cycle, and the signal edge can be placed at any position within the clock cycle. The number of CARRY units is at least two, and each CARRY unit is connected in series in sequence. The CARRY unit at the head end is connected to the waveform synthesis module 120, and the CARRY unit at the end is used to connect the device to be tested DUT; the data selector connects the taps of each CARRY unit and the tap setting unit, and the tap setting unit is connected to the output configuration module 140. The tap setting unit delays the connected waveform according to the tap value configured by the output configuration module 140, and the delayed waveform is output through the data selector.

[0054] In one embodiment, the output signal delay module 130 includes an IDELAY unit, an ODELAY unit and a tap configuration unit, and the number of the IDELAY unit and the ODELAY unit can be one or at least two. After the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit at the head end is connected to the waveform synthesis module 120, the ODELAY unit at the tail end is used to connect the device to be tested DUT, and the tap configuration unit connects the IDELAY unit, the ODELAY unit and the output configuration module 140. The tap configuration unit delays the connected waveform according to the IDELAY tap value and the ODELAY tap value configured by the output configuration module 140, and the delayed waveform is output through the ODELAY unit at the tail end.

[0055] The above-mentioned test device first synthesizes the waveform format of the original data stream according to the configured waveform format through the waveform synthesis module 120 to obtain a synthesized waveform, and then delays the synthesized waveform according to the configured output delay value through the output signal delay module 130. The output waveform is obtained by first synthesizing the waveform and then delaying it. The output waveform can be obtained without adjusting the driving clock phase, and a general chip can be used to implement the waveform output function, which reduces the design complexity.

[0056] In one embodiment, Figure 4 As shown, a test system is also provided, including a PE (Pin Electronics Driver / Comparator) module 210 and the above-mentioned test device, the output signal delay module 130 is connected to the PE module 210, the PE module 210 is connected to the device to be tested DUT, and the signal delay parallel sampling module 220 is connected to the PE module 210.

[0057] Specifically, the output data source module 110, the waveform synthesis module 120, the output signal delay module 130, the PE module 210 and the device under test DUT are connected in sequence, the waveform format synthesis is first performed on the original data stream and then the signal delay is performed, and finally the excitation signal is output to the device under test DUT through the PE module 210. Among them, the output data source module 110 can be ALPG (Algorithmic Pattern Generator, algorithmic graphic generation module), which automatically generates the original data stream according to the written program. The output data source module 110 can also be PG (Pattern Generator, graphic generation module), which generates the original data stream according to the specified test vector. The PE module 210 receives the output waveform obtained by the output signal delay module 130, converts it according to the set level threshold value (VIH\VIL) to obtain the excitation signal and sends it to the device under test DUT.

[0058] Furthermore, the PE module 210 also compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value, and outputs the comparison signal to the signal delay parallel sampling module 220. The value of the preset level threshold value is not unique and can be adjusted during the test process. Specifically, the comparison signal output by the PE module 210 includes two output signals, and the number of the signal delay parallel sampling module 220 and the selection output module 230 are both two, and the signal delay sampling cache and sampling output are performed on the two output signals of the PE module 210 respectively.

[0059] In one embodiment, the preset level threshold value includes a threshold value VOH and a threshold value VOL. The values ​​of the threshold value VOH and the threshold value VOL are not unique and can be set according to actual needs. It only needs to satisfy that the threshold value VOH is greater than the threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. Figure 5 As shown, when the input signal is less than the threshold value VOL, the output signal CA is at a low level and the output signal CB is at a low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is at a low level and the output signal CB is at a high level; when the input signal is greater than the threshold value VOH, the output signal CA is at a high level and the output signal CB is at a high level.

[0060] In one embodiment, the test system also includes a comparison processing module 250 connected to the selection output module 230. The comparison processing module 250 is used to determine the actual sampling value based on the sampling signal analysis output by the selection output module 230, and to compare and judge the actual sampling value with a preset expected value to obtain a comparison result.

[0061] Specifically, the comparison processing module 250 performs a table lookup analysis based on the two received sampling signals to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain a comparison result and output it. For example, the comparison processing module 250 can analyze the two sampling signals according to the set comparison truth table to determine the actual sampling value, and then perform a comparison and judgment based on the actual sampling value and the preset expected value to obtain a comparison result. The principle of comparison is as follows Figure 6 , and give the corresponding comparison result according to the actual sampling value of the output signal CA\output signal CB. The parallel matching truth table method is used to realize the signal parallel comparison judgment processing. It is not necessary to decompose the output signal CA\output signal CB to gradually judge whether the output signal CA is consistent with the expected value, and then judge whether the output signal CB is consistent with the expected value. Instead, the actual value is directly determined by matching and comparing through the table lookup method, and then the actual value and the expected value are matched and compared to analyze whether the output result is consistent with the expectation, and the detection efficiency is high.

[0062] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An input signal sampling control device, characterized in that: include: A signal delay parallel sampling module is used to perform delay sampling on the signal fed back by the device to be tested according to the configured delay parameters to obtain a sampling signal; A selection output module is connected to the signal delay parallel sampling module and is used to select and output the sampling signal according to the configured sampling time; An input configuration module is connected to the signal delay parallel sampling module and the selection output module, and is used to set the delay parameter of the signal delay parallel sampling module according to the sampling time.

2. The input signal sampling control device according to claim 1, characterized in that: The signal delay parallel sampling module includes a CARRY carry chain and a D-type flip-flop, and the selection output module includes a multiplexer; the CARRY carry chain is connected to the D-type flip-flop, the D-type flip-flop is connected to the multiplexer, and the input configuration module is connected to the CARRY carry chain and the multiplexer.

3. The input signal sampling control device according to claim 2, characterized in that: The CARRY carry chain includes at least two CARRY units, the number of the D-type flip-flops is the same as the number of the CARRY units, the CARRY units are connected in sequence, each of the D-type flip-flops is respectively connected to the tap of the corresponding CARRY unit, and each of the D-type flip-flops is connected to the multiplexer.

4. An input signal sampling control method, characterized in that: include: The input configuration module sets the delay parameters of the signal delay parallel sampling module according to the sampling time; The signal delay parallel sampling module performs delay sampling on the signal fed back by the device to be tested according to the configured delay parameters to obtain a sampling signal; The selection output module selects and outputs the sampling signal according to the configured sampling time.

5. The method according to claim 4, characterized in that The signal delay parallel sampling module includes a CARRY carry chain and a D-type flip-flop, and the selection output module includes a multiplexer; the CARRY carry chain is connected to the D-type flip-flop, the D-type flip-flop is connected to the multiplexer, and the input configuration module is connected to the CARRY carry chain and the multiplexer; The selection output module selects and outputs the sampling signal according to the configured sampling time, including: the multiplexer determines the sampling output beat and the corresponding target tap according to the configured sampling time, selects the sampling signal of the target tap in the CARRY carry chain from the D-type trigger, and outputs the sampling signal of the target tap according to the sampling output beat; wherein the sampling signal is obtained by the D-type trigger sampling and caching the output signal of the corresponding tap in the CARRY carry chain according to the clock signal.

6. The method according to claim 5, characterized in that The signal delay parallel sampling module performs delayed sampling on the signal fed back by the device to be tested according to the configured delay parameters, including: utilizing the propagation delay of the CARRY carry chain to cache the signal fed back by the device to be tested, and sampling the signal in the CARRY carry chain according to the clock signal through the D-type trigger.

7. A testing device, characterized in that: It comprises a waveform synthesis module, an output signal delay module and the input signal sampling control device according to any one of claims 1 to 3, wherein the waveform synthesis module is connected to the output signal delay module, and the output signal delay module is used to connect to the device to be tested.

8. The testing device according to claim 7, characterized in that: It also includes an output data source module connected to the waveform synthesis module.

9. The testing device according to claim 7, characterized in that: It also includes an output configuration module, which is connected to the waveform synthesis module and the output signal delay module.

10. A testing system, characterized in that: It comprises a PE module and the test device according to any one of claims 7 to 9, wherein the output signal delay module is connected to the PE module, the PE module is connected to a device to be tested, and the signal delay parallel sampling module is connected to the PE module.

11. The test system according to claim 10, characterized in that: The PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the signal delay parallel sampling module.

12. The test system according to claim 10, characterized in that: It also includes a comparison processing module connected to the selection output module, the comparison processing module is used to determine the actual sampling value according to the sampling signal analysis output by the selection output module, and compare and judge according to the actual sampling value and the preset expected value to obtain a comparison result.

13. The test system according to claim 12, characterized in that: The comparison processing module performs a table lookup analysis based on the two received sampling signals to determine the actual sampling value, performs a parallel comparison and judgment based on the actual sampling value and the preset expected value, obtains the comparison result and outputs it.

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