Method for adjusting signal acquisition delay in mask alignment system

Abstract

The invention provides a signal acquisition delay adjusting method in the technical field of mask alignment. The device is characterized by comprising a clock counter 1, an internal controller 2, an adder 3, a comparator 4 and a delay setting register 5. The method can be applied to an FPGA digital processing part in a mask alignment system, an adjustable delay function is added, the trigger time of data acquisition is adjusted within delay setting, and synchronization of optical pulse and optical pulse signal acquisition is facilitated.

Description

(I) Technical field

[0001] The present invention belongs to the technical field of mask alignment and is a method for adjusting signal acquisition delay. The method can be applied to the FPGA digital processing part in the mask alignment system, and an adjustable delay function is added to adjust the trigger time of data acquisition within the range of the delay setting, so as to facilitate the synchronization of light pulse and light pulse signal acquisition. (II) Background technology

[0002] Mask alignment technology is an important step in semiconductor technology and one of the key steps in chip manufacturing. In the chip manufacturing process, photoresist needs to be coated on the silicon wafer, and then the photoresist is exposed in specific areas through the pattern on the mask. Mask alignment technology is to ensure the precise alignment of the pattern position in this process. In this process, the relative position relationship between the silicon wafer surface and the mask surface must first be determined, and then exposure is performed based on this relative position relationship.

[0003] In the mask alignment technology, since the laser emits pulsed light and the duration of the pulsed light is short, it is not conducive to AD acquisition. Therefore, an integration circuit is used to widen the signal time, and the capacitor in the circuit integrates the charge to widen the signal width. And when the mask is aligned, the energy of the pulsed light collected is the largest. The laser emission signal and the trigger signal of TCB are synchronous signals. After the pulsed light passes through the integration circuit and the filtering circuit, the point with the largest relative energy in its waveform has a certain time delay with the trigger signal. And for different sampling frequencies, the sampling period is different, so the maximum delay time needs to be set, and the acquisition delay needs to be adjusted to facilitate the synchronization of the light pulse and the light pulse signal acquisition. (III) Summary of the invention

[0004] In order to solve the problems existing in the background technology, the present invention discloses a method for adjusting a signal acquisition delay based on the field of mask alignment technology. The present invention can adjust the acquisition delay under the input conditions of pulsed light of different frequencies, thereby solving the problems of asynchrony between light pulse and light pulse signal acquisition and inability to align the mask, so that the silicon wafer surface and the mask surface can be accurately aligned, and the silicon wafer alignment system can operate normally, and can be applied in the field of mask alignment technology.

[0005] The present invention provides a method for signal acquisition delay in a mask alignment system, such as Figure 1 As shown, it is composed of a clock counter 1, an internal controller 2, a delay setting register 3, an adder 4, and a comparator 5.

[0006] The clock counter 1 counts once every 50ns, for a total of 40,000 times; after counting to 2ms, it starts cyclic counting.

[0007] The internal controller 2 includes a FIFO for storing the time value of the arrival of the trigger input signal from the TCB. The FIFO capacity is 256*18=4608 bits, which can realize the storage function of 256 18-bit time values.

[0008] Once the trigger delay module in the internal controller 2 receives the trigger signal, it locks the count value of the current time counter into the FIFO in the internal controller.

[0009] The adder 4 reads the trigger arrival time value stored in the internal controller FIFO and the value of the delay setting register 3, adds the two together, and outputs the addition result to the comparator 5.

[0010] Comparator 5 determines whether the value output by the adder is equal to the output value of the 2ms clock counter. If they are not equal, a low level is output; if they are equal, a high level is output. When the internal controller captures the rising edge of the comparator output signal, it outputs a 1us trigger and sends the next value in the internal FIFO to the OUT terminal for output. If the FIFO of the internal controller is empty, when the counter is written from IN, it is directly sent to the OUT terminal.

[0011] The state machine process of the trigger delay module in the internal controller 2 of the present invention is as follows: Figure 2 As shown, the following steps are included:

[0012] Step 1: After the trigger signal enters the internal controller 2, df_sm0 first determines whether there is any remaining bit width in the FIFO. If there is, the FIFO read enable is pulled high, the trigger output is low, and the df_sm1 state machine is entered. If not, the FIFO read enable is low, the trigger output is also low, and then the df_sm0 state machine is still entered.

[0013] Step 2: The next state trigger output in the df_sm1 state machine is low, the FIFO read enable is low, and the df_sm2 state machine is entered.

[0014] Step 3: In df_sm2, determine whether the sum of the delay time and the trigger time value output by the FIFO is greater than 2ms. If it is greater than 2ms, delay_reg is the added value minus 2ms, and enters the df_sm3 state machine. If the sum of the delay time in df_sm2 and the trigger time value output by the FIFO is less than 2ms, enter df_sm3 directly.

[0015] Step 4: The next state trigger output in the df_sm3 state machine is low, the FIFO read enable is low, and the df_sm4 state machine is entered.

[0016] Step 5: In the df_sm4 state machine, determine whether the output value of delay_reg is equal to the clock counter value. If they are equal, the trigger output is high, and the FIFO read enable is low, and enter the df_sm5 state machine. If they are not equal, the trigger output is 0, and the FIFO read enable is low, and continue to return to the df_sm4 state machine.

[0017] Step 6: The trigger output in the df_sm5 state machine is low, the FIFO read enable is low, and then enters the df_sm0 state machine.

[0018] The signal connection of trigger delay module is as follows Figure 3 As shown, data[15:0] input by the VME_svsi module to the DELAY module is used to set the delay time value and is stored in the delay setting register 5. lwr_n is a write enable signal. The delay time value can be set only when lwr_n is at a low level. Laddr[14:0] is an input address signal. The delay time can be set only when laddr[14:0] is equal to a certain address value. The trigger test input by the VME module to the DELAY module is a sampling trigger test signal from the VME bus. clr is a clear signal from the VME module. Trigger in is a trigger input signal from the TCB. The output trigger_out from the DELAY module to the ASDL module is a sampling trigger output signal, which outputs a delayed sampling trigger signal to the ASDL module. Busy is a signal that maintains a high level state when the delay module contains an unissued trigger signal. (IV) Description of the drawings

[0019] Figure 1 It is a schematic diagram of adjustable delay adjustment in the mask alignment system.

[0020] Figure 2 It is a schematic diagram of the trigger delay module state machine.

[0021] Figure 3 This is the connection diagram of the trigger delay module. (V) Specific implementation methods

[0022] The present invention will be further illustrated below with reference to specific examples.

[0023] First, set data[15:0] and store the delay value in delay setting register 5. Set Laddr[14:0] to the corresponding address. Set Lwr_n to low level. When the pulse laser emitter emits pulse light, the TCB board receives the Triggerin trigger input, and the clock counter 1 starts counting in a loop.

[0024] When the trigger signal is pulled high, the read enable of the FIFO read module in the internal controller 2 is pulled high, and the counter moment value when the trigger signal is pulled high is stored. The moment value is transmitted to the adder 3 after passing through the internal controller 2, and the delay moment value in the pre-set delay setting register 5 is added to the moment value. The addition result is then passed to the comparator 4 through the adder 3, and the comparator 4 checks whether the value output by the adder 3 is equal to the output value of the clock counter 1. If they are not equal, a low level is output; if they are equal, a high level is output. When the internal controller 2 captures the rising edge of the output signal of the comparator 4, a 1us trigger is output, and the next value in the internal FIFO is sent to the OUT terminal for output. If the FIFO of the internal controller is empty, when the counter is written from IN, it is directly sent to the OUT terminal.

[0025] The trigger delay module contains 6 state machines, namely df_sm0, df_sm1, df_sm2, df_sm3, df_sm4, and df_sm5. Among them, df_sm1, df_sm3, and df_sm5 are state machines in which the next state trigger output is low and the FIFO read enable is low. df_sm0 first determines whether the FIFO has remaining bit width. If so, the FIFO read enable is pulled high, the trigger output is low, and the df_sm1 state machine is entered. If not, the FIFO read enable is low, the trigger output is also low, and then the df_sm0 state machine is still entered. In the df_sm1 state machine, the next state trigger output is low, the FIFO read enable is low, and the df_sm2 state machine is entered. In df_sm2, it is determined whether the sum of the delay time and the trigger time value output by the FIFO is greater than 2ms. If it is greater than 2ms, delay_reg is the added value minus 2ms, and enters the df_sm3 state machine, and then enters df_sm4 to determine whether the output value of delay_reg is equal to the clock counter value. If they are equal, the trigger output is high, and the FIFO read enable is low, and enters the df_sm5 state machine. If they are not equal, the trigger output is 0, and the FIFO read enable is low, and continue to return to the df_sm4 state machine. If the sum of the delay time in df_sm2 and the trigger time value output by the FIFO is less than 2ms, it directly enters df_sm3, and then enters df_sm4 for judgment. In the df_sm5 state machine, the trigger output is low, the FIFO read enable is low, and then enters the df_sm0 state machine.

[0026] When in the df_sm4 state machine, if the output value of delay_reg is equal to the clock counter value, the trigger output is high. In this way, the trigger signal is equivalent to being pulled high after a preset delay time. This method can be used to adjust the trigger time of data acquisition within the delay setting range, which is convenient for the synchronization of optical pulse and optical pulse signal acquisition.

Claims

1. A method for signal acquisition delay in a mask alignment system, characterized by: It is composed of a clock counter 1, an internal controller 2, an adder 3, a comparator 4, and a delay setting register 5. In the method, when the pulse laser emitter emits pulse light, the trigger signal is pulled high and first enters the internal controller 2, and the clock counter 1 starts to count in a cycle. When the trigger signal is pulled high, the read enable of the FIFO read module in the internal controller 2 is pulled high, and the counter moment value when the trigger signal is pulled high is stored. The moment value is transmitted to the adder 3 after passing through the internal controller 2, and the delay moment value in the delay setting register 5 set in advance is added to the moment value. Then the addition result is passed to the comparator 4 through the adder 3, and the comparator 4 checks whether the value output by the adder 3 is equal to the output value of the clock counter 1. If they are not equal, a low level is output; if they are equal, a high level is output. When the internal controller 2 captures the rising edge of the output signal of the comparator 4, a 1us trigger is output, and the next value in the internal FIFO is sent to the OUT terminal for output. If the FIFO of the internal controller is empty, when the counter is written from IN, it is directly sent to the OUT terminal. Through this method, the trigger time of data acquisition is adjusted within the range of the delay setting, which facilitates the synchronization of optical pulse and optical pulse signal acquisition.

2. The time delay method according to claim 1, characterized in that: The trigger delay module contains 6 state machines, namely df_sm0, df_sm1, df_sm2, df_sm3, df_sm4, and df_sm5. Among them, df_sm1, df_sm3, and df_sm5 are state machines in which the next state trigger output is low and the FIFO read enable is low. df_sm0 first determines whether the FIFO has remaining bit width. If so, the FIFO read enable is pulled high, the trigger output is low, and the df_sm1 state machine is entered. If not, the FIFO read enable is low, the trigger output is also low, and then the df_sm0 state machine is still entered. In the df_sm1 state machine, the next state trigger output is low, the FIFO read enable is low, and the df_sm2 state machine is entered. In df_sm2, it is determined whether the sum of the delay time and the trigger time value output by the FIFO is greater than 2ms. If it is greater than 2ms, delay_reg is the added value minus 2ms, and enters the df_sm3 state machine, and then enters df_sm4 to determine whether the output value of delay_reg is equal to the clock counter value. If they are equal, the trigger output is high, and the FIFO read enable is low, and enters the df_sm5 state machine. If they are not equal, the trigger output is 0, and the FIFO read enable is low, and continue to return to the df_sm4 state machine. If the sum of the delay time in df_sm2 and the trigger time value output by the FIFO is less than 2ms, it directly enters df_sm3, and then enters df_sm4 for judgment. In the df_sm5 state machine, the trigger output is low, the FIFO read enable is low, and then enters the df_sm0 state machine.

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