A PCIe switch chip system supporting online computing

Abstract

The present invention belongs to the field of switching chips, and relates to a PCIe switching chip system supporting on-line computing, which is provided with a distributed switching unit, and the distributed switching unit includes a front-end processing module, a task scheduling module, a storage module, a computing module and a switching network; the front-end processing module includes a PCIe protocol processing module, a DMA function module and an on-line computing analysis module. The present invention adopts a distributed on-line computing architecture of a distributed switching unit, which has the characteristics of high resource utilization and simple back-end implementation compared to centralized on-line computing, can achieve efficient transmission performance, can flexibly support a variety of network topologies, and realize high-bandwidth and low-latency on-line computing acceleration and data exchange; it also has the advantages of simple and flexible hardware implementation, friendly back-end implementation, support for parallel multi-group on-line computing, and is suitable for the design and implementation of other network switching chips.

Description

Technical Field

[0001] The invention relates to a PCIe switching chip system supporting on-line computing, belonging to the technical field of switching chips. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the demand for computing power has shown an unprecedented rapid growth trend. This trend has not only pushed the boundaries of data processing capabilities, but also prompted the birth of new computing architectures. Among them, super node servers have emerged as a solution that can provide higher node computing power and have become a key infrastructure to meet the needs of large-scale AI applications.

[0003] In the domestic market, the mainstream computing server architecture has generally integrated the central processing unit (CPU), accelerator (GPU) and PCIe switch chip, which together constitute the core unit of the computing server. As the computing core in the traditional sense, the CPU is responsible for processing complex logical operations; and the GPU, with its powerful parallel processing capabilities, has become an ideal choice for accelerating tasks such as deep learning and image processing. Among them, the PCIe switch chip plays a vital role. It is not only a high-speed channel for data transmission between the CPU and GPU, but also a bridge for efficient collaboration between GPUs, ensuring that computing resources can be smoothly allocated and scheduled within the server.

[0004] At the same time, faced with increasingly complex computing tasks and growing amounts of data, simply relying on improving hardware performance can no longer meet the needs of efficient computing power utilization. In order to more effectively improve computing power utilization and significantly reduce latency and performance loss caused by communications, the industry has begun to explore the implementation of on-line computing technology at key nodes in communication networks. This innovative strategy aims to reduce unnecessary data transmission and significantly improve communication efficiency by directly processing and analyzing data during network transmission. On-line computing technology can not only effectively alleviate the bandwidth pressure of computing power servers, but also further shorten the overall data processing cycle. It is one of the key technologies to achieve a leap in computing power server performance.

[0005] It is worth noting that the current PCIe switch chip is still limited to the function of peripheral IO (input / output) interconnection expansion in traditional servers, and has not fully realized its potential in promoting computing power optimization. At present, the technical exploration of network computing is still mainly concentrated in Ethernet switching networks and custom networks, while the potential of PCIe switch chips in network computing has not been fully explored.

[0006] Based on this, the present invention is proposed. Summary of the invention

[0007] The present invention provides a PCIe switching chip system supporting online computing, and the specific technical solution is as follows:

[0008] In a first aspect, a PCIe switching chip system supporting on-line computing is provided with a distributed switching unit, wherein the distributed switching unit includes a front-end processing module, a task scheduling module, a storage module, a computing module and a switching network;

[0009] The front-end processing module includes a PCIe protocol processing module, a DMA function module and an on-line computing analysis module. The PCIe protocol processing module implements the physical layer, data link layer, transaction layer and configuration-related content specified in the PCIe protocol, and completes the management of the PCIe link and data packet transmission;

[0010] The DMA function module supports the PCIe switch chip to directly access the memory space of the device, completing the interaction between the device memory and the local cache data;

[0011] The on-line computing parsing module is used to parse the data message and identify the control information, scheduling information and data information of the on-line computing;

[0012] The task scheduling module stores network topology information, information and status information of each port participating in collective communication; the task scheduling module sends the task to the computing module according to the on-line computing information of the received data message, combined with the network topology information and port information, and sends the routing information to the switching network according to the global network topology information;

[0013] The storage module is used to store data to be processed;

[0014] The computing module reads the data to be processed from the storage module according to the instructions issued by the task scheduling module, and sends it to the next processing node after the operation is completed;

[0015] The switching network is an output path for data, receives instructions from the task scheduling module, determines routing information, transmits data to the correct node or port, and supports flexible switching network topology.

[0016] As a further improvement, the control information includes in-network computing topology management information and in-network computing data processing commands.

[0017] As a further improvement, the scheduling information includes data transmission address information and task division information.

[0018] As a further improvement, the data information is a data stream involved in online computing.

[0019] As a further improvement, the computing module supports multiple operators for on-line computing.

[0020] As a further improvement, the switching network has N input ports and N output ports, and implements N*N non-blocking switching through a three-level crossbar architecture.

[0021] In a second aspect, a workflow of a PCIe switching chip system supporting online computing includes the following steps:

[0022] Step 1: Topology discovery

[0023] Follow the topology discovery provisions of the PCIe protocol and establish network topology relationships during port enumeration;

[0024] Step 2: Establish the network computing topology

[0025] The topology of the on-line computing is established according to the network topology, and the topology information is sent to each PCIe switch chip. The task scheduling module of the switch chip records the topology information to complete the establishment of the on-line computing topology;

[0026] Step 3: Start the task

[0027] Then, the device initiates an on-line computing request to the PCIe switching chip. The front-end processing module of each port of the PCIe switching chip parses the request and sends the request to the task scheduling module. The task scheduling module notifies the computing module to perform the corresponding calculation and notifies the switching network to transmit the calculation result to the corresponding port.

[0028] Step 4: Mission Completed

[0029] The online computing task is completed and exit.

[0030] Beneficial effects of the present invention:

[0031] 1. The present invention adopts a distributed on-line computing architecture of a distributed switching unit. Compared with centralized on-line computing, this architecture has the characteristics of high resource utilization and simple back-end implementation.

[0032] 2. The distributed network computing architecture provided by the present invention can achieve efficient transmission performance through reasonable distribution of computing resources.

[0033] 3. The present invention can flexibly support a variety of network topologies. Common crossbar architecture / ring architecture / mesh architecture / hybrid architecture can all be designed using the present invention, which can flexibly support the needs of multi-port data exchange and achieve high-bandwidth and low-latency on-line computing acceleration and data exchange.

[0034] 4. The present invention has the advantages of simple and flexible hardware implementation and friendly back-end implementation.

[0035] 5. The present invention adopts a distributed computing module. The entire switching network is composed of multiple switching nodes. Each switching node supports the acceleration of the on-line computing of the port to which it is connected, and sends the result to the aggregation node for the next step of computing.

[0036] 6. The present invention supports parallel multi-group on-line computing and can achieve more efficient data transmission through reasonable topology division.

[0037] 7. The distributed on-line computing architecture proposed in the present invention is also applicable to the design and implementation of other network switching chips (such as Ethernet switching networks). BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a structural diagram of a distributed switching unit.

[0039] Figure 2 This is the structural diagram of the front-end processing module.

[0040] Figure 3 The present invention is a workflow diagram of a PCIe switching chip system supporting on-line computing.

[0041] Figure 4 It is an N*N three-level switching network. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] Definitions of Abbreviations and Key Terms

[0044] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard;

[0045] In-network computing: In-network computing, which moves computing from traditional computing nodes to interconnected networks to improve efficiency;

[0046] Enumeration: The host on the PCIe RC side discovers the PCIe bus topology and moves its devices to the host address space;

[0047] DMA: Direct Memory Access, data migration is completed by a dedicated hardware unit without going through the CPU;

[0048] Crossbar architecture: a topology used to achieve efficient data exchange and communication in computer systems.

[0049] Ring architecture: a topology used to achieve efficient data exchange and communication in computer systems.

[0050] Mesh architecture: a topology used to achieve efficient data exchange and communication in computer systems.

[0051] Node: is a connection point or endpoint in a network, which can be a processor, controller or workstation, etc.

[0052] group: refers to a group of computing nodes or resources on the network that work together to complete a specific computing task. Example 1

[0053] A PCIe switching chip system supporting online computing can flexibly form a variety of network topologies by setting up distributed switching units, thereby realizing switching chips and systems that meet different transmission requirements. Distributed switching units such as Figure 1 As shown in Figure 1, it mainly includes front-end processing module, task scheduling module, storage module, computing module and switching network. Figure 1 In the figure, P0, P1, and P2 respectively represent different ports connected to the PCIe switch chip, which are devices that meet the PCIe interface standard. The present invention does not limit the number of ports.

[0054] like Figure 2 As shown, the front-end processing module mainly includes a PCIe protocol processing module, a DMA functional module and an on-line computing analysis module, wherein the PCIe protocol processing module implements the physical layer, data link layer, transaction layer and configuration-related contents specified in the PCIe protocol, and mainly completes the management of the PCIe link and the transmission of data packets; the DMA functional module mainly supports the PCIe switching chip to directly access the memory space of the device, and can complete the interaction between the device memory and the local cache data; the on-line computing analysis module is mainly used to parse data packets, identify the control information, scheduling information and data information of the on-line computing, etc.; the above-mentioned control information includes the on-line computing topology management information and the on-line computing data processing command information, the scheduling information includes the data transmission address information and the task division information, and the data information is the data flow participating in the on-line computing.

[0055] The task scheduling module stores network topology information, information about each port involved in collective communication, and status information. The task scheduling module sends tasks to the computing module based on the on-line computing information of the received data message, combined with the network topology information and port information, and sends routing information to the switching network based on the global network topology information.

[0056] The storage module is used to store data to be processed. The data to be processed may be to be calculated on the network at the current node, or may just be transmitted to the next node through the current node.

[0057] The computing module reads the data to be processed from the storage module according to the instructions issued by the task scheduling module, and sends it to the next processing node after the operation is completed. The computing module supports a variety of operators for online computing, which are not limited here.

[0058] The switching network is the output path for data. It receives instructions from the task scheduling module, determines routing information, transmits data to the correct node or port, and supports flexible switching network topology. Example 2

[0059] Based on Example 1, Figure 3 As shown, the workflow of a PCIe switching chip system supporting online computing provided by the present invention is as follows:

[0060] Step 1: Topology discovery

[0061] Follow the topology discovery provisions of the PCIe protocol and establish network topology relationships during port enumeration;

[0062] Step 2: Establish the network computing topology

[0063] The topology of the on-line computing is established according to the network topology, and the topology information is sent to each PCIe switch chip. The task scheduling module of the switch chip records the topology information to complete the establishment of the on-line computing topology;

[0064] Step 3: Start the task

[0065] Then, the device initiates an on-line computing request to the PCIe switching chip. The front-end processing module of each port of the PCIe switching chip parses the request and sends the request to the task scheduling module. The task scheduling module notifies the computing module to perform the corresponding calculation and notifies the switching network to transmit the calculation result to the corresponding port.

[0066] Step 4: Mission Completed

[0067] The online computing task is completed and exit. Example 3

[0068] Figure 4 It is a possible switch chip network topology. Figure 4The switching network shown has N input ports and N output ports, and realizes N*N non-blocking switching through a three-level crossbar architecture. Assume that the N ports are divided into k groups, each with n ports, that is, N=k*n. The input L1 layer is k n*m fully interconnected distributed switching units, the middle L2 layer is m k*k fully interconnected distributed switching units, and the output L3 layer is k m*n fully interconnected distributed switching units. By setting parameters reasonably (for example, m≥2n-1), a strictly non-blocking switching network can be realized, that is, to ensure that any unoccupied input and output ports can have a path to use. Among them, N, k, n, and m are all integers greater than 2.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A PCIe switch chip system supporting on-line computing, characterized in that: A distributed switching unit is provided, and the distributed switching unit includes a front-end processing module, a task scheduling module, a storage module, a computing module and a switching network; The front-end processing module includes a PCIe protocol processing module, a DMA function module and an on-line computing analysis module. The PCIe protocol processing module implements the physical layer, data link layer, transaction layer and configuration-related content specified in the PCIe protocol, and completes the management of the PCIe link and data packet transmission; The DMA function module supports the PCIe switch chip to directly access the memory space of the device, completing the interaction between the device memory and the local cache data; The on-line computing parsing module is used to parse the data message and identify the control information, scheduling information and data information of the on-line computing; The task scheduling module stores network topology information, information and status information of each port participating in collective communication; The task scheduling module sends the task to the computing module according to the online computing information of the received data message, combined with the network topology information and the port information, and sends the routing information to the switching network according to the global network topology information; The storage module is used to store data to be processed; The computing module reads the data to be processed from the storage module according to the instructions issued by the task scheduling module, and sends it to the next processing node after the operation is completed; The switching network is an output path for data, receives instructions from the task scheduling module, determines routing information, transmits data to the correct node or port, and supports flexible switching network topology.

2. A PCIe switch chip system supporting on-line computing according to claim 1, characterized in that: The control information includes in-network computing topology management information and in-network computing data processing commands.

3. The PCIe switch chip system supporting on-line computing according to claim 1, characterized in that: The scheduling information includes data transmission address information and task division information.

4. The PCIe switch chip system supporting on-line computing according to claim 1, characterized in that: The data information is the data flow involved in the online calculation.

5. The PCIe switch chip system supporting on-line computing according to claim 1, characterized in that: The computing module supports multiple operators for on-line computing.

6. A PCIe switch chip system supporting on-line computing according to claim 1, characterized in that: The switching network has N input ports and N output ports, and implements N*N non-blocking switching through a three-level crossbar architecture.

7. The workflow of a PCIe switch chip system supporting on-line computing according to any one of claims 1 to 6, characterized in that: The steps include: Step 1: Topology discovery Follow the topology discovery provisions of the PCIe protocol and establish network topology relationships during port enumeration; Step 2: Establish the network computing topology The topology of the on-line computing is established according to the network topology, and the topology information is sent to each PCIe switch chip. The task scheduling module of the switch chip records the topology information to complete the establishment of the on-line computing topology; Step 3: Start the task Then, the device initiates an on-line computing request to the PCIe switch chip, and the front-end processing module of each port of the PCIe switch chip parses the request and sends the request to the task scheduling module; The task scheduling module notifies the calculation module to perform corresponding calculations and notifies the switching network to transmit the calculation results to the corresponding ports; Step 4: Mission Completed The online computing task is completed and exit.

Images