A video codec performance analysis device, method, equipment and medium

Abstract

The present invention discloses a video coding and decoding performance analysis device, method, equipment and medium, belonging to the field of data processing, providing a real-time performance evaluation function, capable of analyzing the video coding and decoding performance in real time, and reporting the real-time performance analysis to the central processing unit. The central processing unit makes optimization adjustments according to the real-time data, so as to maintain high-quality performance in different video coding and decoding scenarios; the performance analysis device is an independent module, which optimizes the video coding and decoding algorithm at the hardware level. Through targeted hardware design and implementation, the efficiency and speed of video coding and decoding can be improved, thereby obtaining better performance. It can adapt to the evolving video coding and decoding standards and application requirements, and provide support for future technological development.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of data processing, and more particularly to a video codec performance analysis device, method, equipment, and medium. Background Art

[0002] Today, significant progress has been made in video codec technology. From traditional standard compression algorithms (such as H.264, H.265, etc.) to modern efficient codec technologies (such as AV1, VP9, etc.), video codec standards have been continuously updated and iterated to provide better compression ratios and visual quality.

[0003] At the same time, integrated circuit technology plays a crucial role in the field of information processing. The continuous development of integrated circuits makes it possible to integrate more computing and processing capabilities on a chip, which provides new opportunities for improving video codec performance. Innovations in integrated circuit design can optimize video codec algorithms at the hardware level, improve processing speed and energy efficiency, and adapt to different application scenarios and requirements.

[0004] However, with the increase in video resolution, the diversification of multimedia applications, and the changes in network transmission, video codec technology faces new challenges and requires more in-depth performance analysis and optimization.

[0005] However, there are still some limitations in current video codec performance analysis methods: currently, the time unit of performance analysis tools is in seconds (s), which can only analyze performance over a relatively long period of time and cannot more accurately know the real-time video processing performance. Moreover, for different video codec formats, different performance analysis modules need to be developed, which is very inconvenient to use, resulting in the inability of existing performance analysis tools to comprehensively and accurately evaluate the performance of different video codec algorithms on different hardware platforms. Summary of the Invention

[0006] The purpose of the present invention is to provide a video codec performance analysis device, method, equipment, and medium to at least partially solve the above problems.

[0007] According to one aspect of the present invention, a video codec performance analysis device is proposed, including:

[0008] A video codec working state monitoring unit for real-time monitoring of the video codec working state;

[0009] A video codec performance monitoring unit for counting the number of video codec request signals and response signals initiated at each rising edge of the video codec working clock, and statistically obtaining the delay information between each request and response;

[0010] A delay information sending unit for sending the delay information to the central processing unit;

[0011] The performance analysis device is respectively coupled to the central processing unit and the video codec module.

[0012] In some embodiments, the device further includes monitoring the working state of the video codec in real time, specifically, collecting the working state signal value at the rising edge of each working clock in real time;

[0013] The working state includes idle, working, or waiting.

[0014] In some embodiments, the device further includes a time configuration unit, which is respectively coupled to the central processing unit and the analysis device,

[0015] A first variable and a second variable are respectively configured in the time configuration unit and the analysis device, and the value ranges of the first variable and the second variable are natural numbers.

[0016] Collect the working state signal value at the rising edge of each working clock. When the working state signal value indicates a working state, the value of the second variable is set to 0;

[0017] When the working state signal value indicates an idle state or a waiting state, the value of the second variable is incremented by 1 and compared with the value of the first variable. If the value of the second variable is less than or equal to the value of the first variable, continue to monitor the working state; if the value of the second variable is greater than the value of the first variable, the performance analysis device uploads this information to the central processing unit, and the central processing unit controls to reduce the working frequency of the video codec.

[0018] In some embodiments, the device further includes that the central processing unit configures the value of the first variable, and the performance analysis device counts the number of times the request signal and the response signal are initiated at the rising edge of each working clock. At the same time, when the value of the first variable is decremented to 0, the performance analysis device calculates the average bandwidth and average delay information of the video codec during this period and reports them to the central processing unit.

[0019] According to another aspect of the present invention, a video codec performance analysis method is proposed, including:

[0020] This method is implemented based on the above device.

[0021] Start the performance analysis device to monitor the working state of the video codec.

[0022] At the rising edge of each video codec working clock, count the number of times the video codec request signal and the response signal are initiated, and count and obtain the delay information between each request and response.

[0023] And send the delay information to the central processing unit.

[0024] In some embodiments, the real-time monitoring of the video codec working state specifically means that the working state signal value is collected at the rising edge of each working clock in real time;

[0025] The working state includes idle, working, or waiting.

[0026] In some embodiments, the working state signal value is collected at the rising edge of each working clock. When the working state signal value indicates the working state, the second variable value is set to 0;

[0027] When the working state signal value indicates the idle state or the waiting state, the second variable value is incremented by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working state is continuously monitored; if the second variable value is greater than the first variable value, the performance analysis device uploads this information to the central processing unit, and the central processing unit controls the reduction of the working frequency of the video codec.

[0028] In some embodiments, the central processing unit configures the value of the first variable. The performance analysis device counts the number of times the request signal and the response signal are initiated at the rising edge of each working clock. At the same time, when the value of the first variable is decremented until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video codec during this period and reports it to the central processing unit.

[0029] An embodiment of the present application further provides an electronic device, which includes a memory and a processor. A computer program is stored in the memory, and the processor executes the steps in the method of any of the above embodiments by calling the computer program stored in the memory.

[0030] An embodiment of the present application further provides a computer-readable storage medium, storing a computer program, characterized in that: when the computer program is run by a processor, it executes the steps in the method of any of the above embodiments.

[0031] The present invention implements a video codec performance analysis device, provides a real-time performance evaluation function, can analyze the video codec performance in real time, and reports the real-time performance analysis to the central processing unit. The central processing unit makes optimization adjustments according to the real-time data, so as to maintain high-quality performance in different video codec scenarios; the performance analysis device is an independent module, which optimizes the video codec algorithm at the hardware level. Through targeted hardware design and implementation, the efficiency and speed of video codec can be improved, thereby obtaining better performance. It can adapt to the evolving video codec standards and application requirements, and provide support for future technological development.

[0032] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the specification, claims as well as the drawings. Brief Description of the Drawings

[0033] Figure 1 Schematic diagram of a video codec performance analysis device provided by an embodiment of the present application.

[0034] Figure 2 Schematic diagram of a video codec performance analysis method provided by an embodiment of the present application.

[0035] Figure 3 Schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Detailed Embodiments

[0036] The following further describes the detailed embodiments of the present invention with reference to the drawings. It should be noted here that the description of these embodiments is for helping to understand the present invention, but does not constitute a limitation to the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", etc. is the description of the structure of the present invention based on the drawings shown, and is only for the convenience of describing the present invention simply, rather than indicating or implying that the system or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0038] For the "first" and "second" in the present technical solution, they are only the appellation distinctions for the same or similar structures, or corresponding structures with similar functions, and do not represent the importance ranking of these structures, nor do they have a ranking, or comparison of sizes, or other meanings.

[0039] In addition, unless otherwise clearly specified and defined, the terms "installation" and "connection" should be understood in a broad sense. For example, the connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two structures. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the general idea of the present invention and in connection with the specific circumstances of this solution.

[0040] The first aspect of the present invention discloses a video codec performance analysis device, as Figure 1As shown, it is a schematic diagram of a video encoding performance analysis device according to an embodiment of the present invention. Refer to Figure 1 As shown, the analysis device includes:

[0041] A video codec working status monitoring unit for monitoring the working status of the video codec in real time;

[0042] A video codec performance monitoring unit for counting the number of times the video codec request signal and response signal are initiated at each rising edge of the video codec working clock, and statistically obtaining the delay information between each request and response;

[0043] A delay information sending unit for sending the delay information to the central processing unit;

[0044] The analysis device is respectively coupled to the central processing unit and the video codec unit.

[0045] In some embodiments, the performance analysis unit is connected to the working status signal in the video codec module corresponding to signal A, and there are three working statuses in total: idle, working, and waiting;

[0046] The performance analysis unit is connected to the video codec working clock corresponding to signal B, and the clock frequency can reach above 1 GHz, that is, at the nanosecond (ns) level;

[0047] The performance analysis unit is connected to the request signal in the video codec module corresponding to signal C;

[0048] The performance analysis unit is connected to the response signal in the video codec module corresponding to signal D;

[0049] The performance analysis unit is connected to the receiving signal in the central processing unit (CPU) corresponding to signal E.

[0050] In some embodiments, when monitoring the working status of the video codec, the performance analysis device monitors and records the value of signal A at each rising edge (signal B) in real time, and reports the working status of the video codec module to the central processing unit through the performance analysis module (signal E). The central processing unit can master the working status of the video codec module. The central processing unit is the brain of the chip. It executes instructions, processes data, and controls the operation of the chip, and is a crucial component in the chip. The video codec module is an important component in the chip, responsible for encoding (compressing) and decoding (decompressing) video data, so as to effectively process the video stream when storing, transmitting, and playing videos, enabling the video data to be efficiently transmitted, stored, and played on different platforms and applications while maintaining appropriate quality.

[0051] In some embodiments, when monitoring the real-time video encoding and decoding performance, the performance analysis device starts to work. At the rising edge of each video encoding and decoding working clock (signal B), it counts the number of times the video encoding and decoding request signal (signal C) and the response signal (signal D) are initiated, and counts the delay between each request and response.

[0052] Embodiments of the present invention can analyze the performance of different encoding and decoding formats. Through experimental tests, the read bandwidth of the JPEG format encoding and decoding performance reaches 5.5 Gbps, and the average delay is 5.5 ns. The read bandwidth of the HEVC format encoding performance test reaches 12.4 Gbps, and the average delay is 45 ns. The read bandwidth of the H264 format encoding performance test reaches 11.8 Gbps, and the average delay is 2.5 ns.

[0053] The test passes the performance analysis module (signal E) to report real-time data to the central processing unit, and the central processing unit can master the performance of the video encoding and decoding module in real-time processing data.

[0054] In some embodiments, the performance analysis device can also cooperate with the time configuration module to reduce CPU power consumption. The time configuration unit is respectively coupled to the central processing unit and the analysis device. The time configuration module receives information from the central processing unit and configures time variables, and cooperates with the performance analysis device to jointly complete the monitoring and analysis of the video encoding and decoding module.

[0055] A first variable and a second variable are respectively configured in the time configuration unit and the analysis device, and the value ranges of the first variable and the second variable are natural numbers.

[0056] At the rising edge of each working clock, the working state signal value is collected. When the working state signal value indicates the working state, the value of the second variable is set to 0.

[0057] When the working state signal value indicates the idle state or the waiting state, the value of the second variable is incremented and compared with the value of the first variable. If the value of the second variable is less than or equal to the value of the first variable, the working state is continuously monitored; if the value of the second variable is greater than the value of the first variable, the performance analysis device uploads this information to the central processing unit, and the central processing unit controls to reduce the working frequency of the video encoding and decoding, thereby reducing power consumption.

[0058] In some embodiments, the performance analysis device can also cooperate with the time configuration module to analyze the average performance of the video encoding and decoding over a period of time. The central processing unit configures the value of the first variable. The performance analysis device counts the number of times the request signal and the response signal are initiated at the rising edge of each working clock. At the same time, when the value of the first variable is decremented until it reaches 0, the performance analysis device calculates the average bandwidth and average delay information of the video encoding and decoding during this period and reports it to the central processing unit.

[0059] The time configuration unit corresponding signal F is connected to the central processor time configuration register. For example, it configures the monitoring video codec module to enter the frequency reduction time and configures the average performance of the time statistics video codec, so as to achieve less power consumption during the idle or waiting period of the video codec and analyze the average performance of the video codec over a period of time, improving the accuracy of performance analysis.

[0060] The second aspect of the present invention discloses a method for analyzing video codec performance, such as Figure 2 shown, the method includes:

[0061] Step S1, start the performance analysis device to monitor the working state of the video codec,

[0062] Step S2, at the rising edge of each video codec working clock, count the number of times the video codec request signal and response signal are initiated, and count the delay information between each request and response.

[0063] Step S3, and send the delay information to the central processor.

[0064] The method of the present invention will be described in detail below with specific examples.

[0065] Example 1: The central processor allocates the video codec module to perform encoding processing on a frame of data, and the steps are as follows:

[0066] The central processor issues an instruction, configures the corresponding register and starts the video codec module. The video codec module parses the instruction, then reads data from the corresponding memory and starts encoding processing. At the same time, the performance analysis module starts to monitor the video codec module.

[0067] The video codec module will have a jump in the working state. In the idle stage, it receives the central processor configuration register instruction, then changes from the idle state to the working state and starts data encoding processing. When a frame of data encoding processing is completed, it will change from the working state to the waiting state. The performance analysis module monitors the working state of the video codec and reports it to the central processor, facilitating the central processor to master the real-time working state of the video codec module.

[0068] In some embodiments, the central processor can master the working performance of the video codec over a period of time. When the video codec module is working, the central processor issues an instruction to configure the time variable in the time configuration module, and cooperate with the performance analysis device to count the number of times the request signal and response signal are initiated at the rising edge of each clock over a period of time, and count the delay between each request and response. The performance analysis module calculates the average bandwidth and average delay over a period of time and reports the information to the central processor.

[0069] The central processing unit can grasp the real-time working performance of video encoding and decoding. When the video encoding and decoding module is working, the central processing unit issues instructions to configure the performance analysis module, counts the number of request signals and response signals at each rising clock edge, and reports the information to the central processing unit after analysis. When the central processing unit knows that the video encoding and decoding module has completed processing a frame of data, it issues instructions to configure the corresponding register, telling the video encoding and decoding module that there is no new data to process, and the video encoding and decoding module changes from the waiting state to the idle state.

[0070] Example 2: The central processing unit allocates the video encoding and decoding module to perform encoding processing on two frames of data. The steps are as follows:

[0071] The central processing unit issues an instruction to start the video encoding and decoding module to perform encoding processing on the first frame of data, and at the same time starts the performance analysis module to monitor the working state of the video encoding and decoding module.

[0072] After the video encoding and decoding module finishes encoding the first frame of data, it jumps from the working state to the waiting state. The performance analysis module monitors the working state of video encoding and decoding at each rising clock edge, and reports to the central processing unit when it detects that the video encoding and decoding enters the waiting state. When the central processing unit knows that the video encoding and decoding module has completed encoding processing of a frame of data, it issues a new instruction to configure the register to let the video encoding and decoding module enter the encoding processing of the second frame of data.

[0073] The video encoding and decoding module parses the instruction, changes from the waiting state to the working state, reads data from the corresponding memory according to the instruction requirements to perform encoding processing on the second frame of data, and the performance analysis module continues to monitor the video encoding and decoding module.

[0074] After the video encoding and decoding finishes encoding the second frame of data, it changes from the working state to the waiting state. The performance analysis module monitors the working state of the video encoding and decoding module at each rising clock edge, and reports to the central processing unit when it monitors that the working state changes to waiting. When the central processing unit knows that the video encoding and decoding module has completed processing the second frame of data, it issues instructions to configure the corresponding register, notifies the video encoding and decoding module that there is no new data to process, and the video encoding and decoding module changes from waiting to the idle state.

[0075] Example 3: The central processing unit controls the video encoding and decoding module to enter the frequency reduction state to reduce power consumption. The steps are as follows:

[0076] The central processing unit writes an initial value to the time variable in the time configuration module, and at the same time issues an instruction to start the video encoding and decoding module to start working.

[0077] The video encoding and decoding module analyzes the instructions, starts to read data from the memory for encoding work, and at the same time, the working state changes from the idle state to the working state. Meanwhile, the performance analysis module monitors the working state of the video encoding and decoding module at each rising edge of the clock. At this time, the video encoding and decoding module is in the working state. When the performance analysis module monitors that the video encoding and decoding is in the working state at each rising edge of the clock, it writes the value of the time variable in the performance analysis device as 0. At this time, the value of the time variable in the performance analysis device <= the value of the time variable in the time configuration module, and continues to monitor.

[0078] After the video encoding and decoding module completes the encoding of one frame of data, it changes from the working state to the waiting state. When the central processing unit does not issue instructions, the video encoding and decoding will remain in the waiting state. At this time, the performance analysis device monitors the waiting state at each rising edge of the clock, and the value of the time variable in the performance analysis device is incremented by 1 and compared with the value of the time variable in the time configuration module. If the value of the time variable in the performance analysis device < the value of the time variable in the time configuration module, continue to monitor; if the value of the time variable in the performance analysis device > the value of the time variable in the time configuration module, it means that the video encoding and decoding has not worked for a sufficient long time, and the performance analysis device uploads the information to the central processing unit. The central processing unit issues a command to reduce the clock frequency of the video encoding and decoding module to reduce power consumption.

[0079] When the central processing unit has new data that needs to be processed by the video encoding and decoding module, it issues a command to restore the clock frequency of the video encoding and decoding module, and then issues an instruction to the video encoding and decoding module to continue the encoding work. After parsing the instruction, the video encoding and decoding module changes from the waiting state to the working state and performs the encoding work for a new frame of data. This saves the steps of restarting the video encoding and decoding module, and at the same time, when the video encoding and decoding module is not needed, the power consumption is reduced by reducing the frequency.

[0080] The third aspect of the present invention discloses an electronic device, which can be a terminal or a server. As Figure 3 shown, Figure 3 is a schematic structural diagram of the electronic device provided by the embodiment of the present application.

[0081] The electronic device 300 includes a processor 301 with one or more processing cores, a memory 302 with one or more computer-readable storage media, and a computer program stored on the memory 302 and executable on the processor. Among them, the processor 301 is electrically connected to the memory 302. Those skilled in the art can understand that the structure of the electronic device shown in the figure does not constitute a limitation on the electronic device, and it may include more or fewer components than shown in the figure, or combine some components, or arrange different components.

[0082] The processor 301 is the control center of the electronic device 300, connecting various parts of the entire electronic device 300 through various interfaces and circuits. By running or loading software programs (computer programs) and / or units stored in the memory 302, and by invoking the data stored in the memory 302, it executes various functions of the electronic device 300 and processes data, thereby monitoring the electronic device 300 as a whole.

[0083] In the embodiments of the present application, the processor 301 in the electronic device 300 will load the instructions corresponding to the processes of one or more application programs into the memory 302 according to the following steps, and the processor 301 will run the application programs stored in the memory 302 to implement various functions:

[0084] Start the performance analysis device to monitor the working state of video encoding and decoding.

[0085] At the rising edge of each video encoding and decoding working clock, count the number of times the video encoding and decoding request signal and response signal are initiated, and count and obtain the delay information between each request and response.

[0086] And send the delay information to the central processing unit.

[0087] Optionally, as Figure 3 shown, the electronic device 300 further includes: a performance analysis device 303, a communication module 304, an input unit 305, and a power supply 306. Among them, the processor 301 is electrically connected to the performance analysis device 303, the communication module 304, the input unit 305, and the power supply 306 respectively. Those skilled in the art can understand that Figure 3 the structure of the electronic device shown in

[0088] does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0089] The performance analysis device 303 can be used to implement the performance analysis of video encoding and decoding.

[0090] The communication module 304 can be used to communicate with other devices.

[0091] The power supply 306 is used to supply power to various components of the electronic device 300. Optionally, the power supply 306 can be logically connected to the processor 301 through a power management system, so as to realize functions such as management of charging, discharging, and power consumption management through the power management system. The power supply 306 can also include any components such as one or more DC or AC power supplies, a recharge system, a power failure detection circuit, a power converter or inverter, a power status indicator, etc.

[0092] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] A fourth aspect of the present invention discloses a computer-readable storage medium. Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling relevant hardware through instructions. The instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0094] Therefore, an embodiment of the present application provides a computer-readable storage medium, in which multiple computer programs are stored. The computer programs can be loaded by a processor to execute the steps of a video codec performance analysis method provided by the embodiment of the present application. For example, the computer program can execute the following steps:

[0095] Start the performance analysis device to monitor the video codec working state.

[0096] At each rising edge of the video codec working clock, count the number of times the video codec request signal and response signal are initiated, and count and obtain the delay information between each request and response.

[0097] And send the delay information to the central processing unit.

[0098] For the specific implementation of the above operations, reference can be made to the foregoing embodiments, and details are not described herein again.

[0099] Among them, the computer-readable storage medium can include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), a magnetic disk or an optical disc, etc.

[0100] Since the computer programs stored in the storage medium can execute the steps in any video codec performance analysis method provided by the embodiment of the present application, the beneficial effects that can be achieved by any video codec performance analysis method provided by the embodiment of the present application can be realized. For details, see the foregoing embodiments, and details are not described herein again.

[0101] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a system for implementing the functions specified in the Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0102] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction system that implements the functions specified in the Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0103] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in the Figure 1 one or more flows and / or blocks Figure 1 one or more blocks.

[0104] The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, without departing from the principles and spirit of the present invention, various changes, modifications, substitutions, and variations to these embodiments still fall within the protection scope of the present invention.

Claims

1. A video encoding and decoding performance analysis device, characterized in that: The device comprises: A video codec working status monitoring unit is used to monitor the video codec working status in real time; The video codec performance monitoring unit is used to count the number of times the video codec request signal and response signal are initiated at each rising edge of the video codec working clock, and to obtain the delay information between each request and response; A delay information sending unit, used for sending the delay information to a central processing unit; The video coding and decoding performance analysis device is coupled to the central processing unit and the video coding and decoding module respectively.

2. The device according to claim 1, characterized in that: The real-time monitoring of the video codec working state is specifically to monitor each rising edge of the working clock in real time and collect the working state signal value; The working status includes idle, working or waiting.

3. The device according to claim 2, characterized in that Also includes: a time configuration unit, coupled to the central processor and the video encoding and decoding performance analysis device respectively, The time configuration unit and the video coding performance analysis device are respectively configured with a first variable and a second variable, the value ranges of the first variable and the second variable are natural numbers, wherein the first variable and the second variable are time variables, The working state signal value is collected at each rising edge of the working clock, and when the working state signal value indicates that the working state is in progress, the second variable value is set to 0; When the working status signal value indicates an idle state or a waiting state, the second variable value is increased by 1 and compared with the first variable value. If the second variable value is less than or equal to the first variable value, the working status continues to be monitored; if the second variable value is greater than the first variable value, the video codec performance analysis device uploads the information to the central processing unit, and the central processing unit controls the reduction of the working frequency of the video codec.

4. The device according to claim 3, characterized in that: The central processing unit configures the value of the first variable, and the video codec performance analysis device counts the number of times each request signal and response signal of the working clock rising edge is initiated. At the same time, when the value of the first variable is reduced by 1 until it reaches 0, the video codec performance analysis device calculates the average bandwidth and average delay information of the video codec during this period of time, and reports it to the central processing unit.

5. A video encoding and decoding performance analysis method, characterized in that: The method is implemented based on a video encoding and decoding performance analysis device according to any one of claims 1 to 4, and the method specifically comprises: Starting the video codec performance analysis device to monitor the video codec working status, At each rising edge of the video codec working clock, the number of times the video codec request signal and response signal are initiated is counted, and the delay information between each request and response is obtained. And send the delay information to the central processing unit.

6. An electronic device, characterized in that: The method comprises a memory storing executable program code and a processor coupled to the memory; wherein the processor calls the executable program code stored in the memory to execute the method according to claim 5.

7. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to claim 5 is performed.

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