Printed wiring board

Abstract

The invention provides a printed wiring board in which a conductor circuit is difficult to peel off from a resin insulating layer even if the width of the conductor circuit is reduced. The printed wiring board includes: a first resin insulating layer; a first conductor layer formed on the first resin insulating layer; a second resin insulating layer formed on the first resin insulating layer and the first conductor layer, the second resin insulating layer having an opening for a via conductor reaching the first conductor layer; a second conductor layer formed on the second resin insulating layer; and a via hole conductor which is formed in the opening and connects the first conductor layer and the second conductor layer. The second conductor layer is composed of a seed layer on the second resin insulating layer, the seed layer is formed of a first film in contact with the second resin insulating layer and a second film on the first film, the first film is formed of an alloy containing copper and titanium, and the second film is formed of an electroplating film on the seed layer. The alloy contains carbon, oxygen, and silicon as impurities, and the second film is formed of copper.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a printed wiring board. Background Art

[0002] Patent document 1 discloses a printed wiring board having a resin substrate, a resin insulating layer formed on the resin substrate, and a conductor circuit. The conductor circuit is formed on the resin insulating layer via an alloy layer containing a specific metal. For example, paragraph

[0008] of Patent document 1 shows the specific metal.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2000-124602

[0004] [Problem of Patent Document 1]

[0005] In the printed wiring board having an alloy layer of Patent Document 1, it is considered that when the width of the conductor circuit is reduced, the conductor circuit is peeled off from the resin insulating layer. Summary of the invention

[0006] The printed wiring board of the present invention comprises: a first resin insulating layer; a first conductor layer formed on the first resin insulating layer; a second resin insulating layer formed on the first resin insulating layer and the first conductor layer and having an opening for a via conductor reaching the first conductor layer; a second conductor layer formed on the second resin insulating layer; and a via conductor formed in the opening and connecting the first conductor layer and the second conductor layer. The second conductor layer is composed of a seed layer on the second resin insulating layer and a plated film on the seed layer, the seed layer being formed of a first film in contact with the second resin insulating layer and a second film on the first film, the first film being formed of an alloy containing copper and titanium, the alloy containing carbon, oxygen and silicon as impurities, and the second film being formed of copper.

[0007] In the printed wiring board of the embodiment of the present invention, the first film in contact with the second resin insulating layer is formed of an alloy containing copper and titanium. The alloy contains carbon, oxygen, and silicon as impurities. Therefore, the bonding force with the second resin insulating layer containing carbon, oxygen, and silicon is large. The adhesion between the first film and the second resin insulating layer is high. Therefore, even if the width of the conductor circuit is small, it is difficult to peel off from the second resin insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A It is a cross-sectional view schematically showing a printed wiring board according to the embodiment.

[0009] Figure 1B It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0010] Figure 1CIt is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0011] Figure 1D It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0012] Figure 1E It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0013] Figure 2A It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0014] Figure 2B It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0015] Figure 2C It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0016] Figure 2D It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0017] Figure 2E It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0018] Figure 3A It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0019] Figure 3B It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0020] Figure 3C It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0021] Figure 3D It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0022] Figure 4A It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0023] Figure 4B It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0024] Figure 4C It is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0025] Figure 4DIt is a cross-sectional view schematically showing a method for manufacturing a printed wiring board according to an embodiment.

[0026] Description of symbols

[0027] 1: substrate; 2: copper foil; 3: conductor layer; 3a: through hole; 4: roughened surface; 5: metal particle paste; 6: chemically plated copper film; 7: electroplated copper film; 8: anti-corrosion agent; 9: lower conductor circuit; 10: conductor layer; 11: roughened layer; 12L: resin insulating layer; 12U: resin insulating layer; 13: opening for via conductor; 14: seed layer; 14a: Cu / Ti alloy layer; 14b: Cu layer; 15: electroplated copper film; 15A: via conductor; 16: anti-plating agent; 18L: solder mask pattern layer; 18U: solder mask pattern layer; 19: upper conductor circuit; 20: alloy layer; 21L: opening; 21U: opening; 22: gold plating layer; 23: solder bump; 80L: build-up layer; 80U: build-up layer; 100: printed wiring board; 120L: resin layer; 120U: resin layer. DETAILED DESCRIPTION

[0028] <Printed wiring board of embodiment>

[0029] Figure 1A 1 is a cross-sectional view of a printed wiring board 100 according to an embodiment. Figure 1A As shown, printed wiring board 100 includes substrate 1 and build-up layers 80U and 80L formed on the front and back surfaces of substrate 1. On substrate 1, a first conductor layer including lower conductor circuit 9 and conductor layer 10 is formed.

[0030] The build-up layers 80U and 80L are formed by resin insulating layers 12U and 12L, a second conductor layer and a via conductor 15A, wherein the second conductor layer is composed of a seed layer 14 and a copper electroplating film 15 (electroplating film) on the seed layer 14, and the via conductor 15A penetrates the resin insulating layers 12U and 12L and connects the adjacent conductor layers. The resin insulating layers 12U and 12L are second resin insulating layers. The resin insulating layers 12U and 12L have via conductor openings 13 that reach the lower conductor circuit 9 and the conductor layer 10. The resin insulating layers 12U and 12L contain glass particles. The resin insulating layers 12U and 12L contain carbon, oxygen, and silicon.

[0031] The seed layer 14 is formed of a Cu / Ti alloy layer (first film) 14 a in contact with the resin insulating layers 12U, 12L and a Cu layer 14 b (second film) on the Cu / Ti alloy layer 14 a .

[0032] The Cu / Ti alloy layer 14a is formed of an alloy containing copper and titanium. The alloy contains carbon, oxygen and silicon as impurities. The amount of carbon in the alloy is greater than 0.05 at% and less than 25 at%. The amount of oxygen in the alloy is greater than 0.05 at% and less than 25 at%. The amount of silicon in the alloy is greater than 0.05 at% and less than 3 at%. The amount of copper in the alloy is greater than 50 at% and less than 90 at%. The amount of titanium in the alloy is greater than 1 at% and less than 30 at%. The thickness of the Cu / Ti alloy layer 14a is greater than 10 nm and less than 500 nm.

[0033] The Cu layer 14b is formed of copper and has a thickness of 100 nm to 500 nm.

[0034] The second conductor layer includes a plurality of conductor circuits. Among the plurality of conductor circuits, the conductor circuit having the smallest width (the smallest conductor circuit) has a width of 1.5 μm or more and 5 μm or less.

[0035] The Cu / Ti alloy layer 14a in contact with the resin insulating layers 12U and 12L is formed of an alloy containing copper and titanium, and the alloy contains carbon, oxygen, and silicon as impurities. Therefore, the adhesive force with the resin insulating layers 12U and 12L containing carbon, oxygen, and silicon is large. The Cu / Ti alloy layer 14a has a high adhesion with the resin insulating layers 12U and 12L. Therefore, even if the width of the conductor circuit of the second conductor layer is small, it is difficult to peel off from the resin insulating layers 12U and 12L.

[0036] In addition, Figure 1A In the process of multi-layering described later, the following multi-layering process is omitted. Figure 4C The substrate 1 having the upper conductor circuit 19 etc. formed therein is illustrated as having a buildup layer 80U, 80L consisting of resin insulation layers 12U, 12L, a second conductor layer and a via conductor 15A. Actually, through the above-mentioned multilayering process, in the buildup layers 80U, 80L, a resin insulation layer (first resin insulation layer) which is the second layer from the outermost layer is stacked on the inner layer side of the outermost resin insulation layer (second resin insulation layer). A conductor layer (first conductor layer) is formed on the resin insulation layer which is the second layer from the outermost layer. The outermost resin insulation layer is formed on the resin insulation layer which is the second layer from the outermost layer and the first conductor layer. The conductor layer (second conductor layer) formed on the outermost resin insulation layer and the resin insulation layer which is the second layer from the outermost layer are connected to each other through a via conductor formed in an opening for a via conductor reaching the first conductor layer.

[0037] Printed wiring board 100 has solder resist pattern layers 18U and 18L on buildup layers 80A and 80B. Solder resist pattern layers 18U and 18L have openings 21U and 21L. The second conductor layer exposed through openings 21U and 21L functions as a pad for mounting electronic components. Solder bumps 23 for mounting electronic components are formed on the pads.

[0038] <Method for Manufacturing Printed Wiring Board According to Embodiment>

[0039] Figure 1B to Figure 4D A method for manufacturing printed wiring board 100 according to the embodiment will be described. Figure 1B to Figure 4D It is a cross-sectional view.

[0040] like Figure 1B As shown, a copper-clad laminate having copper foil 2 attached to both sides of a substrate 1 is used as a starting material. Figure 1C As shown in FIG. 1 , a through hole for a through hole is formed by drilling a copper-clad laminate. Then, chemical plating is performed to form a chemical plating film on the entire surface of the substrate 1. Furthermore, electroplating copper is performed to form an electroplated copper film. Figure 1D As shown, a conductor layer 3 including through holes 3 a is formed on the entire surface of a substrate 1 .

[0041] The substrate 1 having the conductor layer 3 formed thereon is washed with water and dried. Then, the substrate 1 is subjected to an oxidation-reduction treatment using an oxidation bath (blackening bath) and a reduction bath composed of a predetermined aqueous solution, such as Figure 1E As shown, the roughened surface 4 is formed on the entire surface of the conductor layer 3 including the through hole 3a.

[0042] like Figure 2A As shown, metal particle paste 5 containing copper particles is filled into through hole 3a by screen printing, dried and solidified. Then, the metal particle paste 5 exposed from roughened surface 4 formed on the surface of conductor layer 3 and through hole 3a is removed by grinding to flatten the surface of substrate 1.

[0043] like Figure 2B As shown, the chemically plated copper film 6 is formed by performing chemical plating on the planarized surface of the substrate 1 .

[0044] Thereafter, copper electroplating is performed under predetermined conditions to form a copper electroplating film 7. Figure 2D In the process, the portion that becomes the lower-layer conductor circuit 9 is thickened and the portion that becomes the conductor layer 10 covering the metal particle paste 5 filled in the through hole 3a is formed.

[0045] like Figure 2C As shown, a photosensitive dry film is attached to both surfaces of the substrate 1 where the lower conductor circuit 9 and the conductor layer 10 are formed, and after a mask is placed and exposed, a development process is performed to form a resist 8.

[0046] like Figure 2D As shown, the plated film is dissolved and removed by etching at the portion where the resist 8 is not formed. Thereafter, the resist 8 is removed by lift-off, and the independent lower-layer conductor circuit 9 and conductor layer 10 are formed.

[0047] like Figure 2E As shown, roughened layer 11 is formed on the surfaces of lower conductor circuit 9 and conductor layer 10 , and a Sn layer (not shown) is further formed on the surface of roughened layer 11 .

[0048] like Figure 3A As shown, an epoxy resin composition is applied to both surfaces of substrate 1 to form resin layers 120U, 120L serving as resin insulating layers 12U, 12L.

[0049] like Figure 3B As shown, after the resin layers 120U and 120L are formed, exposure and development treatment using ultraviolet rays are appropriately performed to form the via conductor openings 13. Furthermore, the resin insulating layers 12U and 12L are formed by thermal curing.

[0050] like Figure 3C As shown in FIG. 1 , a Cu / Ti alloy layer 14a is formed on the resin insulating layers 12U, 12L, the via conductor openings 13, the lower conductor circuit 9, and the conductor layer 10 by predetermined sputtering. Furthermore, a Cu layer 14b is formed by predetermined sputtering. In addition, the alloy layer 14a and the Cu layer 14b are thin films, and it is difficult to clearly illustrate the two, so the alloy layer 14a and the Cu layer 14b are combined with the reference numeral 14 and are collectively referred to as "seed layer 14".

[0051] like Figure 3D As shown, a photosensitive dry film is attached to both surfaces of the substrate 1 on which the Cu layer 14 b is formed, a photomask film is placed thereon and exposed, and then a development process is performed to form a pattern of the plating resist 16 .

[0052] like Figure 4A As shown in FIG. 1 , electroplating is performed under specified conditions to form an electroplated copper film 15. In addition, the electroplated copper film 15 is used to thicken the lower conductor circuit 9 and fill the via hole portion with plating (see the following description). Figure 4B ). The via conductor 15A is formed by the electroplated copper film 15 in the via hole portion.

[0053] like Figure 4B As shown, after the plating resist 16 is stripped off, the seed layer 14 present under the plating resist 16 is removed by etching. An upper conductor circuit 19 composed of the seed layer 14 and the electroplated copper film 15 including the via conductor 15A is formed.

[0054] like Figure 4CAs shown in FIG. 1 , the substrate 1 having the upper conductor circuit 19 formed thereon is subjected to a predetermined sputtering process to form an alloy layer 20 composed of Ni—Sn on the surface of the upper conductor circuit 19. Figure 3A to Figure 4C The process is multi-layered.

[0055] Appropriate solder resist composition is applied to both sides of substrate 1 and dried. Then, a photomask having a pattern of solder resist openings is placed in close contact with the solder resist layer, exposed with ultraviolet light, and developed to form openings. Furthermore, the solder resist layer is cured by heating under prescribed conditions, such as Figure 4D As shown, solder resist pattern layers 18U, 18L having openings 21U, 21L are formed.

[0056] The substrate 1 formed with the solder resist pattern layers 18U and 18L is immersed in a predetermined chemical plating solution to form a gold plating layer 22 on the nickel plating layer. After that, solder paste is printed on the openings 21U and 21L of the solder resist pattern layers 18U and 18L, and solder bumps 23 are formed by reflow. The printed wiring board 100 of the embodiment is obtained (see Figure 1A ).

Claims

1. A printed wiring board comprising: a first resin insulating layer; a first conductor layer formed on the first resin insulating layer; a second resin insulating layer formed on the first resin insulating layer and the first conductor layer and having an opening for a via conductor reaching the first conductor layer; a second conductor layer formed on the second resin insulating layer; as well as a via conductor formed in the opening to connect the first conductor layer and the second conductor layer, in, The second conductor layer is composed of a seed layer on the second resin insulation layer and a plated film on the seed layer. the seed layer is formed of a first film in contact with the second resin insulating layer and a second film on the first film, the first film is formed of an alloy including copper and titanium, The alloy contains carbon, oxygen and silicon as impurities, The second film is formed of copper.

2. The printed wiring board according to claim 1, wherein The first film and the second film are formed by sputtering.

3. The printed wiring board according to claim 1, wherein The thickness of the first film is greater than or equal to 10 nm and less than or equal to 500 nm. The second film has a thickness of 100 nm or more and 500 nm or less.

4. The printed wiring board according to claim 1, wherein The amount of carbon in the alloy is 0.05 at % or more and 25 at % or less, The amount of oxygen is 0.05 at % or more and 25 at % or less, The amount of silicon is 0.05 at% or more and 3 at% or less, The amount of copper is 50 at % or more and 90 at % or less, The amount of titanium is 1 at % or more and 30 at % or less.

5. The printed wiring board according to claim 1, wherein The second resin insulating layer contains glass particles.

6. The printed wiring board according to claim 5, wherein The second resin insulating layer contains carbon, oxygen, and silicon.

7. The printed wiring board according to claim 1, wherein The second conductor layer comprises a plurality of conductor circuits. The conductor circuit having the smallest width among the plurality of conductor circuits is the smallest conductor circuit, and a width of the smallest conductor circuit is greater than or equal to 1.5 μm and less than or equal to 5 μm.

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