Semiconductor device, manufacturing method thereof and electronic equipment
Through flip chip bonding and transition layer electrical connection, the hollowing problem and ion implantation difficulty caused by deep burial of bit lines in DRAM devices is solved, improving electrical performance and reducing costs.
Patent Information
- Application Number
- CN202310753419.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-26
- Publication Date
- 2024-12-27
AI Technical Summary
In the process of manufacturing DRAM devices for vertical channel transistors, the bit lines need to be buried deep, resulting in huge holes in the material during preparation, which seriously damages electrical performance. The excessively deep ion implantation position brings huge ion implantation to ion implantation The challenge.
By flip chip bonding, the first bonding layer on the semiconductor layer is bonded to the second bonding layer on the substrate, so that the bit line is transferred between the bottom of the semiconductor column and the surface of the substrate, and the transition layer is used to transfer the bit line to the bottom of the semiconductor column and the substrate surface. The bit lines are electrically connected to the semiconductor column, reducing leakage effects and are packaged and protected by the first and second barrier layers.
The problem of holes in the center of the bit line is solved, the electrical performance is improved, the leakage effect is reduced, the leakage-proof ion implantation process is saved, the cost is reduced, and the structure manufacturing is simplified.
Smart Images
Figure CN119212380A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of storage technology, and specifically relate to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density. With the development of technology, the application of DRAM memory is becoming more and more extensive.
[0003] In the preparation process of DRAM devices containing vertical channel transistors (VCT), since the bit line needs to be buried under the channel, atomic layer deposition is required for preparation. In addition, due to the limitation of deep burial, huge voids will inevitably appear in the middle of the material during preparation, which seriously damages the electrical performance of the DRAM device.
[0004] In traditional memories, the formation of the source, channel, and drain usually relies on ion implantation of different doping types. Therefore, in the process of manufacturing vertical channel transistors, ion implantation is required at different depths of the silicon wafer. Under the premise of being able to effectively repair lattice damage, the requirement for an excessively deep position poses a huge challenge to ion implantation. Summary of the invention
[0005] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.
[0006] In a first aspect, an embodiment of the present disclosure provides a memory, including:
[0007] substrate;
[0008] a second bonding layer disposed on the substrate;
[0009] A first bonding layer disposed on a side of the second bonding layer away from the substrate;
[0010] A bit line disposed on a side of the first bonding layer away from the substrate;
[0011] A semiconductor column disposed on a side of the bit line away from the substrate;
[0012] The semiconductor pillar includes a first electrode, a channel, and a second electrode, the first electrode being electrically connected to the bit line.
[0013] In an exemplary embodiment, the bit line is linear, and the bit line includes a bottom surface located near a side of the substrate, and the bottom surface is flat in an extending direction of the bit line.
[0014] In an exemplary embodiment, a transition layer is further included. The transition layer is disposed between the bit line and the semiconductor pillar. The transition layer electrically connects the bit line to the first electrode. The transition layer includes silicon.
[0015] In an exemplary embodiment, the material of the transition layer is at least one of polysilicon, doped polysilicon and metal silicide.
[0016] In an exemplary embodiment, a first barrier layer and a second barrier layer are further included, wherein the first barrier layer is disposed between the bit line and the first bonding layer, and the second barrier layer is disposed between the bit line and the semiconductor pillar.
[0017] In an exemplary embodiment, a first metal layer and a second metal layer are further included, wherein the first metal layer is disposed on a side of the first barrier layer close to the first bonding layer, and the second metal layer is disposed on a side of the second barrier layer close to the semiconductor pillar.
[0018] In an exemplary embodiment, the first metal layer serves as the first bonding layer.
[0019] In an exemplary embodiment, a gate insulating layer and a gate electrode are further included, and the gate electrode and the gate insulating layer are disposed around the sidewall of the channel of the semiconductor column.
[0020] In a second aspect, an embodiment of the present disclosure further provides an electronic device, comprising the aforementioned semiconductor device.
[0021] In a third aspect, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising:
[0022] providing a semiconductor layer;
[0023] forming a conductive layer on the semiconductor layer;
[0024] forming the first bonding layer on a side of the conductive layer away from the semiconductor layer;
[0025] forming the second bonding layer on the substrate;
[0026] Bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding;
[0027] Using an etching process to form the bit line from the conductive layer;
[0028] The semiconductor layer is formed into the semiconductor pillar.
[0029] In an exemplary embodiment, before the conductive layer is formed into the bit line, the method further includes:
[0030] The semiconductor layer is subjected to a thinning process.
[0031] In an exemplary embodiment, performing a thinning process on the semiconductor layer includes:
[0032] Using a lift-off process to thin the semiconductor layer;
[0033] Alternatively, the semiconductor layer is thinned by using a chemical mechanical polishing process.
[0034] In an exemplary embodiment, thinning the semiconductor layer using a lift-off process includes:
[0035] Before forming a conductive layer on the semiconductor layer, injecting hydrogen ions into a predetermined position of the semiconductor layer to form a peeling layer;
[0036] When the first bonding layer on the semiconductor layer is bonded to the second bonding layer on the substrate by flip chip bonding, one or more cavities are formed in the release layer;
[0037] The release layer is broken to release the semiconductor layer located on a side of the release layer away from the conductive layer.
[0038] In an exemplary embodiment, before forming a conductive layer on the semiconductor layer, the method further includes:
[0039] Doping the semiconductor layer to form a first doping layer and a second doping layer connected to each other;
[0040] After bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding, the method further comprises:
[0041] doping the semiconductor layer so that the semiconductor layer forms a third doping layer located on a side of the first doping layer away from the second doping layer;
[0042] Forming the semiconductor layer into the semiconductor column comprises:
[0043] An etching process is adopted to form a channel in the first doping layer, a first electrode in the second doping layer, and a second electrode in the third doping layer.
[0044] In an exemplary embodiment, before forming a conductive layer on the semiconductor layer, the method further includes:
[0045] forming a transition film on the semiconductor layer, wherein the transition film comprises silicon;
[0046] forming a conductive layer on a side of the transition film away from the semiconductor layer;
[0047] The step of forming the conductive layer into the bit line comprises:
[0048] The transition film is formed into a transition layer by using an etching process, and the conductive layer is formed into the bit line.
[0049] In an exemplary embodiment, forming a conductive layer on the semiconductor layer includes:
[0050] A second metal layer, a second barrier layer, a conductive layer, a first barrier layer and a first metal layer are sequentially formed on the semiconductor layer.
[0051] In an exemplary embodiment, bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding includes:
[0052] forming a first bonding layer on a side of the first metal layer away from the semiconductor layer; or using the first metal layer as the first bonding layer;
[0053] forming a second bonding layer on the substrate;
[0054] The first bonding layer is bonded to the second bonding layer by a flip chip bonding method.
[0055] In an exemplary embodiment, after forming the semiconductor layer into the semiconductor pillar, the method further includes:
[0056] Using an etching process to expose the sidewalls of the semiconductor pillar;
[0057] Using an atomic deposition process, forming a gate insulating layer on the sidewall of the semiconductor column;
[0058] A gate electrode is formed on the gate insulating layer by adopting an atomic deposition process, and the gate electrode and the gate insulating layer are arranged around the side wall of the semiconductor column.
[0059] The substrate and the bit line of the semiconductor device in the embodiment of the present application can be bound by a first bonding layer and a second bonding layer using a flip chip bonding method, so that the bit line is transferred between the bottom of the semiconductor column and the surface of the substrate, so that the bit line has a uniform and tight internal structure, solves the problem of the void in the center of the bit line, and ensures the electrical performance of the semiconductor device.
[0060] The semiconductor device of the embodiment of the present application electrically connects the bit line to the semiconductor column through the transition layer, so that the bit line and the semiconductor column form an ohmic contact, which greatly improves the electrical performance of the bit line.
[0061] The semiconductor device of the embodiment of the present application forms semiconductor pillars on the first bonding layer and the second bonding layer, thereby reducing the leakage effect of the semiconductor device, saving the process of ion implantation related to leakage prevention, and helping to reduce costs.
[0062] The semiconductor device of the embodiment of the present application is convenient for ion implantation into the semiconductor layer by binding the first bonding layer with the second bonding layer, so that the semiconductor layer forms a first electrode, a channel and a second electrode, thereby solving the process problem of ion implantation difficulty during the manufacturing process of the semiconductor device structure.
[0063] The semiconductor device of the embodiment of the present application is used to encapsulate and protect the bit line through the first barrier layer and the second barrier layer, which has the function of isolating oxygen.
[0064] The semiconductor device of the embodiment of the present application uses the first metal layer and the second metal layer to enable the first metal layer to better bond the first barrier layer to other film layers, and the second metal layer to better bond the second barrier layer to other film layers, and the first metal layer can serve as a first bonding layer to bond to the second bonding layer on the substrate.
[0065] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0066] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0067] Figure 1 This is a schematic diagram of the planar structure of a semiconductor device according to an embodiment of the present application;
[0068] Figure 2 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 1 ;
[0069] Figure 3 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 2 ;
[0070] Figure 4a This is a schematic diagram of a semiconductor device after a second doping layer and a first doping layer are formed in a manufacturing process of the semiconductor device according to an embodiment of the present application;
[0071] Figure 4bIt is a schematic diagram of a semiconductor device after a peeling layer is formed in the manufacturing process of the embodiment of the present application;
[0072] Figure 4c It is a schematic diagram after forming a transition film, a second barrier layer, a conductive layer, a first barrier layer and a first metal layer in the manufacturing process of the semiconductor device according to an embodiment of the present application;
[0073] Figure 4d This is a schematic diagram of a semiconductor device after a second bonding layer is formed in a manufacturing process of the semiconductor device according to an embodiment of the present application;
[0074] Figure 4e This is a schematic diagram of a first bonding layer and a second bonding layer after bonding during the manufacturing process of a semiconductor device according to an embodiment of the present application;
[0075] Figure 4f This is a schematic diagram of a semiconductor layer after a thinning process is performed during the manufacturing process of a semiconductor device according to an embodiment of the present application;
[0076] Figure 4g This is a schematic diagram of a semiconductor device after a gate insulating layer and a gate electrode are formed during the manufacturing process of the semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION
[0077] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.
[0078] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.
[0079] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
[0080] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.
[0081] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.
[0082] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The memory has a channel region between a drain electrode (also referred to as a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (also referred to as a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region through which current mainly flows.
[0083] In this specification, the first electrode mentioned below may be a drain electrode, and the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In practical applications, which of the first electrode and the second electrode is the source electrode and which is the drain electrode is related to the direction of current flow. Generally, current flows from the source electrode to the drain electrode. In the case of using transistors with opposite polarities or the case where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.
[0084] In this specification, "electrical connection" includes the situation where the components are connected together through an element having some electrical function, such as a physical connection relationship or a signal connection relationship. There is no particular limitation on the "element having some electrical function" as long as it can carry out electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
[0085] In this specification, the following parallel or perpendicular means approximately parallel and approximately perpendicular within the error range. "Parallel" means the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.
[0086] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".
[0087] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.
[0088] An embodiment of the present application provides a semiconductor device, including:
[0089] substrate;
[0090] a second bonding layer disposed on the substrate;
[0091] A first bonding layer disposed on a side of the second bonding layer away from the substrate;
[0092] A bit line disposed on a side of the first bonding layer away from the substrate;
[0093] A semiconductor column disposed on a side of the bit line away from the substrate;
[0094] The semiconductor pillar includes a first electrode, a channel, and a second electrode, the first electrode being electrically connected to the bit line.
[0095] In an exemplary embodiment, the bit line is linear, and the bit line includes a bottom surface located near a side of the substrate, and the bottom surface is flat in an extending direction of the bit line.
[0096] In an exemplary embodiment, a transition layer is further included. The transition layer is disposed between the bit line and the semiconductor pillar. The transition layer electrically connects the bit line to the first electrode. The transition layer includes silicon.
[0097] The solution of this embodiment is described below by means of some examples.
[0098] Figure 1 FIG. 1 is a schematic diagram of a planar structure of a semiconductor device according to an embodiment of the present application. In an exemplary embodiment, Figure 1As shown, the semiconductor device of the embodiment of the present application includes a substrate and a plurality of mutually spaced memory cells 11 disposed on the substrate. The memory cells 11 include a word line 12 disposed on the substrate and extending along a first direction D1, a bit line 13 extending along a second direction D2, a semiconductor column 50 extending along a direction perpendicular to the substrate, and a gate that surrounds a channel of the semiconductor column 50 and is insulated from each other.
[0099] In an exemplary embodiment, if Figure 1 As shown, a plurality of mutually spaced memory cells 11 are spaced apart and arranged along a first direction D1 to form a memory cell row, and a word line 12 is electrically connected to the gates of all the memory cells 11 in a memory cell row.
[0100] In an exemplary embodiment, if Figure 1 As shown, a plurality of mutually spaced memory cells 11 are spaced apart and arranged along the second direction D2 to form a memory cell column, and a bit line 13 is electrically connected to electrodes of semiconductor pillars 50 of all memory cells 11 in a memory cell column.
[0101] In an exemplary embodiment, the bit line 13 may be made of a metal material, such as tungsten.
[0102] In an exemplary embodiment, the orthographic projection of the semiconductor pillar 14 on the substrate may adopt various shapes, for example, regular or irregular shapes such as circle, ellipse, rectangle, diamond, triangle, pentagon, hexagon, etc.
[0103] The semiconductor device of the embodiment of the present application has a vertical channel transistor (Vertical Channel Transistor, VCT). The semiconductor device of the embodiment of the present application can be used as a dynamic random access memory (Dynamic Random Access Memory, DRAM), which can reduce the area of the memory and improve the storage density.
[0104] In some embodiments, the semiconductor device of the embodiment of the present application may also be other storage structures in which the bit lines are buried in the channel close to the substrate side, and the embodiment of the present application will not be described in detail here.
[0105] Figure 2 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 1 , Figure 3 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 2 .in, Figure 2 Can be Figure 1 Schematic diagram of the cross section along the a-a' direction; Figure 3 Can be Figure 1 In the exemplary embodiment, as shown in FIG. Figure 2 and Figure 3As shown, in a direction perpendicular to the substrate, the memory cell 11 includes a second bonding layer 22 disposed on the substrate 101, a first bonding layer 21 disposed on a side of the second bonding layer 22 away from the substrate 101, a first metal layer disposed on a side of the first bonding layer 21 away from the substrate 101, a first barrier layer 31 disposed on a side of the first metal layer away from the substrate 101, a bit line 13 disposed on a side of the first barrier layer 31 away from the substrate 101, a second barrier layer 32 disposed on a side of the bit line 13 away from the substrate 101, a second metal layer 41 disposed on a side of the second barrier layer 32 away from the substrate 101, a transition layer 40 disposed on a side of the second metal layer 41 away from the substrate 101, and a semiconductor pillar 50 disposed on a side of the transition layer 40 away from the substrate 101. The first metal layer can be used as a first bonding layer for bonding with the second bonding layer, that is, the first metal layer and the first bonding layer are the same film layer.
[0106] In an exemplary embodiment, the materials of the first metal layer and the first bonding layer are both titanium, and the material of the second bonding layer is silicon dioxide.
[0107] In some embodiments, the first metal layer and the first bonding layer may be film layers of different materials, and the first bonding layer is disposed on a side of the first metal layer away from the substrate, which will not be described in detail in the embodiments of the present disclosure.
[0108] In an exemplary embodiment, the material of the first bonding layer and the material of the second bonding layer are both titanium; or, the material of the first bonding layer is titanium, and the material of the second bonding layer is silicon; or, the material of the first bonding layer is silicon dioxide, and the material of the second bonding layer is silicon dioxide; or, the material of the first bonding layer is silicon, and the material of the second bonding layer is silicon dioxide.
[0109] The substrate 101 and the bit line 13 of the semiconductor device in the embodiment of the present application can be bound by a first bonding layer 21 and a second bonding layer 22 using a flip chip bonding method, so that the bit line is transferred between the bottom of the semiconductor column and the surface of the substrate, so that the bit line 13 has a uniform and tight internal structure, solves the problem of the void in the center of the bit line 13, and ensures the electrical performance of the semiconductor device.
[0110] In an exemplary embodiment, the bit line 13 is linear, and the bit line 13 includes a bottom surface located on a side close to the substrate 101, and the bottom surface is flat in the extension direction of the bit line 13. The bit line of the semiconductor device of the embodiment of the present application is first formed by depositing a conductive film, then by an etching process, and finally, by a flip chip bonding method, the bit line is transferred between the bottom of the semiconductor column and the surface of the substrate, so that the surface (e.g., bottom surface) of the bit line 13 is flat, and the inside is uniform and tight, thereby ensuring the electrical performance of the bit line 13.
[0111] In an exemplary embodiment, the semiconductor pillar 50 includes a first electrode 51, a second electrode 53, and a channel 52 located between the first electrode 51 and the second electrode 53. The first electrode 51 and the second electrode 53 are both electrically connected to the channel 52. The first electrode 51 is located on a side of the channel 52 close to the substrate 101, and the first electrode 51 is electrically connected to the bit line 13; the second electrode 53 is located on a side of the channel 52 away from the substrate 101, and the first electrode 51 is connected to the second electrode through the channel 52.
[0112] In an exemplary embodiment, the first electrode 51 is electrically connected to the bit line 13 through a transition layer 40. The transition layer 40 includes silicon. For example, the transition layer 40 may be made of at least one of polysilicon, doped polysilicon and silicide.
[0113] In an exemplary embodiment, the material of the transition layer 40 is phosphorus-doped polysilicon, boron-doped polysilicon, indium-doped polysilicon, arsenic-doped polysilicon, aluminum-doped polysilicon, antimony-doped polysilicon, or bismuth-doped polysilicon, and the concentration of the dopant in the doped polysilicon is 10 18 -10 20 cm -3 .
[0114] The semiconductor device of the embodiment of the present application electrically connects the bit line 13 to the first electrode 51 of the semiconductor column 50 through the transition layer 40 , so that the bit line 13 and the first electrode 51 can easily form an ohmic contact, which greatly improves the electrical performance of the bit line 13 .
[0115] In an exemplary embodiment, the first barrier layer 31 and the second barrier layer 32 are used to encapsulate and protect the bit line 13 and have the function of isolating oxygen. The material of the first barrier layer 31 and the second barrier layer 32 can both be titanium nitride.
[0116] In an exemplary embodiment, the first metal layer and the second metal layer 41 can play an adhesion role, so that the first metal layer can better bond the first barrier layer with other film layers, and the second metal layer can better bond the second barrier layer with other film layers. In addition, the first metal layer can serve as a first bonding layer 21, bonded to the second bonding layer 22 on the substrate.
[0117] In an exemplary embodiment, if Figure 2 As shown, in the second direction D2, a first trench 61 is provided between the semiconductor pillars 50 of adjacent memory cells, the first trench 61 extends along the first direction D1, the first trench 61 extends to the transition layer 40, and the bottom wall of the first trench 61 is the surface of the transition layer 40 away from the substrate. The bit line and the gate are provided in the first trench 61. The first direction D1 intersects with the second direction D2, and for example, the first direction D1 is perpendicular to the second direction D2.
[0118] In an exemplary embodiment, if Figure 3 As shown, in the first direction D1, a second trench 62 is provided between the semiconductor pillars 50 of adjacent memory cells, the second trench 62 extends to the second bonding layer 22, and the bottom wall of the second trench 62 is the surface of the second bonding layer 22 away from the substrate. The second trench 62 extends along the second direction D2, and an insulating dielectric layer 63 is provided in the second trench 62, and the insulating dielectric layer 63 separates the first bonding layer 21, the bit line 13, the transition layer 40 and the semiconductor pillar 50 of the adjacent memory cells in the first direction D1. The material of the insulating dielectric layer 63 can be an inorganic material, and for example, the material of the insulating dielectric layer 63 can be silicon dioxide.
[0119] In an exemplary embodiment, the memory cell further includes a gate electrode, which is disposed around the outside of the channel 52, and the gate electrode extends on the sidewall of the channel 52 to form a ring-shaped conductive layer extending in a direction perpendicular to the substrate. A gate insulating layer is disposed between the gate electrode and the channel 52, and the gate insulating layer separates the gate electrode from the channel 52, thereby insulating the gate electrode from the channel 52.
[0120] The ring-gate structure of the transistor in the embodiment of the present application has strong gate control, can increase the area of the channel region, and can improve the retention time. In addition, the ring-gate structure can reduce the area of the semiconductor device.
[0121] The embodiment of the present application further provides a method for manufacturing a semiconductor device, wherein the semiconductor device may be any of the semiconductor devices described above, and the method for manufacturing the semiconductor device includes:
[0122] providing a semiconductor layer;
[0123] forming a conductive layer on the semiconductor layer;
[0124] forming the first bonding layer on a side of the conductive layer away from the semiconductor layer;
[0125] forming the second bonding layer on the substrate;
[0126] Bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding;
[0127] Using an etching process to form the bit line from the conductive layer;
[0128] The semiconductor layer is formed into the semiconductor pillar.
[0129] In an exemplary embodiment, before the conductive layer is formed into the bit line, the method further includes:
[0130] The semiconductor layer is subjected to a thinning process.
[0131] In an exemplary embodiment, performing a thinning process on the semiconductor layer includes:
[0132] Using a lift-off process to thin the semiconductor layer;
[0133] Alternatively, the semiconductor layer is thinned by using a chemical mechanical polishing process.
[0134] In an exemplary embodiment, thinning the semiconductor layer using a lift-off process includes:
[0135] Before forming a conductive layer on the semiconductor layer, injecting hydrogen ions into a predetermined position of the semiconductor layer to form a peeling layer;
[0136] Bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding, and forming one or more cavities in the peeling layer;
[0137] The release layer is broken to release the semiconductor layer located on a side of the release layer away from the conductive layer.
[0138] In an exemplary embodiment, before forming a conductive layer on the semiconductor layer, the method further includes:
[0139] Doping the semiconductor layer to form a first doping layer and a second doping layer connected to each other;
[0140] Forming the semiconductor layer into the semiconductor column comprises:
[0141] The first doped layer forms a channel, and the second doped layer forms a first electrode.
[0142] In an exemplary embodiment, before forming a conductive layer on the semiconductor layer, the method further includes:
[0143] Doping the semiconductor layer to form a first doping layer and a second doping layer connected to each other;
[0144] After bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding, the method further comprises:
[0145] doping the semiconductor layer so that the semiconductor layer forms a third doping layer located on a side of the first doping layer away from the second doping layer;
[0146] Forming the semiconductor layer into the semiconductor column comprises:
[0147] An etching process is adopted to form a channel in the first doping layer, a first electrode in the second doping layer, and a second electrode in the third doping layer.
[0148] In an exemplary embodiment, before forming a conductive layer on the semiconductor layer, the method further includes:
[0149] forming a transition film on the semiconductor layer, wherein the transition film comprises silicon;
[0150] forming a conductive layer on a side of the transition film away from the semiconductor layer;
[0151] The step of forming the conductive layer into the bit line comprises:
[0152] The transition film is formed into a transition layer by using an etching process, and the conductive layer is formed into the bit line.
[0153] In an exemplary embodiment, forming a conductive layer on the semiconductor layer includes:
[0154] A second metal layer, a second barrier layer, a conductive layer, a first barrier layer and a first metal layer are sequentially formed on the semiconductor layer.
[0155] In an exemplary embodiment, the flip chip bonding method of bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate includes:
[0156] forming a first bonding layer on a side of the first metal layer away from the semiconductor layer; or using the first metal layer as the first bonding layer;
[0157] forming a second bonding layer on the substrate;
[0158] The first bonding layer is bonded to the second bonding layer by a flip chip bonding method.
[0159] The technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".
[0160] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:
[0161] S101) Provide a semiconductor layer 71, wherein the semiconductor layer 71 can be a P-type silicon wafer.
[0162] S102) P-type doping (doping B) and N-type doping (doping P) are performed at different depths of the semiconductor layer 71 through an ion implantation process; subsequently, a heat treatment is performed to repair the lattice, and the P-type doping region in the semiconductor layer 71 forms a first doping layer 72, and the N-type doping region forms a second doping layer 73, and the second doping layer 73 is connected to the first doping layer 72, as shown in FIG. Figure 4a The first doping layer 72 is used to form a channel later, and the second doping layer 73 is used to form a first electrode later.
[0163] S103) injecting an appropriate dose of hydrogen ions into a predetermined position of the semiconductor layer 71, the hydrogen ions are concentrated in the semiconductor layer 71, and a stripping layer 74 is formed. The stripping layer 74 is located on the side of the first doping layer 72 away from the second doping layer 73, and the stripping layer 74 penetrates the semiconductor layer 71 along the second direction D2. Figure 4b shown.
[0164] S104) forming a transition film 75, a second metal layer 41, a second barrier layer 32, a conductive layer 77, a first barrier layer 31 and a first bonding layer 21 (first metal layer) on the second doping layer 73 of the semiconductor layer 71 in sequence, as shown in FIG. Figure 4cAs shown, the material of the first bonding layer 21 may be titanium metal, the first bonding layer 21 may be a first metal layer, and the material of the conductive layer 77 may be tungsten metal. The transition film 75 is used to form a subsequent transition layer, and the conductive layer 77 is used to form a subsequent bit line.
[0165] S105) providing a substrate 101, and then forming a second bonding layer 22 on the substrate 101, such as Figure 4d The material of the substrate 101 may be a silicon wafer; the material of the second bonding layer 22 may be silicon dioxide.
[0166] S106) The first bonding layer 21 on the semiconductor layer 71 is bonded to the second bonding layer 22 on the substrate 101 by flip chip bonding, and one or more cavities are formed in the peeling layer 74 through a heat treatment process during bonding. Figure 4e shown.
[0167] S107) performing a thinning process on the semiconductor layer. The thinning process on the semiconductor layer includes: breaking the stripping layer 74, stripping the semiconductor layer located on the side of the stripping layer 74 away from the conductive layer 77, and retaining part of the semiconductor layer 71, the first doping layer 72 and the second doping layer 73; then performing N-type doping (doping P) on the retained semiconductor layer 71 to form a third doping layer 78 on the semiconductor layer, and the third doping layer 78 is located on the side of the first doping layer 72 away from the second doping layer 73, such as Figure 4f At this time, the semiconductor layer includes a second doping layer 73, a first doping layer 72 and a third doping layer 78 arranged in sequence in a direction away from the substrate 101, the second doping layer 73 is used to form a first electrode, the first doping layer 72 is used to form a channel, and the third doping layer 78 is used to form a second electrode.
[0168] The preparation process of the semiconductor device in the embodiment of the present application adopts a stripping process to thin the semiconductor layer. The stripped semiconductor layer can be reused, saving the material of the semiconductor layer and reducing the loss.
[0169] In some embodiments, a chemical mechanical polishing process may be used to thin the semiconductor layer.
[0170] S108) forms a second groove. Forming the second groove includes: forming a plurality of second grooves 62 in the third doping layer 78, the first doping layer 72, the second doping layer 73, the transition film 75, the second barrier layer 32, the conductive layer 77, the first barrier layer 31 and the first bonding layer 21, wherein the plurality of second grooves 62 are arranged at intervals along the first direction D1, the second grooves 62 extend along the second direction D2, the second grooves 62 extend to the second bonding layer 22, and the bottom wall of the second groove 62 is the surface of the second bonding layer 22 and the side away from the substrate. The transition film forms a transition layer 40, and the conductive layer forms a bit line 13; then, the insulating dielectric layer 63 is filled in the second groove 62, and the insulating dielectric layer 63 separates the adjacent first bonding layer 21, the bit line 13, the transition layer 40, the first electrode 51, the channel 52 and the drain electrode in the first direction D1, as shown in FIG. Figure 3 shown.
[0171] S109) forming a first groove. The forming of the first groove includes: forming a plurality of first grooves 61 in the third doping layer 78, the first doping layer 72 and the second doping layer 73, the plurality of first grooves 61 are arranged at intervals along the second direction D1, the first grooves 61 extend along the first direction D1, the first grooves 61 extend to the transition layer 40, and the bottom wall of the first groove 61 is the surface of the transition layer 40 away from the substrate. The third doping layer forms the second electrode 53, the first doping layer forms the channel 52, and the second doping layer forms the first electrode 51, as shown in FIG. Figure 2 The first electrode 51 , the channel 52 and the second electrode 53 form a semiconductor column 50 extending in a direction perpendicular to the substrate, and the first trench 61 exposes the sidewalls of the first electrode 51 , the channel 52 and the second electrode 53 of the semiconductor column 50 .
[0172] In some embodiments, step S105) may be performed simultaneously with steps S101) to S104), or may be performed before steps S101) to S104), or may be performed after steps S101) to S104), and the embodiments of the present application will not be described in detail herein.
[0173] In some embodiments, step S102) may be performed after step S107).
[0174] S120) forming a gate insulating layer and a gate electrode.
[0175] The gate insulating layer and the gate electrode are formed by: forming a gate insulating layer 82 on the exposed sidewall of the semiconductor column by an atomic deposition process; then, forming a gate electrode 82 on the gate insulating layer 82 by an atomic deposition process, wherein the gate electrode 82 surrounds the sidewall of the channel 52 of the semiconductor column through the gate insulating layer 81, as shown in FIG. Figure 4g shown.
[0176] The manufacturing method of the semiconductor device of the present application has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost and high yield rate.
[0177] The manufacturing method of the semiconductor device in the embodiment of the present application can bind the substrate and the bit line through the first bonding layer and the second bonding layer by means of flip chip bonding, so that the bit line has a uniform and tight internal structure, solves the problem of the void in the center of the bit line, and ensures the electrical performance of the semiconductor device.
[0178] The method for manufacturing a semiconductor device in the embodiment of the present application electrically connects the bit line to the source electrode of the semiconductor column through a transition layer, so that the bit line and the source electrode can easily form an ohmic contact, which greatly improves the electrical performance of the bit line.
[0179] The semiconductor device of the embodiment of the present application forms semiconductor pillars on the first bonding layer and the second bonding layer, thereby reducing the leakage effect of the semiconductor device, saving the process of ion implantation related to leakage prevention, and helping to reduce costs.
[0180] The semiconductor device of the embodiment of the present application is convenient for ion implantation into the semiconductor layer by binding the first bonding layer with the second bonding layer, so that the semiconductor layer forms a first electrode, a channel and a second electrode, thereby solving the process problem of ion implantation difficulty during the manufacturing process of the semiconductor device structure.
[0181] The semiconductor device of the embodiment of the present application is used to encapsulate and protect the bit line through the first barrier layer and the second barrier layer, which has the function of isolating oxygen.
[0182] The semiconductor device of the embodiment of the present application uses the first metal layer and the second metal layer to enable the first metal layer to better bond the first barrier layer to other film layers, and the second metal layer to better bond the second barrier layer to other film layers, and the first metal layer can serve as a first bonding layer to bond to the second bonding layer on the substrate.
[0183] The embodiment of the present application also provides an electronic device, comprising any of the semiconductor devices described above. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device.
[0184] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.
[0185] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.
Claims
1. A semiconductor device, characterized in that: include: substrate; a second bonding layer disposed on the substrate; A first bonding layer disposed on a side of the second bonding layer away from the substrate; A bit line disposed on a side of the first bonding layer away from the substrate; A semiconductor column disposed on a side of the bit line away from the substrate; The semiconductor pillar includes a first electrode, a channel, and a second electrode, the first electrode being electrically connected to the bit line.
2. The semiconductor device according to claim 1, wherein: The bit line is linear and includes a bottom surface located close to one side of the substrate, and the bottom surface is flat in the extending direction of the bit line.
3. The semiconductor device according to claim 1, wherein: The device further comprises a transition layer, wherein the transition layer is disposed between the bit line and the semiconductor column, the transition layer electrically connects the bit line to the first electrode, and the transition layer comprises silicon element.
4. The semiconductor device according to claim 3, characterized in that The material of the transition layer is at least one of polysilicon, doped polysilicon and metal silicide.
5. The semiconductor device according to claim 1, wherein: The invention also includes a first barrier layer and a second barrier layer, wherein the first barrier layer is disposed between the bit line and the first bonding layer, and the second barrier layer is disposed between the bit line and the semiconductor pillar.
6. The semiconductor device according to claim 5, characterized in that The first metal layer is arranged on a side of the first barrier layer close to the first bonding layer, and the second metal layer is arranged on a side of the second barrier layer close to the semiconductor column.
7. The semiconductor device according to claim 6, characterized in that The first metal layer serves as the first bonding layer.
8. The semiconductor device according to any one of claims 1 to 7, characterized in that: It also includes a gate insulating layer and a gate electrode disposed on the substrate, wherein the gate electrode and the gate insulating layer are disposed around the side wall of the channel of the semiconductor column.
9. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 8.
10. A method for manufacturing a semiconductor device, characterized in that: The method for manufacturing the semiconductor device comprises: providing a semiconductor layer; forming a conductive layer on the semiconductor layer; forming a first bonding layer on a side of the conductive layer away from the semiconductor layer; forming a second bonding layer on the substrate; Bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding; Using an etching process to form a bit line on the conductive layer; The semiconductor layer is formed into the semiconductor pillar.
11. The method for manufacturing a semiconductor device according to claim 10, wherein: Before the conductive layer is formed into the bit line, the method further includes: The semiconductor layer is subjected to a thinning process.
12. The method for manufacturing a semiconductor device according to claim 11, wherein: The process of thinning the semiconductor layer includes: Using a lift-off process to thin the semiconductor layer; Alternatively, the semiconductor layer is thinned by using a chemical mechanical polishing process.
13. The method for manufacturing a semiconductor device according to claim 12, wherein: The thinning of the semiconductor layer by a lift-off process includes: Before forming a conductive layer on the semiconductor layer, injecting hydrogen ions into a predetermined position of the semiconductor layer to form a peeling layer; When the first bonding layer on the semiconductor layer is bonded to the second bonding layer on the substrate by flip chip bonding, one or more cavities are formed in the release layer; The release layer is broken to release the semiconductor layer located on a side of the release layer away from the conductive layer.
14. The method for manufacturing a semiconductor device according to claim 10, wherein: Before forming a conductive layer on the semiconductor layer, the method further comprises: Doping the semiconductor layer to form a first doping layer and a second doping layer connected to each other; After bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding, the method further comprises: doping the semiconductor layer so that the semiconductor layer forms a third doping layer located on a side of the first doping layer away from the second doping layer; Forming the semiconductor layer into the semiconductor column comprises: An etching process is adopted to form a channel in the first doping layer, a first electrode in the second doping layer, and a second electrode in the third doping layer.
15. The method for manufacturing a semiconductor device according to claim 10, wherein: Before forming a conductive layer on the semiconductor layer, the method further comprises: forming a transition film on the semiconductor layer, wherein the transition film comprises silicon; forming a conductive layer on a side of the transition film away from the semiconductor layer; The step of forming the conductive layer into the bit line comprises: The transition film is formed into a transition layer by using an etching process, and the conductive layer is formed into the bit line.
16. The method for manufacturing a semiconductor device according to claim 10, wherein: Forming a conductive layer on the semiconductor layer comprises: A second metal layer, a second barrier layer, a conductive layer, a first barrier layer and a first metal layer are sequentially formed on the semiconductor layer.
17. The method for manufacturing a semiconductor device according to claim 16, wherein: Bonding the first bonding layer on the semiconductor layer to the second bonding layer on the substrate by flip chip bonding includes: forming a first bonding layer on a side of the first metal layer away from the semiconductor layer; or using the first metal layer as the first bonding layer; forming a second bonding layer on the substrate; The first bonding layer is bonded to the second bonding layer by a flip chip bonding method.
18. The method for manufacturing a semiconductor device according to any one of claims 10 to 17, characterized in that: After the semiconductor layer is formed into the semiconductor column, the method further includes: Using an etching process to expose the sidewalls of the semiconductor pillar; Using an atomic deposition process, forming a gate insulating layer on the sidewall of the semiconductor column; A gate electrode is formed on the gate insulating layer by adopting an atomic deposition process, and the gate electrode and the gate insulating layer are arranged around the side wall of the semiconductor column.