Semiconductor device, manufacturing method thereof and electronic equipment
Through flip chip bonding and high-stress thin film technology, the problem of large material loss in semiconductor device preparation is solved, the process flow is simplified, the cost is reduced, and the conductivity and electrical performance is improved, and efficient semiconductor device manufacturing is achieved.
Patent Information
- Application Number
- CN202310753425.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-26
- Publication Date
- 2024-12-27
AI Technical Summary
In the preparation process of semiconductor devices containing vertical channel transistors, a large number of chemical mechanical grinding processes are required to perform a very thick single crystal silicon substrate, resulting in long process cycles, large material losses and high costs, which seriously restricts the development of technology.
By flip chip bonding, the semiconductor layer is bonded to the substrate, and a peeling layer is formed at the bottom of the first groove of the semiconductor layer to peel it, forming a support column and depositing a high-stress film to break the peeling layer, reducing material Loss and improves conductivity and packaging protection by forming a barrier layer and metal layer.
It has achieved the reduction of the loss of semiconductor layer materials, simplified process flow, reduced production costs, improved the conductivity and electrical performance of bit lines, and improved process compatibility and production efficiency.
Smart Images
Figure CN119212381A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure relate to, but are not limited to, the field of storage technology, and specifically relate to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density. With the development of technology, the application of DRAM memory is becoming more and more extensive.
[0003] In the preparation process of semiconductor devices containing vertical channel transistors (VCT), such as DRAM devices, a large number of chemical mechanical polishing steps are required to grind a very thick single crystal silicon substrate to the required thickness. This not only requires a long process cycle, but also causes a large amount of single crystal silicon loss, resulting in high costs, which seriously restricts the technological development of the process. Summary of the invention
[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.
[0005] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising:
[0006] providing a semiconductor layer;
[0007] Performing a patterning process on the semiconductor layer to form a plurality of first grooves and walls that are spaced apart and extend along a first direction;
[0008] forming a peeling layer at the bottom of the first groove;
[0009] forming a conductive structural layer on the top of the wall;
[0010] Bonding the side of the semiconductor layer where the conductive structure layer is formed to the substrate by flip chip bonding;
[0011] The peeling layer is broken to peel off the bottom of the first groove from the wall;
[0012] The conductive structure layer is formed into a bit line, and the plurality of walls are respectively formed into semiconductor columns, wherein the semiconductor columns include a first electrode, a channel and a second electrode.
[0013] In an exemplary embodiment, forming a release layer at the bottom of the first groove includes:
[0014] forming a barrier film on the plurality of walls and the first groove;
[0015] Etching and removing the blocking film on the bottom of the first groove;
[0016] Using an etching process, etching the bottom of the first groove to form a support column at the connection between the wall and the semiconductor layer;
[0017] The electron cyclotron resonance low-temperature nitridation process is adopted to form a nitride with high stress on the support column.
[0018] In an exemplary embodiment, after forming the support column into a nitride with high stress, the method further includes:
[0019] An atomic layer deposition process is used to deposit a high stress film on the sidewall of the support column to form a peeling layer having one or more holes at the bottom of the first groove.
[0020] In an exemplary embodiment, the material of the high stress film is the same as the nitride formed by the support pillar.
[0021] In an exemplary embodiment, the middle portion of the side wall of the support column is an arc-shaped structure recessed toward the inside of the support column; the plurality of holes in the stripping layer are spaced apart in a direction parallel to the plane where the semiconductor layer is located, and the material of the stripping layer is disposed between adjacent holes.
[0022] In an exemplary embodiment, the release layer is fractured by a heat treatment process or ultraviolet light irradiation.
[0023] In an exemplary embodiment, a conductive structural layer is formed on top of the wall, comprising:
[0024] forming a first metal layer, a second barrier layer, a conductive layer, a first barrier layer and a second metal layer in sequence on the top of the wall;
[0025] The first metal layer, the second barrier layer, the conductive layer, the first barrier layer and the second metal layer form the conductive structure layer.
[0026] In an exemplary embodiment, before forming the conductive structure layer on the top of the wall, the method further includes:
[0027] At least one transition layer is formed on the top of the wall; wherein the transition layer includes silicon element.
[0028] In an exemplary embodiment, bonding the side of the semiconductor layer on which the conductive structure layer is formed to the substrate by flip chip bonding includes:
[0029] forming a first bonding layer on a side of the second metal layer away from the wall; or using the second metal layer as the first bonding layer;
[0030] forming a second bonding layer on the substrate;
[0031] The first bonding layer is bonded to the second bonding layer by a flip chip bonding method.
[0032] In a second aspect, an embodiment of the present disclosure further provides a semiconductor device, comprising a substrate, a bit line arranged on one side of the substrate surface, and a semiconductor column arranged on a side of the bit line away from the substrate, wherein the substrate surface is a flat surface, the semiconductor column extends in a direction perpendicular to the substrate, the semiconductor column comprises a first electrode, a channel, and a second electrode, and the first electrode is electrically connected to the bit line.
[0033] In an exemplary embodiment, it also includes a first metal layer, a second barrier layer, a first barrier layer and a second metal layer, the second barrier layer is arranged on the side of the bit line close to the substrate, the first metal layer is arranged on the side of the second barrier layer close to the substrate, the first barrier layer is arranged on the side of the bit line away from the substrate, and the second metal layer is arranged on the side of the first barrier layer away from the substrate.
[0034] In an exemplary embodiment, a first bonding layer is further included, and the first bonding layer is arranged on a side of the second metal layer away from the substrate, or the second metal layer serves as the first bonding layer.
[0035] In an exemplary embodiment, at least one transition layer is further included. The transition layer is disposed between the bit line and the semiconductor column. The bit line is electrically connected to the semiconductor column through the transition layer. The transition layer includes silicon.
[0036] In an exemplary embodiment, the bit line is linear, and the bit line includes a bottom surface located near a side of the substrate, and the bottom surface is flat in an extending direction of the bit line.
[0037] In a third aspect, an embodiment of the present disclosure further provides an electronic device, comprising the aforementioned semiconductor device.
[0038] The preparation process of the semiconductor device in the embodiment of the present application forms a peeling layer at the bottom of the first groove of the semiconductor layer. After the semiconductor layer is bonded to the substrate, the peeling layer is peeled off, and the peeled semiconductor layer can be reused, thereby saving the material of the semiconductor layer and reducing the loss.
[0039] The manufacturing method of the semiconductor device in the embodiment of the present application forms a support column at the connection between the wall and the semiconductor layer, and forms a nitride with high stress on the support column, so that the peeling layer is easy to be peeled off.
[0040] The manufacturing method of the semiconductor device in the embodiment of the present application deposits a high-stress film so that the high-stress film and the support pillar form a peeling layer with one or more holes, so that the peeling layer can be easily peeled off.
[0041] The method for manufacturing a semiconductor device in an embodiment of the present application forms the first barrier layer and the second barrier layer to encapsulate and protect the conductive layer, thereby isolating oxygen.
[0042] The manufacturing method of the semiconductor device in the embodiment of the present application forms the first metal layer and the second metal layer, so that the first metal layer can better bond the second barrier layer and other film layers together, and the second metal layer can better bond the first barrier layer and other film layers together, and the second metal layer can serve as a first bonding layer to bond with the second bonding layer on the substrate.
[0043] The manufacturing method of the semiconductor device in the embodiment of the present application adopts a flip-chip bonding method to transfer the bit line to between the bottom of the semiconductor column and the surface of the substrate, so that the bit line has a uniform and tight internal structure and low resistance, avoids the occurrence of voids in the bit line, and improves the conductivity of the bit line.
[0044] The manufacturing method of the semiconductor device in the embodiment of the present application adopts a flip-chip bonding method to facilitate ion implantation into the wall to form the first electrode, the channel and the second electrode of the semiconductor column, thereby solving the problem of difficult ion implantation in the semiconductor device structure manufacturing process.
[0045] The manufacturing method of the semiconductor device of the embodiment of the present application adopts at least one transition layer to electrically connect the bit line to the semiconductor column through the transition layer, thereby reducing the contact resistance between the bit line and the semiconductor column, forming an ohmic contact between the bit line and the semiconductor column, and greatly improving the electrical performance of the bit line.
[0046] The manufacturing method of the semiconductor device of the present application has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost and high yield rate.
[0047] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0049] Figure 1 This is a schematic diagram of the planar structure of a semiconductor device according to an embodiment of the present application;
[0050] Figure 2 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 1 ;
[0051] Figure 3 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 2 ;
[0052] Figure 4a This is a schematic diagram of a semiconductor device after a first doping layer and a second doping layer are formed in a manufacturing process of the semiconductor device according to an embodiment of the present application;
[0053] Figure 4b This is a schematic diagram of a semiconductor device after a wall is formed in the manufacturing process of the embodiment of the present application;
[0054] Figure 4c This is a schematic diagram of etching the barrier film on the bottom of the first groove during the manufacturing process of the semiconductor device according to the embodiment of the present application;
[0055] Figure 4d This is a schematic diagram of a semiconductor device after a support column is formed in a manufacturing process of the semiconductor device according to an embodiment of the present application;
[0056] Figure 4e This is a schematic diagram of forming nitride on a support column during the manufacturing process of a semiconductor device according to an embodiment of the present application;
[0057] Figure 4f It is a schematic diagram of a semiconductor device after a peeling layer is formed in the manufacturing process of the embodiment of the present application;
[0058] Figure 4g It is a schematic diagram after forming a first transition layer, a second transition layer, a first metal layer, a second barrier layer, a conductive layer, a first barrier layer and a second metal layer in the manufacturing process of the semiconductor device according to an embodiment of the present application;
[0059] Figure 5a This is a schematic diagram of bonding a substrate to a semiconductor layer during the manufacturing process of a semiconductor device according to an embodiment of the present application;
[0060] Figure 5b This is a schematic diagram of a semiconductor layer after being peeled off during the manufacturing process of the semiconductor device according to an embodiment of the present application;
[0061] Figure 6 This is a schematic diagram of a semiconductor device after a second trench and a first insulating film are formed in a manufacturing process of the semiconductor device according to an embodiment of the present application;
[0062] Figure 7 This is a schematic diagram of a semiconductor device after a second insulating film and a third insulating film are formed in a manufacturing process of the semiconductor device according to an embodiment of the present application;
[0063] Figure 8aIt is a cross-sectional view in the second direction after the second isolation layer is formed in the manufacturing process of the semiconductor device according to the embodiment of the present application;
[0064] Figure 8b It is a cross-sectional view in the first direction after a second isolation layer is formed in the manufacturing process of the semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION
[0065] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.
[0066] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.
[0067] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
[0068] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.
[0069] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.
[0070] In this specification, a memory refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The memory has a channel region between a drain electrode (also referred to as a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (also referred to as a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.
[0071] In this specification, the first electrode mentioned below may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In practical applications, which of the first electrode and the second electrode is the source electrode and which is the drain electrode is related to the direction of current flow. Generally, the current flows from the source electrode to the drain electrode. In the case of using a memory with opposite polarity or the case where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged.
[0072] In this specification, "electrical connection" includes the situation where the components are connected together through an element having some electrical function, such as a physical connection relationship or a signal connection relationship. There is no particular limitation on the "element having some electrical function" as long as it can carry out electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements, resistors, inductors, capacitors, and other elements with various functions.
[0073] In this specification, the following parallel or perpendicular means approximately parallel and approximately perpendicular within the error range. "Parallel" means the state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes the state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means the state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes the state where the angle is greater than 85° and less than 95°.
[0074] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".
[0075] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.
[0076] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device comprising:
[0077] providing a semiconductor layer;
[0078] Performing a patterning process on the semiconductor layer to form a plurality of first grooves and walls that are spaced apart and extend along a first direction;
[0079] forming a peeling layer at the bottom of the first groove;
[0080] forming a conductive structural layer on the top of the wall;
[0081] Bonding the side of the semiconductor layer where the conductive structure layer is formed to the substrate by flip chip bonding;
[0082] The peeling layer is broken to peel off the bottom of the first groove from the wall;
[0083] The conductive structure layer is formed into a bit line, and the plurality of walls are respectively formed into semiconductor columns, wherein the semiconductor columns include a first electrode, a channel and a second electrode.
[0084] The solution of this embodiment is described below by means of some examples.
[0085] Figure 1 FIG. 1 is a schematic diagram of a planar structure of a semiconductor device according to an embodiment of the present application. In an exemplary embodiment, Figure 1 As shown, the semiconductor device of the embodiment of the present application includes a substrate and a plurality of mutually spaced memory cells 11 disposed on the substrate. The memory cells 11 include a word line 12 disposed on the substrate and extending along a first direction D1, a bit line 13 extending along a second direction D2, a semiconductor column 14 extending along a direction perpendicular to the substrate, and a channel surrounding the semiconductor column 14 and mutually insulated gate electrodes.
[0086] In an exemplary embodiment, if Figure 1 As shown, a plurality of mutually spaced memory cells 11 are spaced apart and arranged along a first direction D1 to form a memory cell row. A word line 12 is electrically connected to gate electrodes of all memory cells 11 in a memory cell row. All memory cells 11 in a memory cell row can share one word line 12 .
[0087] In an exemplary embodiment, if Figure 1As shown, a plurality of mutually spaced memory cells 11 are spaced apart and arranged along the second direction D2 to form a memory cell column, a bit line 13 is electrically connected to the semiconductor pillars 14 of all memory cells 11 in a memory cell column, and all memory cells 11 in a memory cell column can share one bit line 13.
[0088] In an exemplary embodiment, the bit line 13 may be made of a metal material, such as tungsten.
[0089] In an exemplary embodiment, the orthographic projection of the semiconductor pillar 14 on the substrate may adopt various shapes, for example, regular or irregular shapes such as circle, ellipse, rectangle, diamond, triangle, pentagon, hexagon, etc.
[0090] The semiconductor device of the embodiment of the present application may be a vertical channel transistor. The semiconductor device of the embodiment of the present application may be used as a read transistor and / or a write transistor in a dynamic random access memory (DRAM), which can reduce the area of the memory and improve the storage density.
[0091] In some embodiments, the semiconductor device of the embodiment of the present application may also be other storage structures in which the bit lines are buried in the channel close to the substrate side, and the embodiment of the present application will not be described in detail here.
[0092] Figure 2 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 1 , Figure 3 The cross-sectional structure of the semiconductor device of the embodiment of the present application is shown in FIG. Figure 2 .in, Figure 2 Can be Figure 1 Schematic diagram of the cross section along the a-a' direction; Figure 3 Can be Figure 1 In the exemplary embodiment, as shown in FIG. Figure 2 and Figure 3As shown, in a direction perpendicular to the substrate, the memory cell 11 includes a second bonding layer 92 disposed on the substrate 101, a second metal layer 91 disposed on the side of the second bonding layer 92 away from the substrate 101, a first barrier layer 93 disposed on the side of the second metal layer 91 away from the substrate 101, a bit line 13 disposed on the side of the first barrier layer 93 away from the substrate 101, a second barrier layer 94 disposed on the side of the bit line 13 away from the substrate 101, a first metal layer 40 disposed on the side of the second barrier layer 94 away from the substrate 101, a second transition layer 42 disposed on the side of the first metal layer 40 away from the substrate 101, a first transition layer 41 disposed on the side of the second transition layer 42 away from the substrate 101, and a semiconductor pillar 50 disposed on the side of the first transition layer 41 away from the substrate 101. The surface of the substrate 101 is a flat surface. The second metal layer 91 can be used as a first bonding layer for bonding with the second bonding layer 92.
[0093] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the semiconductor column 50 includes a first electrode 51, a second electrode 53, and a channel 52 located between the first electrode 51 and the second electrode 53. The first electrode 51 and the second electrode 53 are both electrically connected to the channel 52. The first electrode 51 is located on a side of the channel 52 close to the substrate 101, and the first electrode 51 is electrically connected to the bit line 13; the second electrode 53 is located on a side of the channel 52 away from the substrate 101.
[0094] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the memory cell 11 further includes a gate electrode 30, which is disposed around the outside of the channel 52. The gate electrode 30 extends on the sidewall of the channel 52 to form a ring-shaped conductive layer extending in a direction perpendicular to the substrate 101. A gate insulating layer 31 is disposed between the gate electrode 30 and the channel 52, and the gate insulating layer 31 separates the gate electrode 30 from the channel 52, thereby insulating the gate electrode 30 from the channel 52.
[0095] In an exemplary embodiment, the gate insulating layer 31 may be made of a material with a wide bandgap and a high dielectric constant, or a material suitable for making extremely small size devices, such as hafnium dioxide. The gate insulating layer 31 may be made of a single layer of dielectric material, such as oxide or nitride; or, the gate insulating layer 31 may be made of a multilayer dielectric material, such as a combination of oxide and nitride.
[0096] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the gate electrode 30 is insulated from the first electrode 51 , the second electrode 53 and the bit line 13 .
[0097] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the gate electrode 30 is arranged opposite to the channel 52, and the gate electrode 30 does not cover the first electrode 51 and the second electrode 53. The gate electrode 30 can surround part or all of the channel 52 to form a ring gate structure. For example, the gate electrode 30 can be ring-shaped, and the gate electrode 30 surrounds the channel 52.
[0098] In an exemplary embodiment, the gate electrode 30 may be made of metal, for example, conductive metals such as tin and tungsten.
[0099] The ring-gate structure of the transistor in the embodiment of the present application has strong gate control, can increase the area of the channel region, and can improve the retention time. In addition, the ring-gate structure can reduce the area of the semiconductor device.
[0100] The substrate 101 and the bit line 13 of the semiconductor device in the embodiment of the present application can be bound by a first bonding layer and a second bonding layer 92 using a flip chip bonding method, so that the bit line is transferred between the bottom of the semiconductor column and the surface of the substrate, so that the bit line has a uniform and tight internal structure, low resistance, avoids the occurrence of voids in the bit line, and improves the conductivity of the bit line.
[0101] In an exemplary embodiment, the bit line 13 is linear, and the bit line 13 includes a bottom surface located on a side close to the substrate 101, and the bottom surface is flat in the extension direction of the bit line 13. The bit line of the semiconductor device of the embodiment of the present application is first formed by depositing a conductive film, then by an etching process, and finally, by a flip chip bonding method, the bit line is transferred between the bottom of the semiconductor column and the surface of the substrate, so that the surface (for example, the bottom surface) of the bit line 13 is flat, and the inside is uniform and tight, thereby ensuring the electrical performance of the bit line 13.
[0102] In an exemplary embodiment, the second metal layer 91 may serve as a first bonding layer.
[0103] In some embodiments, the first bonding layer and the second metal layer are different film layers, and the first bonding layer is disposed on a side of the second metal layer away from the substrate.
[0104] In an exemplary embodiment, the material of the first bonding layer is titanium, and the material of the second bonding layer is silicon dioxide; or, the material of the first bonding layer and the material of the second bonding layer are both titanium; or, the material of the first bonding layer is titanium, and the material of the second bonding layer is silicon; or, the material of the first bonding layer is silicon dioxide, and the material of the second bonding layer is silicon dioxide; or, the material of the first bonding layer is silicon, and the material of the second bonding layer is silicon dioxide.
[0105] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the first transition layer 41 and the second transition layer 42 are both located between the first electrode 51 and the bit line 13. The first transition layer 41 and the second transition layer 42 both include silicon elements, and are used to electrically connect the first electrode 51 to the bit line 13. For example, the first transition layer 41 can be made of metal silicide, such as cobalt silicide. The second transition layer 42 can be made of doped polysilicon. For example, the doped polysilicon is boron-doped polysilicon, and the boron doping concentration in the boron-doped polysilicon is 10 18 cm -3 .
[0106] The semiconductor device of the embodiment of the present application reduces the contact resistance between the bit line 13 and the first electrode 51 of the semiconductor column 50 through the first transition layer and the second transition layer, so that the bit line 13 forms an ohmic contact with the first electrode 51, which greatly improves the electrical performance of the bit line 13.
[0107] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the second metal layer 91 is located on the side of the first barrier layer 93 close to the substrate 101, and the first metal layer 40 is arranged on the side of the second barrier layer 94 close to the substrate 101. Both the first metal layer 40 and the second metal layer 91 can be made of metal titanium.
[0108] The first metal layer 40 and the second metal layer 91 can play an adhesion role, so that the first metal layer can better bond the second barrier layer to other film layers, and the second metal layer can better bond the first barrier layer to other film layers. In addition, the second metal layer can be used as a first bonding layer to bond with the second bonding layer on the substrate. The first metal layer 40 can also form a metal silicide with the silicon element in the second transition layer 42, and the metal silicide can reduce the contact resistance between the bit line 13 and the first electrode 51 of the semiconductor column 50, so that the bit line 13 forms an ohmic contact with the first electrode 51, which greatly improves the electrical performance of the bit line 13.
[0109] In an exemplary embodiment, the first barrier layer 93 and the second barrier layer 94 are used to encapsulate and protect the bit line 13 and have the function of isolating oxygen. The material of the first barrier layer 93 and the second barrier layer 94 can both be titanium nitride.
[0110] In an exemplary embodiment, if Figure 2 and Figure 3As shown, the memory cell 11 further includes a first isolation layer 81, which is disposed on the side of the semiconductor column 50 away from the substrate and in contact with the second electrode 53 of the semiconductor column 50. The orthographic projection of the first isolation layer 81 on the substrate covers the orthographic projection of the semiconductor column 50 on the substrate, and the first isolation layer 81 is used to isolate the surface of the second electrode 53 of the semiconductor column 50 to avoid affecting the semiconductor column 50 during the process of forming the gate electrode 30.
[0111] In an exemplary embodiment, if Figure 2 As shown, in the second direction D2, a first trench 61 is provided between the semiconductor pillars 50 of adjacent memory cells, the first trench 61 extends along the first direction D1, the first trench 61 extends to the first transition layer 41, and the bottom of the first trench 61 is the surface of the first transition layer 41 away from the substrate. The gate electrode 30 and the gate insulating layer 31 are provided in the first trench 61. The first direction D1 intersects with the second direction D2 and are both parallel to the substrate. For example, the first direction D1 is perpendicular to the second direction D2.
[0112] In an exemplary embodiment, if Figure 2 As shown, the semiconductor device further includes a first insulating layer 21 and a second insulating layer 22, both of which are disposed in the first trench 61. In the second direction D2, the first insulating layer 21 is located between the gate electrodes 30 and the second electrodes 53 of adjacent memory cells 11, isolating the gate electrodes 30 and the second electrodes 53 of adjacent memory cells 11, and insulating the gate electrodes 30 and the second electrodes 53 of adjacent memory cells 11 from each other. In the direction perpendicular to the substrate, the second insulating layer 22 is located between the gate electrode 30 of a memory cell 11 and the bit line 13 of the memory cell 11, isolating the gate electrode 30 from the bit line 13, and insulating the gate electrode 30 from the bit line 13. The material of the first insulating layer 21 can be an inorganic material, and for example, the material of the first insulating layer 21 can be silicon dioxide. The second insulating layer 22 can be made of the same material as the gate insulating layer 31.
[0113] In an exemplary embodiment, if Figure 2 As shown, the semiconductor device further includes a third insulating layer 23 . The third insulating layer 23 is disposed on a side of the first insulating layer 21 away from the substrate. The third insulating layer 23 is located between the first isolation layers 81 on adjacent memory cells 11 .
[0114] In an exemplary embodiment, if Figure 3As shown, in the first direction D1, a second trench 62 is provided between the semiconductor pillars 50 of adjacent memory cells, and the second trench 62 extends along the second direction D2. In a direction perpendicular to the substrate 101, the second trench 62 extends to the second bonding layer 92, and the bottom of the second trench 62 is the surface of the second bonding layer 92. The gate electrode 30 and the gate insulating layer 31 are provided in the second trench 62.
[0115] In an exemplary embodiment, if Figure 3 As shown, the second insulating layer 22 is located in the second trench 62. In the first direction D1, the second insulating layer 22 is located between the bit line 13 and the first electrode 51 of the adjacent memory cell 11, isolating the bit line 13 and the first electrode 51 of the adjacent memory cell 11, so that the bit line 13 and the first electrode 51 of the adjacent memory cell 11 are insulated from each other.
[0116] In an exemplary embodiment, if Figure 3 As shown, the portion of the third insulating layer 23 close to the substrate is located in the second trench 62 and is disposed on the side of the gate electrode 30 away from the substrate. The portion of the third insulating layer 23 away from the substrate is located above the second trench 62 and is disposed between the first isolation layers 81 on adjacent memory cells 11.
[0117] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the semiconductor device further includes a second isolation layer 82, which is located in the first trench 61 and the second trench 62. The second isolation layer 82 is disposed around the sidewall of the second electrode 53 of the semiconductor column 50, and the second isolation layer 82 is used to isolate the sidewall of the second electrode 53 of the semiconductor column 50 to avoid affecting the semiconductor column 50 during the formation of the gate electrode 30. The material of the second isolation layer 82 can be an inorganic material, and for example, the material of the second isolation layer 82 can be silicon dioxide.
[0118] In an exemplary embodiment, if Figure 2 and Figure 3 As shown, the semiconductor device further includes a covering layer 90 , which is located on the semiconductor pillar 50 and the third insulating layer 23 on a side away from the substrate. The covering layer 90 can cover one or more semiconductor pillars 50 to protect the semiconductor pillars 50 .
[0119] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device may be any of the semiconductor devices described above, and the method for manufacturing the semiconductor device includes:
[0120] providing a semiconductor layer;
[0121] Performing a patterning process on the semiconductor layer to form a plurality of first grooves and walls that are spaced apart and extend along a first direction;
[0122] forming a peeling layer at the bottom of the first groove;
[0123] forming a conductive structural layer on the top of the wall;
[0124] Bonding the side of the semiconductor layer where the conductive structure layer is formed to the substrate by flip chip bonding;
[0125] The peeling layer is broken to peel off the bottom of the first groove from the wall;
[0126] The conductive structure layer is formed into a bit line, and the plurality of walls are respectively formed into semiconductor columns, wherein the semiconductor columns include a first electrode, a channel and a second electrode.
[0127] The technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".
[0128] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:
[0129] S101) provides a semiconductor layer 71, wherein the semiconductor layer 71 can be a P-type silicon wafer. Subsequently, by ion implantation, P-type doping (doping B) and N-type doping (doping P) are performed at different depths of the semiconductor layer 71; subsequently, heat treatment is performed to perform lattice repair, and the P-type doping region in the semiconductor layer 71 forms a first doping layer 72, and the N-type doping region forms a second doping layer 73, and the second doping layer 73 is connected to the first doping layer 72, such as Figure 4a The first doping layer 72 is used to form a channel later, and the second doping layer 73 is used to form a source electrode later.
[0130] S102) forms a wall. The forming of the wall includes: performing a patterning process on the first doping layer 72, the second doping layer 73 and the semiconductor layer 71, so that the first doping layer 72, the second doping layer 73 and a portion of the semiconductor layer 71 form a first groove 121 extending along the first direction D1 and a wall 120, the first groove 121 is located between adjacent walls 120, the first doping layer of the wall 120 can form a channel 52, the second doping layer of the wall 120 can form a first electrode 51, and the bottom of the first groove 121 exposes the surface of the semiconductor layer 71, such as Figure 4b shown.
[0131] S103) using an atomic deposition process or a thermal oxidation process to form a barrier film 122 on the wall 120 and the first groove 121, the barrier film 122 covers the top surface and the side surface of the wall 120 and the bottom of the first groove 121; then, the barrier film 122 on the bottom of the first groove 121 is etched away to expose the surface of the bottom of the first groove, such as Figure 4c The material of the blocking film 122 can be silicon dioxide.
[0132] S104) A punch & pullback process is used to remove part of the material at the connection between the wall 120 and the semiconductor layer 71 from the bottom of the first groove 121, that is, the connection between the wall 120 and the semiconductor layer 71 is etched along a direction parallel to the plane where the bottom of the first groove of the semiconductor layer is located, so that the width or diameter of the connection in the direction parallel to the plane where the semiconductor layer 71 is located is reduced, so that a support column 123 is formed at the connection between the wall and the semiconductor layer, and the middle part of the side wall of the support column 123 is an arc-shaped structure recessed toward the inner side of the support column, and the arc-shaped structure is a structure recessed toward the inner side of the support column 123 along a direction parallel to the plane where the bottom of the first groove is located, and the orthographic projection of the middle part of the side wall of the support column 123 on the bottom of the first groove of the semiconductor layer is located in the orthographic projection of the corresponding wall on the bottom of the first groove of the semiconductor layer, so that a second groove 124 is formed between adjacent support columns 123, as shown in FIG. Figure 4d shown.
[0133] S105) using an electron cyclotron resonance low temperature nitridation process to form a nitride with high stress on the support column 123 through the second groove 124, such as Figure 4e As shown. For example, the high stress nitride may be Si3N4.
[0134] Further, an atomic deposition process (ALD) is used to deposit a high stress film on the sidewall of the support column, so that the high stress film and the support column 123 form a peeling layer 125 having one or more holes 126, the peeling layer 125 is arranged on one side of the bottom of the first groove, and the plurality of holes 126 are arranged at intervals along a direction parallel to the plane where the semiconductor layer 71 is located, and the peeling layer 125 material is arranged between adjacent holes 126, wherein the material of the high stress film is the same as the nitride formed by the support column 123, for example, the high stress film can be Si3N4;
[0135] S106) Fill the first groove 121 with an insulating dielectric film 127, fill the first groove 121 with the insulating dielectric film 127, and then grind the insulating dielectric film 127 to expose the top of the wall 120, such as Figure 4f shown.
[0136] S107) forming a cobalt metal film on the top of the wall 120, and performing annealing heat treatment so that the cobalt metal film and the top of the wall 120 form a cobalt silicide film, and then washing with sulfuric acid to remove excess cobalt metal film, and then grinding to expose the cobalt silicide film, so that the cobalt silicide film forms a first transition layer 41; forming a second transition layer 42 on the first transition layer 41; the first transition layer 41 and the second transition layer 42 both include silicon elements, the first transition layer 41 can be made of metal silicide, such as cobalt silicide, and the second transition layer 42 can be made of doped polysilicon;
[0137] Subsequently, the first metal layer 40, the second barrier layer 94, the conductive layer 77, the first barrier layer 93 and the second metal layer 91 are sequentially formed on the second transition layer 42. Figure 4g As shown. The first metal layer 40, the second barrier layer 94, the conductive layer 77, the first barrier layer 93 and the second metal layer 91 form the conductive structure layer. The materials of the first metal layer 40 and the second metal layer 91 can both be titanium metal, and the material of the conductive layer 77 can be tungsten metal. The materials of the first barrier layer 93 and the second barrier layer 94 can be titanium nitride. The second metal layer 91 can serve as a first bonding layer.
[0138] S108) providing a substrate 101, forming a second bonding layer 92 on the substrate 101; then, bonding the second metal layer 91 to the second bonding layer 92 on the substrate 101 by flip chip bonding, such as Figure 5a The material of the substrate 101 may be a silicon wafer; the material of the second bonding layer 92 may be silicon dioxide.
[0139] In some embodiments, step S108) may be performed simultaneously with steps S101) to S107), or may be performed before steps S101) to S107), or may be performed after steps S101) to S107), and the embodiments of the present application will not be described in detail herein.
[0140] S109) performing a thinning process on the semiconductor layer. The thinning process on the semiconductor layer includes: utilizing the stress concentration and easy fracture characteristics of the peeling layer 125 and the thermal expansion principle of the air cavity, by heating the temperature through heat treatment or ultraviolet light irradiation, the peeling layer 125 is broken, and the bottom of the first groove is peeled off from the plurality of walls 120; then, the peeling layer 125 on the wall 120 is smoothed to expose the top surface of the wall 120;
[0141] Subsequently, the portion of the wall 120 away from the substrate 101 is doped to form the second electrode 53, and the second electrode 53, the channel 52 and the first electrode 51 form the semiconductor column 50; and then the lattice is repaired by heat treatment, such as Figure 5b shown.
[0142] S110) In the first direction D1, a second trench 62 is formed between adjacent semiconductor pillars 50, the second trench 62 extends along the second direction D2, the second trench 62 extends to the second bonding layer 92, and the bottom of the second trench 62 is the surface of the second bonding layer 92 and the side away from the substrate; the conductive layer 77 forms a bit line 13;
[0143] Then, an atomic deposition process (ALD) is used to fill the second trench 62 with the first insulating film 131, and the first insulating film 131 fills the second trench 62. Then, the first insulating film 131 is polished by chemical mechanical polishing (CMP) to expose the top surface of the semiconductor pillar 50. Figure 6 shown.
[0144] S112) removing the insulating dielectric film between adjacent semiconductor pillars 50, and forming a first trench 61 between adjacent semiconductor pillars 50 in the second direction D2, wherein the first trench 61 extends along the first direction D1, and the first trench 61 extends to the second transition layer 42, and the bottom of the first trench 61 is the surface of the second transition layer 42 away from the substrate;
[0145] Subsequently, an atomic deposition process (ALD) is used to form a second insulating film 132 on the sidewall and bottom of the first trench 61. Subsequently, the first trench 61 is filled with an isolation material so that the insulating material forms a third insulating film 133 located between the second insulating films 132 in the first trench 61. The second insulating film 132 and the third insulating film 133 are polished flat by chemical mechanical polishing (CMP) to expose the top surface of the semiconductor pillar 50. Figure 7 shown.
[0146] S113) etching away a portion of the second insulating film 132 in the first trench 61 and the first insulating film 131 in the second trench 62 to expose the side wall of the second electrode 53 of the semiconductor pillar 50; then, forming a second isolation layer 82 on the exposed side wall of the second electrode 53, the second isolation layer 82 is arranged around the side wall of the second electrode 53, as shown in FIG. Figure 8a and 8b shown.
[0147] S114) etching and removing a portion of the second insulating film 132 in the first trench 61 and the first insulating film 131 in the second trench 62 to expose the sidewall of the trench 52 of the semiconductor pillar 50; making the retained first insulating film and the second insulating film form the second insulating layer 22; making the third insulating film form the first insulating layer 21;
[0148] Subsequently, a gate insulating layer 31 and a gate electrode 30 are sequentially formed on the sidewalls of the exposed channel 52, and a word line connected to the gate electrode 30 is formed; the gate electrode 30 is arranged around the sidewalls of the channel 52 through the gate insulating layer 31;
[0149] Subsequently, a third insulating layer 23 is formed on the side of the first insulating layer 21 away from the substrate and on the side of the gate electrode 30 away from the substrate; subsequently, a capping layer 90 is formed on the side of the semiconductor pillar 50 away from the substrate and on the side of the third insulating layer 23 away from the substrate. Figure 2 and Figure 3 shown.
[0150] The manufacturing method of the semiconductor device of the embodiment of the application forms a support column at the connection between the wall and the semiconductor layer, and forms a nitride with high stress on the support column, so that the peeling layer is easily peeled off.
[0151] The manufacturing method of the semiconductor device in the embodiment of the present application deposits a high-stress film so that the high-stress film and the support pillar form a peeling layer with one or more holes, so that the peeling layer can be easily peeled off.
[0152] The method for manufacturing a semiconductor device in an embodiment of the present application forms the first barrier layer and the second barrier layer to encapsulate and protect the conductive layer, thereby isolating oxygen.
[0153] The manufacturing method of the semiconductor device in the embodiment of the present application forms the first metal layer and the second metal layer, so that the first metal layer can better bond the second barrier layer and other film layers together, and the second metal layer can better bond the first barrier layer and other film layers together, and the second metal layer can serve as a first bonding layer to bond with the second bonding layer on the substrate.
[0154] The manufacturing method of the semiconductor device in the embodiment of the present application adopts a flip-chip bonding method to transfer the bit line to between the bottom of the semiconductor column and the surface of the substrate, so that the bit line has a uniform and tight internal structure and low resistance, avoids the occurrence of voids in the bit line, and improves the conductivity of the bit line.
[0155] The manufacturing method of the semiconductor device in the embodiment of the present application adopts a flip-chip bonding method to facilitate ion implantation into the wall to form the first electrode, the channel and the second electrode of the semiconductor column, thereby solving the problem of difficult ion implantation in the semiconductor device structure manufacturing process.
[0156] The manufacturing method of the semiconductor device of the embodiment of the present application adopts at least one transition layer to electrically connect the bit line to the semiconductor column through the transition layer, thereby reducing the contact resistance between the bit line and the semiconductor column, forming an ohmic contact between the bit line and the semiconductor column, and greatly improving the electrical performance of the bit line.
[0157] The manufacturing method of the semiconductor device of the present application has good process compatibility, simple process realization, easy implementation, high production efficiency, low production cost and high yield rate.
[0158] The embodiment of the present application also provides an electronic device, comprising any of the semiconductor devices described above. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device.
[0159] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.
[0160] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor layer; Performing a patterning process on the semiconductor layer to form a plurality of first grooves and walls that are spaced apart and extend along a first direction; forming a peeling layer at the bottom of the first groove; forming a conductive structural layer on the top of the wall; Bonding the side of the semiconductor layer where the conductive structure layer is formed to the substrate by flip chip bonding; The peeling layer is broken to peel off the bottom of the first groove from the wall; The conductive structure layer is formed into a bit line, and the plurality of walls are respectively formed into semiconductor columns, wherein the semiconductor columns include a first electrode, a channel and a second electrode.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: Forming a peeling layer at the bottom of the first groove includes: forming a barrier film on the plurality of walls and the first groove; Etching and removing the blocking film on the bottom of the first groove; Using an etching process, etching the bottom of the first groove to form a support column at the connection between the wall and the semiconductor layer; The electron cyclotron resonance low-temperature nitridation process is adopted to form a nitride with high stress on the support column.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: After forming the support column into a nitride with high stress, the method further comprises: An atomic layer deposition process is used to deposit a high stress film on the sidewall of the support column to form a peeling layer having one or more holes at the bottom of the first groove.
4. The method for manufacturing a semiconductor device according to claim 3, wherein: The material of the high stress film is the same as the nitride formed by the supporting pillar.
5. The method for manufacturing a semiconductor device according to claim 3, wherein: The middle part of the side wall of the support column is an arc-shaped structure recessed toward the inner side of the support column; the plurality of holes in the stripping layer are arranged at intervals along a direction parallel to the plane where the semiconductor layer is located, and the material of the stripping layer is arranged between adjacent holes.
6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: The peeling layer is broken by a heat treatment process or ultraviolet light irradiation.
7. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: A conductive structure layer is formed on the top of the wall, comprising: forming a first metal layer, a second barrier layer, a conductive layer, a first barrier layer and a second metal layer in sequence on the top of the wall; The first metal layer, the second barrier layer, the conductive layer, the first barrier layer and the second metal layer form the conductive structure layer.
8. The method for manufacturing a semiconductor device according to any one of claims 1 to 5, characterized in that: Before forming the conductive structure layer on the top of the wall, the method further comprises: At least one transition layer is formed on the top of the wall; wherein the transition layer includes silicon element.
9. The method for manufacturing a semiconductor device according to claim 7, wherein: Bonding the side of the semiconductor layer on which the conductive structure layer is formed to the substrate by flip chip bonding includes: forming a first bonding layer on a side of the second metal layer away from the wall; or using the second metal layer as the first bonding layer; forming a second bonding layer on the substrate; The first bonding layer is bonded to the second bonding layer by a flip chip bonding method.
10. A semiconductor device, characterized in that: It includes a substrate, a bit line arranged on one side of the substrate surface, and a semiconductor column arranged on a side of the bit line away from the substrate, the substrate surface is a flat surface, the semiconductor column extends in a direction perpendicular to the substrate, the semiconductor column includes a first electrode, a channel and a second electrode, and the first electrode is electrically connected to the bit line.
11. The semiconductor device according to claim 10, characterized in that It also includes a first metal layer, a second barrier layer, a first barrier layer and a second metal layer, the second barrier layer is arranged on the side of the bit line close to the substrate, the first metal layer is arranged on the side of the second barrier layer close to the substrate, the first barrier layer is arranged on the side of the bit line away from the substrate, and the second metal layer is arranged on the side of the first barrier layer away from the substrate.
12. The semiconductor device according to claim 11, characterized in that It also includes a first bonding layer, which is arranged on a side of the second metal layer away from the substrate, or the second metal layer serves as the first bonding layer.
13. The semiconductor device according to claim 10, characterized in that It also includes at least one transition layer, which is arranged between the bit line and the semiconductor column. The bit line is electrically connected to the semiconductor column through the transition layer, and the transition layer includes silicon.
14. The semiconductor device according to claim 10, characterized in that The bit line is linear and includes a bottom surface located close to one side of the substrate, and the bottom surface is flat in the extending direction of the bit line.
15. An electronic device, characterized in that: A semiconductor device comprising any one of claims 10 to 14.