Semiconductor structure and preparation method thereof

Abstract

The disclosed embodiments relate to a semiconductor structure and a method for preparing the same. The method includes: providing a first substrate, and forming a first storage structure on the first surface of the first substrate; providing a second substrate, and forming a first control structure on the first surface of the second substrate; bonding the first substrate to the first surface side of the second substrate, after bonding, the first control structure is electrically connected to the first storage structure; forming a second control structure on the second surface of the second substrate, the second surface of the second substrate being the opposite surface of the first surface of the second substrate; providing a third substrate, and forming a second storage structure on the first surface of the third substrate; bonding the third substrate to the second surface side of the second substrate, after bonding, the second storage structure and the second control structure are electrically connected. This method realizes a method in which a substrate with control structures formed on both surfaces of an opposite arrangement simultaneously controls the substrates forming storage structures on both surfaces, thereby improving the storage density of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] As the 3D NAND channel (3D NAND flash memory channel) gradually increases, the channel current gradually decreases. Typically, in order to increase the storage density of memory devices, a bonding process (chip bonding process) is used to achieve bonding between a wafer forming a CMOS and a wafer forming an array (storage array). How to further improve the storage density of memory devices has become an urgent problem that needs to be solved. Summary of the Invention

[0003] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can further improve the storage density of a memory device.

[0004] The present disclosure provides a method for preparing a semiconductor structure, comprising:

[0005] Providing a first substrate and forming a first storage structure on a first surface of the first substrate;

[0006] Providing a second substrate and forming a first control structure on a first surface of the second substrate;

[0007] Bonding the first substrate to the first surface side of the second substrate, wherein after bonding, the first control structure is electrically connected to the first storage structure;

[0008] forming a second control structure on a second surface of the second substrate, wherein the second surface of the second substrate is opposite to the first surface of the second substrate;

[0009] Providing a third substrate and forming a second storage structure on a first surface of the third substrate;

[0010] The third substrate is bonded to the second surface side of the second substrate. After bonding, the second storage structure and the second control structure are electrically connected.

[0011] In one embodiment, bonding the first substrate to the first surface side of the second substrate includes:

[0012] The first substrate is bonded to the first surface side of the second substrate through a hybrid bonding process.

[0013] In one embodiment, after forming the second control structure on the second surface of the second substrate and before bonding the third substrate to the second surface of the second substrate, the method further includes:

[0014] forming a first contact hole penetrating the second substrate;

[0015] A first contact structure is formed in the first contact hole, and the first contact structure is used to realize the interconnection between the first control structure and the second control structure.

[0016] In one embodiment, after forming the second control structure on the second surface of the second substrate and before bonding the third substrate to the second surface of the second substrate, the method further includes:

[0017] forming a second contact hole on the second surface of the second substrate;

[0018] A second contact structure is formed in the second contact hole, and the second contact structure is used to lead the second control structure to the second surface of the second substrate.

[0019] In one embodiment, the second contact structure includes a hybrid bonding structure and a through-hole contact structure; after bonding the third substrate to the second surface side of the second substrate, the method includes:

[0020] forming a third contact hole penetrating the third substrate;

[0021] forming a third contact structure in the third contact hole, wherein the third contact structure contacts the through-hole contact structure;

[0022] The hybrid bonding structure is used to achieve hybrid bonding between the second surface of the second substrate and the first surface of the third substrate, and the size of the hybrid bonding structure is smaller than the size of the through-hole contact structure.

[0023] In the above-mentioned method for preparing the semiconductor structure, the first storage structure on the first substrate is controlled by the first control structure located on the first surface of the second substrate, and the second storage structure on the third substrate is controlled by the second control structure located on the second surface of the second substrate, thereby realizing a method in which a substrate having control structures formed on two relatively arranged surfaces simultaneously controls the substrates having storage structures formed on the two surfaces, thereby improving the storage density of the semiconductor structure.

[0024] The present disclosure also provides a semiconductor structure, comprising:

[0025] a first substrate, wherein a first storage structure is formed on a first surface of the first substrate;

[0026] a second substrate, wherein a first control structure is formed on a first surface of the second substrate, a second control structure is formed on a second surface of the second substrate, and the second surface of the second substrate is opposite to the first surface of the second substrate;

[0027] a third substrate, wherein a second storage structure is formed on a first surface of the third substrate;

[0028] The first substrate is bonded to the first surface side of the second substrate, the third substrate is bonded to the second surface side of the second substrate, the first storage structure is electrically connected to the first control structure, and the second storage structure is electrically connected to the second control structure.

[0029] In one embodiment, the first surface of the first substrate is close to the first surface of the second substrate, and the first surface of the third substrate is close to the second surface of the second substrate.

[0030] In one embodiment, the first storage structure and the second storage structure are both 3D NAND storage structures, and the first control structure and the second control structure are both CMOS structures.

[0031] In one embodiment, the semiconductor structure further comprises:

[0032] The first contact structure penetrates the second substrate and is used to interconnect the first control structure and the second control structure.

[0033] In one embodiment, the semiconductor structure further comprises:

[0034] a second contact structure, located on the second surface of the second substrate, and used to lead the second control structure to the second surface of the second substrate;

[0035] a third contact structure extending through the third substrate;

[0036] The second contact structure includes:

[0037] a hybrid bonding structure for achieving hybrid bonding between the second surface of the second substrate and the first surface of the third substrate;

[0038] The through-hole contact structure contacts the third contact structure, and the size of the through-hole contact structure is larger than that of the hybrid bonding structure.

[0039] In the above-mentioned semiconductor structure, a first control structure is formed on the first surface of the second substrate, and a second control structure is formed on the second surface of the second substrate. The first control structure is electrically connected to the first storage structure on the first substrate to control the first storage structure, and the second control structure is electrically connected to the second storage structure on the third substrate to control the second storage structure. This realizes a method in which a substrate with control structures formed on two relatively arranged surfaces simultaneously controls the substrate with storage structures formed on the two surfaces, thereby improving the storage density of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0042] Figure 2 is a schematic cross-sectional view of a semiconductor structure after a first contact structure is formed in one embodiment;

[0043] Figure 3 is a schematic flow chart of a method for preparing a semiconductor structure according to another embodiment;

[0044] Figure 4 is a schematic diagram of a process of a semiconductor structure in another embodiment;

[0045] Figure 5 is a schematic cross-sectional view of a semiconductor structure after a third substrate is bonded to a second substrate in one embodiment;

[0046] Figure 6 FIG. 4 is a flow chart of a semiconductor structure in another embodiment.

[0047] Description of reference numerals:

[0048] 100, first substrate; 102, second substrate; 103, first storage structure; 104, first control structure; 106, second control structure; 108, third substrate; 110, second storage structure; 202, first contact hole; 204, first control terminal; 206, second control terminal; 208, third contact hole; 302, first storage terminal; 303, first lead-out structure; 304, first contact structure; 306, fourth contact structure; 308, fifth contact structure; 309, hybrid bonding structure; 310, second contact structure; 311, through-hole contact structure; 312, second storage terminal; 314, third through-hole; 316, third lead-out hole; 318, third contact structure; 320, third lead-out structure; 322, third through-hole structure. DETAILED DESCRIPTION

[0049] To facilitate understanding of the embodiments of the present disclosure, a more comprehensive description of the embodiments of the present disclosure will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the embodiments of the present disclosure. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the embodiments of the present disclosure.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure relates. The terms used herein in the specification of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0051] In the description of the embodiments of the present disclosure, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present disclosure.

[0052] It will be understood that the terms "first," "second," etc., used in this disclosure may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this disclosure, a first substrate may be referred to as a second substrate, and similarly, a second substrate may be referred to as a first substrate. Both the first substrate and the second substrate are substrates, but they are not the same substrate.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present disclosure, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0054] Figure 1 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in one embodiment. Figure 1 As shown, in this embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0055] S102 , providing a first substrate, and forming a first storage structure on a first surface of the first substrate.

[0056] A first substrate is provided, and a plurality of first storage structures are formed on a first surface of the first substrate. The data stored in each first storage structure may be the same or different. The first substrate may be formed of materials including, but not limited to, undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the first substrate is formed of single crystal silicon.

[0057] S104 , providing a second substrate, and forming a first control structure on a first surface of the second substrate.

[0058] A second substrate is provided, and a plurality of first control structures are formed on a first surface of the second substrate, wherein each first control structure can be used to send the same or different control signals, and can also be used to receive the same or different storage signals. The constituent materials of the second substrate include, but are not limited to, undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the second substrate is single crystal silicon. As an example, the constituent material of the second substrate is the same as the constituent material of the first substrate, or the constituent material of the second substrate is different from the constituent material of the first substrate.

[0059] S106 , bonding the first substrate to the first surface side of the second substrate. After bonding, the first control structure is electrically connected to the first storage structure.

[0060] A bonding process is used to bond the first substrate to the second substrate to form the first surface side of the first control structure. After bonding, the first control structure and the first storage structure are electrically connected. A first control signal can be sent to the first storage structure through the first control structure. The first control signal indicates the storage data that needs to be stored in the first storage structure, or the first control signal indicates a signal for controlling the first storage structure to be turned on or off. The first storage signal sent by the first storage structure can also be received through the first control structure. The first storage signal indicates the readable data stored in the first storage structure.

[0061] It can be understood that any one of the first control structures can be electrically connected to more than or equal to one first storage structure to simultaneously send the same control signal to each of the first storage structures electrically connected to it, or receive the storage signal sent by any of the first storage structures electrically connected to it; similarly, any one of the first storage structures can be electrically connected to more than or equal to one first control structure to simultaneously receive the control signal sent by each of the first control structures, or send the same storage signal to each of the first control structures electrically connected to it.

[0062] S108 , forming a second control structure on a second surface of the second substrate, where the second surface of the second substrate is opposite to the first surface of the second substrate.

[0063] A plurality of second control structures are formed on the second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate. Each second control structure can be used to transmit the same or different control signals, and can also be used to receive the same or different storage signals. Optionally, the performance of the second control structure can be the same as that of the first control structure, or can be different from that of the first control structure.

[0064] S110 , providing a third substrate, and forming a second storage structure on a first surface of the third substrate.

[0065] A third substrate is provided, and a plurality of second storage structures are formed on a first surface of the third substrate, wherein the data stored in each second storage structure may be the same or different. The constituent material of the third substrate includes, but is not limited to, undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the third substrate is single crystal silicon. Optionally, the constituent material of the third substrate is the same as the constituent material of the second substrate and the constituent material of the first substrate, or the constituent material of the third substrate is different from the constituent material of the second substrate and the constituent material of the first substrate.

[0066] S112 , bonding the third substrate to the second surface side of the second substrate. After bonding, the second storage structure and the second control structure are electrically connected.

[0067] A bonding process is used to bond the third substrate to the second substrate to form the second surface side of the second control structure. After bonding, the second control structure and the second storage structure are electrically connected. A second control signal can be sent to the second storage structure through the second control structure. The second control signal indicates the storage data that needs to be stored in the second storage structure, or the second control signal indicates a signal for controlling the second storage structure to be turned on or off. The second storage signal sent by the second storage structure can also be received through the second control structure. The second storage signal indicates the readable data stored in the second storage structure.

[0068] In the above-mentioned method for preparing the semiconductor structure, the first storage structure on the first substrate is controlled by the first control structure located on the first surface of the second substrate, and the second storage structure on the third substrate is controlled by the second control structure located on the second surface of the second substrate, thereby realizing a method in which a substrate having control structures formed on two relatively arranged surfaces simultaneously controls the substrates having storage structures formed on the two surfaces, thereby improving the storage density of the semiconductor structure.

[0069] Exemplarily, the second control structure and the first control structure are independent entities, and the second control structure and the first control structure that send or receive the same type and do not work at the same time can be electrically connected together. The first storage structure and the second storage structure are independent entities, and the first storage structure and the second storage structure can be connected together as a storage structure to increase the amount of data stored in the storage structure.

[0070] Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after forming a first contact structure in one embodiment. Figure 2 As shown, in one embodiment, bonding the first substrate 100 to the first surface side of the second substrate 102 includes: bonding the first substrate 100 to the first surface side of the second substrate 102 through a hybrid bonding process.

[0071] Specifically, after forming the first storage structure 103 on the first surface of the first substrate 100 and before bonding the first substrate 100 to the first surface side of the second substrate 102, the method further includes: forming a first groove on the first storage terminal 302 of the first storage structure 103 to expose the first storage terminal 302 or to lead out a contact structure of the first storage terminal 302, wherein the first storage terminal 302 includes but is not limited to one or more of the first word line terminal, the first bit line terminal, and the first capacitor terminal of the first storage structure 103; after forming the first control structure 104 on the first surface of the second substrate 102 and before bonding the first substrate 100 to the first surface side of the second substrate 102, the method further includes: forming a first control terminal 204 of the first control structure 104 on the first control terminal 204 of the first control structure 104; A second groove is formed to expose the first control terminal 204 or the contact structure leading out of the first control terminal 204, where the first control terminal 204 includes but is not limited to one or more of the first source terminal, the first drain terminal, the first gate terminal, and the first power terminal of the first power supply of the first control transistor; then, according to the corresponding connection relationship, the first storage terminal 302 (or the contact structure leading out of the first storage terminal 302) and the first control terminal 204 (or the contact structure leading out of the first control terminal 204) are bonded to each other through a hybrid bonding process to achieve contact electrical connection between the first storage terminal 302 and the first control terminal 204, and at the same time, the first dielectric layer on the first surface of the first substrate 100 and the second dielectric layer on the first surface of the second substrate 102 are bonded to each other.

[0072] In other embodiments, after the first storage structure 103 is formed on the first surface of the first substrate 100 and before the first substrate 100 is bonded to the first surface side of the second substrate 102, the method further includes: forming a fourth contact hole on the first surface of the first substrate 100, the fourth contact hole exposing the first storage terminal 302 of the first storage structure 103; filling the fourth contact hole to form a fourth contact structure 306, the fourth contact structure 306 being used to lead the first storage terminal 302 of the first storage structure 103 to the first surface of the first substrate 100, wherein the first storage terminal 302 includes but is not limited to one or more of the first word line terminal, the first bit line terminal and the first capacitor terminal of the first storage structure 103.

[0073] Exemplarily, the constituent materials of the fourth contact structure 306 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0074] In other embodiments, after the first control structure 104 is formed on the first surface of the second substrate 102 and before the first substrate 100 is bonded to the first surface side of the second substrate 102, the method further includes: forming a fifth contact hole on the first surface of the second substrate 102, the fifth contact hole exposing the first control end 204 of the first control structure 104 or a contact structure leading out the first control end 204; filling the fifth contact hole to form a fifth contact structure 308, the fifth contact structure 308 being used to lead the first control end 204 of the first control structure 104 out to the first surface of the second substrate 102, wherein the first control structure 104 includes but is not limited to one or more of a first transistor and a first power supply, and the first control end 204 includes but is not limited to one or more of a first source terminal, a first drain terminal, and a first gate terminal of the first control transistor and a first power supply terminal of the first power supply.

[0075] Exemplarily, the material constituting the fifth contact structure 308 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitride includes titanium nitride (TiN); conductive metal oxide includes iridium oxide (IrO2); and metal silicide includes tungsten silicon (WSi). The material constituting the fifth contact structure may be the same as or different from the material constituting the fourth contact structure.

[0076] In one embodiment, after bonding the first substrate 100 to the first surface side of the second substrate 102 and before forming the second control structure 106 on the second surface of the second substrate 102, the method further includes: thinning the second surface of the second substrate 102 using a chemical mechanical polishing process and a tetramethylammonium hydroxide wet etching process (TMAH process) to reduce the thickness of the second substrate 102 to a first predetermined value. Exemplarily, the first predetermined value is greater than or equal to 1.5 μm and less than or equal to 3 μm, such as 1.7 μm, 1.9 μm, 2.0 μm, 2.2 μm, 2.5 μm, 2.7 μm, 2.9 μm, etc.

[0077] Figure 3 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in another embodiment. Figure 2 、 Figure 3 As shown, in one embodiment, before bonding the third substrate to the second surface side of the second substrate 102, the method further includes:

[0078] S202 , forming a first contact hole penetrating the second substrate.

[0079] S204 , forming a first contact structure in the first contact hole, where the first contact structure is used to interconnect the first control structure and the second control structure.

[0080] A first contact hole 202 is formed on the second surface of the second substrate 102 by photolithography and etching processes. The first contact hole 202 penetrates the second substrate 102. The first contact hole 202 exposes the first control end 204 of the first control structure 104 formed on the first surface of the second substrate 102 or a contact structure leading out the first control end 204. The first control structure 104 includes but is not limited to one or more of a first transistor and a first power supply. The first control end 204 includes but is not limited to one or more of a first source end, a first drain end, and a first gate end of the first control transistor and a first power supply end of the first power supply.

[0081] It is understandable that, depending on the process requirements, the first contact hole 202 penetrating the second substrate 102 can be formed after the second control structure 106 is formed on the second surface of the second substrate 102; or the first contact hole 202 penetrating the second substrate 102 can be formed before the second control structure 106 is formed on the second surface of the second substrate 102. The present disclosure does not impose any restrictions on this.

[0082] A first contact structure 304 is filled and formed in the first contact hole 202. Exemplarily, the first contact structure 304 includes a first connection structure and a first lead-out structure 303, wherein the first connection structure realizes the interconnection between the second control structure 106 and the first control structure 104 including the first control terminal 204. The same control signal can be simultaneously sent to the first control structure 104 and the second control structure 106 connected to the first connection structure through the first connection structure. The storage signal received by the first control structure 104 connected to the first connection structure or the storage signal received by the second control structure 106 connected to the first connection structure can be obtained through the first connection structure; the first lead-out structure 303 leads the first control terminal 204 to the second surface of the second substrate 102, so as to facilitate the sending of control signals to the first control terminal 204 or the reception of storage signals sent by the first control terminal 204.

[0083] Exemplarily, the material constituting the first contact structure 304 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitride includes titanium nitride (TiN); conductive metal oxide includes iridium oxide (IrO2); and metal silicide includes tungsten silicon (WSi). The material constituting the first contact structure 304 may be the same as or different from the material constituting the fourth contact structure 306 and the material constituting the fifth contact structure 308.

[0084] Figure 4 is a schematic diagram of a process of a semiconductor structure in another embodiment, Figure 5 FIG. 1 is a cross-sectional view of a semiconductor structure after the third substrate is bonded to the second substrate in one embodiment. Figure 4 、 Figure 5 As shown, in one embodiment, after forming the second control structure 106 on the second surface of the second substrate 102 and before bonding the third substrate 108 to the second surface side of the second substrate 102, the method further includes:

[0085] S302 , forming a second contact hole on the second surface of the second substrate.

[0086] S304 , forming a second contact structure in the second contact hole, where the second contact structure is used to lead the second control structure to the second surface of the second substrate.

[0087] Specifically, a second contact hole is formed on the second surface of the second substrate 102 through photolithography and etching processes, and the second contact hole exposes the second control end 206 of the second control structure 106; a second contact structure 310 is filled in the second contact hole, and the second contact structure 310 is used to lead the second control structure 106 to the second surface of the second substrate 102, that is, the second control end 206 of the second control structure 106 is led to the second surface of the second substrate 102, wherein the second control structure 106 includes but is not limited to one or more of a second transistor and a second power supply, and the second control end 206 includes but is not limited to one or more of a second source end, a second drain end, a second gate end of the second control transistor and a second power supply end of the second power supply.

[0088] Exemplarily, the materials constituting the second contact structure 310 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitride includes titanium nitride (TiN); conductive metal oxide includes iridium oxide (IrO2); and metal silicide includes tungsten silicon (WSi). The material constituting the second contact structure may be the same as or different from the material constituting the fourth contact structure, the material constituting the fifth contact structure, and the material constituting the first contact structure.

[0089] In one embodiment, the second contact structure 310 includes a hybrid bonding structure 309, which is used to achieve hybrid bonding between the second surface of the second substrate 102 and the first surface of the third substrate 108, wherein the top surface of the hybrid bonding structure 309 is lower than the top surface of the second control structure 106 (before the hybrid bonding process, the top surface of the hybrid bonding structure 309 is lower than the top surface of the second control structure 106). After forming the second storage structure 110 on the first surface of the third substrate 108 and before bonding the third substrate 108 to the second surface side of the second substrate 102, the method further includes: forming a third groove on the second storage terminal 312 of the second storage structure 110 to expose the second storage terminal 312 or a contact structure for leading out the second storage terminal 312, where the second storage terminal 312 includes but is not limited to one or more of a second word line terminal, a second bit line terminal, and a second capacitor terminal of the second storage structure 110; bonding the second storage terminal 312 (or the contact structure for leading out the second storage terminal 312) and the hybrid bonding structure 309 to each other through a hybrid bonding process according to the corresponding connection relationship, thereby achieving contact and electrical connection between the second storage terminal 312 (or the contact structure for leading out the second storage terminal 312) and the hybrid bonding structure 309, and simultaneously bonding the third dielectric layer on the second surface of the second substrate 102 and the fourth dielectric layer on the first surface of the third substrate 108 to each other.

[0090] Figure 5 FIG. 1 is a flow chart of a semiconductor structure in another embodiment. Figure 5 、 Figure 6 As shown, in one embodiment, the second contact structure includes a hybrid bonding structure 309 and a through-hole contact structure 311; after bonding the third substrate 108 to the second surface side of the second substrate 102, the method includes:

[0091] S402 , forming a third contact hole penetrating the third substrate.

[0092] S404 , forming a third contact structure in the third contact hole, wherein the third contact structure contacts the through-hole contact structure.

[0093] A third contact hole 208 is formed on the third substrate 102 through photolithography and etching processes. The third contact hole 208 penetrates the third substrate 108 and includes a third through-hole 314 and a third lead-out hole 316. The third through-hole 314 exposes the first contact structure 304 on the second surface of the second substrate 102. The third lead-out hole 316 exposes the second control terminal 206 of the second control structure 106 formed on the second surface of the second substrate 102 or the contact structure (second contact structure 310) for leading the second control terminal 206 out of the second control terminal 206. That is, the third lead-out hole 316 exposes the through-hole contact structure 311 on the second surface of the second substrate 102 for leading the second control terminal 206 or leading the second control terminal 206 out to the second surface of the second substrate 102. Exemplarily, the third contact hole 208 is opened on the second surface of the third substrate 102. Exemplarily, on a horizontal plane (parallel to the plane in which the first storage structure 103 is formed on the first substrate 100), the size of the hybrid bonding structure 309 is smaller than the size of the through-hole contact structure 311. A third contact structure is filled and formed in the third contact hole 208. The third contact structure 318 includes a third lead-out structure 320 in contact with the second control end 206 (through-hole contact structure 311) of the second control structure 106 and a third through-hole structure 322 in contact with the first contact structure 304. The third lead-out structure 320 is used to lead the second control end 206 of the second control structure 106 to the second surface of the third substrate 108. The third through-hole structure 322 includes a fourth through-hole structure in contact with the first connection structure and a fourth lead-out structure in contact with the first lead-out structure 303. The fourth through-hole structure is used to lead the first control structure 104 and the second control structure 106 to the second surface of the third substrate 108. The fourth lead-out structure is used to lead the first control end 204 of the first control structure 104 to the second surface of the third substrate 108.

[0094] Exemplarily, the material constituting the third contact structure 318 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitride includes titanium nitride (TiN); conductive metal oxide includes iridium oxide (IrO2); and metal silicide includes tungsten silicon (WSi). The material constituting the third contact structure 318 may be the same as or different from the material constituting the fourth contact structure 306, the material constituting the fifth contact structure 308, the material constituting the first contact structure 304, and the material constituting the second contact structure 310.

[0095] In one embodiment, after bonding the third substrate 108 to the second surface side of the second substrate 102 and before forming the third contact hole 208 penetrating the third substrate 108, the method further includes: thinning the second surface of the third substrate 108 using a chemical mechanical polishing process and a tetramethylammonium hydroxide wet etching process (TMAH process) to reduce the thickness of the third substrate 108 to a second predetermined value. Exemplarily, the second predetermined value is greater than or equal to 1.5 μm and less than or equal to 3 μm, such as 1.7 μm, 1.9 μm, 2.0 μm, 2.2 μm, 2.5 μm, 2.7 μm, 2.9 μm, etc.

[0096] In one embodiment, the first storage structure 103 and the second storage structure 110 are both 3D NAND storage structures, and the first control structure and the second control structure are both CMOS structures.

[0097] It should be understood that although Figure 1 、 Figure 2 、 Figure 4 and Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 、 Figure 2 、 Figure 4 and Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0098] like Figure 5 As shown, in this embodiment, the present disclosure also provides a semiconductor structure, including: a first substrate 100, a second substrate 102 and a third substrate 108, the first surface of the first substrate 100 is formed with a first storage structure 103; the first surface of the second substrate 102 is formed with a plurality of first control structures 104, the second surface of the second substrate 102 is formed with a plurality of second control structures 106, the second surface of the second substrate 102 is the opposite surface of the first surface of the second substrate 102; the first surface of the third substrate 108 is formed with a plurality of second storage structures 110; wherein, the first substrate 100 is bonded to the first surface side of the second substrate 102, the third substrate 108 is bonded to the second surface side of the second substrate 102, the first storage structure 103 and the first control structure 104 are electrically connected, and the second storage structure 110 and the second control structure 106 are electrically connected.

[0099] Optionally, the data stored in each first storage structure 103 can be the same or different; each first control structure 104 can be used to send the same or different control signals, or to receive the same or different storage signals; each second control structure 106 can be used to send the same or different control signals, or to receive the same or different storage signals. For example, the performance of the second control structure 106 can be the same as that of the first control structure 104, or the performance of the second control structure 106 can be different from that of the first control structure 104, or there can be multiple second control structures 106 with the same performance as the first control structure 104.

[0100] The materials constituting the first substrate 100, the second substrate 102, and the third substrate 108 include, but are not limited to, undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). By way of example, in this embodiment, the materials constituting the first substrate 100, the second substrate 102, and the third substrate 108 are all single crystal silicon. By way of example, the materials constituting the second substrate 102 and the first substrate 100 are the same, or the materials constituting the second substrate 102 and the first substrate 100 are different. The materials constituting the third substrate 108 are the same, or the materials constituting the second substrate 102 and the first substrate 100 are different.

[0101] The first control structure 104 is electrically connected to the first storage structure 103. The first control structure 104 can send a first control signal to the first storage structure 103, where the first control signal indicates storage data to be stored in the first storage structure 103, or a signal to control the first storage structure 103 to be turned on or off. The first control structure 104 can also receive a first storage signal sent by the first storage structure 103, where the first storage signal indicates readable data stored in the first storage structure 103. It is understood that any one first control structure 104 can be electrically connected to one or more first storage structures 103 to simultaneously send the same control signal to each of the first storage structures 103 electrically connected thereto, or receive a storage signal sent by any of the first storage structures 103 electrically connected thereto. Similarly, any one first storage structure 103 can be electrically connected to one or more first control structures 104 to simultaneously receive control signals sent by each of the first control structures 104, or simultaneously send the same storage signal to each of the first control structures 104 electrically connected thereto.

[0102] The second control structure 106 is electrically connected to the second storage structure 110. The second control structure 106 can send a second control signal to the second storage structure 110, where the second control signal indicates storage data that needs to be stored in the second storage structure 110, or the second control signal indicates a signal for controlling the second storage structure 110 to be turned on or off. The second control structure 106 can also receive a second storage signal sent by the second storage structure 110, where the second storage signal indicates readable data stored in the second storage structure 110.

[0103] In the above-mentioned semiconductor structure, a first control structure 104 is formed on the first surface of the second substrate 102, and a second control structure 106 is formed on the second surface of the second substrate 102. The first control structure 104 is electrically connected to the first storage structure 103 on the first substrate 100 to control the first storage structure 103, and the second control structure 106 is electrically connected to the second storage structure 110 on the third substrate 108 to control the second storage structure 110. This realizes a method in which a substrate with control structures formed on two relatively arranged surfaces simultaneously controls the substrate with storage structures formed on the two surfaces, thereby improving the storage density of the semiconductor structure.

[0104] Exemplarily, the second control structure 106 and the first control structure 104 are independent entities, and the second control structure 106 and the first control structure 104 that send or receive the same type of data and do not work at the same time can be electrically connected together. The first storage structure 103 and the second storage structure 110 are independent entities, and the first storage structure 103 and the second storage structure 110 can be connected together as a storage structure to increase the amount of data stored in the storage structure.

[0105] Continue to refer Figure 6 In one embodiment, the first surface of the first substrate 100 is close to the first surface of the second substrate 102 , and the first surface of the third substrate 108 is close to the second surface of the second substrate 102 .

[0106] In one embodiment, the first storage structure 103 and the second storage structure 110 are both 3D NAND storage structures, and the first control structure 104 and the second control structure 106 are both CMOS structures.

[0107] In one embodiment, the semiconductor structure further includes: a first contact structure 304 penetrating the second substrate 102 for interconnecting the first control structure 104 and the second control structure 106 .

[0108] In one embodiment, the first contact structure 304 includes a first connection structure and a first lead-out structure 303, wherein the first connection structure realizes the interconnection between the second control structure 106 and the first control structure 104 including the first control terminal 204, and the same control signal can be simultaneously sent to the first control structure 104 and the second control structure 106 connected to the first connection structure through the first connection structure, and the storage signal received by the first control structure 104 connected to the first connection structure or the storage signal received by the second control structure 106 connected to the first connection structure can be obtained through the first connection structure; the first lead-out structure 303 leads the first control terminal 204 to the second surface of the second substrate 102, so as to facilitate the sending of control signals to the first control terminal 204 or the reception of storage signals sent by the first control terminal 204.

[0109] Exemplarily, the constituent materials of the first contact structure 304 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0110] In one embodiment, the semiconductor structure further includes: a second contact structure 310, the second contact structure 310 is located on the second surface of the second substrate 102, and is used to lead the second control structure 106 to the second surface of the second substrate 102; that is, the second control end 206 of the second control structure 106 is led to the second surface of the second substrate 102, wherein the second control structure 106 includes but is not limited to one or more of a second transistor and a second power supply, and the second control end 206 includes but is not limited to one or more of a second source end, a second drain end, a second gate end of the second control transistor and a second power supply end of the second power supply.

[0111] Exemplarily, the material constituting the second contact structure 310 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitride includes titanium nitride (TiN); conductive metal oxide includes iridium oxide (IrO2); and metal silicide includes tungsten silicon (WSi). The material constituting the second contact structure 310 may be the same as or different from the material constituting the first contact structure 304.

[0112] In one embodiment, the second contact structure 310 includes a hybrid bonding structure 309 and a through-hole contact structure 311, and the hybrid bonding structure 309 is used to achieve hybrid bonding between the second surface of the second substrate 102 and the first surface of the third substrate 108; the semiconductor structure also includes: a third contact structure 318, the third contact structure 318 passes through the third substrate 108; the third contact structure 318 is in contact with the through-hole contact structure 311, and is used to lead the second control end 206 of the second control structure 106 to the second surface of the third substrate 108.

[0113] Exemplarily, the size of the through-hole contact structure 311 is larger than the size of the hybrid bonding structure 309 .

[0114] In one embodiment, the third contact structure 318 includes a third through-hole structure 322 in contact with the first contact structure 304, wherein the third through-hole structure 322 includes a fourth through-hole structure in contact with the first connection structure and a fourth lead-out structure in contact with the first lead-out structure 303, the fourth through-hole structure is used to lead the contacted first control structure 104 and the second control structure 106 to the second surface of the third substrate 108, and the fourth lead-out structure is used to lead the first control end 204 of the first control structure 104 to the second surface of the third substrate 102.

[0115] Exemplarily, the materials constituting the third contact structure 318 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); conductive metal nitride includes titanium nitride (TiN); conductive metal oxide includes iridium oxide (IrO2); and metal silicide includes tungsten silicon (WSi). The materials constituting the third contact structure 318 may be the same as or different from the materials constituting the first contact structure 304 and the second contact structure 310.

[0116] The present disclosure also provides an electronic device comprising any of the above semiconductor structures.

[0117] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0118] The above-described embodiments merely represent several implementation methods of the embodiments of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that a person of ordinary skill in the art can make several modifications and improvements without departing from the concept of the embodiments of the present disclosure, all of which fall within the scope of protection of the embodiments of the present disclosure. Therefore, the scope of protection of the patent for the embodiments of the present disclosure shall be based on the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a first substrate, and forming a first storage structure on a first surface of the first substrate; Providing a second substrate, and forming a first control structure on a first surface of the second substrate; bonding the first substrate to the first surface side of the second substrate, wherein after bonding, the first control structure is electrically connected to the first storage structure; forming a second control structure on a second surface of the second substrate, wherein the second surface of the second substrate is opposite to the first surface of the second substrate; Providing a third substrate, and forming a second storage structure on a first surface of the third substrate; The third substrate is bonded to the second surface side of the second substrate. After bonding, the second storage structure and the second control structure are electrically connected.

2. The preparation method according to claim 1, characterized in that The step of bonding the first substrate to the first surface side of the second substrate includes: The first substrate is bonded to the first surface side of the second substrate through a hybrid bonding process.

3. The preparation method according to claim 1, characterized in that After forming the second control structure on the second surface of the second substrate and before bonding the third substrate to the second surface of the second substrate, the method further includes: forming a first contact hole penetrating the second substrate; A first contact structure is formed in the first contact hole, where the first contact structure is used to interconnect the first control structure and the second control structure.

4. The preparation method according to claim 1, characterized in that After forming the second control structure on the second surface of the second substrate and before bonding the third substrate to the second surface of the second substrate, the method further includes: forming a second contact hole on the second surface of the second substrate; A second contact structure is formed in the second contact hole, where the second contact structure is used to lead the second control structure to the second surface of the second substrate.

5. The preparation method according to claim 4, characterized in that The second contact structure includes a hybrid bonding structure and a through-hole contact structure; after bonding the third substrate to the second surface side of the second substrate, the method includes: forming a third contact hole penetrating the third substrate; forming a third contact structure in the third contact hole, wherein the third contact structure contacts the through-hole contact structure; The hybrid bonding structure is used to achieve hybrid bonding between the second surface of the second substrate and the first surface of the third substrate, and the size of the hybrid bonding structure is smaller than that of the through-hole contact structure.

6. A semiconductor structure, characterized in that include: a first substrate, wherein a first storage structure is formed on a first surface of the first substrate; a second substrate, wherein a first control structure is formed on a first surface of the second substrate, a second control structure is formed on a second surface of the second substrate, and the second surface of the second substrate is opposite to the first surface of the second substrate; a third substrate, wherein a second storage structure is formed on a first surface of the third substrate; The first substrate is bonded to the first surface side of the second substrate, the third substrate is bonded to the second surface side of the second substrate, the first storage structure is electrically connected to the first control structure, and the second storage structure is electrically connected to the second control structure.

7. The semiconductor structure according to claim 6, wherein: The first surface of the first substrate is close to the first surface of the second substrate, and the first surface of the third substrate is close to the second surface of the second substrate.

8. The semiconductor structure according to claim 6, wherein: The first storage structure and the second storage structure are both 3D NAND storage structures, and the first control structure and the second control structure are both CMOS structures.

9. The semiconductor structure according to claim 6, wherein: Also includes: The first contact structure penetrates the second substrate and is used to realize the interconnection between the first control structure and the second control structure.

10. The semiconductor structure according to claim 6, wherein: Also includes: a second contact structure, located on the second surface of the second substrate, for leading the second control structure to the second surface of the second substrate; a third contact structure penetrating the third substrate; The second contact structure includes: a hybrid bonding structure for achieving hybrid bonding between the second surface of the second substrate and the first surface of the third substrate; A through-hole contact structure is in contact with the third contact structure, and a size of the through-hole contact structure is larger than a size of the hybrid bonding structure.

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