Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes: a gate stack including a plurality of conductive lines extending in a first horizontal direction; first and second slits passing through the gate stack in a vertical direction and extending in a first horizontal direction; and a plurality of cell plugs extending in a vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. Each of the first slit and the second slit includes a first portion extending in a diagonal direction between a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and a second portion extending in the first horizontal direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-1023-0082574 filed in the Korean Intellectual Property Office on June 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices, and more particularly, to semiconductor devices and methods of manufacturing the semiconductor devices. Background Art

[0004] A nonvolatile memory element is a memory element in which stored data is maintained even if the supplied power is cut off. Recently, as the degree of integration of a two-dimensional nonvolatile memory element in which memory cells are formed in a single layer on a substrate has reached a limit, a three-dimensional nonvolatile memory element in which memory cells are vertically stacked on a substrate has been proposed.

[0005] The three-dimensional nonvolatile memory element includes interlayer insulating layers and gate electrodes stacked alternately, and a channel structure passing through the interlayer insulating layers and the gate electrodes, and the memory cells are stacked along the channel structure. Various structures and manufacturing methods have been developed to improve the reliability of nonvolatile memory elements having such a three-dimensional structure. Summary of the invention

[0006] According to one embodiment of the present disclosure, a semiconductor device includes: a gate stack including a plurality of conductive lines extending in a first horizontal direction; a first slit and a second slit passing through the gate stack in a vertical direction and extending in the first horizontal direction; and a plurality of cell plugs extending in a vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit. Each of the first slit and the second slit includes a first portion and a second portion, the first portion extending in a diagonal direction between the first horizontal direction and the second horizontal direction, and the second portion extending in the first horizontal direction.

[0007] According to one embodiment of the present disclosure, a semiconductor device includes: a gate stack including a plurality of conductive lines extending in a first horizontal direction; a first slit and a second slit, which are disposed at both ends of the gate stack and extend parallel to the first horizontal direction; a plurality of cell plugs, which extend in a vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit; and at least one third slit, which extends in the first horizontal direction by passing through an upper portion of the gate stack between the first slit and the second slit with a predetermined thickness, and extends in parallel with the first slit and the second slit. The first slit and the second slit have a wave pattern or a zigzag pattern along the first horizontal direction.

[0008] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: forming a plurality of preliminary channel holes and a plurality of preliminary slit holes through a stack, wherein a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked in the stack; filling the plurality of preliminary channel holes and the plurality of preliminary slit holes with gap filling patterns; forming a first insulating layer on the stack, and forming channel holes by selectively etching the first insulating layer, wherein the channel holes expose the gap filling patterns formed inside the plurality of preliminary channel holes; extending the channel holes into the stack by removing the gap filling patterns exposed through the channel holes; forming cell plugs inside the channel holes; and forming a plurality of cell plugs between the cell plugs and the first insulating layer. A second insulating layer is formed on the insulating layer, and a slit hole is formed by selectively etching the second insulating layer and the first insulating layer, the slit hole exposing the gap filling pattern formed inside the plurality of preliminary slit holes; a recessed region is formed by removing the gap filling pattern exposed by the slit holes and etching the plurality of interlayer insulating layers exposed by the sidewalls of the slit holes by a predetermined thickness; after removing the plurality of sacrificial layers exposed by the slit holes, a plurality of conductive layers are formed in the space where the plurality of sacrificial layers are removed; a groove is formed by removing the plurality of conductive layers remaining inside the slit holes, the slit holes are connected to each other in the groove; and a slit is formed by filling the groove with an insulating material. The recessed regions of adjacent slit holes are in contact with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and Figure 1B is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 is a cross-sectional view illustrating a peripheral circuit structure.

[0011] Figure 3A and Figure 3B 2 are a plan view and a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 4A to 4K are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present disclosure.

[0013] Figure 5 is a plan view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0014] Figure 6 is a plan view illustrating a semiconductor device according to still another embodiment of the present disclosure.

[0015] Figure 7 is a block diagram illustrating a configuration of a memory system according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In the following, some embodiments of the present disclosure are described. In the accompanying drawings, thicknesses and distances are indicated for ease of description and may be exaggerated relative to actual physical thicknesses. In describing the present disclosure, known configurations that are not relevant to the subject matter of the present disclosure may be omitted. It should be noted that when reference numerals are added to components of each of the accompanying drawings, even if the same components are shown in different drawings, the same components have the same reference numerals when possible.

[0017] Throughout the specification, in the case where a part is “connected” to another part, the case includes not only the case where the part is “directly connected” to the other part, but also the case where the part is “indirectly connected” to the other part (with another element interposed therebetween). Throughout the specification, in the case where a part includes components, the case means that the part may further include other components without excluding the other components unless otherwise specifically stated.

[0018] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the same. According to embodiments of the present technology, by extending a slit structure in a zigzag direction, tensile stress or compressive stress generated in one direction of a memory block can be distributed.

[0019] Figure 1A and Figure 1B is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0020] refer to Figure 1A and Figure 1B , each of the semiconductor devices according to the embodiments of the present disclosure may include a peripheral circuit structure PC and a cell array CAR disposed on a substrate SUB.

[0021] The substrate SUB may be a single crystal semiconductor layer. For example, the substrate SUB may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin layer formed by a selective epitaxial growth method.

[0022] The cell array CAR may include a plurality of memory blocks. Each memory block in the memory block may include a plurality of cell strings. Each cell string in the cell string is electrically connected to a bit line, a source line, a word line, and a selection line. Each cell string in the cell string may include a memory cell and a selection transistor connected in series. Each selection line in the selection line serves as a gate electrode of a selection transistor corresponding thereto, and each word line in the word line serves as a gate electrode of a memory cell corresponding thereto.

[0023] The peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors and capacitors electrically connected to the cell array CAR. The NMOS and PMOS transistors, resistors and capacitors may be used as elements to configure a row decoder, a column decoder, a page buffer and a control circuit.

[0024] like Figure 1A As shown, the peripheral circuit structure PC may be disposed on a partial region of the substrate SUB that does not overlap with the cell array CAR.

[0025] Alternatively, Figure 1B As shown, the peripheral circuit structure PC may be disposed between the cell array CAR and the substrate SUB. In this case, since the peripheral circuit structure PC overlaps the cell array CAR, the area of ​​the substrate SUB occupied by the cell array CAR and the peripheral circuit structure PC may be reduced.

[0026] Figure 2 is a cross-sectional view illustrating a peripheral circuit structure. Figure 2 The peripheral circuit structure PC shown in the figure may be included in Figure 1A The peripheral circuit structure shown in the Figure 1B The peripheral circuit structure shown in FIG.

[0027] refer to Figure 2 , the peripheral circuit structure PC may include a peripheral gate electrode PEG, a peripheral gate insulating layer PGI, a junction Jn, a peripheral circuit line PCL, a peripheral contact plug PCP, and a peripheral circuit insulating layer PIL.

[0028] Each of the peripheral gate electrodes PEG may be used as a gate electrode of an NMOS transistor and a PMOS transistor of the peripheral circuit structure PC. A peripheral gate insulating layer PGI is provided between each of the peripheral gate electrodes PEG and the substrate SUB.

[0029] The junction Jn is a region defined by implanting n-type or p-type impurities into the active region of the substrate SUB, is disposed on both sides of each of the peripheral gate electrodes PEG in the peripheral gate electrodes PEG, and serves as a source junction or a drain junction. The active region of the substrate SUB may be segmented by an isolation layer ISO formed in the substrate SUB. The isolation layer ISO is formed of an insulating material.

[0030] The peripheral circuit lines PCL may be electrically connected to the circuits of the peripheral circuit structure PC through the peripheral contact plugs PCP.

[0031] The peripheral circuit insulating layer PIL may cover the circuits of the peripheral circuit structure PC, the peripheral circuit lines PCL, and the peripheral contact plugs PCP. The peripheral circuit insulating layer PIL may include insulating layers stacked in a plurality of layers.

[0032] Figure 3A and Figure 3B 2 are a plan view and a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0033] Figure 3A FIG1 illustrates the layout of the cell array CAR, and Figure 3B A cross section of the cell array CAR of FIG. 1 is illustrated.

[0034] refer to Figure 3A , the cell array may include a gate stack GST, a plurality of cell plugs CP, first and second slits SLIT1 and SLIT2 , and one or more third slits SLIT3_A and SLIT3_B.

[0035] The gate stack GST may include a line pattern stacked in a vertical direction. The vertical direction may be a direction perpendicularly crossing the first horizontal direction X and the second horizontal direction Y. The line pattern may include an interlayer insulating layer and a conductive pattern. Figure 3B Describe the stacked structure of interlayer insulating layers and conductive patterns.

[0036] The gate stack GST may be separated by the first slit SLIT1 and the second slit SLIT2. For example, the first slit SLIT1 and the second slit SLIT2 may extend in the vertical direction in the gate stack GST, may pass through the gate stack GST, and may extend in the first horizontal direction X. The first horizontal direction X may be a word line extension direction. The first slit SLIT1 and the second slit SLIT2 may extend in the first horizontal direction X, and may have a wavy pattern or a zigzag pattern along the extension direction as shown in the figure. The first slit SLIT1 and the second slit SLIT2 may be arranged to be spaced apart from each other by a predetermined distance in the second horizontal direction Y, and may be arranged in parallel. The second horizontal direction Y may be a direction perpendicularly intersecting the first horizontal direction X. The second horizontal direction Y may be a bit line extension direction. Because the first slit SLIT1 and the second slit SLIT2 extend in the first horizontal direction X and have a wavy pattern or a zigzag pattern along the extension direction, the first slit SLIT1 and the second slit SLIT2 may include a portion extending a predetermined length in the diagonal direction between the first horizontal direction X and the second horizontal direction Y. According to the arrangement position of the cell plug CP, an angle θ between portions extending in the diagonal direction of each of the first slit SLIT1 and the second slit SLIT2 may be adjusted.

[0037] Each of the first slit SLIT1 and the second slit SLIT2 may include an extension portion FS, which is a sidewall extending a predetermined length at a bent portion where the extension direction changes. The extension portion FS may extend in a direction parallel to the first horizontal direction X, which is the extension direction of the word line. As shown in the figure, the extension portion FS may have a flat shape. That is, the bent portion where the extension direction of each of the first slit SLIT1 and the second slit SLIT2 changes may be formed to have a sidewall parallel to the first horizontal direction X. The length D of the extension portion FS may be equal to or greater than the critical dimension of one cell plug CP. Therefore, the outer sidewall portion of the portion where the extension direction of each of the first slit SLIT1 and the second slit SLIT2 changes and bends (that is, the portion extending in the diagonal direction and the outer sidewall of the extension portion FS) may form an obtuse angle. When the outer sidewall of the portion where the extension direction of each of the first slit SLIT1 and the second slit SLIT2 changes and bends has a V-shape, the setting space of the cell plug CP is reduced. Therefore, in one embodiment of the present disclosure, a portion where the extension direction of each of the first and second slits SLIT1 and SLIT2 is changed and bent may be formed to have a sidewall parallel to the first horizontal direction X, and thus a maximum disposition space of the cell plug CP may be ensured.

[0038] The first slits SLIT1 and the second slits SLIT2 may be respectively disposed at boundaries between the memory blocks.

[0039] A plurality of cell plugs CP may extend in a vertical direction in the gate stack GST between the first slit SLIT1 and the second slit SLIT2, and may be regularly arranged. For example, a plurality of cell plugs CP may be arranged in a zigzag pattern or a matrix pattern. A plurality of cell plugs CP may be arranged by passing through the gate stack GST in a vertical direction. Each of the plurality of cell plugs CP may be formed in a columnar shape. Each of the plurality of cell plugs CP may include a channel structure CH extending in a vertical direction and a memory layer ML surrounding the sidewall of the channel structure CH.

[0040] At least one or more third slits SLIT3_A and SLIT3_B may extend in the first horizontal direction X by passing through the gate stack GST between the first slit SLIT1 and the second slit SLIT2 at a predetermined depth. At least one or more third slits SLIT3_A and SLIT3_B may have a wave pattern or a zigzag pattern extending in the first horizontal direction X. At least one or more third slits SLIT3_A and SLIT3_B may overlap with some of the cell plugs CP in a partial region. At least one or more third slits SLIT3_A and SLIT3_B may pass through the gate stack GST at a predetermined depth, and, for example, at least one or more third slits SLIT3_A and SLIT3_B may be formed so that a conductive line for a drain selection line included in the gate stack GST is separated to both ends by at least one or more third slits SLIT3_A and SLIT3_B.

[0041] The width of at least one or more third slits SLIT3_A and SLIT3_B may be formed to be different from the width of the first slit SLIT1 and the second slit SLIT2. For example, the width of at least one or more third slits SLIT3_A and SLIT3_B may be formed to be narrower than the width of the first slit SLIT1 and the second slit SLIT2. The present disclosure is not limited thereto.

[0042] The first and second slits SLIT1 and SLIT2 may be disposed to be spaced apart from each other by a predetermined distance and disposed in parallel in the second horizontal direction Y. Therefore, the number of cell plugs CP arranged in the second horizontal direction Y between the first and second slits SLIT1 and SLIT2 may be uniform.

[0043] The plurality of cell plugs CP may be divided into a plurality of groups GR1 to GR4 by at least one or more third slits SLIT3_A and SLIT3_B. The plurality of groups GR1 to GR4 may be individually controlled by conductive lines for drain selection lines separated by one or more third slits SLIT3_A and SLIT3_B. Although the plurality of groups are shown and described as four in one embodiment of the present disclosure, the present disclosure is not limited thereto, and the number of cell plugs CP included in one group is not limited.

[0044] Figure 3B The diagram shows the Figure 3A A cross section of the cell array is taken along line Y1-Y2 shown in FIG.

[0045] refer to Figure 3B The semiconductor device may include: a gate stack GST stacked on a substrate SUB, a plurality of cell plugs CP extending in a vertical direction Z in the gate stack GST, a first slit SLIT1 and a second slit SLIT2 passing through the gate stack GST in the vertical direction Z, and at least one or more third slits SLIT3_A and SLIT3_B passing through a portion of an upper portion of the gate stack GST.

[0046] The gate stack GST may include interlayer insulating layers ILD and conductive lines CL that are alternately stacked. Each of the interlayer insulating layers ILD and the conductive lines CL may be Figure 3A . A part of the conductive lines CL may be lines for word lines, and another part may be lines for selection lines. For example, at least one conductive line CL disposed at the lowermost end of the conductive lines CL may be a line for a source selection line, at least one conductive line CL disposed at the uppermost end among the conductive lines CL may be a line for a drain selection line, and a conductive line CL disposed between a line for a source selection line and a line for a drain selection line may be a line for a word line.

[0047] The conductive line CL may include a conductive material such as polysilicon or a metal (e.g., tungsten, molybdenum). The interlayer insulating layer ILD may be used to insulate the stacked conductive lines CL from each other. The interlayer insulating layer ILD may include an insulating material such as oxide, nitride, or an air gap. Among the interlayer insulating layers ILD, the interlayer insulating layer ILD disposed at the uppermost portion may be formed to be thicker than the remaining interlayer insulating layers ILD.

[0048] The first slit SLIT1 and the second slit SLIT2 may be disposed inside the gate stack GST. The first slit SLIT1 and the second slit SLIT2 may pass through the gate stack GST in the vertical direction Z to separate adjacent gate stacks GST from each other. The first slit SLIT1 and the second slit SLIT2 may be formed of an insulating material.

[0049] A plurality of cell plugs CP may be disposed in the gate stack GST between the first slit SLIT1 and the second slit SLIT2. The plurality of cell plugs CP may extend in the vertical direction Z. Each of the plurality of cell plugs CP may include a channel structure CH extending in the vertical direction Z and a memory layer ML surrounding a sidewall of the channel structure CH.

[0050] The channel structure CH may include a channel layer CHL extending in the vertical direction Z, and may further include a core insulation layer CO extending in the vertical direction Z inside the channel layer CHL and a cap layer CAP disposed on the core insulation layer CO.

[0051] The channel layer CHL may include a semiconductor layer. As an example, the channel layer CHL may include silicon. The core insulating layer CO may include an insulating layer. The cap layer CAP may be a silicon layer into which impurities are implanted.

[0052] The memory layer ML may include a tunnel insulating layer, a data storage layer, and a blocking insulating layer. The tunnel insulating layer may extend in a vertical direction Z while surrounding the channel layer CHL. The tunnel insulating layer may be formed of a silicon oxide layer capable of charge tunneling. The data storage layer may extend in a vertical direction Z while surrounding the tunnel insulating layer. The data storage layer may be formed of a material layer capable of storing changed data using Fowler-Nordheim tunneling. As an embodiment, the data storage layer may be formed of a charge trapping nitride layer. The blocking insulating layer may extend in a vertical direction Z while surrounding the data storage layer. The blocking insulating layer may include an oxide layer capable of blocking charges.

[0053] At least one or more third slits SLIT3_A and SLIT3_B may pass through the gate stack GST between the first slit SLIT1 and the second slit SLIT2 at a predetermined depth. At least one or more third slits SLIT3_A and SLIT3_B may overlap with the cell plug CP in a partial area. One or more third slits SLIT3_A and SLIT3_B may pass through the gate stack GST at a predetermined depth, and for example, one or more third slits SLIT3_A and SLIT3_B may be formed so that: a conductive line for a drain selection line included in the gate stack GST is separated to both ends by the one or more third slits SLIT3_A and SLIT3_B. At least one or more third slits SLIT3_A and SLIT3_B may be formed of an insulating material.

[0054] The plurality of cell plugs CP may be divided into a plurality of groups GR1 to GR4 by at least one or more third slits SLIT3_A and SLIT3_B.

[0055] As described above, since the first slits SLIT1 and the second slits SLIT2 are arranged to extend in the first horizontal direction X which is the extension direction of the word line and have a zigzag pattern or a waveform pattern, the tensile stress or compressive stress generated in one direction of the memory block (for example, the first horizontal direction X) can be distributed in the second horizontal direction Y.

[0056] Figures 4A to 4K are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present disclosure.

[0057] refer to Figure 4A , a stack ST in which the interlayer insulating layers 103 and the sacrificial layers 105 are alternately stacked may be formed. The stack ST may be formed on a substrate 101 including a peripheral circuit (not shown).

[0058] The sacrificial layer 105 may be formed of a material different from that of the interlayer insulating layer 103. For example, the interlayer insulating layer 103 may be formed of an oxide such as silicon oxide. The sacrificial layer 105 may be formed of a material having an etching rate different from that of the interlayer insulating layer 103. For example, the sacrificial layer 105 may be formed of a nitride such as silicon nitride.

[0059] The interlayer insulating layer 103 disposed at the lowermost portion and the interlayer insulating layer 103 disposed at the uppermost portion may be formed to be thicker than the remaining interlayer insulating layer 103 .

[0060] Thereafter, a mask pattern (not shown) is formed on the stack ST, a portion of which is opened in a region where a cell plug is to be formed and a region where a first slit and a second slit are to be formed, and an etching process using the mask pattern is performed to form a plurality of preliminary channel holes H1 and a plurality of preliminary slit holes H2 passing through the stack ST. The diameter of the plurality of preliminary slit holes H2 may be equal to or greater than the diameter of the plurality of preliminary channel holes H1.

[0061] Figure 4B is executed on it with Figure 4A A plan view of a semiconductor device with associated processing steps. Figure 4B , the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2 may be spaced apart from each other and arranged regularly. For example, the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2 may be arranged in a zigzag pattern.

[0062] The region where the first slit and the second slit are to be formed may have a zigzag pattern. Therefore, a plurality of preliminary slit holes H2 may also be formed in the region where the first slit and the second slit are to be formed, and may be arranged in a zigzag pattern. As another embodiment, the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2 may be arranged in a matrix pattern.

[0063] refer to Figure 4C By filling the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2 with a gap-filling material, a gap-filling pattern 107 is formed. The gap-filling pattern 107 may include carbon.

[0064] Thereafter, after etching a portion of the upper end of the gap filling pattern 107, an auxiliary pattern 109 may be formed in the portion where the gap filling pattern 107 is etched and removed. That is, the gap filling pattern 107 may be formed at the lower end and middle portion of each of the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2, and the auxiliary pattern 109 contacting the gap filling pattern 107 may be formed at the upper end of each of the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2. The auxiliary pattern 109 may include a tungsten pattern, and may further include a titanium nitride layer surrounding a surface of the tungsten pattern.

[0065] As another embodiment, each of the plurality of preliminary channel holes H1 and the plurality of preliminary slit holes H2 may be filled with only the gap-filling pattern 107 without forming the auxiliary pattern 109 .

[0066] refer to Figure 4D and Figure 4EAfter forming the first insulating layer 111 on the stack ST, the first insulating layer 111 is selectively etched to form a channel hole H3 through which the auxiliary pattern 109 formed in the plurality of preliminary channel holes H1 is exposed. At this time, the auxiliary pattern 109 formed in the plurality of preliminary slit holes H2 is not exposed by the first insulating layer 111.

[0067] refer to Figure 4F An etching process is performed to remove the auxiliary pattern 109 exposed through the channel hole H3 and the gap-filling pattern 107 inside the plurality of preliminary channel holes H1. Therefore, the channel hole H3 may extend in the vertical direction Z so that the substrate 101 is exposed.

[0068] At this time, the auxiliary patterns 109 and the gap-filling patterns 107 formed in the plurality of preliminary slit holes H2 are protected by the first insulating layer 111 and are not removed.

[0069] refer to Figure 4G , a cell plug CP is formed inside each of the channel holes H3 .

[0070] For example, the memory layer 113 is formed by sequentially forming a blocking insulating layer, a data storage layer, and a tunnel insulating layer on the sidewall of each of the channel holes H3. The blocking insulating layer may be formed on the sidewall of each of the channel holes H3. The blocking insulating layer may include an oxide layer capable of blocking charges. As an embodiment, the blocking insulating layer may be made of aluminum oxide Al. 2 O 3 The data storage layer may be formed on the sidewalls of the blocking insulating layer. The data storage layer may be formed of a charge trapping layer, a material layer including conductive nanodots, or a phase change material layer. For example, the data storage layer may use Fowler-Nordheim tunneling to store changed data. For this purpose, the data storage layer may be formed of a silicon nitride layer capable of trapping charges. The tunnel insulating layer may be formed on the sidewalls of the data storage layer. The tunnel insulating layer may be formed of a silicon oxide layer capable of performing charge tunneling.

[0071] Thereafter, a channel layer 115 is formed on the sidewall of the memory layer 113. As an embodiment, the channel layer 115 may include silicon. Thereafter, a core insulating layer 117 may be formed by filling a central region of each of the channel holes H3 with an insulating material.

[0072] Thereafter, upper portions of the channel layer 115 and the core insulating layer 117 may be etched by a predetermined thickness, and a cap layer 119 may be formed in a space where the channel layer 115 and the core insulating layer 117 are removed. The cap layer 119 may be formed of a doped semiconductor layer.

[0073] refer to Figure 4H , a second insulating layer 121 is formed on the first insulating layer 111 and the cell plugs CP. The second insulating layer 121 may include oxide.

[0074] Thereafter, the second insulating layer 121 is selectively etched to form a slit hole H4, which exposes the Figure 4G A plurality of preliminary slit holes H2 are formed Figure 4G At this time, the cell plug CP is not exposed by the second insulating layer 121.

[0075] Afterwards, you can remove Figure 4G The auxiliary patterns 109 and the gap-filling patterns 107 are exposed so that the slit holes H4 extend downward.

[0076] refer to Fig. 4I , an additional etching process is performed to etch the sidewall of the interlayer insulating layer 103 exposed through the slit hole H4 by a predetermined thickness to form a recessed region R. Therefore, the slit holes H4 adjacent to each other may be connected to each other through the recessed region R.

[0077] refer to Figure 4J , can be removed by Fig. 4I The slit hole H4 exposes Fig. 4I The sacrificial layer 105 is removed by Fig. 4I The sacrificial layer 105 is adjacent to each other Fig. 4I The slit holes H4 may be connected to each other, and thus a through hole is formed in the region where the first slit and the second slit are formed. Fig. 4I The stack ST exposes the trench T1 of the substrate 101. Figure 3B The first slit SLIT1 and the second slit SLIT2 may be formed in the first horizontal direction X. As another embodiment, the trench T1 may have a zigzag pattern or a wave pattern and may extend in the first horizontal direction X. Figure 5 The first and second slits SLIT1 and SLIT2 may have a zigzag pattern or a wave pattern and may include a portion extending in a line shape in the first horizontal direction X.

[0078] Thereafter, the conductive material is filled therefrom to remove Fig. 4I The plurality of conductive patterns 123 are formed by occupying spaces of the sacrificial layer 105. For example, the plurality of conductive patterns 123 may be formed by including a conductive material such as polysilicon doped with N-type impurities, tungsten, tungsten silicide, molybdenum, or metal.

[0079] The plurality of interlayer insulating layers 103 , the plurality of conductive patterns 123 , the first insulating layer 111 , and the second insulating layer 121 may be defined as a gate stack GST.

[0080] Thereafter, the conductive material inside the trench T1 may be removed so that the plurality of conductive patterns 123 are separated from each other by the trench T1 .

[0081] refer to Figure 4K , the first and second slits 125 are formed by filling the trench T1 with an insulating material. The first and second slits 125 may include oxide.

[0082] The first slit and the second slit 125 may be formed in a manner similar to Figure 3B The first slits SLIT1 and the second slits SLIT2 may be in a zigzag pattern or a wave pattern, extending in the first horizontal direction X. As another embodiment, the first slits and the second slits 125 may have a shape similar to that described later. Figure 5 The first and second slits SLIT1 and SLIT2 may have a zigzag pattern or a wave pattern, and may include a portion extending in a straight line in the first horizontal direction X in one portion.

[0083] Thereafter, an etching process is performed to form second and third trenches T2 and T3 that pass through an upper portion of the gate stack GST with a predetermined thickness. The second and third trenches T2 and T3 may be formed to pass through at least one conductive pattern 123 used as a drain selection line among a plurality of conductive patterns 123. The second and third trenches T2 and T3 may be formed to overlap a portion of the cell plug CP.

[0084] Thereafter, the third slit 127 is formed by filling the second trench T2 and the third trench T3 with an insulating material. The third slit 127 may be similar to Figure 3B The third slits SLIT3_A and SLIT3_B extend in the first horizontal direction X in a zigzag pattern or a wave pattern.

[0085] Figure 5 is a plan view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0086] refer to Figure 5 , the cell array may include a gate stack GST, a plurality of cell plugs CP, first and second slits SLIT1 and SLIT2 , and at least one third slit SLIT3 .

[0087] The gate stack GST may include a line pattern stacked in a vertical direction. The vertical direction may be a direction perpendicularly intersecting the first horizontal direction X and the second horizontal direction Y. The line pattern may include an interlayer insulating layer and a conductive pattern. The stacked structure of the interlayer insulating layer and the conductive pattern may be the same as that of the above reference. Figure 3B The stacking structure of the gate stack GST described is the same.

[0088] The gate stack GST may be separated by the first slit SLIT1 and the second slit SLIT2. For example, the first slit SLIT1 and the second slit SLIT2 may extend in the vertical direction in the gate stack GST, may pass through the gate stack GST, and may extend in the first horizontal direction X. The first horizontal direction X may be a word line extension direction. The second horizontal direction Y may be a direction perpendicularly intersecting the first horizontal direction X. The second horizontal direction Y may be an extension direction of the bit line BL. The first slit SLIT1 and the second slit SLIT2 may be respectively disposed at the boundaries between the memory blocks.

[0089] The first slits SLIT1 and the second slits SLIT2 may extend in the first horizontal direction X, and may have a wave pattern or a zigzag pattern along the extending direction.

[0090] For example, each of the first slit SLIT1 and the second slit SLIT2 may include a first portion S1 and a second portion S2, the first portion S1 extending in a diagonal direction between the first horizontal direction X and the second horizontal direction Y and having a mirror-symmetrical structure with respect to the second horizontal direction Y, and the second portion S2 connected between the first portions S1 and extending in the first horizontal direction X. For example, one first portion S1 extends in a diagonal direction between the first horizontal direction X and the second horizontal direction Y, and one end of one first portion S1 is connected to one end of the second portion S2 extending in the first horizontal direction X. One end of another first portion S1 is connected to the other end of the second portion S2. That is, each of the first slit SLIT1 and the second slit SLIT2 includes: a portion extending in a diagonal direction between the first horizontal direction X and the second horizontal direction Y, and a portion extending in the first horizontal direction X. The extension length of the second portion S2 may be longer than the arrangement length of at least three cell plugs CP.

[0091] A thickness D2 of a first portion S1 of each of the first and second slits SLIT1 and SLIT2 may be equal to or smaller than a thickness D1 of a second portion S2 .

[0092] The first and second slits SLIT1 and SLIT2 may be disposed to be spaced apart from each other by a predetermined distance and disposed in parallel in the second horizontal direction Y. Therefore, the number of cell plugs arranged in the second horizontal direction Y between the first and second slits SLIT1 and SLIT2 may be uniform.

[0093] The second horizontal direction Y may be a direction perpendicularly crossing the first horizontal direction X. The second horizontal direction Y may be an extending direction of the bit lines BL. The first slits SLIT1 and the second slits SLIT2 may be respectively disposed at boundaries between memory blocks.

[0094] A plurality of cell plugs CP may extend in a vertical direction in the gate stack GST between the first slit SLIT1 and the second slit SLIT2, and may be regularly arranged. For example, a plurality of cell plugs CP may be arranged in a zigzag pattern or a matrix pattern. A plurality of cell plugs CP may be arranged by passing through the gate stack GST in a vertical direction. Each of the plurality of cell plugs CP may be formed in a columnar shape. Each of the plurality of cell plugs CP may include a channel structure CH extending in a vertical direction and a memory layer ML surrounding the sidewall of the channel structure CH.

[0095] In each of the first slit SLIT1 and the second slit SLIT2, an angle θ between the first portion S1 and the second portion S2 may be adjusted according to the arrangement position of the cell plugs CP. For example, when the cell plugs CP are arranged in a matrix pattern, the angle θ may be 90°, and when the cell plugs CP are arranged in a zigzag pattern, the angle θ may have an obtuse angle greater than 90°.

[0096] At least one third slit SLIT3 may extend in the first horizontal direction X by passing through the gate stack GST between the first slit SLIT1 and the second slit SLIT2 at a predetermined depth. The at least one third slit SLIT3 may have a wave pattern or a zigzag pattern extending in the first horizontal direction X. The at least one third slit SLIT3 may overlap with some of the cell plugs CP in a partial area. The at least one third slit SLIT3 may pass through the gate stack GST at a predetermined depth, and, for example, the at least one third slit SLIT3 may be formed so that a conductive line for a drain selection line included in the gate stack GST is separated to both ends by the at least one third slit SLIT3. The at least one third slit SLIT3 may be disposed in parallel to the first slit SLIT1 and the second slit SLIT2 of the first slit SLIT1 and the second slit SLIT2.

[0097] A width of at least one third slit SLIT3 may be formed to be different from widths of the first and second slits SLIT1 and SLIT2 .

[0098] According to the reference Figures 4A to 4K The method for manufacturing a semiconductor device described above is used to manufacture a semiconductor device according to another embodiment of the present disclosure described above. In this case, Figure 4B In the embodiment, the plurality of preliminary slit holes H2 may be formed to include a portion extending in a diagonal direction between the first horizontal direction X and the second horizontal direction Y and a portion extending in the first horizontal direction X by a predetermined length.

[0099] Figure 6is a plan view illustrating a semiconductor device according to still another embodiment of the present disclosure.

[0100] refer to Figure 6 , the cell array may include a gate stack GST, a plurality of cell plugs CP, first and second slits SLIT1 and SLIT2 , and at least one third slit SLIT3 .

[0101] The gate stack GST may include a line pattern stacked in a vertical direction. The vertical direction may be a direction perpendicularly intersecting the first horizontal direction X and the second horizontal direction Y. The line pattern may include an interlayer insulating layer and a conductive pattern. The stacked structure of the interlayer insulating layer and the conductive pattern may be the same as that of the above reference. Figure 3B The stacking structure of the gate stack GST described is the same.

[0102] The gate stack GST may be separated by the first slit SLIT1 and the second slit SLIT2. For example, the first slit SLIT1 and the second slit SLIT2 may extend in the vertical direction in the gate stack GST, may pass through the gate stack GST, and may extend in the first horizontal direction X. The first horizontal direction X may be a word line extension direction. The second horizontal direction Y may be a direction perpendicularly intersecting the first horizontal direction X. The second horizontal direction Y may be an extension direction of the bit line BL. The first slit SLIT1 and the second slit SLIT2 may be respectively disposed at the boundaries between the memory blocks.

[0103] The first slits SLIT1 and the second slits SLIT2 may extend in the first horizontal direction X, and may have a wave pattern or a zigzag pattern along the extending direction.

[0104] For example, each of the first slit SLIT1 and the second slit SLIT2 may include a first portion S11 and a second portion S12, the first portion S11 extending by a predetermined length in a diagonal direction between the first horizontal direction X and the second horizontal direction Y, and the second portion S12 connected between the first portions S11 and extending in the second horizontal direction Y. For example, one first portion S11 extends in a diagonal direction between the first horizontal direction X and the second horizontal direction Y, one end of one second portion S12 extending in the second horizontal direction Y is connected to an end of one first portion S11, and the other end of the second portion S12 is connected to an end of another first portion S11. That is, each of the first slit SLIT1 and the second slit SLIT2 includes a portion extending in a diagonal direction between the first horizontal direction X and the second horizontal direction Y and a portion extending in the second horizontal direction Y.

[0105] The first portion S11 of each of the first and second slits SLIT1 and SLIT2 may be disposed to be spaced a predetermined distance apart from each other and disposed in parallel in the second horizontal direction Y. Therefore, the number of cell plugs arranged in the second horizontal direction Y between the first and second slits SLIT1 and SLIT2 may be uniform.

[0106] The second horizontal direction Y may be a direction perpendicularly crossing the first horizontal direction X. The second horizontal direction Y may be an extending direction of the bit lines BL. The first slits SLIT1 and the second slits SLIT2 may be respectively disposed at boundaries between memory blocks.

[0107] A plurality of cell plugs CP may extend in a vertical direction in the gate stack GST between the first slit SLIT1 and the second slit SLIT2, and may be regularly arranged. For example, a plurality of cell plugs CP may be arranged in a zigzag pattern or a matrix pattern. A plurality of cell plugs CP may be arranged by passing through the gate stack GST in a vertical direction. Each of the plurality of cell plugs CP may be formed in a columnar shape. Each of the plurality of cell plugs CP may include a channel structure CH extending in a vertical direction and a memory layer ML surrounding the sidewall of the channel structure CH.

[0108] In each of the first slit SLIT1 and the second slit SLIT2 , the angle θ between the first portion S11 and the second portion S12 may be adjusted according to the arrangement position of the cell plug CP. For example, the angle θ between the first portion S11 and the second portion S12 may have an acute angle less than 90°.

[0109] At least one third slit SLIT3 may extend in the first horizontal direction X by passing through the gate stack GST between the first slit SLIT1 and the second slit SLIT2 at a predetermined depth. The at least one third slit SLIT3 may have a wave pattern or a zigzag pattern extending in the first horizontal direction X. The at least one third slit SLIT3 may overlap with some of the cell plugs CP in a partial area. The at least one third slit SLIT3 may pass through the gate stack GST at a predetermined depth, and, for example, the at least one third slit SLIT3 may be formed so that a conductive line for a drain selection line included in the gate stack GST is separated to both ends by the at least one third slit SLIT3. The at least one third slit SLIT3 may be disposed in parallel to the first slit SLIT1 and the second slit SLIT2 of the first slit SLIT1 and the second slit SLIT2.

[0110] According to the reference Figures 4A to 4KThe method for manufacturing a semiconductor device described above is used to manufacture a semiconductor device according to another embodiment of the present disclosure described above. In this case, Figure 4B In the embodiment, the plurality of preliminary slit holes H2 may be formed to include a portion extending in a diagonal direction between the first horizontal direction X and the second horizontal direction Y and a portion extending in the second horizontal direction Y by a predetermined length.

[0111] Figure 7 is a block diagram illustrating a configuration of a memory system according to one embodiment of the present disclosure.

[0112] refer to Figure 7 , a memory system 1100 according to an embodiment of the present disclosure includes a memory device 1120 and a memory controller 1110 .

[0113] The memory device 1120 may be a multi-chip package configured of a plurality of flash memory chips.

[0114] The memory controller 1110 may be configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a CPU 1112, a host interface 1113, an error correction code (ECC) 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol of a host connected to the memory system 1100. The ECC 1114 detects and corrects errors included in data read from the memory device 1120. The memory interface 1115 performs an interface connection with the memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) or the like storing code data for interfacing with the host.

[0115] The above-mentioned memory system 1100 may be a memory card or a solid state disk (SSD) in which a memory device 1120 and a memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect-express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

Claims

1. A semiconductor device comprising: a gate stack comprising a plurality of conductive lines extending in a first horizontal direction; a first slit and a second slit that penetrate the gate stack in a vertical direction and extend in the first horizontal direction; as well as a plurality of cell plugs extending in the vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit, Each of the first slit and the second slit includes a first portion and a second portion, the first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and the second portion extending in the first horizontal direction. 2 . The semiconductor device according to claim 1 , wherein the second horizontal direction is a bit line extending direction in which the bit lines extend. 3 . The semiconductor device according to claim 1 , wherein the first horizontal direction is a word line extending direction in which word lines extend. 4 . The semiconductor device according to claim 1 , wherein an angle between the first portion and the second portion is equal to or greater than 90 degrees.

5. The semiconductor device according to claim 1 , wherein the first slit and the second slit are spaced apart from each other in the second horizontal direction, and The number of the plurality of unit plugs arranged between the first slit and the second slit in the second horizontal direction is uniform. 6 . The semiconductor device according to claim 1 , wherein a thickness of the first portion and a thickness of the second portion are different from or equal to each other.

7. The semiconductor device according to claim 1, further comprising: At least one third slit extends in the first horizontal direction and passes through an upper portion of the gate stack between the first slit and the second slit with a predetermined thickness. 8 . The semiconductor device according to claim 1 , wherein the plurality of cell plugs are arranged in a zigzag pattern or a matrix pattern.

9. A semiconductor device comprising: a gate stack comprising a plurality of conductive lines extending in a first horizontal direction; A first slit and a second slit, which are disposed at two ends of the gate stack and extend parallel to the first horizontal direction; a plurality of cell plugs extending in a vertical direction orthogonal to the first horizontal direction in the gate stack between the first slit and the second slit; as well as at least one third slit extending in the first horizontal direction by passing through an upper portion of the gate stack between the first slit and the second slit with a predetermined thickness and extending in parallel with the first slit and the second slit, The first slit and the second slit have a wave pattern or a zigzag pattern along the first horizontal direction.

10. The semiconductor device according to claim 9, wherein each of the first slit and the second slit includes a first portion and a second portion, the first portion extending in a diagonal direction between the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, and the second portion extending in the first horizontal direction. 11 . The semiconductor device according to claim 10 , wherein the first horizontal direction is a word line extending direction in which word lines extend, and the second horizontal direction is a bit line extending direction in which bit lines extend. 12 . The semiconductor device according to claim 10 , wherein an angle between the first portion and the second portion is equal to or greater than 90 degrees. 13 . The semiconductor device according to claim 9 , wherein the plurality of cell plugs are arranged in a zigzag pattern or a matrix pattern.

14. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of preliminary via holes and a plurality of preliminary slit holes through a stack in which a plurality of interlayer insulating layers and a plurality of sacrificial layers are alternately stacked; filling the plurality of preliminary channel holes and the plurality of preliminary slit holes with a gap-fill pattern; forming a first insulating layer on the stack, and forming a channel hole by selectively etching the first insulating layer, the channel hole exposing the gap-filling pattern formed inside the plurality of preliminary channel holes; extending the via hole into the stack by removing the gap-fill pattern exposed by the via hole; forming a cell plug inside the channel hole; forming a second insulating layer on the cell plug and the first insulating layer, and forming a slit hole exposing the gap-filling pattern formed inside the plurality of preliminary slit holes by selectively etching the second insulating layer and the first insulating layer; forming a recessed region by removing the gap filling pattern exposed through the slit hole and etching the plurality of interlayer insulating layers exposed through the sidewalls of the slit hole by a predetermined thickness, the recessed regions of adjacent slit holes contacting each other to be connected to each other; After removing the plurality of sacrificial layers exposed through the slit holes, forming a plurality of conductive layers in spaces where the plurality of sacrificial layers are removed; forming a groove by removing the plurality of conductive layers remaining inside the slit holes, wherein the slit holes are connected to each other; as well as The slits are formed by filling the trenches with an insulating material.

15. The method of claim 14, wherein forming the plurality of preliminary channel holes and the plurality of preliminary slit holes comprises: The plurality of preliminary slit holes are formed to be arranged in a zigzag pattern or a wave pattern. The method of claim 14 , wherein the gap-fill pattern comprises carbon.

17. The method according to claim 14, further comprising: Before forming the first insulating layer, after etching an upper end of the gap-filling pattern to a predetermined thickness, an auxiliary pattern is formed in a region where the gap-filling pattern is etched. 18 . The method of claim 17 , wherein the auxiliary pattern further comprises a tungsten pattern and a titanium nitride layer surrounding a surface of the tungsten pattern. 19 . The method according to claim 14 , wherein the trench extends in a word line extending direction and has a wave pattern or a zigzag pattern along the word line extending direction in which the word line extends.

20. The method of claim 14, further comprising: An additional slit is formed that passes through the second insulating layer, the first insulating layer, and at least one conductive layer disposed on an uppermost portion of the plurality of conductive layers.

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