Non-volatile memory with lower current program verification

Abstract

The memory system programs memory cells connected to selected word lines by applying program doses and performing a program verify between the doses. An efficient and low current program verify operation includes, while scanning a result of a previous program verify operation, ramping up a voltage on a select line for a next program verify operation without waiting for completion of the scan, and after a step signal without waiting for completion of the scan, ramping up the voltage on the select line for the next program verify operation. The voltage on the unselected word line is ramped up for the next program verify operation (such that the voltage applied to the unselected word line is ramped up).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 18 / 357,489, filed in the U.S. Patent and Trademark Office on July 24, 2023, entitled “NON-VOLATILE MEMORY WITH LOWERCURRENT PROGRAM-VERIFY,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 419,210, filed on October 25, 2022. Background Art

[0003] The present disclosure relates to non-volatile storage devices.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memories or volatile memories. Non-volatile memories allow information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). An example of non-volatile memory is flash memory (e.g., NAND-type flash memory and NOR-type flash memory).

[0005] Many electronic devices that use nonvolatile memory are mobile devices that rely on battery power. Therefore, in order to use the battery most efficiently, it is advantageous for the nonvolatile memory to operate at lower power (including using lower current). Using lower current also helps prevent the electronic device from overheating. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0008] Figure 2A is a block diagram of one embodiment of a memory die.

[0009] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0011] Figure 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0012] Figure 4A is a block diagram of one embodiment of a memory structure having two planes.

[0013] Figure 4B Depicted is a top view of a portion of one embodiment of a block of memory cells.

[0014] Figure 4C A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0015] Figure 4D A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0016] Figure 4E is a cross-sectional view of one embodiment of a vertical column of memory cells.

[0017] Figure 4F is a schematic diagram of multiple NAND strings in multiple regions of the same block.

[0018] Figure 5A The threshold voltage distribution is depicted.

[0019] Figure 5B The threshold voltage distribution is depicted.

[0020] Figure 5C The threshold voltage distribution is depicted.

[0021] Figure 5D The threshold voltage distribution is depicted.

[0022] Figure 6 is a flow chart describing one embodiment of a process for programming non-volatile memory.

[0023] Fig. 7A Depicted are the voltage signals applied to a selected word line during programming.

[0024] Figure 7B Depicted are two program voltage pulses applied to a selected word line during programming and a verify voltage pulse between the two program voltage pulses.

[0025] Figure 7C Depicted are two program voltage pulses applied to a selected word line during programming and a verify voltage pulse between the two program voltage pulses.

[0026] Fig. 8A It is a graph that describes the programming process.

[0027] Figure 8B It is a graph that describes the programming process.

[0028] Fig. 9 is a block diagram describing one embodiment of a system for supplying voltage to a word line.

[0029] Fig.10 is a timing diagram depicting the voltages applied to a NAND string during the program verify process.

[0030] Fig.11 Included are graphs of word line voltage and system current.

[0031] Fig.12 Included are graphs of word line voltage and system current.

[0032] Fig.13 Includes graphs of word line voltage and select line voltage.

[0033] Fig.14 is a flow chart describing one embodiment of a programming process including performing program verification.

[0034] Fig.15 is a flow chart describing one embodiment of a programming process including performing program verification.

[0035] Fig.16 is a flow chart describing one embodiment of a programming process including performing program verification.

[0036] Fig.17 is a flow chart describing one embodiment of a process for testing higher verify levels of data states. DETAILED DESCRIPTION

[0037] The memory system programs the memory cells connected to the selected word line by applying a programming dose and performing a program verification between doses. The efficient and low current program verification operation includes: while scanning the results of the previous program verification operation, ramping up the voltage on the selection line for the next program verification operation without waiting for the scan to be completed, and ramping up the voltage on the unselected word line for the next program verification operation after a step signal without waiting for the scan to be completed (so that the voltage applied to the unselected word line is gradually increased).

[0038] Figure 11 is a block diagram of one embodiment of a storage system 100 that implements the technology of the present invention described herein. In one embodiment, the storage system 100 is a solid state drive ("SSD"). The storage system 100 may also be a memory card, a USB drive, or other types of storage systems. The technology of the present invention is not limited to any one type of memory system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but is connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0039] Figure 1 The components of the memory system 100 depicted in FIG. 1 are electronic circuits. The memory system 100 includes a memory controller 120 connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores logic in a physical address translation table ("L2P table").

[0040] The memory controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with NOC 154. DRAM controller 164 is used to operate and communicate with local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, local high-speed volatile memory 140 may be SRAM or another type of volatile memory.

[0041] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0042] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory dies as desired. In order to implement such a system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An example implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0043] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory dies.

[0044] In one embodiment, non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including non-volatile memory 130. Each of the one or more memory dies of non-volatile memory 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are circuits. The memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of the memory array 202 include individual word line layers organized into rows, and individual bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output end 208 of which is connected to the corresponding word line of the memory array 202. The row control circuit 220 receives a set of M row address signals and one or more various control signals from the system control logic circuit 260, and may generally include circuits such as a row decoder 222, an array terminal driver 224, and a block selection circuit 226 for both read operations and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210, which includes a sense amplifier 230, the input end / output end 206 of which is connected to the corresponding bit line of the memory array 202. Although only a single block is shown for array 202, the memory die may include multiple arrays that may be accessed individually. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260, and may generally include circuits such as column decoders 212, array terminal receivers or driver circuits 214, block select circuits 216, and read / write circuits and I / O multiplexers.

[0045] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electronic circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include a charge pump and regulator circuit for generating a regulated voltage. The system control logic 262 includes a storage device 366 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory array 202.

[0046] Commands and data are transmitted between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0047] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on different dies.

[0048] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0049] In another embodiment, the memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR type flash memory) may also be used.

[0050] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0051] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0052] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0053] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be inhibited by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or another wave. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0054] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0055] Figure 2A The components of the invention can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuits, which include Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuits. This can place quite severe constraints on these elements of the peripheral circuits. For example, the need to fit sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 260, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuits.

[0056] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, while the peripheral circuits are often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic component 260 often employ PMOS devices. The processing operations used to manufacture a CMOS die will differ in many ways from processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0057] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 can be separated into separately formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Then some or all of the circuits in the peripheral circuits (even including elements such as decoders and sense amplifiers) can be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are confined to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily combined can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to the peripheral components on the other die. For example, although the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0058] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 may be used to implement the non-volatile memory 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0059] Figure 2B An example of peripheral circuitry is shown, including control circuits formed in a peripheral circuit or control die 211 that are coupled to a memory structure 202 formed in a memory die 201. Common components are shown in a similar manner to Figure 2ASystem control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory die 201. In some embodiments, some circuits in system control logic 260 are located on memory die 201.

[0060] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by conventional processes (e.g., CMOS processes), so that adding elements and functions more commonly found on the memory controller 120, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may also be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, while removing such circuits from a die (such as the memory 2 die 201) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as the control die 211) may not require many additional process steps. Since some or all of the control circuits 260, 210, 220 are implemented using CMOS technology, the control die 211 may also be referred to as a CMOS die.

[0061] Figure 2B Column control circuitry 210 including sense amplifier 230 on control die 211 is shown coupled to memory structure 202 on memory die 201 via electrical path 206. For example, electrical path 206 may provide electrical connections between column decoder 212, driver circuit 214, block selector 216, and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical path 206 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220 (including row decoder 222, array driver 224, and block selector 226) is coupled to memory structure 202 via electrical path 208. Each of the electrical paths 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory die 201 .

[0062] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and / or other similar functional circuitry. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other type of circuitry.

[0063] In some embodiments, there is more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A Depicted is a side view of one embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory dies 201) stacked on a substrate 271. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0064] Each control die 211 is attached (e.g., bonded) to at least one of the memory dies 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in an embodiment, the material can be Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0065] The integrated memory components 207 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., formed to Figure 3A ).

[0066] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0067] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory component 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0068] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are far more than three memory dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 can be bonded to two or more memory dies 201.

[0069] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 207 in FIG. 2 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201 . Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211 .

[0070] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0071] As briefly discussed above, the control die 211 and the memory die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In the embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term can also be applied to the case where the bonding pads are formed by materials other than copper.

[0072] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size and spacing of the bonding pad can be further reduced. The film layer is disposed around the bonding pad. When the die are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technique may be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads may be approximately 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding techniques may be used to provide bonding pads with smaller (or larger) sizes and spacings.

[0073] Some embodiments may include a film on the surface of the tube core 201, 211. If such a film is not initially provided, the space between the tube cores can be filled with epoxy or other resins or polymers at the bottom. The bottom fill material can be applied as a liquid and then hardened into a solid layer. This bottom filling step protects the electrical connection between the tube core 201, 211 and further fixes the tube core together. Various materials can be used as the bottom fill material, but in an embodiment, the bottom fill material can be a Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0074] Figure 4 is a perspective view of a portion of an example embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL, which are located above a stack 401 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into four or five (or a different number of) regions by isolation regions IR. Figure 4 An isolation region IR is shown separating the two regions. A source line layer SL is located below the alternating dielectric layer and word line layer. A memory hole is formed in the stack of alternating dielectric layers and conductive layers. For example, the memory hole is marked as MH. Note that Figure 4 , the dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric layers and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. Thus, non-volatile memory cells are arranged in the memory holes. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0075] Figure 4A is a block diagram illustrating an example organization of a memory structure 202 that is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, a different number of blocks and planes may also be used. In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In other embodiments, a block may be divided into sub-blocks, and a sub-block may be the unit of erase. Memory cells may also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block. Although Figure 4A Two planes 402 / 404 are shown, but more or less than two planes may be implemented. In some embodiments, the memory structure 202 includes eight planes.

[0076] FIG. 4B to FIG. 4 G depicts an example three-dimensional ("3D") NAND structure corresponding to Figure 4 structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4B is a block diagram depicting a top view of a portion 406 of block 2 of plane 402. Figure 4B It can be seen that Figure 4B The blocks depicted in FIG. extend in the direction of 432. In one embodiment, the memory array has many layers; however, Figure 4B Only the top layer is shown.

[0077] Figure 4B A plurality of circles representing memory holes (also referred to as vertical columns) are depicted. Each of the memory holes / vertical columns includes a plurality of select transistors (also referred to as select gates / selection gates) and a plurality of memory cells. In one embodiment, each memory hole / vertical column implements a NAND string. For example, Figure 4B A subset of the memory holes / vertical columns / NAND strings 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0078] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the memory holes / vertical columns of the block. Each of the circles representing memory holes / vertical columns has an "x" to indicate that it is connected to a bit line. For example, bit line 411 is connected to memory holes / vertical columns 436, 446, 456, 466, and 476.

[0079] Figure 4B The block depicted in FIG. 4 includes a set of isolation regions 482, 484, 486, and 488 formed of SiO2; however, other dielectric materials may also be used. Isolation regions 482, 484, 486, and 488 are used to divide the top layer of the block into five regions; for example, Figure 4B The top layer depicted in FIG is divided into regions 430, 440, 450, 460, and 470. In one embodiment, the isolation region divides only the layer used to implement the select gate so that the NAND strings in different regions can be independently selected. In one example implementation, the bit line is connected to one memory hole / vertical column / NAND string in each of the regions 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to five rows in each block. In one embodiment, all five memory holes / vertical columns / NAND strings connected to a common bit line are connected to the same word line group; therefore, the system uses the drain side select line to select one (or another subset) of the five to be performed memory operations (programming, verification, reading, and / or erasing).

[0080] Figure 4BAlso shown is a line interconnect LI, which is a metal connection from above the memory array to the source line SL. Line interconnect LI is located adjacent to regions 430 and 470.

[0081] although Figure 4B Each region 430, 440, 450, 460, and 470 is shown in a block with four rows of memory holes / vertical columns, and five regions have twenty-four rows of memory holes / vertical columns, but these exact numbers are example implementations. Other embodiments may include more or fewer regions per block, more or fewer rows of memory holes / vertical columns per region, and more or fewer rows of vertical columns per block. Figure 4B It is also shown that the memory holes / vertical columns are staggered. In other embodiments, different staggering patterns can be used. In some embodiments, the memory holes / vertical columns are not staggered.

[0082] Figure 4C A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the memory holes / vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Figure 4C The structure includes three drain side selection layers SGD0, SGD1 and SGD2; three source side selection layers SGS0, SGS1 and SGS2; three drain side GIDL generation transistor layers SGDT0, SGDT1 and SGDT2; three source side GIDL generation transistor layers SGSB0, SGSB1 and SGSB2; four drain side dummy word line layers DD0, DD1, DD2 and DD3; four source side dummy word line layers DS0, DS1, DS2 and DS3; dummy word line layers DU and DL; one hundred and sixty-two word line layers WL0-WL161 for connecting to data memory cells, and a dielectric layer DL. Other embodiments may implement more or less than the above embodiments for Figure 4C In one embodiment, SGD0, SGD1, and SGD2 are connected together; and SGS0, SGS1, and SGS2 are connected together. In other embodiments, a smaller or smaller number of SGDs (more or less than three) are connected together, and a larger or smaller number of SGSs (more or less than three) are connected together.

[0083] In one embodiment, erasing a memory cell is performed using gate induced drain leakage (GIDL), which includes generating charge carriers at a GIDL generation transistor such that the carriers are injected into a charge trapping layer of a NAND string to change a threshold voltage of the memory cell. Figure 4CThree GIDL generating transistors at each end of the NAND string are shown; however, in other embodiments, there are more or less than three. Embodiments that use GIDL at both sides of the NAND string may have GIDL generating transistors at both sides. Embodiments that use GIDL only at the drain side of the NAND string may have GIDL generating transistors only at the drain side. Embodiments that use GIDL only at the source side of the NAND string may have GIDL generating transistors only at the source side.

[0084] Figure 4C Three GIDL generating transistors at each end of the NAND string are shown. Charge carriers are likely to be generated by the GIDL at only one of the three GIDL generating transistors at each end of the NAND string. Based on process differences during manufacturing, one of the three GIDL generating transistors at one end of the NAND string is likely to be best suited for the GIDL. For example, the GIDL generating transistor has a mutant pn junction to generate charge carriers for the GIDL, and during manufacturing, phosphorus diffusion is performed at the polysilicon channel of the GIDL generating transistor. In some cases, the GIDL generating transistor with the shallowest phosphorus diffusion is the GIDL generating transistor that generates charge carriers during erase. However, in some embodiments, charge carriers may be generated by the GIDL at multiple GIDL generating transistors at a particular side of the NAND string.

[0085] Memory holes / vertical columns 472 and 474 are depicted as protruding through the drain side selection layer, source side selection layer, dummy word line layer, GIDL generation transistor layer, and word line layer. In one embodiment, each memory hole / vertical column includes a vertical NAND string. Below the memory holes / vertical columns and the layers listed below is a substrate 453, an insulating film 454 on the substrate, and a source line SL. The NAND string of the memory hole / vertical column 472 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B Consistent, Figure 4C Vertical memory wells / columns 472 connected to bit lines 414 via connectors 417 are shown.

[0086] For ease of reference, the drain side selection layer; the source side selection layer, the dummy word line layer, the GIDL generation transistor layer, and the data word line layer are collectively referred to as the conductive layer. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten), metal silicides, such as nickel silicide, tungsten silicide, aluminum silicide, or combinations thereof. In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers is a dielectric layer DL. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0087] The non-volatile memory cells are formed along memory holes / vertical columns that extend through alternating conductive layers and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings. Word line layers WL0 to W161 are connected to memory cells (also referred to as data memory cells). Dummy word line layers are connected to dummy memory cells. Dummy memory cells do not store host data and are not eligible to store host data (data provided from the host, such as data from a host user), while data memory cells are eligible to store host data. In some embodiments, data memory cells and dummy memory cells may have the same structure. Drain side selection layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect the NAND string to the bit line. Source side selection layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect the NAND string to the source line SL.

[0088] Figure 4C The memory array is shown implemented as two layered architectures, where the layers are separated by a bonding region. In one embodiment, etching so many word line layers intermixed with dielectric layers is expensive and / or challenging. To alleviate this burden, one embodiment includes laying a first stack of word line layers (e.g., WL0 to WL80) alternating with dielectric layers, laying a bonding region, and laying a second stack of word line layers (e.g., WL81 to WL161) alternating with dielectric layers. The bonding region is positioned between the first stack and the second stack. In one embodiment, the bonding region is made of the same material as the word line layer. In other embodiments, there may be no bonding region or there may be multiple bonding regions.

[0089] Figure 4D A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the memory holes / vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4D Shown with Figure 4CSame alternating conductive and dielectric layers. Figure 4D Also shown is an isolation region 482. Isolation regions 482, 484, 486, and 488 occupy space that was already used for a portion of the memory holes / vertical columns / NAND strings. For example, isolation region 482 occupies space that was already used for a portion of the memory holes / vertical columns 434. More specifically, a portion of the vertical columns 434 (e.g., half of the diameter) has been removed in layers SGDT0, SGDT1, SGDT2, SGD0, SGD1, SGD2, DD0, DD1, and DD2 to accommodate isolation region 482. Therefore, while most of the vertical columns 434 are cylindrical (having a circular cross-section), portions of the vertical columns 434 in layers SGDT0, SGDT1, SGDT2, SGD0, SGD1, SGD2, DD0, DD1, and DD2 have a semicircular cross-section. In one embodiment, after forming a stack of alternating conductive and dielectric layers, the stack is etched to create space for the isolation regions, and the space is subsequently filled with SiO2.

[0090] Figure 4E Depicted is a portion of a memory hole / vertical column 472 Figure 4C 429 . In one embodiment, the memory holes / vertical columns are circular; however, in other embodiments, other shapes may be used. In one embodiment, the memory holes / vertical columns 472 include an inner core layer 490 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. Note that the channel 491 is connected to the bit line and the source line. Surrounding the channel 491 is a tunneling dielectric 492. In one embodiment, the tunneling dielectric 492 has an ONO structure. Surrounding the tunneling dielectric 492 is a charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0091] Figure 4EA dielectric layer DL is depicted, as well as word line layers WL160, WL159, WL158, WL157, and WL156. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel to and adjacent to the charge trapping layer 493. The physical interaction of the word line layers with the vertical columns forms a memory cell. Thus, in one embodiment, a memory cell includes a channel 491, a tunneling dielectric 492, a charge trapping layer 493, a blocking oxide layer 498, an aluminum oxide layer 497, and a word line region 496. For example, word line layer WL160 and a portion of memory hole / vertical column 472 constitute memory cell MC1. Word line layer WL159 and a portion of memory hole / vertical column 472 constitute memory cell MC2. Word line layer WL158 and a portion of memory hole / vertical column 472 constitute memory cell MC3. Word line layer WL157 and a portion of memory hole / vertical column 472 constitute memory cell MC4. Word line layer WL156 and a portion of memory hole / vertical column 472 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still still be storage cells.

[0092] When programming a memory cell, electrons are stored in a portion of the charge trapping layer 493 that is associated with the memory cell (e.g., in the memory cell). In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0093] Figure 4F yes Figures 4 to 4E Schematic diagram of a portion of memory array 202 is depicted in FIG. Figure 4F Physical data word lines WL0-WL161 are shown extending across the entire block. Figure 4F The structure corresponds to Figure 4A The portion 406 in block 2 includes bit lines 411. Within this block, in one embodiment, each bit line is connected to five NAND strings. Thus, Figure 4FThe bit lines connected to NAND string NS0 (which corresponds to memory hole / vertical column 436), NAND string NS1 (which corresponds to memory hole / vertical column 446), NAND string NS2 (which corresponds to vertical column 456), NAND string NS3 (which corresponds to memory hole / vertical column 466), and NAND string NS4 (which corresponds to memory hole / vertical column 476) are shown. As described above, in one embodiment, for each region separated by isolation regions (482, 484, 486, and 486), SGD0, SGD1, and SGD2 are connected together to operate as a logic select gate to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4. SGS0, SGS1, and SGS2 are also connected together to operate as a logic select gate in Figure 4F 4. The block is operated by a single logic select gate denoted as SGS in FIG. Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4 are isolated from each other due to the isolation regions, the data word lines WL0-WL161 of each region are connected together. Therefore, the data word lines WL0-WL161 are connected to the NAND strings (and memory cells) of each region (430, 440, 450, 460, 470) of the block.

[0094] Isolation regions (482, 484, 486, and 487) are used to allow individual control of regions 430, 440, 450, 460, 470. The first region corresponds to those vertical NAND strings controlled by SGD-s0. The second region corresponds to those vertical NAND strings controlled by SGD-s1. The third region corresponds to those vertical NAND strings controlled by SGD-s2. The fourth region corresponds to those vertical NAND strings controlled by SGD-s3. The fifth region corresponds to those vertical NAND strings controlled by SGD-s4.

[0095] Figure 4F Only the NAND strings connected to bit line 411 are shown. However, a complete schematic diagram of the block would show each bit line and the five vertical NAND strings (in separate areas) connected to each bit line.

[0096] Although Figures 4 to 4F An example memory of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0097] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 5Ais a graph of threshold voltage versus number of memory cells and illustrates an example threshold voltage distribution for a memory array when each memory cell stores one bit of data per memory cell. A memory cell storing one bit of data per memory cell is referred to as a single-level cell ("SLC"). Data stored in an SLC memory cell is referred to as SLC data; therefore, SLC data includes one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Thus, memory cells having threshold voltages in threshold voltage distribution E are in an erased data state (e.g., they are erased). Thus, memory cells having threshold voltages in threshold voltage distribution P are in a programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data "1" and programmed memory cells store data "0". Figure 5A Depicted is a read reference voltage Vr. By testing (eg, performing one or more sensing operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A Also depicted is a verify reference voltage Vv. In some implementations, when programming memory cells to data state P, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv.

[0098] FIG. 5B to FIG. 5D Example threshold voltage distributions for a memory array when each memory cell stores multiple bits of data per memory cell are illustrated. Memory cells that store multiple bits of data per memory cell are referred to as multi-level cells ("MLC"). Data stored in an MLC memory cell is referred to as MLC data; therefore, MLC data includes multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. Figure 5B In an example embodiment, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three bits of data, four bits of data, or five bits of data per memory cell).

[0099] Figure 5B A first threshold voltage distribution E for erasing memory cells is shown. Also depicted are three threshold voltage distributions A, B, and C for programming memory cells. In one embodiment, the threshold voltages in distribution E are negative, and the threshold voltages in distributions A, B, and C are positive. Figure 5BEach different threshold voltage distribution corresponds to a predetermined value for a set of data bits. In one embodiment, each of the two bits of data stored in the memory cell is in a different logical page, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all data bits stored in the memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. Table 1 provides an example encoding scheme.

[0100] Table 1

[0101] E A B C LP 1 0 0 1 UP 1 1 0 0

[0102] In one implementation, referred to as full sequence programming, the Figure 6 The process of programming memory cells directly from erased data state E to any of programmed data states A, B, or C (discussed below) is used. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program the memory cells directly to data states A, B, and / or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrows represent full sequence programming. In some embodiments, data states AC may overlap, where the memory controller 120 (or control die 211) relies on error correction to identify the correct data being stored.

[0103] Figure 5C Example threshold voltage distributions for memory cells are depicted, where each memory cell stores three bits of data per memory cell (which is another example of MLC data). Figure 5CEight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells, and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. In one embodiment, the data value is assigned to the threshold voltage range using Gray code distribution, so that if the threshold voltage of the memory is incorrectly shifted to its adjacent physical state, only one bit will be affected. Table 2 provides an example of a coding scheme for an embodiment in which each bit of the three bits of data stored in the memory cell is in different logical pages, and the logical page is called a lower page (LP), a middle page (MP), and an upper page (UP).

[0104] Table 2

[0105] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0106] Figure 5C Seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are shown for reading data from a memory cell. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (i.e., A, B, C, D, ...) that the memory cell is in.

[0107] Figure 5C Also shown are seven verification reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether these memory cells have a threshold voltage greater than or equal to VvA. When programming memory cells to data state B, the system will test whether these memory cells have a threshold voltage greater than or equal to VvB. When programming memory cells to data state C, the system will determine whether these memory cells have a threshold voltage greater than or equal to VvC. When programming memory cells to data state D, the system will test whether these memory cells have a threshold voltage greater than or equal to VvD. When programming memory cells to data state E, the system will test whether these memory cells have a threshold voltage greater than or equal to VvE. When programming memory cells to data state F, the system will test whether these memory cells have a threshold voltage greater than or equal to VvF. When programming memory cells to data state G, the system will test whether these memory cells have a threshold voltage greater than or equal to VvG. Figure 5CAlso shown is Vev, which is a verify voltage used to test whether the memory cells have been properly erased.

[0108] In an implementation utilizing full sequence programming, the Figure 6 The process of programming memory cells from erased data state Er directly to any of programmed data states AG (discussed below) can be used. For example, a group of memory cells to be programmed can be first erased so that all memory cells in the group are in erased data state Er. Then, the programming process is used to program the memory cells directly to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and / or from data state Er to data state C, and so on. Figure 5C The arrows represent full sequence programming. In some embodiments, data states AG may overlap, where the control die 211 and / or memory controller 120 rely on error correction to identify the correct data being stored. Note that in some embodiments, the system may use a multi-pass programming process known in the art instead of using full sequence programming.

[0109] Generally speaking, during a verify operation and a read operation, a selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (eg, see Figure 5C read comparison voltages / levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or verification operations (e.g., see Figure 5C The verification target voltage / level VvA, VvB, VvC, VvD, VvE, VvF and VvG) is specified in order to determine whether the threshold voltage of the associated memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also called bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0110] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has been discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other reading and verification techniques known in the art can also be used.

[0111] Figure 5D Depicted is a threshold voltage distribution when each memory cell stores four bits of data, which is another example of MLC data. Figure 5D It is shown that there may be some overlap between the threshold voltage distributions (data states) S0 to S15. This overlap may occur due to factors such as memory cells losing charge (and therefore the threshold voltage drops). Program disturbances may unintentionally increase the threshold voltage of a memory cell. Similarly, read disturbances may unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distribution may change. Such changes may increase the bit error rate, thereby increasing the decoding time or even making decoding impossible. Changing the read reference voltage may help mitigate such effects. Using ECC during the read process may repair errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of the memory cell populations storing four bits of data per memory cell do not overlap and are separated from each other. Figure 5D The threshold voltage distribution will include a read reference voltage and a verify reference voltage, as discussed above.

[0112] When four bits are used per memory cell, the memory can be programmed using the full sequence programming discussed above or a multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted for the cell. Table 3 provides an example of an encoding scheme for an embodiment in which each bit of the four bits of data stored in the memory cell is in a different logical page, which is referred to as the lower page (LP), the middle page (MP), the upper page (UP), and the top page (TP).

[0113] Table 3

[0114] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0115] Figure 62 is a flow chart describing one embodiment of a process for programming memory cells. For the purposes of this document, the term programming is synonymous with writing. In one example embodiment, memory array 202 is programmed using one or more of the control circuits discussed above (e.g., system control logic 260, column control circuit 210, row control circuit 220). Figure 6 In one example embodiment, Figure 6 The process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory die 201. The process includes multiple cycles, each cycle including a programming phase and a verification phase. Figure 6 process to achieve full sequence programming and other programming schemes including multi-level programming. When implementing multi-level programming, Figure 6 The process is used to implement any / each stage of the multi-level programming process.

[0116] Typically, the programming voltage applied to the control gate (via the selected data word line) during a programming operation is applied as a series of programming pulses (e.g., voltage pulses). Between the programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 6In step 602, the programming voltage signal (Vpgm) is initialized to a starting value (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and all connected to the same word line (the selected word line). There may be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. In addition, when the memory cells reach their expected target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to prohibit programming, and these strings include memory cells that are connected to the selected word line to be prohibited from programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not enough to cause programming. To help boost, in step 604, the control die will precharge the channel of the NAND string including the memory cells connected to the selected word line that will be prohibited from programming. In step 606, the NAND strings including memory cells connected to the selected word lines to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as "unselected NAND strings". In one embodiment, the unselected word lines receive one or more boost voltages (e.g., about 7 volts to 11 volts) to perform the boosting scheme. The program inhibit voltage is applied to the bit lines coupling the unselected NAND strings.

[0117] In step 608, a programming voltage pulse of a programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If the memory cell on the NAND string should be programmed, the corresponding bit line is biased at a programming enable voltage. In step 608, a programming pulse is applied simultaneously to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed simultaneously (unless they are prohibited from programming). That is, they are programmed at the same time or during overlapping times (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltages changed at the same time unless they are prohibited from programming.

[0118] In step 610, program verification is performed, which includes testing whether the memory cell being programmed has successfully reached its target data state. The memory cell that has reached its target state is locked out and cannot be further programmed by the control die. Step 610 includes performing verification of programming by sensing at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verification reference voltage. In step 610, the memory cell can be locked out after the memory cell has been verified (by testing of Vt) that the memory cell has reached its target state.

[0119] In one embodiment of step 610, smart verification techniques are used so that the system verifies only a subset of data states during a programming cycle (steps 604-628). For example, the first programming cycle includes verification of data state A (see Figure 5C ), depending on the result of the verification operation, the second programming loop can perform verification on data states A and B, depending on the result of the verification operation, the third programming loop can perform verification on data states B and C, and so on.

[0120] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution is counted. That is, the number of memory cells that have so far been unable to reach their target state is counted. This counting may be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0121] In step 617, the system determines whether the verification operation in the most recent execution of step 610 included a verification of the last data state (e.g., Figure 5CThe data state G) of the memory cell is verified. If so, then in step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the reading process of the page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can be stopped and a "pass" state is reported in step 614. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the reading process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the reading process to allow for future / additional errors. When programming less than all memory cells of a page, the predetermined limit can be a portion (proportional or not) of the number of bits that can be corrected by ECC during the reading process of the page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0122] If it is determined in step 617 that the verify operation in the most recent execution of step 610 did not include verifying the last data state, or it is determined in step 618 that the number of failed memory cells is not less than a predetermined limit, then in step 619, the data state to be verified in the next execution of step 610 (in the next programming cycle) is adjusted according to the smart verification scheme discussed above. In step 620, the program counter PC is checked against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the program counter PC is not less than the programming limit value PL, then the programming process is considered to have failed and a "failed" status is reported in step 624. If the program counter PC is less than the programming limit value PL, then the process continues at step 626, during which the program counter PC is incremented by 1 and the program voltage signal Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is a step size ΔVpgm (e.g., a step size of 0.1 volts to 1.0 volts) greater than the previous pulse. After step 626, the process continues at step 604 and another programming pulse is applied (control die) to the selected word line, causing execution Figure 6 Another programming cycle of the programming process (steps 604 to 626).

[0123] In one embodiment, the memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from Figure 5A The state P changes to state E, from Figure 5B The state A / B / C changes to state E, from Figure 5C Change from state A to state G to state Er or from Figure 5D States S1 to S15 are changed to state S0.

[0124] One technique for erasing memory cells in some memory devices is to bias the p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the memory cell. This is referred to herein as p-well erase.

[0125] Another method of erasing a memory cell is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. This is referred to herein as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of a memory cell.

[0126] In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a GIDL generating transistor (e.g., a transistor connected to SGDT0, SGDT1, SGDT2, SGSB0, SGSB1, and SGSB2). In some embodiments, a select gate (e.g., SGD or SGS) may be used as a GIDL generating transistor. The drain-to-gate voltage of the transistor that generates the GIDL current is referred to herein as the GIDL voltage. When the GIDL generating transistor drain voltage is significantly higher than the GIDL generating transistor control gate voltage, a GIDL current may be generated. The GIDL current is the result of carrier generation, i.e., electron-hole pair generation and / or trap-assisted generation due to band-band tunneling. In one embodiment, the GIDL current may cause one type of carrier (also referred to as charge carrier) (e.g., hole) to move primarily into the NAND channel, thereby increasing or changing the potential of the channel. Another type of carrier (e.g., electron) is extracted from the channel by an electric field in the direction of the bit line or in the direction of the source line. During erase, holes can tunnel from the channel to the charge storage region of the memory cell (eg, to the charge trapping layer 493) and recombine with electrons therein to lower the threshold voltage of the memory cell.

[0127] A GIDL current may be generated at either end of a NAND string. A first GIDL voltage may be generated between two terminals of a GIDL generating transistor (e.g., connected to SGDT0, SGDT1, SGDT2) connected to or near a bit line to generate a transistor to generate a first GIDL current. A second GIDL voltage may be generated between two terminals of a GIDL generating transistor (e.g., SGSB0, SGSB1, and SGSB2) connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current at only one end of a NAND string is referred to as single-sided GIDL erasing. Erasing based on GIDL current at both ends of a NAND string is referred to as double-sided GIDL erasing. The techniques described herein may be used with single-sided GIDL erasing and double-sided GIDL erasing.

[0128] Fig. 7A The programming signal Vpgm is depicted as a series of programming voltage pulses, so that Figure 6 A pulse of the programming signal Vpgm is applied each time step 608 is performed. These programming voltage pulses are an example of a programming dose applied to the plurality of non-volatile memory cells being programmed. In one embodiment, the programming voltage pulses increase in voltage magnitude by a step size ΔVpgm from pulse to pulse. In some embodiments, ΔVpgm may be changed during the programming process. Figure 6 As described above, the system performs program verification between programming doses (between or after programming voltage pulses), such as Figure 7B and Figure 7C shown. Figure 7B An example of performing program verification on a verification level is illustrated, which depicts Fig. 7A 702 and 704. Between the programming voltage pulses 702 and 704 is a verify voltage pulse 710. In one embodiment, the verify voltage pulse 710 has a magnitude of any one of the verify reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG (see Figure 5C ), and represents a system that performs program verification (step 610) between programming doses (consecutive iterations of step 608). In other embodiments, verify voltage pulse 710 has a magnitude that is intermediate voltages for data states, as will be discussed below. In some embodiments, between programming voltage pulses, the system will perform program verification on all data states, while in other embodiments, the system will perform program verification on one data state or a subset of data states at a time.

[0129] Figure 7C An example of performing program verification on two verification levels is illustrated, which depicts Fig. 7ATwo of the programming voltage pulses 702 and 704 are provided. Between the programming voltage pulses 702 and 704 are verify voltage pulses 710 and 712. In one embodiment, the verify voltage pulses 710 and 712 are for the same data state, while in other embodiments, the verify voltage pulses 710 and 712 are for different data states.

[0130] One means of verifying programming (ie, program-verify) is to test conduction at specific compare points (eg, Figure 5C The memory cells verified as fully programmed are locked, for example, by raising the bit line voltage from 0 to Vdd (e.g., 1v to 3v) to stop the programming process of those memory cells. For example, Fig. 8A The threshold voltage (Vth) versus time and the bit line voltage (Vbl) versus time are plotted. Fig. 7A When the programming voltage Vpgm is increased, the threshold voltage of the memory cell increases. When the threshold voltage of the memory cell reaches the verification reference voltage Vvx (eg, Figure 5C When a verification reference voltage VvA, VvB, VvC, VvD, VvE, VvF, and VvG is used as the verification reference voltage, the bit line voltage is raised to Vinhibit (e.g., Vdd).

[0131] When Fig. 8A When programming and verifying are performed as shown, there is a tradeoff between programming speed and programming accuracy. Programming accuracy is related to the threshold voltage distribution of the programmed memory cells after the programming process. The tighter the threshold voltage distribution, the easier it is to clearly read the memory cells. For multi-level memory cells storing multi-bit data, the need for tight threshold voltage distribution is even more important because the reading process needs to clearly distinguish different threshold voltage distributions (e.g., for data states Er to G). In order to obtain a tight threshold voltage distribution, a smaller step size (e.g., a smaller ΔVpgm) can be used for the programming voltage Vpgm. However, using a smaller step size slows down the programming process.

[0132] Improvements to the programming process Figure 8B As shown in , this can be called a coarse / fine programming process. Figure 8B The process will Fig. 7AA programming voltage signal Vpgm is applied to the control gate of the memory cell to be programmed. Between programming voltage pulses, a programming verification operation is performed. If the threshold voltage of the memory cell being programmed is lower than the intermediate verification reference voltage Vv_low (lower verification voltage), programming of the memory cell continues, with the bit line voltage remaining low (e.g., 0 volts). This is the coarse stage of the coarse / fine programming process because the memory cell is programmed faster. If the threshold voltage of the memory cell being programmed is higher than the intermediate verification reference voltage Vv_low and lower than the final verification reference voltage Vv_high (higher verification voltage), an intermediate bit line voltage (e.g., 0.5 volts to 1.0 volts) is applied. Due to the intermediate bit line voltage, the channel voltage of the memory cell will increase, and the programming of the memory cell will slow down because the shift in the threshold voltage due to each programming voltage pulse will decrease. This is the fine stage of the coarse / fine programming process. For multiple programming voltage pulses, the bit line will remain at the intermediate bit line voltage until the threshold voltage of the memory cell reaches the final verification reference voltage Vv_high. When the threshold voltage of the memory cell reaches the final verification reference voltage Vv_high, the bit line will be raised to inhibit further programming (e.g., by raising the bit line voltage to Vinhibit (e.g., Vdd, which may be 1 volt to 3 volts). Note that the final verification reference voltage Vv_high corresponds to the verification reference voltage of the data state to which the memory cell is being programmed (e.g., Figure 5C In one embodiment, the intermediate verification reference voltage Vv_low for a data state is 25 volts lower than the final verification reference voltage Vv_high for the data state. Other separation values ​​between Vv_low and Vv_high for the data state may also be used. In another embodiment, when the threshold voltage of the memory cell being programmed is above Vv_low and below Vv_high, the system may reduce the size of Vpgm to slow programming during the fine phase, rather than raising the bit line to an intermediate bit line voltage.

[0133] Replay Figure 7C , the verify voltage pulse 710 may be set to Vv_low, and the verify voltage pulse 712 may be set to Vv_high. Thus, the memory system performs two sensing operations: one sensing operation for Vv_low (pulse 710) and one sensing operation for Vv_high (pulse 712). After each sensing operation, the memory system performs a scan of the results (e.g., checking the results of the sensing for each bit line or each memory cell being programmed). In one embodiment, when starting to program a data state (e.g., Figure 5C When performing programming verification, according to the data state AG Figure 7B, the memory system will start by sensing only the Vv_low verify level of the data state. Figure 7C For example, once one or both memory cells have reached the Vv_low verify level of the data state, the memory system will sense at both the Vv_low and Vv_high data states.

[0134] use Figure 8B The method results in a programming threshold voltage distribution ratio Fig. 8A The process is narrow because the shift of each programming pulse of the threshold voltage decreases once the threshold voltage approaches the target value (for example, when the threshold voltage is above Vv_low and below Vv_high). Figure 8B The method slows down the programming process because each data state being program-verified now requires two sensing operations (e.g., one sensing operation at Vv_low and one sensing operation at Vv_high). In order to reduce the time required for program verification, part of the process for verifying at Vv_low is performed simultaneously with part of the process for verifying at Vv_high. Fig.12 More details will be discussed below.

[0135] The programming, verify / sense, and erase processes discussed above all require the application of various voltages to the word lines of a selected block of memory cells. Fig. 9 is a block diagram depicting the charge pump, control gate driver, switch network, and word line switches used to apply those voltages to the word lines. Fig. 9 A group of charge pumps 902 are shown, which provide multiple different voltage sources for multiple groups of control gate drivers, including a first group of control gate drivers 904, a second group of control gate drivers 906, a third group of control gate drivers 908, ... the Xth group of control gate drivers 910. The charge pump 902 includes multiple charge pumps, which supply different voltages required to perform memory operations. In some embodiments, the voltage generator may also generate some of the different voltages required to perform memory operations. In one embodiment, there is a separate group of one or more charge pumps or voltage generators for each voltage that needs to be applied to the word line. In other embodiments, some charge pumps and / or voltage generators may be the source of multiple voltages by using a voltage divider or other circuits.

[0136] In one embodiment, the first group of control gate drivers 904 includes a plurality of control gate drivers for supplying the necessary voltages to the data word lines (e.g., W1-WL239) in order to perform programming, erasing, and reading. The outputs CGout_A of the first group of control gate drivers 904 (which include a separate output signal for each control gate driver) are provided (connected) to a switch network 920. The first group of control gate drivers 904 are connected to the data word lines via the switch network 920. In one embodiment, all control gate drivers in the first group of control gate drivers 904 have the same structure, receive the same input (voltage source), and provide the same set of voltage outputs.

[0137] In one embodiment, the second group of control gate drivers 906 includes a plurality of control gate drivers for supplying the necessary voltages to the dummy word lines for performing programming, erasing, and reading. The output CGout_B of the second group of control gate drivers 906 (which includes a separate output signal for each control gate driver) is provided (connected) to a switch network 920. The second group of control gate drivers 906 is connected to the dummy word lines via the switch network 920. In one embodiment, all control gate drivers in the second group of control gate drivers 906 have the same structure, receive the same input (voltage source) and provide the same group of voltage outputs.

[0138] In one embodiment, the third group of control gate drivers 908 includes a plurality of control gate drivers for supplying the necessary voltages to the select lines (e.g., SGD and SGS) in order to perform programming, erasing, and reading. The output CGout_C of the third group of control gate drivers 908 (which includes a separate output signal for each control gate driver) is provided (connected) to a switch network 920. The third group of control gate drivers 908 is connected to the select lines via the switch network 920. In one embodiment, all control gate drivers in the third group of control gate drivers 908 have the same structure, receive the same input (voltage source), and provide the same set of voltage outputs.

[0139] Fig. 9Word lines WL0-WL161 for two example blocks (block A and block B) are shown. Each word line WL0-WL161 for each block is connected to the output of the switch network 920 via a word line switch transistor (e.g., 940-966). For example, word line WL0 of block A is connected to the output of word line switch transistor 966, WL159 of block A is connected to the output of word line switch transistor 964, WL160 of block A is connected to the output of word line switch transistor 962, WL161 of block A is connected to the output of word line switch transistor 960, WL0 of block B is connected to the output of word line switch transistor 946, WL159 of block B is connected to the output of word line switch transistor 944, WL160 of block B is connected to the output of word line switch transistor 942, and WL161 of block 1 is connected to the output of word line switch transistor 960. The inputs of the word line switches are connected to the outputs of the switch network 920. In one embodiment, the switch network 920 includes a plurality of high voltage switches (e.g., transistors) to connect the control gate driver to the appropriate word line by routing the output voltage from the control gate driver to the appropriate word line switch transistors 940-966 connected to the word lines WL0-WL161 of each block. Note that in some embodiments, multiple word lines can share a single control gate driver. The switch network is also connected to the select lines SGS and SGD (in order to Fig. 9 Easier to read, Fig. 9 is omitted).

[0140] Fig. 9 Also depicted is a voltage control circuit 903 connected to the charge pump 902. The voltage control circuit 903 controls the output of the charge pump. In one embodiment, the voltage control circuit 903 receives a digital signal indicating a desired charge pump output from a state machine or other processor, and the voltage control circuit 903 includes a digital-to-analog conversion circuit that outputs a signal to the charge pump indicating a requested voltage signal to be output by the charge pump.

[0141] Fig.10is a timing diagram depicting the behavior of the following signals during a program verify operation: BL(sel), BL(unsel), SGD(sel), SGD(unsel), WLunsel, WLn, SGS, and SL. Signal BL(sel) is a voltage applied to a bit line connected to a NAND string that has a memory cell selected for sensing / reading. Signal BL(unsel) is a voltage applied to a bit line connected to a NAND string that does not have any memory cells selected for sensing / reading. In some embodiments, all bit lines will be selected for sensing / reading. Signal SGD(sel) is a voltage applied to the drain side select (SGD) lines (e.g., SGD0, SGD1, and SGD2 connected together for one region) of the region selected for sensing / reading (e.g., regions 420, 430, 440, 450, 460, and 470). Signal SGD (unsel) is a voltage applied to drain side select (SGD) lines (e.g., SGD0, SGD1, and SGD2 connected together for one region) of regions not selected for sensing / reading (e.g., regions 420, 430, 440, 450, 460, and 470). Signal SGS is a voltage applied to source side select (SGS) lines (e.g., SGS0, SGS1, and SGS2 connected together). Signal SL is a voltage applied to source lines. Signal WLn is a voltage applied to word lines selected for programming and program verification (i.e., word lines connected to memory cells selected for programming). Signal WLunsel is a voltage applied to word lines not selected for programming.

[0142] exist Fig.10 At time t0, Fig.10 All signals depicted in are at Vss (ground or 0 volts). At time t1, BL(sel) is raised to Vbl (e.g., 0.5v to 1.5v), and WLunsel is raised to Vread (e.g., 6 volts to 8 volts). Vread is an example of an overdrive voltage because it is high enough to turn on the memory cell regardless of which data state the memory cell has been programmed to. Also at time t1, SGD(sel) is raised to Vsg (e.g., 3.5v to 6v), an example of a sense enable voltage, in two steps, such that it reaches Vdd at t2 and Vsg at t3. At t1, a voltage spike is applied to WLn, and after the voltage on WLn stabilizes, WLn is raised to Vcgv (e.g., Figure 5CAt time t4, SGS is raised to Vsg, which provides a path for the bit line voltage to dissipate. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will conduct current and the bit line voltage will dissipate via the source line, as depicted by curve 994. If Vcgv is greater than the threshold voltage of the selected memory cell, the selected memory cell will not conduct current and the bit line voltage will not dissipate via the source line, as depicted by curve 992. The sense amplifier will sense whether the selected memory cell is turned on at time t5. At time t6, BL(sel) is lowered to Vss. At time t7, SGD(sel), WLunsel, WLn, and SGS are lowered to Vss. When sensing is performed at t5, the result of the sensing is stored in the latch at the corresponding sense amplifier. The system (eg, control circuitry) then scans all of the latches of the sense amplifiers to determine which memory cells are conducting and which are not conducting.

[0143] Fig.11 Two graphs are depicted that are horizontally aligned with each other. The upper graph depicts the voltage applied to the unselected word line (WLunsel), and the lower graph depicts the current drawn by the memory system (ICC). The horizontal axis of both graphs represents time and is divided into two time periods: R1 and R2. Time period R1 corresponds to Fig.10 The time period R2 corresponds to Fig.10 The above figure includes four curves: 1102, 1104, 1106 and 1108. Curves 1102 and 1106 represent the voltage control circuit 903 (see Fig. 9 ) output and input to the charge pump 902. Curve 1102 is a control signal that configures the charge pump 902 to ramp up the word line voltage to Vread as quickly as possible. Curve 1106 is a control signal that configures the charge pump 902 to increase the word line voltage at a slower rate (slower ramp). Curve 1106 can be called a step signal because it increases the voltage in a series of steps. Curve 1104 is the output of the charge pump 902, which is provided to the unselected word lines in response to the voltage control circuit 903 inputting curve 1102 to the charge pump 902 during programming verification. Curve 1108 is the output of the charge pump 902, which is provided to the unselected word lines in response to the voltage control circuit 903 inputting curve 1106 to the charge pump 902 during programming verification. It can be seen that curve 1108 has a more gradual increase in voltage magnitude than curve 1104. Curve 11087 shows that the word line voltage increases stepwise.

[0144] The following figure shows three curves: 1120, 1122, and 1124. Curve 1120 shows the moving average of the current ICC drawn in the memory die when curve 1102 is input to the charge pump 902 in response to the voltage control circuit 903, and curve 1104 is the output of the charge pump 902. Curve 1122 shows the moving average of the current ICC drawn in the memory die when curve 1106 is input to the charge pump 902 in response to the voltage control circuit 903, and curve 1108 is the output of the charge pump 902. When curve 1108 is the output of the charge pump 902 in response to the voltage control circuit 903 inputting curve 1106 to the charge pump 902, curve 1124 (including a series of bell-shaped curves) represents the original current (rather than the moving average). As can be seen from Fig.11 As can be seen in FIG. 1 , slowing down the ramping of the word line voltage (eg, increasing the word line voltage in steps rather than a single high slope ramp) results in a lower current ICC.

[0145] As mentioned above, when using Figure 8B In an embodiment of a memory with coarse / fine programming, in order to reduce the time required for program verification, a portion of the process for verifying at Vv_low is performed simultaneously with a portion of the process for verifying at Vv_high. For example, a scan of the test results of Vv_low stored in the latch of the sense amplifier can be performed during R1 of the verification operation of Vv_high, such as Fig.12 shown.

[0146] Fig.12 Two graphs are depicted that are horizontally aligned with each other. The upper graph depicts the voltage applied to the unselected word line (WLunsel), and the lower graph depicts the current drawn by the memory system (ICC). The horizontal axis of the two graphs represents time and is divided into two time periods: R1 and R2. The upper graph includes two curves: 1202 and 1204. Curve 1202 is a step signal output from the voltage control circuit 903 and input to the charge pump 902 to slowly increase the word line voltage, similar to Fig.11 1106. As the word line voltage ramps to Vread, a scan of the previously sensed results stored in the latch of the sense amplifier (e.g., testing Vv_low) may be performed during R1 of the current sensing operation. In prior systems, time period R1 is extended until the scan is complete; therefore, the charge pump 902 will ignore specific steps of the input signal 905 (curve 1202) and ramp up the word line voltage independently of the steps of curve 1202. Once the scan is complete, the charge pump 902 will follow the input signal 905 (curve 1202) and ramp up the word line voltage in response to the steps of curve 1202. However, the charge pump cannot immediately follow curve 1202, which pulls down the output of the charge pump, causing a large peak current, such as Fig.12More specifically, as the word line voltage ramps up during R1, the control gate of the memory cell is coupled to the channel (SGD rises to Vdd, so the channel is weakly turned on). When the scan ends, the charge pump 902 tries to catch up with curve 1202, but SGD begins to ramp up to Vsg (see Fig.10 ), so the channel of the NAND string begins to conduct. As a result, charge leaks from the channel to the bit line, and the channel potential drops. This in turn pulls down the output of the charge pump 902 until it slowly catches up with curve 1202. The large mismatch between curve 1202 (the output from the voltage control circuit 903) and the output of the charge pump 902 results in a large ICC current.

[0147] In order to reduce the above-mentioned peak current problem during programming verification, it is recommended to separate the scanning of the previous sensing results stored in the latch of the sense amplifier from the time period R1, and to make the charge pump follow the input signal 905 (e.g., curve 1202) from the beginning of the voltage ramp. That is, the scanning of the previous sensing results can still be performed during R1 (simultaneously); however, the time period R1 will not be extended before the scanning is completed. Instead, R1 will be a set time period that ends based on configuration parameters (default values ​​or supplied by the user) rather than based on the completion of the scanning of the previous results. Therefore, it is likely (but not required) that the time period R1 will end before the scanning ends. Therefore, while scanning the results of the previous programming verification operation, the voltage on the selection line for the next programming verification operation (e.g., SGD) will ramp up without waiting for the scanning to be completed, and the voltage on the unselected word line for the next programming verification operation will ramp up and follow the step signal 1202 without waiting for the scanning to be completed. This concept is described in detail in the following sections. Fig.13 Shown in.

[0148] Fig.13 Two sets of graphs 1300 and 1302 are included. Each set of graphs includes an upper graph showing the voltage applied to the select line SGD and a lower graph (horizontally aligned with the upper graph) showing the voltage applied to the unselected word line (WLunsel). For each graph, the horizontal axis is time. The left set of graphs 1300 shows Fig.12, where R1 is stretched until the scan is complete. The right set of graphs 1302 shows the proposed system that separates the scan of the previous sensed result stored in the latch of the sense amplifier from the time period R1 and causes the charge pump to follow the input signal 905 (e.g., curve 1202) from the start of the word line voltage ramp up. Therefore, the lower right figure shows the output signal 1314 from the charge pump 902 following the step signal 1312 input to the charge pump 902 from the voltage control circuit 903. In other words, the output signal 1314 from the charge pump 902 is ramped up (causing the voltage on the unselected word line to ramp up) for the next program verification operation following the step signal 1312 while the memory system is performing a scan 1320 of the results of the previous program verification operation and does not wait for the scan 1320 to complete. As shown in the curve 1302, the voltage on the unselected word line is ramped up to the overdrive voltage Vread by using the charge pump 902, and the scan 1320 of the result of the previous program verification operation is performed in response to the step signal 1312 and without waiting for the scan 1320 to be completed, the voltage on the unselected word line is ramped up to the next program verification operation, so that the voltage applied to the unselected word line 1314 is gradually increased (as shown in the curve 1314). Although Fig.13 A curve 1322 is shown for SGD, but in some embodiments, the same curve 1322 may be used for the voltage applied to SGS. Fig.13 Curves 1312, 1314 and 1322 are the period between R1 and R2. Fig.10 Examples of curves shown.

[0149] In some cases, such as Fig.13 As shown, after the scan 1320 of the result of the previous program verification operation is completed, the voltage on the unselected word line reaches the overdrive voltage Vread. Fig.13 As shown, the voltage on the select line SGD reaches Vdd before the scan 1320 is completed, and reaches the sense enable voltage (Vsg) after the scan 1320 is completed.

[0150] Fig.14 is a flow chart describing one embodiment of a process for programming, including performing program verification based on the embodiment of Figure 1302. Thus, Fig.14 The process includes separating the scanning of the previous sense result stored in the latch of the sense amplifier from the time period R1 and making the charge pump follow the input signal 905 (eg, curve 1312 ) from the beginning of the voltage ramp. Fig.14 The process may be performed by any of the one or more control circuits discussed above. Fig.14 The process can be completely controlled by the control circuit on the memory tube core 200 (see Figure 2A) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.14 In another embodiment, Fig.14 The process is performed by the memory controller 120 or under its command. Figures 1 to 4F and Fig. 9 is performed on the memory of any structure depicted in Fig.14 The process is based on and / or uses Fig.10 process.

[0151] exist Fig.14 In step 1402, by applying a programming dose (e.g., steps 608 and Fig. 7A 1404, program verification is performed between programming doses (e.g., step 610). An example implementation of step 1404 includes ramping up the voltage on the select line (e.g., SGD) for the next program verification operation while performing a scan of the results of the previous program verification operation and not waiting for the scan to complete (step 1420), and ramping up the voltage on the unselected word line (e.g., WLunsel) for the next program verification operation after the step signal (e.g., 1312) while performing a scan of the results of the previous program verification operation (e.g., scan 1320) and not waiting for the scan to complete (step 1422). An example of step 1420 is curve 1322. An example of step 1422 is curve 1314. In one embodiment, the previous program verification operation is started from Vv_low and the next program verification operation is Vv_high for the same data state. This speeds up the program verification process by scanning the results of Vv_low while starting a program verification operation of Vv_high. Thus, in this embodiment, the control circuit is configured to perform program verification between program doses by ramping up the voltage on the select line to test the higher verification level (VV_high) while performing a scan of the results of the test of the lower verification level (Vv_low) and not waiting for the scan to complete, and ramping up the voltage on the unselected word lines to test the higher verification level while performing a scan of the results of the test of the lower verification level and not waiting for the scan to complete. In other embodiments, the previous program verification operation and the next program verification operation can be for different data states, or can be for the same verification reference voltage.

[0152] Fig.151302 is a flowchart describing an embodiment of a process for programming, including performing program verification based on the embodiment of FIG. 1302. Thus, Fig.15 The process includes separating the scanning of the previous sense result stored in the latch of the sense amplifier from the time period R1 and making the charge pump follow the input signal 905 (eg, curve 1312 ) from the beginning of the voltage ramp. Fig.15 The process is Fig.14 An example specific implementation of the process.

[0153] Fig.15 The process may be performed by any of the one or more control circuits discussed above. Fig.15 The process can be completely controlled by the control circuit on the memory tube core 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.15 In another embodiment, Fig.15 The process is performed by the memory controller 120 or under its command. Figures 1 to 4F and Fig. 9 is performed on the memory of any structure depicted in Fig.15 The process is based on and / or uses Fig.10 process.

[0154] exist Fig.15 In step 1502, by applying a programming dose (e.g., steps 608 and Fig. 7A The memory cell is programmed by applying a programming voltage pulse of 1000A. In step 1504, the control circuit verifies the programming state after applying the programming dose (eg, step 610).

[0155] One example implementation of step 1504 includes verifying the state of a lower verify level (e.g., Vv_low) of a data state (step 1512) and verifying the state of a higher verify level (e.g., Vv_high) of the same data state (step 1514). The data state may be as described above with respect to FIG. 5A to FIG. 5D Any programming data status discussed.

[0156] One example implementation of step 1512 includes, after applying the programming dose, performing a first sensing of the memory cells to determine which memory cells have a threshold voltage above a lower verify level in step 1520. In step 1522, scanning the results of the first sensing (see, e.g., scanning 1320). In one embodiment, the scanning includes checking the values ​​stored in the latches of each sense amplifier.

[0157] An example implementation of step 1514 includes implementing Fig.10 The process includes ramping up the voltage on the selection line (e.g., SGD) to a sense enable voltage (e.g., Vsg) in step 1530 to coincide with the scan result of the first sensing and without waiting for its completion (see scan 1320); in step 1532, applying a step signal (e.g., 1312) to control a voltage source (e.g., charge pump 902) connected to an unselected word line (WL_unsel); in step 1534, in response to the step signal, ramping up the voltage on the unselected word line to an overdrive voltage (e.g., Vread) using a voltage source to coincide with the scan result of the first sensing and without waiting for its completion (see scan 1320), so that the voltage applied to the unselected word line is gradually increased (see curve 1314); in step 1542, applying a verification comparison voltage (Vcgv) to the selected word line (WLn) (see Fig.10 ); and sensing the memory cells connected to the selected word line in step 1544 (e.g., Fig.10 at t5).

[0158] Fig.16 1302 is a flowchart describing an embodiment of a process for programming, including performing program verification based on the embodiment of FIG. 1302. Thus, Fig.16 The process includes separating the scanning of the previous sense result stored in the latch of the sense amplifier from the time period R1 and making the charge pump follow the input signal 905 (eg, curve 1202 ) from the beginning of the voltage ramp. Fig.16 The process is Fig.14 process and / or Fig.15 An example specific implementation of the process.

[0159] Fig.16 The process may be performed by any of the one or more control circuits discussed above. Fig.16 The process can be completely controlled by the control circuit on the memory tube core 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.16 In another embodiment, Fig.16 The process is performed by the memory controller 120 or under its command. Figures 1 to 4F and Fig. 9 is performed on the memory of any structure depicted in Fig.16 The process is based on and / or uses Fig.10 process.

[0160] Fig.16 Step 1602 includes applying a programming dose (e.g., steps 608 and 610) to a group of nonvolatile memory cells connected to the selected word line WLn. Fig. 7A programming voltage pulse). Fig.16 Step 1604 of the embodiment includes performing program verification between programming doses, including a lower verification level for the test data state and an upper verification level for the test data state (see step 610, Figure 7C and Figure 8B ).

[0161] Fig.17 is a flow chart describing one embodiment of a process for testing a higher verification level of a data state. Fig.17 The process as Fig.16 as part of step 1604. Fig.17 The process may be performed by any of the one or more control circuits discussed above. Fig.17 The process can be completely controlled by the control circuit on the memory tube core 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.17 In another embodiment, Fig.17 The process is performed by the memory controller 120 or under its command. Figures 1 to 4F and Fig. 9 is performed on the memory of any structure depicted in Fig.17 The process is based on and / or uses Fig.10 process.

[0162] exist Fig.17In step 1702, the voltage on the select line (e.g., SGD) is ramped up (e.g., see curve 1322) to test the higher verify level while performing a scan of the results of the test of the lower verify level (e.g., scan 1320) and without waiting for the scan to complete. In step 1704, the voltage on the unselected word lines is ramped up (e.g., see curve 1314) to test the higher verify level (e.g., Figure 8B Vv_high), while performing verification on lower verification levels (e.g., Figure 8B The scan of the results of the test of the Vv_low of the lower verification level (e.g., scan 1320) is performed simultaneously with or before steps 1702 and 1704. During R1 and R2 (e.g., during Fig.10 Steps 1702-1706 are performed between t1-t3. In step 1708, a verification comparison voltage Vcgv is applied to the selected word line WLn (see Fig.10 In step 1710, a sense amplifier is used to sense the memory cells connected to the selected word line WLn (eg, Fig.10 At time t5). In step 1712, the control circuit will slow down programming in response to the memory cell having a threshold voltage greater than the lower verify level of the data state; for example, by raising the bit line voltage (see, for example, Figure 8B ) or reduce Vpgm.

[0163] A memory system including a highly efficient and low-current program verification operation has been proposed.

[0164] One embodiment includes a nonvolatile memory device, the nonvolatile memory device including: a plurality of nonvolatile memory cells; a plurality of word lines connected to the memory cells; a first selection line connected to the memory cells; and a control circuit connected to the memory cells and the word lines and the first selection line. The control circuit is configured to program the memory cells by applying a programming dose, and to perform programming verification between programming doses. The control circuit is configured to perform programming verification between programming doses by ramping up the voltage on the first selection line for the next programming verification operation, while performing a scan of the results of the previous programming verification operation and not waiting for the scan to be completed; and ramping up the voltage on the unselected word line for the next programming verification operation after a step signal, while performing a scan of the results of the previous programming verification operation and not waiting for the scan to be completed.

[0165] In one example implementation, the control circuit is further configured to perform programming verification between programming doses by testing a lower verification level of a data state and testing a higher verification level of the data state; and the previous programming verification operation includes the test of the lower verification level of the data state, and the next programming verification operation includes the test of the higher verification level of the data.

[0166] In one example implementation, the control circuit is further configured to perform program verification between programming doses by testing a lower verification level of a data state and testing a higher verification level of the data state; and the previous program verification operation includes the test of the lower verification level of the data state, and the next program verification operation includes the test of the higher verification level of the data state. The control circuit is configured to perform program verification between programming doses by ramping up the voltage on the first select line to test the higher verification level, while performing a scan of the result of the test of the lower verification level and not waiting for the scan to complete; and ramping up the voltage on the unselected word line to test the higher verification level, while performing a scan of the result of the test of the lower verification level and not waiting for the scan to complete.

[0167] In one example implementation, the control circuit is further configured to perform program verification between programming doses by testing whether a memory cell connected to a selected word line has a threshold voltage greater than a lower verification level of a data state, and testing whether a memory cell connected to the selected word line has a threshold voltage greater than a higher verification level of the data state between programming doses; the previous program verification operation includes the testing whether the memory cell connected to the selected word line has a threshold voltage greater than the lower verification level of the data state; the testing whether the memory cell connected to the selected word line has a threshold voltage greater than the lower verification level of the data state includes the scanning of the result; the next program verification operation includes the testing whether the memory cell connected to the selected word line has a threshold voltage greater than the higher verification level of the data state. In addition, the control circuit is further configured to slow down programming of memory cells having a threshold voltage greater than the lower verification level and less than the higher verification level.

[0168] In an example implementation, during programming verification between programming doses, the control circuit is further configured to apply the step signal to control a voltage source connected to an unselected word line; and the control circuit is configured to ramp up the voltage on the unselected word line to an overdrive voltage by using the voltage source, while performing the scan of the result of the previous programming verification operation in response to the step signal and without waiting for the scan to be completed, to ramp up the voltage on the unselected word line for the next programming verification operation, so that the voltage applied to the unselected word line gradually increases. In addition, in some cases, the control circuit is further configured to perform programming verification between programming doses by testing a lower verification level of a data state and testing a higher verification level of the data state; the previous programming verification operation includes the test of the lower verification level of the data state, and the next programming verification operation includes the test of the higher verification level of the data; during programming verification between programming doses, the control circuit is further configured to apply a verification comparison voltage to a selected word line and sense memory cells connected to the selected word line; and the control circuit is further configured to slow down programming of memory cells having a threshold voltage greater than the lower verification level and less than the higher verification level.

[0169] In an example implementation, ramping the voltage on the first selection line includes ramping the voltage on the first selection line to a sensing enable voltage while performing the scan of the result of the previous programming verification operation and not waiting for the scan to be completed, after which the scan of the result of the previous programming verification operation is completed, the voltage on the first selection line reaches the sensing enable voltage; and ramping the voltage on the unselected word line includes ramping the unselected word line to an overdrive voltage while performing the scan of the result of the previous programming verification operation and not waiting for the scan to be completed, after which the scan of the result of the previous programming verification operation is completed, the voltage on the unselected word line reaches the overdrive voltage.

[0170] In one example implementation, the programming dose is a voltage pulse applied to the selected word line, the voltage pulse increasing in magnitude from pulse to pulse.

[0171] In one example implementation, the plurality of nonvolatile memory cells are arranged in NAND strings, and the plurality of word lines and the select line are connected to each of the NAND strings.

[0172] In one example implementation, the plurality of nonvolatile memory cells are arranged in NAND strings and the plurality of word lines; the select line is connected to each of the NAND strings; a second select line is connected to each of the NAND strings, the first select line is connected to each of the NAND strings at a first end of the NAND string, and the second select line is connected to each of the NAND strings at a second end of the NAND string; a plurality of bit lines are connected to the NAND string at the first end of the NAND string; and a source line is connected to the NAND string at the second end of the NAND string, the control circuit being further configured to apply a verification compare voltage to the selected word line and sense the memory cells connected to the selected word line as part of performing a programming verification between programming doses.

[0173] One embodiment includes a method, the method comprising: applying a programming dose to a group of nonvolatile memory cells connected to a selected word line; and performing programming verification between the programming doses including testing a lower verification level of a data state and testing a higher verification level of the data state. The testing of the higher verification level of the data state includes: ramping up a voltage on a select line to test the higher verification level while performing a scan of the result of the test of the lower verification level and not waiting for the scan to complete; and ramping up a voltage on an unselected word line to test the higher verification level while performing the scan of the result of the test of the lower verification level and not waiting for the scan to complete.

[0174] In one example implementation, the process includes slowing down programming in response to a memory cell having a threshold voltage greater than the lower verify level for the data state.

[0175] In an example implementation, the testing of the higher verification level also includes: applying a step signal to control a voltage source connected to an unselected word line; the ramping of the voltage on the unselected word line includes responding to the step signal, using the voltage source to ramp the voltage on the unselected word line to an overdrive voltage, simultaneously with the scanning of the result of the test of the lower verification level and without waiting for its completion, so that the voltage applied to the unselected word line is gradually increased.

[0176] In one example implementation, the ramping up of the voltage on the unselected word lines is done gradually.

[0177] In one example implementation, the testing the higher verify level of the data state further includes: applying a verify compare voltage to a selected word line; and sensing memory cells connected to the selected word line.

[0178] In one example implementation, the ramping of the voltage on the select line first raises the select line to a positive supply voltage and then to a sense enable voltage; the select line reaches the positive supply voltage before the scan of the result of the test to the lower verify level is completed; and the select line reaches the sense enable voltage after the scan of the result of the test to the lower verify level is completed.

[0179] In one example implementation, the ramping of the voltage on the unselected word line raises the unselected word line to an overdrive voltage; the ramping of the voltage on the unselected word line begins before the scanning of the result of the test to the lower verification level is completed; and the unselected word line reaches the overdrive voltage after the scanning of the result of the test to the lower verification level is completed.

[0180] One embodiment includes a nonvolatile memory device, which includes: a plurality of nonvolatile memory cells; a plurality of word lines connected to the memory cells; a selection line connected to the memory cells; and a control circuit connected to the memory cells and the word lines and the selection line, the control circuit being configured to program the memory cells by applying a programming dose, and verifying a programming state after applying the programming dose, the verifying programming state including a state of a lower verification level of a data state and a state of a higher verification level of the data state after applying the programming dose, the verifying the state of the lower verification level of the data state including a first sensing of the memory cells to determine which memory cells have a threshold voltage higher than the lower verification level and a scan result of the first sensing. The state of the higher verification level of the data state is verified by ramping the voltage on the selection line to a sense enable voltage to coincide with the scan result of the first sensing and without waiting for its completion; applying a step signal to control a voltage source connected to an unselected word line; in response to the step signal, using the voltage source to ramp the voltage on the unselected word line to an overdrive voltage to coincide with the scan result of the first sensing and without waiting for its completion, so that the voltage applied to the unselected word line is gradually increased; applying a verification comparison voltage to the selected word line; and sensing the memory cell connected to the selected word line. In an example implementation, the plurality of nonvolatile memory cells are arranged in a NAND string; and the plurality of word lines and the selection line are connected to each of the NAND strings.

[0181] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0182] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0183] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0184] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0185] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0186] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: a plurality of non-volatile memory cells; a plurality of word lines connected to the memory cells; a first selection line connected to the memory cell; and a control circuit connected to the memory cell and the word line and the first selection line, the control circuit being configured to program the memory cell by applying a programming dose and to perform program verification between programming doses; The control circuit is configured to perform program verification between programming doses by: ramping up the voltage on the first select line for the next program verification operation, concurrently performing a scan of results of a previous program-verify operation and without waiting for the scan to complete; as well as The voltage on the unselected word lines is ramped up for the next program verification operation after the step signal while performing a scan of the result of the previous program verification operation and without waiting for the scan to be completed.

2. The nonvolatile memory device according to claim 1, wherein: The control circuit is further configured to perform program verification between program doses by testing a lower verify level of a data state and testing an upper verify level of the data state; and The previous program verify operation includes the test of the lower verify level of the data state, and the next program verify operation includes the test of the higher verify level of the data.

3. The nonvolatile memory device according to claim 1, wherein: The control circuit is further configured to perform program verification between program doses by testing a lower verify level of a data state and testing an upper verify level of the data state; and The previous program verify operation includes the test of the lower verify level of the data state, and the next program verify operation includes the test of the higher verify level of the data state, so that the control circuit is configured to perform program verification between program doses by: ramping up a voltage on the first select line to test the upper verify level while performing a scan of the results of the test of the lower verify level and without waiting for the scan to complete; as well as ramping up the voltage on the unselected word lines to test the higher verify level, A scan of the results of the test of the lower verify level is performed concurrently and without waiting for the scan to complete.

4. The nonvolatile memory device according to claim 1, wherein: The control circuit is further configured to perform program verification between programming doses by testing whether memory cells connected to a selected word line have a threshold voltage greater than a lower verify level for a data state and testing whether memory cells connected to the selected word line have a threshold voltage greater than an upper verify level for the data state between programming doses; The previous program verification operation includes the testing whether a memory cell connected to the selected word line has a threshold voltage greater than the lower verification level of the data state; said testing whether a memory cell connected to said selected word line has a threshold voltage greater than a lower verify level of said data state comprises said scanning of said results; and The next program verification operation includes the testing whether memory cells connected to the selected word line have a threshold voltage greater than the higher verification level of the data state.

5. The nonvolatile memory device according to claim 4, wherein: The control circuit is also configured to slow down programming of memory cells having a threshold voltage greater than the lower verify level and less than the upper verify level.

6. The nonvolatile memory device according to claim 1, wherein: During a program verification between program doses, the control circuit is further configured to apply the step signal to control a voltage source connected to an unselected word line; and The control circuit is configured to ramp up the voltage on the unselected word line to an overdrive voltage by using the voltage source, and at the same time perform the scan of the result of the previous programming verification operation in response to the step signal and without waiting for the scan to be completed, so as to ramp up the voltage on the unselected word line for the next programming verification operation, so that the voltage applied to the unselected word line gradually increases.

7. The nonvolatile memory device according to claim 6, wherein: The control circuit is further configured to perform program verification between program doses by testing a lower verify level of a data state and testing an upper verify level of the data state; the previous program verify operation includes the test of the lower verify level of the data state, and the next program verify operation includes the test of the higher verify level of the data; During a program verification between program doses, the control circuit is further configured to apply a verification compare voltage to a selected word line and sense memory cells connected to the selected word line; and The control circuit is also configured to slow down programming of memory cells having a threshold voltage greater than the lower verify level and less than the upper verify level.

8. The nonvolatile memory device according to claim 1, wherein: The ramping up of the voltage on the first selection line includes ramping up the voltage on the first selection line to a sense enable voltage while performing the scanning of the result of the previous program verification operation and without waiting for the scanning to be completed, after the scanning of the result of the previous program verification operation is completed, the voltage on the first selection line reaches the sense enable voltage; as well as Ramping up the voltage on the unselected word line includes ramping up the unselected word line to an overdrive voltage while performing the scanning of the result of the previous programming verification operation and without waiting for the scanning to be completed, after the scanning of the result of the previous programming verification operation is completed, the voltage on the unselected word line reaches the overdrive voltage.

9. The nonvolatile memory device according to claim 1, wherein: The programming dose is a voltage pulse applied to the selected word line, the voltage magnitude of the voltage pulse increasing from pulse to pulse.

10. The nonvolatile memory device according to claim 1, wherein: The plurality of nonvolatile memory cells are arranged in NAND strings; and The plurality of word lines and the select line are connected to each of the NAND strings.

11. The nonvolatile storage device according to claim 10, further comprising: a second select line connected to each of the NAND strings, the first select line connected to each of the NAND strings at a first end of the NAND strings, the second select line connected to each of the NAND strings at a second end of the NAND strings; a plurality of bit lines connected to the NAND string at the first end of the NAND string; and A source line is connected to the NAND string at the second end of the NAND string, and the control circuit is also configured to apply a verify compare voltage to the selected word line and sense the memory cells connected to the selected word line as part of performing program verification between programming doses.

12. A method comprising: applying a programming dose to a group of nonvolatile memory cells connected to a selected word line; as well as Performing program verification between the program doses includes testing a lower verification level of a data state and testing a higher verification level of the data state, wherein the testing the higher verification level of the data state includes: ramping up a voltage on a select line to test said higher verify level while performing a scan of the results of said testing of said lower verify level and without waiting for said scan to complete; as well as The voltage on unselected word lines is ramped up to test the higher verify level while performing the scanning of the results of the testing of the lower verify level and without waiting for the scanning to complete.

13. The method according to claim 12, further comprising: Responsive to a memory cell having a threshold voltage greater than the lower verify level for the data state, programming is slowed.

14. The method of claim 12, wherein said testing said higher verification level further comprises: applying a step signal to control a voltage source connected to an unselected word line; The ramping up of the voltage on the unselected word line includes, in response to the step signal, using the voltage source to ramp up the voltage on the unselected word line to an overdrive voltage, simultaneously with the scanning of the result of the test of the lower verification level and without waiting for its completion, so that the voltage applied to the unselected word line is gradually increased.

15. The method of claim 12, wherein: The ramping up of the voltage on the unselected word lines is done gradually.

16. The method of claim 12, wherein said testing said higher verify level of said data state further comprises: applying a verify compare voltage to the selected word line; as well as Memory cells connected to the selected word line are sensed.

17. The method of claim 12, wherein: The ramping up of the voltage on the select line first raises the select line to a positive supply voltage and then to a sense enable voltage; the select line reaches the positive supply voltage before the scanning of the results of the testing of the lower verify level is completed; and After the scanning of the results of the testing of the lower verify level is completed, the select line reaches the sense enable voltage.

18. The method of claim 12, wherein: The ramping up of the voltage on the unselected word line raises the unselected word line to an overdrive voltage; said ramping up voltage on unselected word lines begins before said scanning of said results of said testing of said lower verify level is completed; and After the scanning of the results of the testing of the lower verify level is completed, the unselected word lines reach the overdrive voltage.

19. A non-volatile storage device, comprising: a plurality of non-volatile memory cells; a plurality of word lines connected to the memory cells; a select line connected to the memory cell; and a control circuit connected to the memory cell and the word line and the select line, the control circuit being configured to program the memory cell by applying a programming dose, and verifying a programming state after applying the programming dose, the verifying the programming state comprising verifying a state of a lower verification level of a data state and verifying a state of a higher verification level of the data state after applying the programming dose, the verifying the state of the lower verification level of the data state comprising first sensing of the memory cells to determine which memory cells have a threshold voltage higher than the lower verification level and a scan result of the first sensing, the verifying the state of the higher verification level of the data state comprising: ramping a voltage on a select line to a sense enable voltage simultaneously with said scan result of said first sensing and without waiting for its completion; applying a step signal to control a voltage source connected to an unselected word line; In response to the step signal, ramping up the voltage on the unselected word line to an overdrive voltage using the voltage source, simultaneously with the scan result of the first sensing and without waiting for its completion, so that the voltage applied to the unselected word line is gradually increased; applying a verify compare voltage to the selected word line; and Memory cells connected to the selected word line are sensed.

20. The non-volatile memory device according to claim 19, wherein: The plurality of nonvolatile memory cells are arranged in NAND strings; and The plurality of word lines and the select line are connected to each of the NAND strings.

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