Accelerated encryption during power loss

Abstract

The present disclosure generally relates to XTS cache operations during power-off events. Upon detection of power loss, the data to be encrypted needs to be refreshed to the memory device. For any unaligned data or data smaller than a flash memory management unit (FMU) size, these data are grouped together and, if necessary, will be filled to reach the FMU size, then encrypted, merged with other data FMU, and written to a memory device. The filling amount required for achieving the size of the FMU is reduced for unaligned data packets, and the amount of data to be encrypted is also reduced. Thus, during a power loss event, a limited amount of remaining power may be used to complete data refresh.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and is hereby incorporated by reference in its entirety, U.S. Non-Provisional Application No. 17 / 870,395, filed on July 21, 2022, and entitled “Accelerated Encryption During Power Loss,” for all purposes. Background Art Technical Field

[0003] Embodiments of the present disclosure generally relate to XTS cache operations during power outage events.

[0004] Description of Related Art

[0005] During a power loss event, any data stored in the cache needs to be written to the memory device in a process commonly referred to as refreshing the data. Once the external power source is lost, a backup power source, such as a capacitor, is used to supply power to the data storage device. Capacitors have a limited amount of power available, and refreshing the data is one of the many processes that should be performed during a power loss event.

[0006] To refresh the data, the data in the cache is collected, encrypted, and written to the memory device. The data should be aligned when written to the memory device, but the data in the cache is often misaligned. In this scenario, the misaligned data is filled with dummy data, which is used as placeholder data to fill in the location of the data that is usually aligned to the Flash Management Unit (FMU) size. The data is then encrypted and finally written to the memory device. Unfortunately, the misaligned data may span multiple FMUs, so that multiple FMUs need to be filled and encrypted. Encrypting the FMU takes time, and in a power loss event, time is very valuable and there is not much power available to ensure the completion of multiple operations during the power loss event.

[0007] Therefore, there is a need in the art for efficient data refreshing during power loss events. Summary of the invention

[0008] The present disclosure generally relates to XTS cache operation during a power outage event. When a power loss is detected, data awaiting encryption needs to be flushed to a memory device. For any data that is misaligned or smaller than the Flash Management Unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size, then encrypted, merged with other data FMUs, and written to the memory device. Grouping the misaligned data reduces the amount of padding required to reach the FMU size and also reduces the amount of data to be encrypted. Therefore, during a power loss event, a limited amount of remaining power can be used to complete the data flush.

[0009] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine that a first cache contains data; determine that at least some of the data in the first cache is unaligned; combine the unaligned first cache data; and send the combined unaligned first cache data to the memory device.

[0010] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: detect that power-on has occurred; check data stored using a pFail key in the memory device; read data associated with the pFail key from the memory device, wherein the read data is unaligned; and place the unaligned read data in a first cache.

[0011] In another embodiment, a data storage device includes: a memory component; and a controller coupled to the memory component, wherein the controller is configured to: combine non-contiguous logical block address (LBA) data stored in a cache into data packets, wherein the cache is different from the memory component; and store the data packets in the memory component, wherein the combining and storing are responsive to a power failure event. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief overview, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0013] Figure 1 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a data storage device may be used as a storage device for a host device.

[0014] Figure 2is a schematic diagram of a solid state device (SSD) system according to one embodiment.

[0015] Figure 3A is a flow chart illustrating a cache fetch operation according to one embodiment.

[0016] Figure 3B is Figure 3A Schematic diagram of the commands processed during a cache fetch operation.

[0017] Figure 4 is a flow chart illustrating a power-off cache fetch operation according to one embodiment.

[0018] Figure 5 is a flow chart illustrating a power-up operation following a power-down cache fetch operation according to one embodiment.

[0019] Figure 6 is a schematic diagram of a memory system according to one embodiment.

[0020] Figure 7 is a schematic diagram of a power-off cache fetch operation according to another embodiment.

[0021] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0022] Hereinafter, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0023] The present disclosure generally relates to XTS cache operation during a power outage event. When a power loss is detected, data awaiting encryption needs to be flushed to a memory device. For any data that is misaligned or smaller than the Flash Management Unit (FMU) size, the data is grouped together and, if necessary, padded to reach the FMU size, then encrypted, merged with other data FMUs, and written to the memory device. Grouping the misaligned data reduces the amount of padding required to reach the FMU size and also reduces the amount of data to be encrypted. Therefore, during a power loss event, a limited amount of remaining power can be used to complete the data flush.

[0024] Figure 1 1 is a schematic block diagram of a storage system 100 according to certain embodiments, wherein a host device 104 communicates with a data storage device 106. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that collectively function as a mass storage device for the host device 104.

[0025] Host device 104 may store data to and / or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet computer, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other device capable of sending or receiving data from a data storage device.

[0026] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, and write buffer 116. In some examples, for clarity, data storage device 106 may include Figure 1. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., an HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIex1, x4, x8, x16, PCIe Mini card, MiniPCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered or inserted into a connector) to a motherboard of the host device 104.

[0027] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, as Figure 1 As shown, power supply 111 may receive power from host device 104 via interface 114 .

[0028] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data and a message from controller 108 indicating that the memory cell stores the data. Similarly, the memory cell may receive a message from controller 108 indicating that the memory cell retrieves data. In some examples, each of the memory cells may be referred to as a die. In some examples, NVM 110 may include multiple dies (e.g., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0029] In some examples, each memory cell may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0030] NVM 110 may include multiple flash memory devices or memory cells. NVM flash memory devices may include NAND or NOR-based flash memory devices, and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into multiple dies, wherein each of the multiple dies includes multiple physical or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. The rows of NVM cells may be electrically connected using word lines to define pages in multiple pages. The corresponding cells in each of the multiple pages may be electrically connected to the corresponding bit lines. In addition, the NVM flash memory device may be a 2D or 3D device, and may be a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The controller 108 may write data to and read data from the NVM flash memory device at the page level, and erase data from the NVM flash memory device at the block level.

[0031] The power supply 111 can provide power to one or more components of the data storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as the host device 104 to power one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to power one or more components. In some examples, the power supply 111 may include one or more power storage components that are configured to power one or more components when operating in a shutdown mode, such as when power is stopped from being received from an external device. In this way, the power supply 111 can be used as an onboard backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of such one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0032] Volatile memory 112 may be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. Figure 1 As shown, the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0033] The controller 108 can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory of the controller 108 (i.e., the second volatile memory 150), which can be an SRAM memory, before sending the data to the NVM 110.

[0034] Figure 2 2 is a schematic diagram of a solid state device (SSD) system 200 according to one embodiment. Data from a host 202 is transferred using a PCIe transport layer 208. Direct memory access (DMA) 212 reads data from the host 202. Data is temporarily stored in an XTS cache 214 before being encrypted by an XTS 216. The encrypted data is then temporarily stored in a page aligned cache (PAC) 218. A flash interface module (FIM) 220 then writes the encrypted data to a memory device 206. The SSD system 200 includes an external capacitor. One function of the external capacitor is to store sufficient power to allow the SSD system 200 to clear the entire XTS cache 214 and PAC 218 during a power failure event.

[0035] In certain embodiments, controller 204 utilizes XTS cache 214 and PAC 218 during the write command flow. XTS cache 214 and PAC 218 are used for at least two functions. The first function is to receive data and allow SSD system 200 to send a completion notification even before the data is sent to memory device 206. The second function is to allow controller 204 to align data with memory device 206.

[0036] In one embodiment, the memory device 206 includes, for example, NAND flash memory and contains at least two regions. One region includes single-level cell (SLC) memory, where each cell stores a single bit. Another region includes quad-level cell (QLC) memory, where each cell stores multiple bits. To increase storage capacity, the target destination of data is QLC memory, because the granularity of SLC pages is 16KB, while the granularity of QLC pages is 32KB or larger (if more bits are used per cell).

[0037] From a NAND perspective, the optimal "unit" size is the page size, which is approximately 32K. The SSD system 200 needs to add metadata to the 32K of user data to ensure correct behavior. The metadata can include error correction codes (ECC) and other control and status information. However, most operating systems in the host 202 work at 4K+ or 512-byte granularity. Even at 512-byte granularity, performance requirements have 4K granularity. The host 202 achieves the optimal "unit" size by using multiples of 8 LBAs per command to achieve 4K alignment.

[0038] The security device requires that all data be encrypted in the memory device 206. Data passing through the security engine cannot be protected from bit flips by parity or error correction code (ECC), so the entire unencrypted data is padded with a cyclic redundancy check (CRC), which is also encrypted. This protection from the CRC increases the size of the payload. Even with the increased payload size, the generation of the keys required for encryption introduces more latency and therefore affects performance. Due to the additional payload from the CRC and the latency from generating the keys, the system only encrypts at a 4K granularity to minimize both effects.

[0039] Figure 3A 3 is a flow chart illustrating a cache fetch operation according to one embodiment. For ease of description, cache fetch operations are described with reference to SSD system 200, although any suitable system may be used.

[0040] After starting at block 302 , at block 304 , the data storage device waits for data to be written from the host 202 to the XTS cache 214 .

[0041] At decision block 306, the controller 204 determines whether the data in the XTS cache 214 is 4K or larger. If the data is 4K or larger, any fully 4K aligned data is encrypted at block 310. The controller then proceeds to mark any misaligned sectors from the beginning and end at block 312.

[0042] After marking the misaligned sectors at block 312 , or if the controller determines at decision block 306 that the data in the XTS cache 214 is not 4K or larger, the controller merges any misaligned LBAs at block 308 .

[0043] At decision block 314, the controller then determines whether the merged data has reached 4K alignment. If the data is 4K aligned, then at block 316, the data is encrypted. Any merged data that is not 4K aligned remains in the XTS cache, and the process ends at block 318.

[0044] Figure 3B is Figure 3A Schematic diagram of commands 350, 360, 370 processed during a cache fetch operation of . For ease of description, cache fetch operations are described with reference to SSD system 200, but any suitable data storage device may be used.

[0045] The first command 350 includes logical block addresses (LBAs) 3 to 24. Each LBA is equal to 512 bytes, and therefore, LBAs 8-15 and LBAs 16-23 each represent a complete 4K aligned unit. LBAs 8-15 and LBAs 16-23 are sent to XTS 216, leaving XTS cache 214 with LBAs 3, 4, 5, 6, 7, and 24.

[0046] The second command 360 includes LBAs 0-2. These LBAs are sent to the XTS cache 214 where they are merged with LBAs 3-7 to form a contiguous 4K aligned unit and sent to the XTS 216. LBA 24 remains in the XTS cache 214.

[0047] The third command 370 includes LBAs 30 and 31. LBA 30, LBA 31, and the previously cached LBA 24 all belong to the same contiguous 4K aligned unit, but LBAs 25-29 are not in the cache, so that unit is not sent to the XTS 216. This results in LBAs 24, 30, and 31 being left in the XTS cache 214.

[0048] When a power failure is detected, it is necessary to flush all contents to the memory device 206 as quickly as possible while the capacitors can still provide enough power. To do this, LBAs 24, 30, and 31 are filled with dummy data from LBAs 25-30 to achieve 4K alignment. The 4K aligned cells are sent to the XTS 216 for encryption. After the XTS 216, if necessary, the aligned cells are filled again to achieve 32K alignment and written to the memory device 206.

[0049] Figure 4 4 is a flow chart illustrating a power-off cache fetch operation according to one embodiment. For ease of description, the power-off cache fetch operation is described with reference to the SSD system 200, but any suitable data storage device may be used.

[0050] The process starts at block 402. At block 404, the controller coalesces any LBAs in the XTS cache 214. The controller does not check for consecutive groupings of LBAs.

[0051] At decision block 406, the controller checks whether the merged LBA has reached 4K alignment. If the merged LBA has reached 4K alignment, the flow continues to block 410. If the merged LBA is not 4K aligned, the flow proceeds to block 408.

[0052] At block 408 , the merged LBAs are filled with dummy data to achieve the 4K alignment required for encryption. This results in only 4K aligned LBAs remaining in the XTS cache 214 .

[0053] At block 410, the controller sends all 4K aligned data in the XTS cache 214 to the XTS 216 for encryption. All data is encrypted using the same device internal pFail key. The pFail key is already prepared and therefore does not increase latency. After the 4K aligned data is encrypted with the pFail key, the data is sent to the PAC 218.

[0054] Then, at block 412, all data present in PAC 218 is merged to achieve 16K alignment. Then, at decision block 414, the controller determines whether all merged data is 16K aligned. If the merged data is not 16K aligned, the flow moves to block 416.

[0055] The merged data that is not 16K aligned is filled with dummy data at block 416. Since the data is not stored in the destination, one bit per cell is sufficient for the temporary.

[0056] Finally, at block 418, all 16K aligned data in the PAC 218 is sent to the memory device 206 to be written before total power is lost.

[0057] Figure 5 5 is a flow chart 500 illustrating a power up operation following a power down cache fetch operation according to one embodiment. For ease of description, the power up operation is described with reference to SSD system 200, although any suitable data storage device may be used.

[0058] The process starts at block 502. When power is restored, flow proceeds to block 504 where the controller detects the presence of the pFail key. Then, at block 506, data is read from the memory device 206 that was earlier stored to the memory device 206 using the pFail key during the power-off cache fetch operation.

[0059] At block 508, the data read back from the memory device 206 is checked for 4K alignment, and any data found to be 4K aligned is placed in the PAC 218. At block 510, the unaligned data read back from the memory device 206 is placed back into the XTS cache 214. Once all data written to the memory device 206 during the power-off cache fetch operation has been read back from memory into the XTS cache 214 and PAC 218, the flow ends at block 512.

[0060] Figure 6 6 is a schematic diagram of a memory system 600 according to one embodiment. Data from the host 202 is transferred to the controller 602 using a host interface module (HIM) 604. The controller 602 contains an internal processor 606. Data is sent from the HIM 604 to both the command scheduler 608 and the cache 612. The command scheduler 608 keeps track of the read and write operations of the system. The cache 612 acts as a buffer for the encryption / decryption engine 614. Once the data is encrypted, the data is sent to the data path ECC, RAID 616, and then to the FIM 610 to transfer the data to the memory device 206.

[0061] XTS Key 618 has a table of dedicated keys, including one for power failure scenarios. In these scenarios, the power failure key is used to speed up the refresh process while using power provided by the capacitor. Without the pFail key, the device may need to obtain the real encryption key from the memory device 206, resulting in further delays and power consumption.

[0062] Data encrypted and stored during the power outage may be identified from the pFail encryption. Any data encrypted with the pFail key may be identified as pFail data 620. Before power is restored, pFail data 620 is stored in memory device 206 and the data may be restored to the data state prior to the power loss.

[0063] By allowing the controller to use an internal pFail key to store data within the SLC, the time required to enter power down is greatly reduced. The main advantage of reducing the time required is that the required capacitors can be smaller and therefore reduce the bill of materials.

[0064] Figure 7 700 is a flow chart of a power-off cache fetch operation according to another embodiment. For ease of description, the power-off cache fetch operation is described with reference to the SSD system 200, but any suitable data storage device may be used.

[0065] The process begins at block 702 where the controller detects a power loss event. When a power loss is detected, any data remaining in the volatile memory needs to be flushed and written to the non-volatile memory to prevent data loss.

[0066] At block 704, the controller checks the XTS cache 214 to see if there is any remaining data that needs to be flushed. If there is no data in the XTS cache 214 at block 706, then at block 708, there is no data to be flushed from the XTS cache, and the flow continues to block 722 to check the PAC 218 for data to be flushed.

[0067] If the data is found in the XTS cache 214 at block 706, flow proceeds to decision block 710 to check if the data is 4K aligned Flash Management Unit (FMU). If the data found in the XTS cache 214 is 4K aligned, the 4K FMU is sent to the XTS 216 engine for encryption at block 712. If the data is not 4K aligned, flow continues to block 714.

[0068] At block 714, the unaligned data is grouped together, regardless of any typical requirement for contiguous LBAs, in order to quickly form as few 4K aligned FMUs as possible to encrypt during a power loss event. The goal is to reduce the number of encryptions required, thereby reducing the total power and time required for a power outage.

[0069] At decision block 716, the controller determines whether any FMU in the XTS cache 214 is filled to achieve 4K alignment. Any 4K aligned FMU is sent to be encrypted at block 712, and at block 718, any FMU that is still not 4K is filled with dummy data and then sent to be encrypted at block 712.

[0070] For all FMUs that require encryption during the power outage, a single pFail key is used to perform encryption at block 712. Using a single pre-generated key eliminates the need to generate or read conventional encryption keys from the memory device 206, thereby saving valuable time.

[0071] Next, at block 720, the pFail encrypted FMU is sent to the PAC 218. At decision block 722, the controller checks to see if there is enough data in the PAC 218 to form a 16K aligned page. If there is enough data to form a 16K aligned page, then at block 726, the data is grouped together and written to the memory device 206. If there is not enough data, then the flow continues to block 724.

[0072] At block 724, the controller fills the grouped FMUs in the PAC 218 with dummy data to achieve 16K alignment. Because the information filled is not important, the filling only requires storing a single bit per cell to reduce the time required. Then, at block 726, the filled 16K aligned page is written to the memory device 206 before the device is fully powered off.

[0073] By grouping together unaligned data or data smaller than the Flash Management Unit (FMU) size, the amount of padding required to reach the FMU size is reduced. In addition, the amount of data to be encrypted is also reduced. Therefore, data refresh operations require less power. As a result, smaller capacitors can be used to reduce the bill of materials (BOM).

[0074] For example, the host may send a single command or seven separate commands including LBAs 0, 8, 16, 24, 32, 40, and 48. Typically, the LBAs are not grouped together for 4K alignment because they are not contiguous LBAs. Therefore, the LBAs remain in the XTS cache. Initially, in the event of a power loss, the seven LBAs would need to be individually populated to achieve 4K alignment, and all seven populated FMUs would need to be encrypted by seven unique encryption keys. According to the present disclosure, in the event of a power loss, the seven LBAs can be grouped together without regard to any contiguous requirements. Seven LBAs still need to be populated to achieve a 4K aligned FMU, but only a single LBA fill is used. Then, a single FMU is sent to encrypt with a pre-generated pFail key. In this example, seven fill and encryption instances were not performed before the power failure, but only one fill and encryption instance was performed, which is both faster and uses less power.

[0075] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine that a first cache contains data; determine that at least some of the data in the first cache is misaligned; combine the misaligned first cache data; and send the combined misaligned first cache data to the memory device. The controller is further configured to detect a power loss, and wherein the determination that the first cache contains data is performed in response to detecting the power loss. The controller is further configured to: determine whether the combined misaligned first cache data has a size equal to a flash management unit (FMU); and fill the combined misaligned first cache data with dummy data to form the FMU. The controller is further configured to send the combined misaligned first cache data to an encryption unit to encrypt the combined misaligned first cache data before sending the combined misaligned first cache data to the memory device. The controller is configured to create a pFail key for the encrypted combined misaligned first cache data. The controller is further configured to identify data encrypted by the pFail key. The encryption unit is an XTS encryption unit. The controller is further configured to send the encrypted combined misaligned first cache data to a second cache. The controller is further configured to determine whether the data in the second cache matches the page size when combined. The controller is configured to combine the encrypted combined unaligned first cache data with one or more of the second cache data and the dummy data to reach the page size.

[0076] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: detect that power-on has occurred; check data stored using a pFail key in the memory device; read data associated with the pFail key from the memory device, wherein the read data is unaligned; and place the unaligned read data in a first cache. The unaligned read data is encrypted. The controller is further configured to decrypt the encrypted unaligned read data before placing the unaligned read data in the first cache. The controller is further configured to cache the pFail key before reading the data. The controller is further configured to store the aligned data in a second cache. The aligned data in the second cache is encrypted. The read data includes dummy data.

[0077] In another embodiment, a data storage device includes: a memory component; and a controller coupled to the memory component, wherein the controller is configured to: combine non-contiguous logical block address (LBA) data stored in a cache into data packets, wherein the cache is different from the memory component; and store the data packets in the memory component, wherein the combining and storing are responsive to a power failure event. The controller is configured to add dummy data to the non-contiguous LBA data to create the data packets. The controller is further configured to: detect a power-on event; and write the data packets to the cache using a pFail key.

[0078] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, comprising: Memory devices; and a controller coupled to the memory device, wherein the controller is configured to: determining that a first cache contains data; determining that at least some data in the first cache is misaligned; combining the unaligned first cache data; and The combined unaligned first cache data is sent to the memory device.

2. The data storage device of claim 1, wherein the controller is further configured to detect a loss of power, and wherein the determining that the first cache contains data is performed in response to the detecting a loss of power.

3. The data storage device according to claim 1, wherein: The controller is further configured to: determining whether the combined unaligned first cache data has a size equal to a flash management unit (FMU); and The combined unaligned first cache data is filled with dummy data to form the FMU.

4. The data storage device of claim 1 , wherein the controller is further configured to send the combined unaligned first cache data to an encryption unit to encrypt the combined unaligned first cache data before sending the combined unaligned first cache data to the memory device. 5 . The data storage device of claim 4 , wherein the controller is configured to create a pFail key for the cryptographically combined misaligned first cache data. 6 . The data storage device of claim 5 , wherein the controller is further configured to identify data encrypted by the pFail key.

7. The data storage device of claim 4, wherein the encryption unit is an XTS encryption unit.

8. The data storage device of claim 4, wherein the controller is further configured to send the encrypted combined unaligned first cache data to a second cache.

9. The data storage device of claim 8, wherein the controller is further configured to determine whether the data in the second cache, when combined, matches a page size.

10. The data storage device of claim 9, wherein the controller is configured to combine the encrypted combined unaligned first cache data with one or more of second cache data and dummy data to reach the page size.

11. A data storage device, comprising: Memory devices; and a controller coupled to the memory device, wherein the controller is configured to: Detect that power-on has occurred; Checking the storage device for data stored using the pFail key; reading data associated with the pFail key from the memory device, wherein the read data is unaligned; as well as The unaligned read data is placed in a first cache.

12. The data storage device of claim 11, wherein the unaligned read data is encrypted.

13. The data storage device of claim 12, wherein the controller is further configured to decrypt the encrypted unaligned read data before placing the unaligned read data in the first cache.

14. The data storage device of claim 11, wherein the controller is further configured to cache the pFail key before reading the data. 15 . The data storage device of claim 11 , wherein the controller is further configured to store the aligned data in the second cache.

16. The data storage device of claim 15, wherein the aligned data in the second cache is encrypted.

17. The data storage device of claim 11, wherein the read data comprises dummy data.

18. A data storage device, the data storage device comprising: a memory component; and a controller coupled to the memory device, wherein the controller is configured to: grouping non-contiguous logical block address (LBA) data stored in a cache memory distinct from the memory component into data packets; as well as The data packets are stored in the memory component, wherein the combining and storing is responsive to a power failure event.

19. The data storage device of claim 18, wherein the controller is configured to add dummy data to the non-contiguous LBA data to create the data grouping.

20. The data storage device of claim 18, wherein the controller is configured to: Detect power-on events; decrypting using the pFail key; and The data packet is written to the cache.

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