X-direction partition sub-block mode in NAND

Abstract

A memory system having an x-direction (bit line direction) split sub-block pattern is described. Each block is divided in the y-direction and x-direction into a plurality of contiguous NAND string groups, referred to as XY sub-blocks. The memory system performs memory operations in parallel in a plurality of XY sub-blocks in a block while inhibiting the memory operations in other XY sub-blocks in the block. Each XY sub-block on which the memory operation is performed has its NAND string connected to a different group of contiguous bit lines. In an aspect, the memory operation is a program operation in which selected memory cells are programmed in parallel in each XY sub-block of the plurality of XY sub-blocks while all memory cells in all other XY sub-blocks in the block are inhibited from being programmed. In one aspect, the memory operation is an erase operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 358,654, filed with the U.S. Patent and Trademark Office on July 25, 2023, entitled “X-DIRECTION DIVIDED SUB-BLOCK MODE IN NAND,” and is incorporated herein by reference in its entirety for all purposes, which U.S. non-provisional application claims priority to U.S. Provisional Application No. 63 / 477,355, filed on December 27, 2022. Background Art

[0003] The present disclosure relates to non-volatile memory.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0005] The memory structure in the memory system usually contains many memory cells and various control lines. The memory structure can be three-dimensional. One type of three-dimensional structure has non-volatile memory cells arranged as vertical NAND strings. The memory structure can be arranged into units commonly referred to as blocks. For example, a block in a NAND memory system contains many NAND strings. The NAND string includes memory cell transistors connected in series, a drain side selection gate at one end, and a source side selection gate at the other end. Each NAND string is associated with a bit line. The block usually has many word lines that provide voltage to the control gate of the memory cell transistor. In some architectures, each word line is connected to the control gate of a memory cell on each corresponding NAND string in the block. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0008] Figure 2A is a block diagram of one embodiment of a memory die.

[0009] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0011] Figure 4A is a perspective view of a portion of an example embodiment of a monolithic three dimensional memory structure.

[0012] Figure 4B is a block diagram illustrating an example organization of one plane of the memory structure.

[0013] Figure 4C It is a depiction Figure 4B FIG. 4 is a block diagram of a top view of a portion 407 of one of the X sub-blocks in FIG.

[0014] Figure 4D Describe along Figure 4C Cross-sectional view of the block at line AA.

[0015] Figure 4E Describe along Figure 4C Cross-sectional view of the block along line BB.

[0016] Figure 5A One embodiment of a source side selection layer for a block is depicted.

[0017] Figure 5B One embodiment of the source line (SL) layer of a depiction block.

[0018] Fig. 6A Describe along Figure 4C A cross-sectional view of an embodiment of the block along line AA.

[0019] Figure 6B One implementation of a source line (SL) layer is depicted for a block having two source lines.

[0020] Figure 6C One embodiment of a source line (SL) layer for a block having a source line for each XY sub-block is depicted.

[0021] Fig.6D Describe along Figure 4C A cross-sectional view of an embodiment of the block along line BB.

[0022] Figure 7 Further details of a portion of one implementation of a NAND string are depicted.

[0023] Figure 8 A flow chart depicting one embodiment of a process for performing memory operations in parallel in multiple XY sub-blocks in a block.

[0024] Fig. 9A flow chart depicting one embodiment of a process for performing programming operations in parallel in multiple XY sub-blocks in a block.

[0025] Fig.10 A flow chart depicting one embodiment of a process for performing programming operations in parallel in multiple XY sub-blocks in a block, where each XY sub-block has its own source line.

[0026] Fig.11 A flow chart depicting one embodiment of a process for performing erase operations in parallel in multiple XY sub-blocks in a block.

[0027] Fig.12 A flow chart depicting one embodiment of a process for performing erase operations in parallel in multiple XY sub-blocks in a block, where each XY sub-block has its own source line. DETAILED DESCRIPTION

[0028] Disclosed herein is a technology for a memory system having an x-direction sub-block pattern. The x-direction is the direction in which a single bit line extends across a block. In an embodiment, the memory system has a three-dimensional memory structure having a plurality of blocks. Each block has a word line and a select line. Each block has a NAND string extending through the block in the z-direction. Each word line of the block is connected to each NAND string in the NAND string. Therefore, the operating voltage applied to the word line can potentially affect (e.g., program, erase) the memory cells on each NAND string in the block. The block is divided into a plurality of adjacent NAND string groups referred to herein as XY sub-blocks in the y-direction and the x-direction. The memory system performs memory operations in parallel in a plurality of XY sub-blocks in the block, while prohibiting the memory operations in other XY sub-blocks in the block. Each XY sub-block on which the memory operation is performed has its NAND string connected to adjacent bit lines of different groups.

[0029] In one embodiment, the memory operation is a program operation. Selected memory cells are programmed in each XY sub-block of the plurality of XY sub-blocks in parallel while all memory cells in all other XY sub-blocks in the block are inhibited from being programmed. In one embodiment, the memory operation is an erase operation. Memory cells in each XY sub-block of the plurality of XY sub-blocks are erased in parallel while all memory cells in all other XY sub-blocks in the block are inhibited from being erased.

[0030] Figure 11 is a block diagram of one embodiment of a storage system 100 that implements the techniques described herein. In one embodiment, the storage system 100 is a solid state drive ("SSD"). The storage system 100 may also be a memory card, a USB drive, or other types of storage systems. The techniques of the present invention are not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but is connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0031] Figure 1 The components of the storage system 100 depicted in FIG. 1 are electronic circuits. The storage system 100 includes a memory controller 120 (or storage device controller) connected to a non-volatile storage device 130 and a local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). The local memory 140 is a non-transient memory that may include a volatile memory or a non-volatile memory. The memory controller 120 uses the local high-speed memory 140 to perform certain operations. For example, the local high-speed memory 140 may store logic in a physical address translation table ("L2P table").

[0032] The memory controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and local memory controller 164 are connected to and communicate with NOC 154. Local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0033] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0034] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory dies as desired. In order to implement such a system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An example implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in the storage device 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed memory 140.

[0035] The memory interface 160 communicates with the non-volatile storage device 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to one or more memory dies and receiving data from one or more memory dies.

[0036] In one embodiment, non-volatile storage 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including a non-volatile storage device 130. Each of the one or more memory dies of the non-volatile storage device 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are circuits. The memory die 200 includes a memory structure 202 (e.g., a memory array), which may include non-volatile memory cells (also referred to as non-volatile storage device cells), as described in more detail below. The array terminal lines of the memory structure 202 include one or more various word line layers organized into rows, and one or more various bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output of which is connected to the corresponding word lines of the memory structure 202. The row control circuit 220 receives a group of M row address signals and one or more various control signals from the system control logic circuit 260, and may generally include circuits such as a row decoder 222, an array driver 224, and a block selection circuit 226 for both read operations and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210, which includes a read / write circuit 225. The read / write circuits 225 may contain sense amplifiers and data latches. One or more sense amplifier inputs / outputs are connected to corresponding bit lines of the memory structure 202. Although only a single block is shown for the structure 202, the memory die may include multiple arrays that can be accessed separately. The column control circuit 210 receives a group of N column address signals and one or more various control signals from the system control logic 260, and may generally include circuits such as a column decoder 212, an array terminal receiver or driver circuit 214, a block select circuit 216, and read / write circuits and I / O multiplexers.

[0037] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is implemented entirely in hardware (e.g., electronic circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 260 may also include a power control module 264 that controls the power and voltage provided to the rows and columns of the memory structure 202 during memory operations. The system control logic 260 includes a storage device 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory structure 202.

[0038] Commands and data are transmitted between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0039] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on a different die than the die containing memory structure 202.

[0040] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0041] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR-type flash memory) may also be used.

[0042] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0043] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0044] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated.

[0045] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be disabled by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0046] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0047] Figure 2AThe components of the invention can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuits, which include Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuits. This can place quite severe constraints on these elements of the peripheral circuits. For example, the need to fit sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 260, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuits.

[0048] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and trade-offs when implementing different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, and the peripheral circuits are often CMOS-based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic unit 260 often use PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures can benefit from specialized processing operations in particular.

[0049] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 can be separated into separately formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Then some or all of the circuits in the peripheral circuits (even including elements such as decoders and sense amplifiers) can be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are confined to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily combined can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to the peripheral components on the other die. For example, although the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0050] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 can be used to implement the non-volatile storage device 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory structure die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory structure die 201. In some embodiments, the memory structure die 201 and the control die 211 are bonded together.

[0051] Figure 2B An example of peripheral circuitry is shown, including control circuits formed in peripheral circuit or control die 211 coupled to memory structures 202 formed in memory structure die 201. Common components are shown in a similar manner to Figure 2ASystem control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory structure die 201. In some embodiments, a portion of the circuitry in system control logic 260 is located on memory structure die 201.

[0052] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by conventional processes (e.g., CMOS processes), so that adding elements and functions more commonly found on the memory controller 120, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may also be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, while removing such circuits from a die (such as the memory structure die 201) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as the control die 211) may not require many additional process steps. Since some or all of the control circuits 260, 210, 220 are implemented using CMOS technology, the control die 211 may also be referred to as a CMOS die.

[0053] Figure 2B Column control circuitry 210 including read / write circuitry 225 on control die 211 is shown coupled to memory structure 202 on memory structure die 201 via electrical path 206. For example, electrical path 206 may provide electrical connections between column decoder 212, driver circuit 214, block selector 216, and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory structure die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical path 206 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220 (including row decoder 222, array driver 224, and block selector 226) is coupled to memory structure 202 via electrical path 208. Each of the electrical paths 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory structure die 201 .

[0054] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, power control 264, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, read / write circuitry 225, sense amplifiers, microcontrollers, microprocessors, and / or other similar functional circuits. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, an FPGA, an ASIC, an integrated circuit, or other types of circuitry.

[0055] For purposes of this document, the term “device” may include, but is not limited to, one or more of the memory system 100 , the memory device 130 , the memory die 200 , the integrated memory component 207 , and / or the control die 211 .

[0056] In some embodiments, there is more than one control die 211 and more than one memory structure die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory structure dies 201. Figure 3A A side view of one embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory structure dies) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are more than three memory structure dies 201 and more than three control dies 211. Figure 3A In the embodiment, there are an equal number of memory structure dies 201 and control dies 211; however, in one embodiment, there are more memory structure dies 201 than control dies 211. For example, one control die 211 can control multiple memory structure dies 201.

[0057] Each control die 211 is attached (e.g., bonded) to at least one of the memory structure dies 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280.

[0058] The integrated memory components 207 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., formed to Figure 3A ).

[0059] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0060] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory component 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0061] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are far more than three memory structure dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory structure die 201. Optionally, the control die 211 can be bonded to two or more memory structure dies 201.

[0062] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3BThe integrated memory component 207 in FIG. 2 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201 . Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211 .

[0063] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0064] As briefly discussed above, the control die 211 and the memory structure die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In an embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term can also be applied to the case where the bonding pads are formed by materials other than copper.

[0065] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size of the bonding pad and the spacing between the bonding pads can be further reduced. The film layer is arranged around the bonding pad. When the die are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technology can be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller sizes and spacings.

[0066] Some embodiments may include a film on the surface of the dies 201, 211. If such a film is not initially provided, the space between the dies may be underfilled with epoxy or other resins or polymers. The underfill material may be applied as a liquid and then allowed to harden into a solid layer. This underfill step protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials may be used as underfill materials.

[0067] Figure 4A is a perspective view of a portion of an example embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4A A portion 401 of a block of memory is shown. The depicted structure includes a set of bit lines BL located above a stack 403 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is labeled D and one of the conductive layers (which may include word line layers and select line layers) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. A source line layer SL is located below the alternating dielectric and conductive layers. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, the memory hole is labeled MH. Note that in Figure 4A In the , dielectric layers are depicted as see-through so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits.

[0068] exist Figure 4A In the embodiment, the topmost conductive layer is a drain side select gate layer (SGD), and the bottommost conductive layer is a source side select gate layer (SGS). In some embodiments, more than one conductive layer operates as SGD and / or more than one conductive layer operates as SGS. Figure 4A An insulating region 405 is shown extending in the y-direction to divide the SGD layer into two regions. There may be more of these insulating regions 405 to separate the SGD layer into more than two regions. Figure 4A An insulating region 409 is shown extending in the y direction to divide the SGS layer into two regions. There may be more of these insulating regions 409 to separate the SGS layer into more than two regions. Figure 4A The separation of the SGD layer and the SGS layer into multiple regions depicted in FIG. 1 divides the block into blocks referred to herein as "Y sub-blocks". The term "Y" is used to indicate that the block is cut in the y direction. In some embodiments, the SGD and SGS are also cut in the x direction. Figure 4AThe x-direction cuts are not depicted in FIG. 2. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0069] Figure 4B 4 is a block diagram illustrating an example organization of a plane 400 of the memory structure 202. The memory structure 202 may have multiple planes 400. The planes are divided into M blocks. In one example, each plane has about 2000 blocks. However, different numbers of blocks and planes may be used. Each block is divided into a plurality of X sub-blocks. Figure 4B In the example of FIG. 1 , each block is divided into two X sub-blocks, but there may be more than two X sub-blocks in one block. Since the cutting is performed in the x direction, the term “X sub-block” is used. Note that the x direction is the direction in which the bit lines extend (see FIG. 1 ). Figure 4A ). Herein, the term "XY sub-block" is used to describe the intersection of one Y sub-block and one X sub-block. As an example, there may be six Y sub-blocks, two X sub-blocks, and twelve XY sub-blocks per block.

[0070] In one embodiment, the XY sub-block of memory cells is the unit of erasure. That is, all memory cells of the XY sub-block are erased together. In an embodiment, multiple XY sub-blocks in a block are erased in parallel, while erasing in all other XY sub-blocks in the block is prohibited. In other embodiments, the entire block can be the unit of erasure. Memory cells can also be grouped into blocks for other reasons, such as to organize memory structures to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a set of common word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block.

[0071] Figure 4C is a block diagram depicting a top view of a portion 407 of an X sub-block 2a. Figure 4C As can be seen in FIG. 4 , the sub-blocks extend in the direction of arrow 431. In one embodiment, the memory array has many layers; however, Figure 4C Only the top layers (eg, SGD layers) are shown.

[0072] Figure 4C A plurality of circles representing vertical columns are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates / selection gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4CVertical columns 422, 432, 442, 452, 453, and 454 are depicted. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. Vertical column 453 implements NAND string 489. Vertical column 454 implements NAND string 498. More details of these vertical columns are provided below. Since the X sub-block extends in the direction of arrow 431, the X sub-block includes more than Figure 4C More vertical columns are depicted.

[0073] Figure 4C Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4C Twenty-four bit lines are shown because only a portion of the X sub-block is depicted. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the X sub-block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, 452, 453, 454. Note that although columns 422, 432, 442, 452, 453, 454 are physically connected to the bit lines, the NAND string channels of NAND strings 482, 484, 486, 488, 489, 498 are not electrically connected to the bit lines at the same time. Instead, the drain-side select gates on the NAND strings can be used to electrically connect / disconnect the channels of the NAND strings to / from the bit lines.

[0074] Figure 4C The X sub-block depicted in FIG. 4 includes a set of isolation regions 402, 404, 406, 408, 410, 421, and 424, which may be formed of SiO2; however, other dielectric materials may also be used. Isolation regions 402, 404, 406, 408, 410, 421, and 424 are used to divide the top layer into six regions; for example, Figure 4C The top layer depicted in FIG. 4 is divided into regions 420, 430, 440, 450, 460, and 461. Each region 420, 430, 440, 450, 460, and 461 may serve as a drain side select line for a different XY sub-block.

[0075] In one embodiment, isolation regions 402 and 424 separate block 407 from adjacent blocks. Therefore, isolation regions 402 and 424 can extend downward to the substrate. In one embodiment, isolation regions 404, 406, 408, 410, and 421 are divided only for implementing the layer of drain side selection gate, so that NAND strings in different XY sub-blocks can be selected independently. In an example implementation, the bit line is only connected to one vertical column / NAND string in each of regions 420, 430, 440, 450, 460, and 461. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to the NAND strings in six rows in each block. In one embodiment, all six vertical columns / NAND strings connected to the common bit line in the block are connected to the same word line group.

[0076] although Figure 4C Shown in blocks with four vertical columns per region, six regions and 24 vertical columns, but these exact numbers are example implementations. Other embodiments may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Figure 4C It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0077] In one embodiment, the SGS layer will also be divided into the same number of regions as the SGD layer. In one embodiment, the SGS layer of the X sub-block is divided into six regions corresponding to Figure 4C Regions 420, 430, 440, 450, 460 and 461 in the SGD layer depicted in FIG. Further details of the SGS layer are described below.

[0078] Figure 4D Describe along Figure 4C 4. A cross-sectional view of a block taken along line AA in FIG. 4. The memory structure comprises alternating conductive and dielectric layers. The memory cells are arranged in NAND strings that extend in the z-direction through the alternating conductive and dielectric layers. Vertical column / NAND string 422 / 482 is depicted along with other vertical columns / NAND strings. Figure 4D Only a few of the many vertical columns / NAND strings are depicted in FIG. There will typically be many more vertical columns / NAND strings in each X sub-block 433. Also note that Figure 4C , there are many rows of NAND strings in a block (in Figure 4C24 rows in the example in FIG. 1 ). One or more of the conductive layers serve as SGD. One or more of the conductive layers serve as SGS. Other conductive layers may serve as word lines. The word line layers are connected to the memory cells. In an embodiment, each word line layer is connected to each NAND string in a block. The drain side selection layer SGD is used to electrically connect and disconnect (or cut off) the channel of the corresponding NAND string to the bit line. The source side selection layer SGS is used to electrically connect and disconnect (or cut off) the channel of the corresponding NAND string to the source line SL.

[0079] The block is divided into two X sub-blocks 433a, 433b. The bit lines 415 are divided into a first contiguous group 415a extending over the X sub-block 433a and a second contiguous group 415b extending over the X sub-block 433b. The SGD is divided into two sections by the SGD x isolation structure 441. The SGS is divided into two sections by the SGS x isolation structure 443. There may be one or more additional SGD x isolation structures 441 and corresponding one or more additional SGS x isolation structures 443 to divide the block into additional XY sub-blocks 433.

[0080] Figure 4E Describe along Figure 4C 4. A cross-sectional view of a block taken along line BB in FIG. The block is divided into a plurality of Y sub-blocks 439-1, 439-2, 439-3, 439-4, 439-5, and 439-6. Bit line 414 extends across a stack of alternative conductive and dielectric layers. Vertical columns / NAND strings 422 / 482, 432 / 484, 442 / 486, 452 / 488, 453 / 489, and 454 / 490 are depicted with their respective connections to bit line 414. Vertical columns 434 (and Figure 4E The other vertical columns depicted in FIG. 4 are not connected to bit line 414 (see also Figure 4C ). Various isolation structures 402, 404, 406, 408, 410, 421 and 424 are Figure 4E 4. Note that isolation structures 404, 406, 408, 410, and 421 can act as SGD y isolation structures. SGS y isolation structures 437 are also depicted. Each SGS y isolation structure 437 extends in the y direction.

[0081] Figure 5A One embodiment of an SGS layer for a block is depicted. In this example, the SGS layer is divided into twelve separate SGS lines 502-1 to 502-12. Each SGS line is in a different XY sub-block. The dashed lines indicate Figure 4D Each X sub-block 433 is divided into six XY sub-blocks, so that there are 12 XY sub-blocks in this example.

[0082] In an embodiment, the SGD layer of a block is divided in the same manner as the source side select layer. Thus, in an embodiment, the SGD layer is also 12 SGD lines. Note that each XY sub-block contains a different group of contiguous NAND strings. "Contiguous NAND strings" means that the NAND strings are grouped together without intervening NAND strings. Figure 4C Contiguous NAND strings in region 420, contiguous NAND strings in region 430, and so on are shown.

[0083] Figure 5B One embodiment of a source line (SL) layer 510 for a block is depicted. In an embodiment, the block has a single source line 510. Thus, in an embodiment, the same source line 510 is connected to each NAND string in the block. In other embodiments, there is more than one source line in the block.

[0084] Fig. 6A Describe along Figure 4C A cross-sectional view of an embodiment of the block along line AA. Fig. 6A An implementation similar to Figure 4D , but with SGS / SL x isolation structure 643 instead of SGS x isolation structure 443 (see Figure 4D ). refer to Fig. 6A , the SGS / SL x isolation structure 643 divides both the SGS layer and the SL into two regions. The SGS / SL x isolation structure 643 extends in the x direction and may be referred to as an "x-cut". The block is divided into two X sub-blocks 433a, 433b. The bit lines 415 are divided into a first contiguous group 415a extending over the X sub-block 433a and a second contiguous group 415b extending over the X sub-block 433b. The vertical columns / NAND strings 422 / 482 are depicted along with the other vertical columns / NAND strings. There may be more than one SGS / SL x isolation structure 643 and correspondingly more than one SGD x isolation structure 441 to divide the block into more than two X sub-blocks 433.

[0085] Figure 6B One embodiment of the source line (SL) layer of a block is depicted. In this embodiment, the block has two source line regions 600-1, 600-2. One source line region 600-1 is the first X sub-block 433a, and the other source line region 600-2 is the second X sub-block 433b. Thus, in this embodiment, the source line region 600-1 will connect to all NAND strings in the first X sub-block 433a, and the source line region 600-2 will connect to all NAND strings in the second X sub-block 433b. Fig. 6A In the embodiment of the structure of FIG. 6 , the source line has two regions 600 - 1 and 600 - 2 .

[0086] Figure 6C Depicting one embodiment of the source line (SL) layer of a block. In this embodiment, the block has 12 source line regions 602-1 through 602-12. Each source line region 602 is in a different XY sub-block. Thus, in this embodiment, source line region 602-1 will connect to all NAND strings in the first XY sub-block, source line region 602-2 will connect to all NAND strings in the second XY sub-block, and so on. Fig. 6A In an embodiment of the structure, the source line has a separate region for each XY sub-block. For example, the source line may have 12 regions 602-1 to 602-12, such as Figure 6C Described in.

[0087] Fig.6D Describe along Figure 4C A cross-sectional view of an embodiment of the block along line BB. Fig.6D An implementation similar to Figure 4E , but with SGS / SL y isolation structure 637 instead of SGS y isolation structure 437 (see Figure 4E ). The block is divided into a plurality of Y sub-blocks 439-1, 439-2, 439-3, 439-4, 439-5 and 439-6. Fig.6D In an embodiment of the present invention, each XY sub-block has its own source line. Therefore, in an example where there are 12 XY sub-blocks, the source line may have 12 source line regions 602-1 to 602-12.

[0088] Figure 7 Further details of a portion of an embodiment of a NAND string are depicted. Data memory cell transistors 720, 721, 722, 723, and 724 are indicated by dashed lines. Multiple layers may be deposited, for example, along the sidewalls (SW) of the memory hole 734 and / or within each word line layer using atomic layer deposition. For example, each column (e.g., a column formed by the material within the memory hole) may include a blocking oxide / block high-k material 760, a charge trapping layer or film 713 (such as SiN or other nitrides), a tunnel layer 714, a polysilicon body or channel 715, and a dielectric core 716. The word line layer may include a conductive metal 712 (such as tungsten) as a control gate. A portion of the conductive metal 712 adjacent to the cell serves as a control gate. In this example, all layers except the metal are provided in the memory hole. In other methods, some of the layers may be in the control gate layer. Additional columns are similarly formed in different memory holes. The column may form a columnar active area (AA) of the NAND string.

[0089] When programming the data memory cell transistor, electrons are stored in a portion of the charge trapping layer associated with the data memory cell transistor. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the data memory cell transistor increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0090] Each of the memory holes may be filled with a plurality of annular layers (also referred to as memory film layers) including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and the WLL in each of the memory holes. In some cases, the tunnel layer 714 may include a plurality of layers, such as in an oxide-nitride-oxide configuration.

[0091] Figure 8 A flow chart depicting one embodiment of a process 800 for performing memory operations in parallel in multiple XY sub-blocks in a block. Each XY sub-block on which the parallel operation is performed is associated with a different set of adjacent bit lines. In addition, memory operations are prevented (or prohibited) in all other XY sub-blocks in the block. Process 800 will be discussed with respect to the example of a first XY sub-block in a first X sub-block 433a and a second XY sub-block in a second X sub-block 433b; however, if there are more X sub-blocks 433 in a block, memory operations may be performed in parallel on more XY sub-blocks. In one embodiment, the memory operation is a programming operation. In one embodiment, the memory operation is an erase operation. The block will have one or more source lines. In one embodiment, the block has a single source line. In one embodiment, the block has one source line for each X sub-block. In one embodiment, the block has one source line for each XY sub-block.

[0092] Step 802 includes applying voltages to word lines and bit lines to perform a memory operation within a selected block. The term "selected block" as used herein means a block containing memory cells undergoing a memory operation. As will be clear from the discussion, some memory cells in a selected block may be prohibited or prevented from undergoing a memory operation. For example, some XY sub-blocks may be selected for memory operations, while other XY sub-blocks may be prohibited / prevented from undergoing memory operations. In one embodiment, a programming voltage is applied to a selected word line and a boost voltage is applied to unselected word lines. Herein, the term "selected word line" in the context of programming means a word line to which a programming voltage is applied. As will be clear to a person skilled in the art from this description, some memory cells connected to a selected word line ("selected memory cells") will receive programming, while other memory cells connected to the selected word line will be prohibited from programming. In the context of programming, the term "unselected word line" as used herein means a word line to which a programming voltage is not applied, so that no memory cells connected to it receive programming. Also in step 802, a voltage is applied to a bit line to enable programming or to prohibit programming. In conjunction with Fig. 9 and Fig.10 Further details of an embodiment in which the memory operation is a programming operation are described. In one embodiment, an erase voltage is applied to the bit line and an erase enable voltage is applied to the word line. Fig.11 and Fig.12 Further details of an embodiment in which the memory operation is an erase operation are described.

[0093] Step 804 includes applying voltages to source side select transistors in the first XY sub-block and the second XY sub-block to enable memory operations. Note that during a typical NAND programming operation, some memory cells in a group of memory cells undergoing programming will receive programming, but other memory cells in the group may be inhibited due to reasons such as their Vt is already at a target Vt. Enabling memory operations in the context of a programming operation does not require that every memory cell in a group of memory cells undergoing programming will receive programming due to factors such as some memory cells in the group are inhibited due to reasons such as their Vt is already at a target Vt. Step 804 may include applying voltages to control terminals of corresponding source side select transistors via source side select lines (SGS). In Figure 5A In the example of , voltages may be applied to any one of SGS lines 502-1 to 502-6 and any one of SGS lines 502-7 to 502-12. For discussion purposes, an example will be described in which an XY sub-block having SGS lines 502-2 and 502-11 is selected for memory operation. In this example, voltages may be applied to SGS lines 502-2 and 502-11 (see Figure 5A). Step 804 may also include applying voltage to any source lines connected to NAND strings in the first XY sub-block and the second XY sub-block. In one embodiment, voltage is applied to a single source line 510 in a block (see Figure 5B In one embodiment, a voltage is applied to a different source line 600 for each X sub-block in a block (see Figure 6B ). In one embodiment, a voltage is applied to a first source line 602 in a first XY sub-block and a second source line in a second XY sub-block. Figure 6C In the example of FIG. 6A , voltage may be applied to source lines 602 - 2 and 602 - 11 .

[0094] Step 806 includes applying a voltage to source-side select transistors in all other XY sub-blocks in the selected block to inhibit memory operations. Step 806 may include applying a voltage to control terminals of corresponding source-side select transistors through source-side select lines (SGS) of all other XY sub-blocks in the block. Figure 5A In the example of , voltages may be applied to source select lines 502-1, 502-3, 502-4, 502-5, 502-6, 502-7, 502-8, 502-9, 502-10, and 502-12. Step 806 may also include applying voltages to any source lines connected to NAND strings in all other XY sub-blocks. Note that if there is only one source line per block or only one source line per X sub-block, then voltages may be applied in step 804. However, if Figure 6C If the source line layer is divided as in step 806, a voltage different from the voltage applied to source lines 602-2 and 602-11 may be applied to source lines 602-1, 602-3, 602-4, 602-5, 602-6, 602-7, 602-8, 602-9, 602-10, and 602-12.

[0095] Fig. 9 A flow chart depicting one embodiment of a process 900 for performing programming operations in parallel in multiple XY sub-blocks in a block. Process 900 provides further details of an embodiment of process 800. For ease of explanation, the steps are described in a certain order. The steps may be performed in a different order. Some steps may occur simultaneously. In one embodiment of process 900, a block has a single source line. For example, referring to Figure 5B , there is a single source line 510 for the block. In one embodiment of process 900, the block has one source line in each X sub-block. For example, referring to Figure 6B , there is a source line 600-1 for the X sub-block 433a and a source line 600-2 for the XY sub-block 433b. There may be more than two X sub-blocks 433, and thus more than two source lines 600 in a block.

[0096] Step 902 includes applying a first data pattern to a first group of bit lines. Step 904 includes applying a second data pattern to a second group of bit lines. The first group of bit lines may be bit lines 415a. The second group of bit lines may be bit lines 415b. The data pattern may be applied by applying a program enable voltage (e.g., 0V) to bit lines connected to memory cells to receive programming and applying a program inhibit voltage (e.g., 2.2V) to bit lines not connected to any memory cells to receive programming. The program enable voltage will facilitate setting a channel condition (e.g., 0V in the channel) to enable programming of memory cells in a selected XY sub-block that receive a programming voltage. The program inhibit voltage will facilitate setting a boosted channel condition (together with the boost voltage of step 916) to inhibit programming of memory cells in a selected XY sub-block, even if the memory cell receives a programming voltage.

[0097] Step 906 includes applying a select voltage (e.g., Vsgd) to the SGD of the selected XY sub-block. A "select voltage" as defined herein in relation to a drain-side select gate is a voltage used to select the XY sub-block for memory operations. In an embodiment, the select voltage has a magnitude that turns on a drain-side select transistor connected to a bit line receiving a program enable voltage but turns off a drain-side select transistor connected to a bit line receiving a program inhibit voltage.

[0098] Step 908 includes applying a cutoff voltage to the SGD of all unselected XY sub-blocks in the block. A "cutoff voltage" is defined herein as a voltage applied to the control gate of a select transistor that will keep the select transistor off, taking into account the voltage on the bit line of the drain-side select transistor or the voltage on the source line of the source-side select transistor. The cutoff voltage of step 906 has a magnitude that will keep the drain-side select transistors in all unselected XY sub-blocks off. Thus, the channels of all NAND strings in the unselected XY sub-blocks will be electrically disconnected (or cut off) from the bit line.

[0099] Step 910 includes applying a channel inhibit voltage to the source line. In one embodiment, the channel inhibit voltage has a magnitude of about (Vpgm+Vpass) / 2, where Vpgm is the programming voltage and Vpass is a boost voltage discussed below. In one embodiment, the same voltage is applied to the source line in each X sub-block. The channel inhibit voltage will be passed to the channels of the NAND strings in the XY sub-block that will not be programmed. The term "channel inhibit voltage" as defined herein is a voltage that will inhibit programming of a memory cell when present in the channel of a NAND string, regardless of whether the programming voltage or the boost voltage is applied to the control gate of the memory cell and regardless of whether the bit line receives a program enable voltage or a program inhibit voltage. For example, the channel inhibit voltage may have a sufficient magnitude such that the memory cell will be inhibited from programming even if the programming voltage is applied to the control gate of the memory cell.

[0100] Step 912 includes applying a gate-induced drain lowering (GIDL) voltage to the source side select lines of the unselected XY sub-blocks to pass a channel inhibit voltage to the NAND channels in the unselected XY sub-blocks. In one embodiment, the GIDL voltage is about 11.5V less than the voltage applied to the source line. In an embodiment, the combination of the GIDL voltage and the source line voltage will produce a GIDL current. Reference Figure 5A In the example SGS layer in FIG. 1 , a GIDL voltage may be applied to source select lines 502 - 1 , 502 - 3 , 502 - 4 , 502 - 5 , 502 - 6 , 502 - 7 , 502 - 8 , 502 - 9 , 502 - 10 , and 502 - 12 .

[0101] Step 914 includes applying a cutoff voltage to the SGS of the selected XY sub-block to prevent the channel inhibit voltage from passing to the NAND channels in the selected XY sub-block. The cutoff voltage has a magnitude that will keep the source side select transistors in the selected XY sub-block turned off. Thus, the channels of all NAND strings in the selected XY sub-block will be electrically disconnected (or cut off) from the source line. Thus, the channel inhibit voltage on the source line will not affect (e.g., will not inhibit) programming in the selected XY sub-block. Reference Figure 5A For example, a cutoff voltage may be applied to the source selection lines 502-2 and 502-11.

[0102] Step 916 includes applying a boost voltage to the unselected word lines in the selected block. The boost voltage (Vpass) has a magnitude substantially lower than Vpgm. For example, Vpgm may be 20V or higher, while Vpass may be approximately 12V. However, these are merely examples of Vpgm and Vpass, and one skilled in the art will recognize that other magnitudes may be used for programming and boosting. The channels of the NAND strings in the selected XY sub-block that will be inhibited from programming (based on the bit line bias) will float. The boost voltage will couple the potential of the (floating) NAND channels in the selected XY sub-block, which will inhibit programming of the memory cells in the selected XY sub-block that are not to be programmed.

[0103] Step 918 includes applying a programming voltage to the selected word line. Memory cells in the selected XY sub-block on the NAND string connected to the bit line receiving the program enable voltage and connected to the selected word line will receive programming. However, memory cells in the selected XY sub-block on the NAND string connected to the bit line receiving the program inhibit voltage will not receive programming (even if connected to the selected word line). In addition, memory cells in the unselected XY sub-blocks will not receive programming.

[0104] Fig.10 A flow chart depicting one embodiment of a process 1000 for performing programming operations in parallel in multiple XY sub-blocks in a block. Process 1000 provides further details of an embodiment of process 800. For ease of explanation, the steps are described in a certain order. The steps may be performed in a different order. The steps may occur simultaneously. In one embodiment of process 1000, a block has a source line for each XY sub-block. For example, Figure 6C An example source line layer is depicted with source lines 602-1 to 602-12 for each of the 12 XY sub-blocks. However, there may be more or less than 12 XY sub-blocks in a block. Some steps of process 1000 are similar to corresponding steps in process 900 and will only be briefly described.

[0105] Step 1002 includes applying a first data pattern to a first group of adjacent bit lines. Step 1004 includes applying a second data pattern to a second group of adjacent bit lines. Step 1006 includes applying a select voltage (e.g., Vsgd) to the SGD of the selected XY sub-block. Step 1008 includes applying a cutoff voltage to the SGD of all unselected XY sub-blocks in the block.

[0106] Step 1010 includes applying a channel inhibit voltage to the source lines of the unselected XY sub-blocks. Figure 6C, an example in which source line 602-2 and source line 602-11 are in the selected XY sub-block will be discussed. Therefore, in step 1010, a channel inhibit voltage will be applied to source lines 602-1, 602-3, 602-4, 602-5, 602-6, 602-7, 602-8, 602-9, 602-10, and 602-12.

[0107] Step 1012 includes applying a low voltage to the source lines of the selected XY sub-block. The low voltage has a significantly smaller magnitude than the channel inhibit voltage applied to the source lines of the unselected XT sub-blocks. An example of the low voltage is approximately 1.5V. Figure 6C For example, a low voltage will be applied to source lines 602-2 and 602-11.

[0108] Step 1014 includes applying a voltage to the source side select lines of the unselected XY sub-blocks to pass the channel inhibit voltage from the source line to the NAND channels in the unselected XY sub-blocks. In one embodiment, the voltage is about 11.5V less than the voltage applied to the source line. In an embodiment, the combination of this voltage and the source line voltage will produce a gate induced drain lowering (GIDL) current. Reference Figure 5A In the example SGS layer in FIG. 5 , voltages may be applied to source select lines 502 - 1 , 502 - 3 , 502 - 4 , 502 - 5 , 502 - 6 , 502 - 7 , 502 - 8 , 502 - 9 , 502 - 10 , and 502 - 12 .

[0109] Step 1016 includes applying a cutoff voltage to the SGS of the selected XY sub-block to prevent the low voltage from passing to the NAND channels in the selected XY sub-block. The cutoff voltage has a magnitude that will keep the source side select transistors in the selected XY sub-block turned off. Thus, the channels of all NAND strings in the selected XY sub-block will be electrically disconnected (or cut off) from the source line. Thus, the low voltage on the source line will not affect (e.g., will not inhibit) programming in the selected XY sub-block. Reference Figure 5A For example, a cutoff voltage may be applied to the source selection lines 502-2 and 502-11.

[0110] Step 1018 includes applying a boost voltage to unselected word lines in the selected block. Step 1020 includes applying a programming voltage to the selected word line. Memory cells in the selected XY sub-block that are connected to a bit line that receives a program enable voltage and to a NAND string connected to the selected word line will receive programming. However, memory cells in the selected XY sub-block that are connected to a NAND string that receives a bit line that receives a program inhibit voltage will not receive programming (even if connected to the selected word line). In addition, memory cells in unselected XY sub-blocks will not receive programming.

[0111] Fig.11A flow chart depicting one embodiment of a process 1100 for performing erase operations in parallel in multiple XY sub-blocks in a block. Each XY sub-block in the erased XY sub-block is connected to a different set of adjacent bit lines. Process 1100 will prevent erasure of other XY sub-blocks in the block. Process 1100 provides further details of an embodiment of process 800. For ease of explanation, the steps are described in a certain order. The steps may be performed in a different order. The steps may occur simultaneously. In one embodiment of process 1100, the block has a single source line. For example, referring to Figure 5B , there is a single source line 510 in the block. In one embodiment of process 1100, the block has one source line in each X sub-block. For example, referring to Figure 6B , there is a source line 600-1 for the X sub-block 433a and a source line 600-2 for the XY sub-block 433b. There may be more than two X sub-blocks 433, and thus more than two source lines 600 in a block.

[0112] Step 1102 includes applying an erase voltage to a bit line. The bit line may include a first group of adjacent bit lines and a second group of adjacent bit lines. The first group of adjacent bit lines may be bit line 415a. The second group of adjacent bit lines may be bit line 415b. Step 1104 includes applying an erase voltage to a source line. Figure 5B For example, an erase voltage may be applied to source line 510. Figure 6B In an example of , an erase voltage may be applied to source lines 600-1 and 600-2. In an embodiment, the erase voltage (Vera) has a magnitude of approximately 20V.

[0113] Step 1106 includes applying a GIDL voltage (e.g., Vgidl) to the SGD of the selected XY sub-block. In an embodiment, given the magnitude of Vera on the bit line, the GIDL voltage has a magnitude that produces a GIDL current in the drain side select transistor. The GIDL voltage may be about 11.5V lower than the erase voltage. The erase voltage will be passed from the bit line to the channel of the NAND string in the selected XY sub-block.

[0114] Step 1108 includes applying a cutoff voltage to the SGD of all unselected XY sub-blocks in the block. The cutoff voltage has a magnitude that will keep the drain side select transistors in all unselected XY sub-blocks turned off. Thus, the channels of all NAND strings in the unselected XY sub-blocks will be electrically disconnected (or cut off) from the bit lines. An example of a cutoff voltage is 0V.

[0115] Step 1110 includes applying an erase enable voltage to the word lines in the block. Assuming the erase voltage is present in the memory cell channel, the erase enable voltage will enable erasure of the memory cells connected to the word lines. An example magnitude of the erase enable voltage is 0.5V.

[0116] Step 1112 includes applying a GIDL voltage to the source side select line (SGS) of the selected XY sub-block to pass the erase voltage from the source line to the NAND channels in the selected XY sub-block. In one embodiment, the voltage is about 11.5V less than the voltage applied to the source line. In an embodiment, the combination of this voltage and the source line voltage will produce a GIDL current. Reference Figure 5A , an example in which the source selection line 502-2 and the source selection line 502-11 are in the selected XY sub-block will be discussed. Therefore, the GIDL voltage may be applied to the source selection lines 502-2 and 502-11.

[0117] Step 1114 includes applying a cutoff voltage to the SGS of the unselected XY sub-blocks to prevent the erase voltage from passing to the NAND channels in the unselected XY sub-blocks. The cutoff voltage has a magnitude that will keep the source side select transistors in the unselected XY sub-blocks off. Therefore, the channels of all NAND strings in the unselected XY sub-blocks will be electrically disconnected (or cut off) from the source line. Therefore, the erase voltage on the source line will not reach the channels of the NAND strings in the unselected XY sub-blocks, thereby preventing erasure of those NAND strings. For example, the cutoff voltage is 0V. Reference Figure 5A , a cutoff voltage may be applied to the source selection lines 502-1, 502-3, 502-4, 502-5, 502-6, 502-7, 502-8, 502-9, 502-10, and 502-12.

[0118] Fig.12 A flow chart depicting one embodiment of a process 1200 for performing erase operations in parallel in multiple XY sub-blocks in a block. Each XY sub-block in the erased XY sub-block is connected to a different set of adjacent bit lines. Process 1200 will prevent erasure of other XY sub-blocks in the block. Process 1200 provides further details of an embodiment of process 800. For ease of explanation, the steps are described in a certain order. The steps may be performed in a different order. The steps may occur simultaneously. In one embodiment of process 1200, the block has a source line for each XY sub-block. For example, Figure 6C An example source line layer is depicted with source lines 602-1 to 602-12 for each of the 12 XY sub-blocks. However, there may be more or less than 12 XY sub-blocks in a block. Some steps of process 1200 are similar to corresponding steps in process 1100 and will only be briefly described.

[0119] Step 1202 includes applying an erase voltage to the bit lines. The bit lines may include a first group of adjacent bit lines and a second group of adjacent bit lines. Step 1204 includes applying an erase voltage to the source lines of the selected XY sub-block. However, no erase voltage is applied to the source lines of the unselected XY sub-blocks. For example, referring to Figure 6CIn an example of , an erase voltage may be applied to source lines 602-2 and 602-11. In an embodiment, the erase voltage (Vera) has a magnitude of approximately 20V.

[0120] Step 1206 includes floating the source lines of the unselected XY sub-blocks. For example, source lines 602-1, 602-3, 602-4, 602-5, 602-6, 602-7, 602-8, 602-9, 602-10, and 602-12 may be floating. In another embodiment, source lines 602-1, 602-3, 602-4, 602-5, 602-6, 602-7, 602-8, 602-9, 602-10, and 602-12 are grounded.

[0121] Step 1208 includes applying a GIDL voltage (e.g., Vgidl) to the SGD of the selected XY sub-block. The erase voltage will be passed from the bit line to the channel of the NAND string in the selected XY sub-block. Step 1210 includes applying a cutoff voltage to the SGD of all unselected XY sub-blocks in the block. An example of a cutoff voltage is 0V.

[0122] Step 1212 includes applying an erase enable voltage to the word lines in the block. An example magnitude of the erase enable voltage is 0.5V. Step 1214 includes applying a GIDL voltage to the source side select line (SGS) of the selected XY sub-block to pass the erase voltage from the source line to the NAND channels in the selected XY sub-block. In one embodiment, the voltage is about 11.5V less than the voltage applied to the source line. In an embodiment, the combination of this voltage and the source line voltage will produce a GIDL current. Reference Figure 5A , the GIDL voltage may be applied to the source selection lines 502 - 2 and 502 - 11 .

[0123] Step 1216 includes applying a cutoff voltage to the SGS of the unselected XY sub-blocks to prevent the erase voltage from being passed to the NAND channels in the unselected XY sub-blocks. For example, the cutoff voltage is 0V. Figure 5A , a cutoff voltage may be applied to source select lines 502-1, 502-3, 502-4, 502-5, 502-6, 502-7, 502-8, 502-9, 502-10, and 502-12. Therefore, the erase voltage on source lines 602-1, 602-3, 602-4, 602-5, 602-6, 602-7, 602-8, 602-9, 602-10, and 602-12 will not reach the channels of NAND strings in unselected XY sub-blocks, thereby preventing erasure of those NAND strings.

[0124] In view of the foregoing, an embodiment includes a device including a three-dimensional memory structure having a plurality of blocks, each block having a plurality of word lines and a selection line. The selection line includes a plurality of source side selection lines and a plurality of drain side selection lines. Each block has a NAND string extending through the block in the z direction. Each NAND string has a memory cell and a selection transistor. Each word line is connected to all NAND strings of the block. Each selection line is connected to a selection transistor on a group of NAND strings including an XY sub-block. Each block has one or more source lines connected to the source terminal of the NAND string of the block. The device also includes a bit line extending across a plurality of blocks in the x direction. The XY sub-block has a plurality of XY sub-block groups, wherein the drain terminal of the NAND string of each XY sub-block group is connected to a different adjacent bit line group. The device also includes one or more control circuits connected to the memory structure and the bit line. The one or more control circuits are configured to perform memory operations in parallel in a plurality of XY sub-blocks while prohibiting memory operations in all other XY sub-blocks in a particular block. Each XY sub-block in a plurality of XY sub-blocks has its drain terminal of its NAND string connected to a different adjacent bit line group.

[0125] In another embodiment, the memory operation comprises a programming operation, and the one or more control circuits are configured to program selected memory cells in each XY sub-block of the plurality of XY sub-blocks in parallel while inhibiting programming of all memory cells in all other XY sub-blocks in the particular block.

[0126] In another embodiment, the one or more control circuits are configured to: apply a channel inhibit voltage to one or more source lines of a particular block; apply a cutoff voltage to source-side select lines of multiple XY sub-blocks to electrically disconnect the one or more source lines from the NAND channels in the multiple XY sub-blocks; and apply a voltage to the source-side select lines of all other XY sub-blocks in the particular block to pass the channel inhibit voltage from the one or more source lines to the channels of the NAND strings in all other XY sub-blocks in the particular block to prevent programming in all other XY sub-blocks in the particular block.

[0127] In another embodiment, the one or more control circuits are configured to apply a programming voltage to selected word lines in a particular block and a boosting voltage to unselected word lines in the particular block. The channel inhibit voltage is approximately half of the sum of the programming voltage and the boosting voltage.

[0128] In another embodiment, the voltage applied to the source side select lines of all other XY sub-blocks in a particular block has a magnitude that produces a gate induced drain lowering (GIDL) current in the source side select transistors in the other XY sub-blocks in the particular block.

[0129] In another embodiment, the memory operation includes an erase operation, and the one or more control circuits are configured to erase the plurality of XY sub-blocks in parallel while inhibiting erasure in all other XY sub-blocks in a particular block.

[0130] In another embodiment, one or more control circuits are configured to: apply an erase enable voltage to word lines in a particular block; apply an erase voltage to one or more source lines of the particular block; apply a voltage to source-side select lines of multiple XY sub-blocks to pass the erase voltage from the one or more source lines to channels of NAND strings in the multiple XY sub-blocks; and apply a cutoff voltage to source-side select lines of all other XY sub-blocks in the particular block to prevent the erase voltage from being passed from the one or more source lines to channels of NAND strings in other XY sub-blocks in the particular block.

[0131] In another embodiment, the one or more source lines of each block include: a first source line associated with a first XY sub-block group whose NAND strings are connected to a first adjacent bit line group; and a second source line associated with a second XY sub-block group whose NAND strings are connected to a second adjacent bit line group.

[0132] In another embodiment, the one or more source lines of each block includes a plurality of source lines, wherein each source line is in a different XY sub-block.

[0133] In another embodiment, the memory operation includes a programming operation, and the one or more control circuits are configured to: apply a channel inhibit voltage to a source line of each XY sub-block in a particular block to be inhibited from programming; apply a voltage lower than the channel inhibit voltage to the source lines of multiple XY sub-blocks; apply a voltage to source-side select lines of the multiple XY sub-blocks to electrically disconnect the source lines of the multiple XY sub-blocks from channels of NAND strings of the multiple XY sub-blocks; and apply a gate induced drain lowering (GIDL) voltage to the source-side select lines of all other XY sub-blocks in the particular block to pass the channel inhibit voltage from the source lines of the other XY sub-blocks to the channels of NAND strings in all other XY sub-blocks in the particular block.

[0134] In another embodiment, the memory operation includes an erase operation, and the one or more control circuits are configured to: float the source line of each XY sub-block in a particular block to be inhibited from erasing; apply an erase voltage to the source lines of the plurality of XY sub-blocks; apply a voltage to the source side select lines of the plurality of XY sub-blocks to pass the erase voltage from the source lines of the plurality of XY sub-blocks to the channels of the NAND strings in the plurality of XY sub-blocks; and apply a cutoff voltage to the source side select lines of all other XY sub-blocks in the particular block to electrically disconnect the source lines from the other XY sub-blocks in the particular block.

[0135] In another embodiment, the memory operation includes an erase operation, and the one or more control circuits are configured to: ground the source line of each XY sub-block in a particular block to be inhibited from programming; apply an erase voltage to the source lines of the plurality of XY sub-blocks; apply a voltage to the source side select lines of the plurality of XY sub-blocks to pass the erase voltage from the source lines of the plurality of XY sub-blocks to the channels of the NAND strings in the plurality of XY sub-blocks; and apply a cutoff voltage to the source side select lines of all other XY sub-blocks in the particular block to electrically disconnect the source lines from the other XY sub-blocks in the particular block.

[0136] One embodiment includes a method for programming a NAND memory. The method includes applying a first data pattern to a first adjacent bit line group connected to a block including a NAND string and applying a second data pattern to a second adjacent bit line group connected to the block including the NAND string. The block includes word lines, each of which is connected to each NAND string of the block. The block includes a first XY sub-block group whose NAND strings are connected to a first set of adjacent bit lines and a second XY sub-block group whose NAND strings are connected to a second set of adjacent bit lines. The method includes applying a programming voltage to a selected word line in the block. The method includes applying a boost voltage to unselected word lines in the block. The method includes applying a channel inhibit voltage to one or more source lines connected to the XY sub-blocks that are to be inhibited from programming. The method includes applying a voltage to a first source side select line connected to source side select gates on NAND strings in a first XY sub-block in a first XY sub-block group and a second source side select line connected to source side select gates on NAND strings in a second XY sub-block in a second XY sub-block group, the voltage enabling programming in the first XY sub-block and the second XY sub-block. The method includes applying a voltage to the source side select line connected to source side select gates on all other NAND strings in the block to pass a channel inhibit voltage from one or more source lines to a channel of a NAND string in all other NAND strings in the block to inhibit programming in all other NAND strings in the block.

[0137] One embodiment includes a nonvolatile storage system, which includes a plurality of bit lines, which include a first adjacent bit line group and a second adjacent bit line group. The storage system includes a three-dimensional memory structure with a plurality of blocks, each block having a NAND string extending through the block in the z direction. Each block has a plurality of word lines. Each word line is connected to all NAND strings in the block. Each block has one or more source lines. Each NAND string has a memory cell, a drain side selection gate connected to a bit line in a plurality of bit lines, and a source side selection gate. Each source side selection gate has a control terminal, a first terminal connected to a channel of the NAND string, and a second terminal connected to a source line in one or more source lines. The storage system also includes one or more control circuits connected to the memory structure and the bit lines. The one or more control circuits are configured to apply voltages to the word lines in the selected block, the first adjacent bit line group, and the second adjacent bit line group to perform memory operations in the selected block. One or more control circuits are configured to apply voltages to control terminals and second terminals of source-side select gates of a first adjacent NAND string group in a selected block connected to a first adjacent bit line group and a second adjacent NAND string group in a selected block connected to a second adjacent bit line group to allow memory operations in the first adjacent NAND string group and the second adjacent NAND string group, and to apply voltages to control terminals and second terminals of source-side select gates of all other NAND strings in the selected block connected to the first adjacent bit line group or the second adjacent bit line group to prevent memory operations in all other NAND strings in the selected block connected to the first adjacent bit line group or the second adjacent bit line group.

[0138] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0139] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0140] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0141] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0142] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0143] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device, comprising: a three-dimensional memory structure having a plurality of blocks, each block having a plurality of word lines and select lines, the select lines comprising a plurality of source-side select lines and a plurality of drain-side select lines, each block having NAND strings extending through the block in a z-direction, each NAND string having a memory cell and a select transistor, each word line connected to all of the NAND strings of the block, each select line connected to select transistors on a group of the NAND strings comprising an XY sub-block, each block having one or more source lines connected to source terminals of the NAND strings of the block; bit lines extending across the plurality of blocks in the x-direction, wherein the XY sub-block has a plurality of XY sub-block groups, wherein drain terminals of the NAND strings of each XY sub-block group are connected to a different adjacent bit line group; and one or more control circuits in communication with the memory structure and the bit lines, wherein the one or more control circuits are configured to: Memory operations are performed in parallel in a plurality of XY sub-blocks while inhibiting the memory operations in all other XY sub-blocks in a particular block, wherein each of the plurality of XY sub-blocks has the drain terminals of its NAND strings connected to a different adjacent group of bit lines.

2. The apparatus of claim 1 , wherein the memory operation comprises a programming operation, and the one or more control circuits are configured to: Selected memory cells are programmed in parallel in each of the plurality of XY sub-blocks while all memory cells in all other XY sub-blocks in the particular block are inhibited from programming.

3. The apparatus of claim 2, wherein the one or more control circuits are configured to: applying a channel inhibit voltage to the one or more source lines of the particular block; applying a cutoff voltage to the source side select lines of the plurality of XY sub-blocks to electrically disconnect the one or more source lines from the NAND channels in the plurality of XY sub-blocks; and A voltage is applied to the source side select lines of all other XY sub-blocks in the particular block to pass the channel inhibit voltage from the one or more source lines to channels of NAND strings in all the other XY sub-blocks in the particular block to prevent programming in all the other XY sub-blocks in the particular block.

4. The device according to claim 3, wherein: The one or more control circuits are configured to: applying a program voltage to a selected word line in the particular block; and applying a boost voltage to unselected word lines in the particular block; and The channel inhibit voltage is approximately half of the sum of the programming voltage and the boosting voltage.

5. The device according to claim 4, wherein: The voltage applied to the source side select line of all other XY sub-blocks in the particular block has a magnitude that produces a gate induced drain lowering (GIDL) current in source side select transistors in the other XY sub-blocks in the particular block.

6. The apparatus of claim 1 , wherein the memory operation comprises an erase operation, and the one or more control circuits are configured to: The plurality of XY sub-blocks are erased in parallel while erasing in all other XY sub-blocks in the particular block is inhibited.

7. The apparatus of claim 6, wherein the one or more control circuits are configured to: applying an erase enable voltage to the word line in the particular block; applying an erase voltage to the one or more source lines of the particular block; applying voltages to the source side select lines of the plurality of XY sub-blocks to pass the erase voltage from the one or more source lines to channels of the NAND strings in the plurality of XY sub-blocks; as well as A cutoff voltage is applied to the source side select lines of all other XY sub-blocks in the particular block to prevent the erase voltage from passing from the one or more source lines to channels of NAND strings in the other XY sub-blocks in the particular block.

8. The apparatus of claim 1 , wherein the one or more source lines of each block comprises: a first source line associated with a first XY sub-block group whose NAND strings are connected to a first adjacent bit line group; and A second source line is associated with a second XY sub-block group whose NAND strings are connected to a second adjacent group of bit lines.

9. The apparatus of claim 1 , wherein the one or more source lines of each block comprises: A plurality of source lines, wherein each source line is in a different XY sub-block.

10. The apparatus of claim 9, wherein the memory operation comprises a programming operation, and the one or more control circuits are configured to: applying a channel inhibit voltage to the source line of each XY sub-block in the particular block to be inhibited from programming; applying a voltage lower than the channel inhibit voltage to the source lines of the plurality of XY sub-blocks; applying a voltage to the source side selection lines of the plurality of XY sub-blocks to electrically disconnect the source lines of the plurality of XY sub-blocks from channels of the NAND strings of the plurality of XY sub-blocks; as well as A gate induced drain lowering (GIDL) voltage is applied to the source side select lines of all other XY sub-blocks in the particular block to transfer the channel inhibit voltage from the source lines of the other XY sub-blocks to channels of NAND strings in all the other XY sub-blocks in the particular block.

11. The apparatus of claim 9, wherein the memory operation comprises an erase operation, and the one or more control circuits are configured to: floating the source line of each XY sub-block in the specific block to be prohibited from being erased; applying an erase voltage to the source lines of the plurality of XY sub-blocks; applying a voltage to the source side select lines of the plurality of XY sub-blocks to transfer the erase voltage from the source lines of the plurality of XY sub-blocks to channels of NAND strings in the plurality of XY sub-blocks; as well as A cutoff voltage is applied to the source-side selection lines of all other XY sub-blocks in the particular block to electrically disconnect the source lines from the other XY sub-blocks in the particular block.

12. The apparatus of claim 9, wherein the memory operation comprises an erase operation, and the one or more control circuits are configured to: grounding the source line of each XY sub-block in the particular block to be inhibited from programming; applying an erase voltage to the source lines of the plurality of XY sub-blocks; applying a voltage to the source side select lines of the plurality of XY sub-blocks to transfer the erase voltage from the source lines of the plurality of XY sub-blocks to channels of NAND strings in the plurality of XY sub-blocks; as well as A cutoff voltage is applied to the source-side selection lines of all other XY sub-blocks in the particular block to electrically disconnect the source lines from the other XY sub-blocks in the particular block.

13. A method for programming a NAND memory, the method comprising: applying a first data pattern to a first set of adjacent bit lines connected to a block including NAND strings and applying a second data pattern to a second set of adjacent bit lines connected to the block including NAND strings, wherein the block includes word lines, wherein each word line is connected to each NAND string of the block, wherein the block includes a first XY sub-block group whose NAND strings are connected to the first set of adjacent bit lines and a second XY sub-block group whose NAND strings are connected to the second set of adjacent bit lines; applying a programming voltage to a selected word line in the block; applying a boost voltage to unselected word lines in the block; applying a channel inhibit voltage to one or more source lines connected to the XY sub-block to be inhibited from programming; applying a voltage to a first source-side select line connected to source-side select gates on NAND strings in a first XY sub-block in the first XY sub-block group and to a second source-side select line connected to source-side select gates on NAND strings in a second XY sub-block in the second XY sub-block group, the voltage enabling programming in the first XY sub-block and the second XY sub-block; as well as A voltage is applied to a source side select line connected to source side select gates on all other NAND strings in the block to pass the channel inhibit voltage from the one or more source lines to the channel of the NAND string in all of the other NAND strings in the block to inhibit programming in all other NAND strings in the block.

14. The method according to claim 13, further comprising: The channel inhibit voltage is applied to one or more source lines connected to the first XY sub-block and the second XY sub-block, wherein applying the voltage to the first source side select line and the second source side select line prevents the channel inhibit voltage from passing from the one or more source lines to the channels of the NAND strings in the first XY sub-block and the second XY sub-block.

15. The method according to claim 13, further comprising: applying a voltage less than the channel inhibit voltage to a first source line of the first XY sub-block and a second source line of the second XY sub-block, wherein applying the voltage to the first source side select line and the second source side select line prevents the voltage less than the channel inhibit voltage from passing from the first source line to the channel of the NAND string in the first XY sub-block and from the second source line to the channel of the NAND string in the second XY sub-block.

16. A non-volatile storage system, comprising: a plurality of bit lines, the plurality of bit lines comprising a first contiguous group of bit lines and a second contiguous group of bit lines; A three-dimensional memory structure having a plurality of blocks, each block having a NAND string extending through the block in a z-direction, each block having a plurality of word lines, each word line connected to all of the NAND strings in the block, each block having one or more source lines, each NAND string having: a memory cell, a drain-side select gate connected to a bit line of the plurality of bit lines, and a source-side select gate, wherein each source-side select gate has a control terminal, a first terminal connected to a channel of the NAND string, and a second terminal connected to a source line of the one or more source lines; and one or more control circuits in communication with the memory structure and the bit lines, wherein the one or more control circuits are configured to: applying voltages to the word lines, the first contiguous group of bit lines, and the second contiguous group of bit lines in a selected block to perform a memory operation within the selected block; as well as A voltage is applied to the control terminal and the second terminal of the source-side selection gates of a first adjacent NAND string group in the selected block connected to the first adjacent bit line group and a second adjacent NAND string group in the selected block connected to the second adjacent bit line group to allow the memory operation in the first adjacent NAND string group and the second adjacent NAND string group, while a voltage is applied to the control terminal and the second terminal of the source-side selection gates of all other NAND strings in the selected block connected to the first adjacent bit line group or the second adjacent bit line group to prevent the memory operation in all other NAND strings in the selected block connected to the first adjacent bit line group or the second adjacent bit line group.

17. The non-volatile storage system according to claim 16, wherein: Each block includes a plurality of source side selection lines, the plurality of source side selection lines including: a first set of source side select lines, each source side select line in the first set connected to the control terminal of a source side select gate of an adjacent group of NAND strings in a first group of adjacent groups of NAND strings connected to the first adjacent group of bit lines; and A second set of source side select lines, each source side select line in the second set connected to the control terminal of the source side select gate of an adjacent group of NAND strings in a second set of adjacent groups of NAND strings connected to the second adjacent group of bit lines.

18. The non-volatile storage system of claim 17, wherein the one or more control circuits are configured to: applying a channel inhibit voltage to the one or more source lines of the selected block; applying a voltage to a first source side select line of the first set of source side select lines, the first source side select line connected to the source side select gates of the first contiguous group of NAND strings to cut off the one or more source lines from the channels of the first contiguous group of NAND strings; applying a voltage to a second source side select line of the second set of source side select lines connected to the source side select gates of the second contiguous group of NAND strings to cut off the one or more source lines from the channels of the second contiguous group of NAND strings; as well as A voltage is applied to the source side select lines connected to all other NAND strings in the selected block to pass the channel inhibit voltage from the one or more source lines to all other NAND strings in the selected block.

19. The non-volatile storage system according to claim 16, wherein: Each block includes a plurality of source lines, the plurality of source lines including: A first set of source lines, each source line in the first set of source lines is connected to the second terminals of the source side select transistors of the first adjacent group of NAND strings connected to the first adjacent group of bit lines; and a second set of source lines, each source line in the second set connected to the second terminal of a source side select transistor of an adjacent group of NAND strings in a second group of adjacent groups of NAND strings connected to the second adjacent group of bit lines; and Each block includes a plurality of source side selection lines, the plurality of source side selection lines including: a first set of source side select lines, each of the first set of source side select lines connected to the control terminal of the source side select transistor of an adjacent group of NAND strings in the first set of adjacent groups of NAND strings; and A second set of source side select lines, each source side select line in the second set connected to the control terminal of the source side select transistor of an adjacent group of NAND strings in the second set of adjacent groups of NAND strings.

20. The non-volatile storage system of claim 19, wherein the one or more control circuits are configured to: applying a channel inhibit voltage to the source line of each contiguous group of NAND strings to be inhibited from programming; applying a voltage lower than the channel inhibit voltage to a first source line connected to the first group of adjacent NAND strings and a second source line connected to the second group of adjacent NAND strings; applying a voltage to the source side select line connected to the source side select transistor of the first contiguous NAND string group to cut the first source line off from the channel of the first contiguous NAND string group; applying a voltage to the source side select line connected to the source side select transistor of the second adjacent NAND string group to cut the second source line off from the channel of the second adjacent NAND string group; and A gate induced drain lowering (GIDL) voltage is applied to the source side select lines connected to all other adjacent NAND string groups in the selected block to pass the channel inhibit voltage from the one or more source lines to all other adjacent NAND string groups in the selected block.

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