Shift register, shift register circuit, display panel and electronic device

Abstract

The embodiment of the invention provides a shift register, a shift register circuit, a display panel and electronic equipment. The shift register comprises an input circuit, a bootstrap circuit and an output circuit, the input circuit is used for obtaining a first input signal and outputting a first voltage control signal according to the first input signal, and the first voltage control signal is used for adjusting the voltage of a first node connected to the input circuit; the bootstrap circuit is used for acquiring a second input signal and outputting a second voltage control signal according to the second input signal, and the second voltage control signal is used for adjusting the voltage of the first node connected to the bootstrap circuit; the output circuit is used for obtaining a third input signal and outputting an output signal according to the third input signal, the third input signal comprises a voltage signal from the first node, the voltage signal comprises a first voltage and a second voltage, the second voltage is lower than the low voltage of the first input signal, and the second voltage is lower than the low voltage of the second input signal. The low voltage of the first input signal is lower than the first voltage. According to the technical scheme, the bias voltage of the terminal of the output circuit can be higher, so that the output rising and falling time is shorter, and a smaller transistor is allowed to keep a narrower frame.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technology, and more specifically, to a shift register, a shift register circuit, a display panel, and an electronic device. Background Art

[0002] Active matrix organic light emitting diode (AMOLED) display is a display technology widely used in many applications such as smartphones, tablets, smart watches and notebook displays. AMOLED displays usually consist of an active area with multiple pixels arranged in an array in rows and columns and a data driver for sequentially providing display data to data lines arranged in the column direction. Gate driver on array (GOA) is a data drive technology in which the data drive circuit is integrated on the array substrate of the display panel. GOA technology can provide a low manufacturing cost drive circuit and a narrow frame.

[0003] The data driving circuit using GOA is also called a GOA circuit or a shift register circuit. The shift register circuit includes a plurality of shift registers, each of which includes a plurality of transistors. Some shift register circuits can generate positive pulses or negative pulses. However, the shift registers in these shift register circuits include a plurality of transistors, which is not conducive to reducing the border of the display. Summary of the invention

[0004] The embodiments of the present application provide a shift register, a shift register circuit, a display panel and an electronic device. The technical solution can provide a narrow frame for the display panel.

[0005] According to a first aspect, an embodiment of the present application provides a shift register, comprising an input circuit, a bootstrap circuit and an output circuit, wherein the input circuit is used to obtain a first input signal and output a first voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust the voltage of a first node connected to the input circuit; the bootstrap circuit is used to obtain a second input signal and output a second voltage control signal according to the second input signal, wherein the second voltage control signal is used to adjust the voltage of the first node connected to the bootstrap circuit; the output circuit is used to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal includes a voltage signal from the first node, and the voltage signal includes: a first voltage and a second voltage, wherein the second voltage is lower than a low voltage of the first input signal, and the low voltage of the first input signal is lower than the first voltage.

[0006] According to the above technical solution, the output circuit is deeply biased with the bootstrap circuit. Using the bootstrap circuit, the input voltage of the output circuit can be pulled down to a second voltage, which is lower than the low voltage of the first input signal. The bias voltage of the output circuit can be lower than the second voltage. The absolute value of the bias voltage Vgs is proportional to the output rise and fall time. Therefore, a lower Vgs (i.e., a larger absolute value) may make the output rise and fall time faster. In addition, according to the basic equation for the on-resistance (Ron) of the transistor, when the absolute value of Vgs becomes smaller (small gate bias voltage), in order to maintain the same Ron value, the transistor channel width should become larger. Therefore, according to the present application, the size of the transistor in the output circuit can be smaller. Correspondingly, the frame of the display panel including the shift register in the first aspect of the present invention can be narrower.

[0007] By convention, the high level signal of the input signal is called VGH, the low level signal of the input signal is called VGL, and the threshold voltage for turning on the transistor in the input circuit is called Vth. 1 , the second voltage Vn1 2 And VGL satisfies: Vn1 2 <VGL<Vn1 3 .

[0008] For example, Vn1 1 , Vn2, VGL and VGH can meet:

[0009] Vn1 1 =VGH;

[0010] Vn1 2 ==VGL–Vth–(VGH–VGL),

[0011] The bias voltage of the output circuit Vgs can be Vgs = 2(VGL – VGH) – Vth. Therefore, if VGL = –5V, VGH = 7V, and Vth = –2V, then Vgs = 2(–5–7) + 2 = –22V. The bias voltage of the output circuit is much higher than the low-level signal of the input signal, making the output rise and fall times faster and allowing smaller transistors to maintain narrower borders.

[0012] In one possible design, the input circuit includes a first transistor, the first input signal includes a first start pulse input signal and a first control signal, the source terminal of the first transistor is used to obtain the first start pulse input signal, the gate terminal of the first transistor is used to obtain the first control signal, and the drain terminal of the first transistor is used to output a first voltage control signal.

[0013] In one possible design, the input circuit includes a first transistor and a second transistor, and the first input signal includes a first start pulse input signal, a first control signal and a fourth control signal, wherein the source terminal of the first transistor is used to obtain the first start pulse input signal, the gate terminal of the first transistor is used to obtain the first control signal, and the gate terminal of the second transistor is used to obtain the fourth control signal; the drain terminal of the first transistor is coupled to the source terminal of the second transistor; and the drain terminal of the second transistor is used to output a first voltage control signal.

[0014] According to the above technical solution, the input unit includes more than one transistor. Therefore, the gate bias voltage stress on each transistor can be reduced. For example, if the input circuit includes only one transistor, the gate bias voltage of the transistor may be 2(VGH–VGL)+Vth. If VGL=–5V, VGH=7V, the gate bias voltage of the transistor may be 22V. However, if the input circuit includes two transistors, for example, a first transistor and a second transistor, the gate bias voltage of the first transistor may be VGH–(VGL–Vth), and the gate bias voltage of the second transistor may be VGL–{VGL–Vth–(VGH–VGL)}. If VGL=–5V, VGH=7V, the bias voltage of the first transistor may be 10V, and the bias voltage of the second transistor may be 10V. Obviously, the gate bias voltage of the transistor in the input circuit is reduced. Therefore, the design difficulty of the input circuit can be reduced.

[0015] In one possible design, the bootstrap circuit includes a third transistor and a first capacitor, and the second input signal includes a second control signal and a voltage signal, wherein the first terminal of the first capacitor is coupled to the gate terminal of the third transistor; the second terminal of the first capacitor is coupled to the drain terminal of the third transistor; the gate terminal of the third transistor is used to obtain the voltage signal; and the source terminal of the third transistor is used to obtain the second control signal.

[0016] In one possible design, the second terminal of the first capacitor is used to output a second start pulse input signal.

[0017] In one possible design, the output circuit includes a fourth transistor, and the third input signal also includes a third control signal, wherein the gate terminal of the fourth transistor is used to obtain the voltage signal, the source terminal of the fourth transistor is used to obtain the third control signal; and the drain terminal of the fourth transistor is used to output the output signal.

[0018] In one possible design, the shift register also includes a charge pump circuit, wherein the charge pump circuit is used to obtain a fourth input signal and output a third voltage control signal based on the fourth input signal; the third input signal also includes a third voltage control signal, and the third voltage control signal includes: a third voltage and a fourth voltage, wherein the fourth voltage is lower than the low voltage of the first input signal, and the low voltage of the first input signal is lower than the third voltage.

[0019] The charge pump unit can generate an additional lower voltage to drive the low-side buffer transistor in the output unit. The output signal of the shift register is periodically discharged to VGL through the transistor. This makes the shift register function stable in variable refresh rate (VRR), especially in 1Hz (ultra-low refresh rate drive).

[0020] In some embodiments, the third voltage may be the same as the first voltage, and the fourth voltage may be the same as the second voltage.

[0021] In some embodiments, the voltage signal further includes a fifth voltage equal to VGL-Vth. The third voltage control signal further includes a sixth voltage equal to the fifth voltage.

[0022] In one possible design, the output circuit includes a fourth transistor and a fifth transistor, and the third input signal also includes a third control signal and a fourth control signal, wherein the drain terminal of the fourth transistor is coupled to the drain terminal of the fifth transistor, and the gate terminal of the fourth transistor is used to obtain a voltage signal; the source terminal of the fourth transistor is used to obtain the third control signal; the drain terminal of the fourth transistor is used to output the output signal; the gate terminal of the fifth transistor is used to obtain the third voltage control signal; and the source terminal of the fifth transistor is used to obtain the fourth control signal.

[0023] In one possible design, the width of the fourth transistor may be 50 μm to 200 μm. In some embodiments, the width of the fourth transistor may be 50 μm to 120 μm. In some embodiments, the width of the fourth transistor may be 60 μm to 80 μm. In some embodiments, the width of the fourth transistor may be 70 μm to 80 μm, for example 72 μm, 75 μm or 77 μm.

[0024] In one possible design, the width of the fifth transistor may be 10 μm to 20 μm. In some embodiments, the width of the fifth transistor may be 15 μm to 20 μm, for example, 18 μm, or 20 μm.

[0025] The output unit includes a path-gate structure, and the path-gate structure includes a fourth transistor and a fifth transistor. The fourth transistor contributes to both charging and discharging of the load. The fifth transistor only needs a small driving capability to keep the output signal of the shift register at VGL during the low level state. The size of the fifth transistor is minimized, thereby maintaining a narrow frame.

[0026] In one possible design, the charge pump circuit includes: a sixth transistor, a seventh transistor, an eighth transistor and a second capacitor, and the fourth input signal includes a second start pulse input signal, a second control signal, a third control signal, a fourth control signal and a fifth control signal, wherein the gate terminal of the seventh transistor is used to obtain the second start pulse input signal; the drain terminal of the sixth transistor is coupled to the gate terminal of the seventh transistor; the source terminal of the sixth transistor and the source terminal of the seventh transistor are used to obtain the fifth control signal; the gate terminal of the eighth transistor is used to obtain the third control signal; the first terminal of the second capacitor is used to obtain the second control signal; the source terminal of the eighth transistor is used to obtain the fourth control signal; the drain terminal of the eighth transistor is coupled to the drain terminal of the seventh transistor and the second terminal of the second capacitor; the second terminal of the second capacitor is used to output a third voltage control signal.

[0027] According to the second aspect, an embodiment of the present application provides a shift register, including an input circuit, a bootstrap circuit and an output circuit, wherein the input circuit is used to obtain a first input signal, and output a first voltage control signal, a second voltage control signal and a third voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust the voltage of the first node, the second voltage control signal is used to adjust the voltage of the second node, and the third voltage control signal is used to adjust the voltage of the third node; the bootstrap circuit is used to obtain the second input signal and output a fourth voltage control signal, wherein the fourth voltage control signal is used to adjust the voltage of the second node; the output circuit is used to obtain the third input signal, and output an output signal according to the third input signal, wherein the third input signal includes a voltage signal from the second node and a voltage signal from the third node.

[0028] The shift register may be an EOA unit in an emission driver on array (EOA) subcircuit. A display panel including the EOA subcircuit may be narrow.

[0029] In one possible design, the input circuit includes an input subcircuit and a charge pump subcircuit, and the first input signal includes a first start pulse input signal and a second start pulse input signal, wherein the input subcircuit is used to output a first voltage control signal according to the first start pulse signal, and the charge pump subcircuit is used to output a second voltage control signal and a third voltage control signal according to the second start pulse input signal.

[0030] In one possible design, the input subcircuit includes a first transistor, and the first input signal also includes a first control signal, wherein the source terminal of the first transistor is used to obtain a first start pulse input signal, the gate terminal of the first transistor is used to obtain the first control signal, and the drain terminal of the first transistor is used to output a first voltage control signal.

[0031] In one possible design, the charge pump subcircuit includes: a second transistor, a third transistor and a first capacitor, and the first input signal also includes a first control signal and a second control signal, wherein the source terminal of the second transistor is used to obtain the second start pulse input signal; the source terminal of the third transistor is used to obtain the second control signal; the gate terminal of the second transistor is used to obtain the first control signal; the drain terminal of the third transistor is used to output the second voltage control signal; the drain terminal of the second transistor is coupled to the gate terminal of the third transistor and the first terminal of the first capacitor; the first terminal of the first capacitor is used to output the third voltage control signal; and the second terminal of the first capacitor is used to obtain the first control signal.

[0032] In one possible design, the output circuit includes a fourth transistor and a fifth transistor, and the third input signal also includes a second control signal and a fourth control signal, wherein the gate terminal of the fourth transistor is coupled to the second node; the gate terminal of the fifth transistor is coupled to the third node; the source terminal of the fourth transistor is used to obtain the second control signal; the source terminal of the fifth transistor is used to obtain the fourth control signal; the drain-source of the fourth transistor is coupled to the drain-source of the fifth transistor; and the drain-source of the fourth transistor is used to output the output signal.

[0033] In one possible design, the width of the transistor may be 50 μm to 200 μm. In some embodiments, the width of the fourth transistor may be 50 μm to 120 μm. In some embodiments, the width of the fourth transistor may be 60 μm to 80 μm. In some embodiments, the width of the fourth transistor may be 70 μm to 80 μm, for example 72 μm, 75 μm or 77 μm.

[0034] In one possible design, the width of the fifth transistor may be 10 μm to 20 μm. In some embodiments, the width of the fifth transistor may be 15 μm to 20 μm, for example, 18 μm, or 20 μm.

[0035] In one possible design, the bootstrap circuit includes a sixth transistor and a second capacitor, and the second input signal includes a voltage signal from a first node and a third control signal, wherein the first terminal of the second capacitor is coupled to the gate terminal of the sixth transistor; the second terminal of the second capacitor is coupled to the drain terminal of the sixth transistor; the gate terminal of the sixth transistor is used to obtain the voltage signal from the first node; the drain terminal of the sixth transistor is coupled to the second node; and the source terminal of the sixth transistor is used to obtain the third control signal.

[0036] According to the third aspect, an embodiment of the present application provides a shift register, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor; the first terminal of the first capacitor is coupled to the drain terminal of the first transistor, the gate terminal of the second transistor, and the gate terminal of the third transistor; the second terminal of the first capacitor is coupled to the drain terminal of the second transistor, the drain terminal of the sixth transistor, and the gate terminal of the fourth transistor; the first terminal of the second capacitor is coupled to the drain terminal of the fourth transistor, the drain terminal of the fifth transistor, the gate terminal of the sixth transistor, and the gate terminal of the seventh transistor; the drain terminal of the seventh transistor is coupled to the drain terminal of the third transistor.

[0037] According to the above technical solution, the output circuit is deeply biased with the bootstrap circuit. Using the bootstrap circuit, the input voltage of the output circuit can be pulled down to a second voltage, which is lower than the low voltage of the first input signal. The bias voltage of the output circuit can be lower than the second voltage. The absolute value of the bias voltage Vgs is proportional to the output rise and fall time. Therefore, a lower Vgs (i.e., a larger absolute value) may make the output rise and fall time faster. In addition, according to the basic equation for the on-resistance (Ron) of the transistor, when the absolute value of Vgs becomes smaller (small gate bias voltage), in order to maintain the same Ron value, the transistor channel width should become larger. Therefore, according to the present application, the size of the transistor in the output circuit can be smaller. Correspondingly, the frame of the display panel including the shift register in the first aspect of the present invention can be narrower.

[0038] By convention, the high level signal of the input signal is called VGH, the low level signal of the input signal is called VGL, and the threshold voltage for turning on the transistor in the input circuit is called Vth. Therefore, the first voltage Vn11, the second voltage Vn12 and VGL satisfy: Vn12 <VGL<Vn13。

[0039] For example, Vn11, Vn2, VGL, and VGH can satisfy:

[0040] Vn11 = VGH;

[0041] Vn12==VGL–Vth–(VGH–VGL),

[0042] The bias voltage of the output circuit Vgs can be Vgs = 2(VGL – VGH) – Vth. Therefore, if VGL = –5V, VGH = 7V, and Vth = –2V, then Vgs = 2(–5–7) + 2 = –22V. The bias voltage of the output circuit is much higher than the low-level signal of the input signal, making the output rise and fall times faster and allowing smaller transistors to maintain narrower borders.

[0043] In one possible design, the width of the third transistor may be 50 μm to 200 μm. In some embodiments, the width of the third transistor may be 50 μm to 120 μm. In some embodiments, the width of the third transistor may be 60 μm to 80 μm. In some embodiments, the width of the third transistor may be 70 μm to 80 μm, for example 72 μm, 75 μm or 77 μm.

[0044] In one possible design, the width of the seventh transistor may be 10 μm to 20 μm. In some embodiments, the width of the seventh transistor may be 15 μm to 20 μm, for example, 18 μm, or 20 μm.

[0045] Furthermore, the shift register includes only 7 transistors and 2 capacitors (hereinafter referred to as a "7T2C shift register"), which will also result in a narrow frame.

[0046] In one possible design, the shift register further includes an eighth transistor having a drain terminal coupled to the source terminal of the first transistor.

[0047] Although the shift register includes additional transistors (i.e., 8 transistors and 2 capacitors, hereinafter referred to as an "8T2C shift register"), the gate bias voltage of the first transistor and the eighth transistor can be reduced. For example, for a 7T2C shift register, the gate bias voltage of the first transistor can be 2(VGH–VGL)+Vth. If VGL=–5V, VGH=7V, the gate bias voltage of the transistor can be 22V. However, for an 8T2C shift register, the gate bias voltage of the first transistor can be VGL–{VGL–Vth–(VGH–VGL)}, and the gate bias voltage of the eighth transistor can be VGH–(VGL–Vth). If VGL=–5V, VGH=7V, the gate bias voltage of the first transistor and the eight transistors can be 10V.

[0048] According to the fourth aspect, an embodiment of the present application provides a shift register, including: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor and a second capacitor; the first terminal of the first capacitor is coupled to the drain terminal of the first transistor and the gate terminal of the third transistor; the second terminal of the first capacitor is coupled to the drain terminal of the third transistor, the drain terminal of the second transistor and the gate terminal of the fifth transistor; the first terminal of the second capacitor is coupled to the gate terminal of the second transistor, the drain terminal of the fourth transistor and the gate terminal of the sixth transistor; the drain terminal of the fifth transistor is coupled to the drain terminal of the sixth transistor.

[0049] The shift register may be an EOA unit in an emission driver on array (EOA) subcircuit. The EOA subcircuit includes only 6 transistors and 2 capacitors. Therefore, a display panel including the EOA subcircuit may be narrow.

[0050] In one possible design, the width of the fifth transistor may be 50 μm to 200 μm. In some embodiments, the width of the fifth transistor may be 50 μm to 120 μm. In some embodiments, the width of the fifth transistor may be 60 μm to 80 μm. In some embodiments, the width of the fifth transistor may be 70 μm to 80 μm, for example 72 μm, 75 μm or 77 μm.

[0051] In one possible design, the width of the sixth transistor may be 10 μm to 20 μm. In some embodiments, the width of the sixth transistor may be 15 μm to 20 μm, for example, 18 μm, or 20 μm.

[0052] According to the fifth aspect, an embodiment of the present application provides a shift register circuit, comprising at least one stage of a shift register in any possible design according to the first aspect or the third aspect, the first stage of the shift register is coupled to a start pulse input signal line, the start pulse input signal line is used to provide a start pulse input signal, each of the remaining stages of the shift register is coupled to the start pulse output terminal of the previous stage of its corresponding shift register, wherein the start pulse output terminal is used to output the corresponding start pulse input signal, and the shift register circuit also includes: a first external control signal line, used to provide a first external control signal to each stage of the shift register; a second external control signal line, used to provide a second external control signal to each stage of the shift register; a first clock signal line, used to provide a first clock signal to each stage of the shift register; a second clock signal line, used to provide a second clock signal to each stage of the shift register; a third clock signal line, used to provide a third clock signal to the odd-numbered stages of the shift register; and a fourth clock signal line, used to provide a fourth clock signal to the even-numbered stages of the shift register.

[0053] The shift register circuit may also be referred to as a GOA circuit. Correspondingly, the shift register in the first aspect and the third aspect may be referred to as a GOA subcircuit or a GOA unit.

[0054] According to a sixth aspect, an embodiment of the present application provides a display panel, comprising a shift register circuit according to the fifth aspect.

[0055] According to a seventh aspect, an embodiment of the present application provides an electronic device, comprising a display panel according to the sixth aspect.

[0056] According to the eighth aspect, an embodiment of the present application provides a shift register circuit, comprising at least one stage of a shift register in any possible design according to the second aspect or the fourth aspect, wherein the first stage of the shift register is coupled to a start pulse input signal line, the start pulse input signal line is used to provide a start pulse input signal, and each of the remaining stages of the shift register is coupled to the start pulse output terminal of the previous stage of its corresponding shift register, wherein the start pulse output terminal is used to output the corresponding start pulse input signal, and the shift register circuit also includes: a first external control signal line, used to provide a first external control signal to each stage of the shift register; a second external control signal line, used to provide a second external control signal to each stage of the shift register; a first clock signal line, used to provide a first clock signal to each stage of the shift register; and a second clock signal line, used to provide a second clock signal to each stage of the shift register.

[0057] The shift register circuit may also be referred to as an EOA circuit. Correspondingly, the shift register in the second aspect and the fourth aspect may be referred to as an EOA subcircuit or an EOA unit.

[0058] According to a ninth aspect, an embodiment of the present application provides a display panel, comprising a shift register circuit according to the eighth aspect.

[0059] According to a tenth aspect, an embodiment of the present application provides an electronic device, comprising a display panel according to the ninth aspect.

[0060] In a possible design, the transistor may be a P-type metal oxide semiconductor (PMOS) transistor.

[0061] In one possible design, the transistor may be a thin-film transistor (TFT). The TFT may be manufactured by a semiconductor process such as low temperature polysilicon (LTPS), low temperature polycrystalline oxide (LTPO), indium gallium zinc oxide (IGZO) or amorphous silicon (aSi).

[0062] In one possible design, the width of the border of the display panel may be 0.8 mm to 1.2 mm, for example, 1.0 mm, or 1.1 mm. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 Schematic diagram of the structure of a shift register according to an embodiment of the present application.

[0064] Figure 2 A schematic diagram of the input circuit is shown.

[0065] Figure 3 A schematic diagram of the structure of the bootstrap circuit is shown.

[0066] Figure 4 A schematic diagram of the output circuit is shown.

[0067] Figure 5 A shift register is shown.

[0068] Figure 6 FIG. 4 is a schematic diagram of the structure of a shift register according to another embodiment of the present application.

[0069] Figure 7A schematic diagram of the structure of a charge pump circuit is shown.

[0070] Figure 8 A schematic diagram of the output circuit is shown.

[0071] Fig. 9 A shift register is shown.

[0072] Fig.10 A shift register is shown.

[0073] Fig.11 Another shift register is shown.

[0074] Fig.12 A timing diagram corresponding to a shift register according to an embodiment of the present application is shown.

[0075] Fig.13 Another timing diagram corresponding to a shift register according to an embodiment of the present application is shown.

[0076] Fig.14 is a schematic diagram of the structure of another shift register according to an embodiment of the present application.

[0077] Fig.15 Schematic diagram of the charge pump circuit.

[0078] Fig.16 Figure 2 is a schematic diagram of the structure of the EOA subcircuit.

[0079] Fig.17 For the corresponding Fig.16 The timing diagram of the EOA subcircuit is shown.

[0080] Fig.18 Schematic diagram of the structure of a shift register circuit according to an embodiment of the present application.

[0081] Fig.19 An example of an even-numbered stage of a shift register is shown.

[0082] Fig. 20 It is a schematic diagram of the structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0083] The technical solution of the present application is described below in conjunction with the accompanying drawings.

[0084] Figure 1 Schematic diagram of the structure of a shift register according to an embodiment of the present application.

[0085] like Figure 1 As shown, the shift register 100 includes an input circuit 110 , a bootstrap circuit 120 , and an output circuit 130 .

[0086] The input circuit 110 includes three terminals, namely, a terminal T11 , a terminal T12 , and a terminal T13 .

[0087] Terminal T11 is used to obtain the start pulse input signal GA(n–1). If the shift register 100 is the first shift register in a shift register circuit including multiple shift registers, the terminal T11 can obtain the start pulse input signal GA(0) from the start pulse input signal line; if the shift register 100 is one of the remaining shift registers in the shift register circuit, the terminal T11 can obtain the start pulse input signal GA(n–1) from the previous shift register. For example, if the shift register 100 is the second shift register in the shift register circuit, the shift register 100 can obtain the start pulse input signal GA(1) from the first shift register in the shift register circuit through terminal T11; if the shift register 100 is the third shift register in the shift register circuit, the shift register 100 can obtain the start pulse input signal GA(2) from the second shift register in the shift register circuit through terminal T11. In some embodiments, the terminal T11 of the input circuit 110 can be referred to as the input terminal of the shift register 100.

[0088] Terminal T12 is used to obtain a control signal.

[0089] Terminal T13 is coupled to the first node. Terminal T13 can output a signal to adjust the voltage of the first node. Therefore, the signal output by terminal T13 can be referred to as a first voltage control signal. The first voltage control signal can pull up or pull down the voltage of the first node according to the control signal obtained from terminal T12 and the start pulse input signal obtained from terminal T11. More specifically, the input circuit 110 may include one or more transistors. The control signal obtained from terminal T12 is used to control the state of the transistor. Therefore, the first voltage control signal output by terminal T13 can correspond to the start pulse input signal obtained from terminal T11 under the control of the control signal obtained from terminal T12.

[0090] The bootstrap circuit 120 includes three terminals, namely, a terminal T21 , a terminal T22 , and a terminal T23 .

[0091] The terminal T21 is coupled to the first node.

[0092] Terminal T22 is used to output the start pulse input signal GA(n). Therefore, the shift register 100 can obtain the start pulse input signal through the terminal T11 of the input circuit, and output the start pulse input signal through the terminal T22 of the bootstrap circuit 120. For convenience, the start pulse input signal obtained by the input circuit 110 can be referred to as the first start pulse input signal, and the start pulse input signal output by the bootstrap circuit can be referred to as the second start pulse input signal. The reason for using the term second start pulse "input signal" to describe the signal output from terminal T22 is that the signal is the start pulse input signal obtained by another shift register in the shift register circuit. For example, if the shift register 100 is the first shift register in the shift register circuit, the shift register 100 can obtain the first start pulse input signal GA(0) from the start pulse input signal line, and output the second start pulse input signal GA(1) to the second shift register in the shift register circuit; if the shift register 100 is the second shift register in the shift register circuit, the shift register 100 can obtain the first start pulse input signal GA(1) from the first shift register, and output the second start pulse input signal GA(2) to the third shift register in the shift register circuit, and so on.

[0093] Terminal T23 is used to obtain a control signal. In some embodiments, the control signal obtained by terminal T23 may be different from the control signal obtained by terminal T12. For convenience, the control signal obtained by terminal T12 may be referred to as a first control signal, and the control signal obtained by terminal T23 may be referred to as a second control signal.

[0094] In some embodiments, the second start pulse input signal output from the terminal T22 corresponds to a second control signal under the first voltage control of the first node.

[0095] In addition, the bootstrap circuit 120 can output a second voltage control signal through the terminal T21. The second voltage control signal is used to adjust the voltage of the first node, and the second voltage control signal corresponds to the second start pulse input signal.

[0096] The output circuit 130 includes three terminals, namely, a terminal T31 , a terminal T32 , and a terminal T33 .

[0097] The terminal T31 is coupled to the first node.

[0098] Terminal T32 is used to obtain a control signal. The control signal obtained by terminal T32 may be different from the control signal obtained by terminal T12 (ie, the first control signal) and the control signal obtained by terminal T23 (ie, the second control signal). For convenience, the control signal obtained by terminal T32 may be referred to as a third control signal.

[0099] The terminal T33 may output an output signal G(n). The output signal G(n) is a driving signal for driving a pixel corresponding to the shift register 100.

[0100] In some embodiments, the output signal G(n) corresponds to a third control signal under the control of the voltage of the first node obtained from the terminal T31.

[0101] Figure 2 A schematic diagram of the input circuit is shown.

[0102] Figure 2 (a) shows an embodiment of the input circuit. Figure 2 (a), the input circuit includes only one transistor M1.

[0103] The source terminal of the transistor M1 is coupled to the terminal T11 of the input circuit; the gate terminal of the transistor M1 is coupled to the terminal T12; and the drain terminal of the transistor M1 is coupled to the terminal T13.

[0104] In some embodiments, the term "coupled to" can be understood as "for". Figure 2 In the input circuit shown in (a), the source terminal of the transistor M1 is the terminal T11, the gate terminal of the transistor M1 is the terminal T12, and the drain terminal of the transistor M1 is the terminal T13.

[0105] Figure 2 (b) shows another embodiment of the input circuit. Figure 2 (b), the input circuit includes two transistors, namely transistor M1 and transistor M8.

[0106] The source terminal of transistor M1 is coupled to terminal T11 of the input circuit, that is, the source terminal of transistor M1 is terminal T11. The drain terminal of transistor M1 is coupled to the source terminal of transistor M8. The drain terminal of transistor M8 is coupled to terminal T13 of the input circuit. Terminal T12 includes two sub-terminals, one of which (first sub-terminal T12-1) is coupled to the gate terminal of transistor M1, and the other sub-terminal (second sub-terminal T12-2) is coupled to the gate terminal of transistor M8. Figure 2 As shown in (b), the control signal acquired by the first sub-terminal T12-1 is different from the control signal acquired by the second sub-terminal T12-2. The control signal acquired by the first sub-terminal T12-1 may be the above-mentioned first control signal. The control signal acquired by the second sub-terminal T12-2 may be called a second external scanning control signal.

[0107] Figure 3 A schematic diagram of the structure of the bootstrap circuit is shown.

[0108] Figure 3(a) shows an embodiment of a bootstrap circuit. Figure 3 As shown in (a), the bootstrap circuit includes a capacitor C1 and a transistor M2.

[0109] The capacitor C1 has a first terminal and a second terminal. The first terminal of the capacitor C1 is coupled to the gate terminal of the transistor M2, and the second terminal of the capacitor C1 is coupled to the drain terminal of the transistor M2. The source terminal of the transistor M2 is coupled to the terminal T23 of the bootstrap circuit, that is, the source terminal of the transistor M2 is the terminal T23. The gate terminal of the transistor M2 is coupled to the terminal T21 of the bootstrap circuit. The drain terminal of the transistor M2 is coupled to the terminal T22 of the bootstrap circuit.

[0110] Figure 3 (b) shows another embodiment of the bootstrap circuit. Figure 3 As shown in (b), two capacitors C11 and C12 are used instead of Figure 3 Capacitor C1 of the bootstrap circuit shown in (a).

[0111] Figure 4 Figure 2 shows the schematic diagram of the output circuit. Figure 4 As shown, the output circuit includes a transistor M3. The gate terminal of the transistor M3 is coupled to the terminal T31 of the output circuit, the source terminal of the transistor M3 is coupled to the terminal T32 of the output circuit, and the drain terminal of the transistor M3 is coupled to the terminal T33 of the output circuit.

[0112] Figure 5 FIG. 1 shows a shift register. Figure 5 As shown, the shift register includes Figure 2 (a) shows the input circuit, Figure 3 The bootstrap circuit shown in (a) and Figure 4 The output circuit is shown.

[0113] Figure 6 FIG. 4 is a schematic diagram of the structure of a shift register according to another embodiment of the present application.

[0114] like Figure 6 As shown, the shift register 600 includes an input circuit 610 , a bootstrap circuit 620 , an output circuit 630 , and a charge pump circuit 630 .

[0115] The connection relationship between the input circuit 610, the bootstrap circuit 620 and the output circuit 630 is the same as that of the shift register. For the convenience and simplicity of description, the details of the connection relationship will not be repeated here.

[0116] like Figure 6As shown, the output circuit further includes a terminal T34 and a terminal T35. The terminal T34 is coupled to the charge pump circuit, and the terminal T35 is used to obtain a control signal. The control signal obtained by the terminal T35 can be called a fourth control signal.

[0117] The charge pump circuit 640 includes three terminals, namely, a terminal T41 , a terminal T42 , and a terminal T43 .

[0118] The terminal T41 is coupled to the second node.

[0119] The terminal T42 is used to obtain a control signal. The details of the control signal obtained by the terminal T42 will be described later.

[0120] The terminal T43 is coupled to the terminal T34 of the output circuit 630. The terminal T43 outputs a third voltage control signal to the output circuit according to the second start pulse input signal acquired from the terminal T41 and the control signal acquired from the terminal T42.

[0121] Figure 7 A schematic diagram of the structure of a charge pump circuit is shown.

[0122] like Figure 7 As shown in (a), the charge pump circuit includes three transistors (ie, transistor M6, transistor M4 and transistor M5) and a capacitor C2.

[0123] The drain terminal of transistor M6 is coupled to the gate terminal of transistor M4. The gate terminal of transistor M4 is coupled to terminal T61 of the charge pump circuit. The drain terminal of transistor M5 is coupled to the first terminal of capacitor C2, and the drain terminal of transistor M5 is coupled to terminal T63 of the charge pump circuit.

[0124] The terminal T62 of the charge pump circuit includes four sub-terminals, ie, a sub-terminal T62 - 1 , a sub-terminal T62 - 2 , a sub-terminal T62 - 3 , and a sub-terminal T62 - 4 .

[0125] The sub-terminal T62-1 is coupled to the source terminal of the transistor M6, the sub-terminal T62-2 is coupled to the gate terminal of the transistor M5, the sub-terminal T62-3 is coupled to the second terminal of the capacitor C2, and the sub-terminal T62-4 is coupled to the source terminal of the transistor M5.

[0126] like Figure 7 As shown in (a), different sub-terminals obtain different control signals. More specifically, sub-terminal T62-1 obtains the fifth control signal, sub-terminal T62-2 obtains the third control signal, sub-terminal T62-3 obtains the second control signal, and sub-terminal T62-4 obtains the fourth control signal.

[0127] Figure 7 (b) shows another charge pump circuit. Figure 7 Compared with the charge pump circuit shown in (a), Figure 7 The charge pump circuit shown in (b) further includes a transistor M8, a transistor M9 and a capacitor C3. Figure 7 As shown in (b), the connection relationship between transistor M4, transistor M5, transistor M6 and capacitor C2 is the same as Figure 7 The connection relationship of the charge pump circuit shown in (a) is the same.

[0128] The gate terminal of transistor M8 is coupled to the second node n2, the source terminal of transistor M8 is coupled to terminal T62-1, and the drain terminal is coupled to the fourth node n4. The gate terminal of transistor M9 is coupled to the drain terminal of transistor M9, and the source terminal of transistor M9 is coupled to the fourth node. The first terminal of the capacitor is coupled to the drain terminal of transistor M9. The first terminal of capacitor C3 is coupled to the fourth node. Figure 7 The charge pump circuit shown in (a) is similar, Figure 7 The charge pump circuit shown in (b) also includes a terminal T61, a terminal T63, and sub-terminals T62-1 to T62-4. Figure 7 The connection relationship between the terminal T61, the sub-terminal T62-1, the sub-terminal T62-3 and the sub-terminal T62-4 of the charge pump circuit shown in (b) is the same as Figure 7 The connection relationship of the charge pump shown in (a) is the same. Figure 7 The sub-terminal T62-2 of the charge pump shown in (b) is coupled to the gate terminal of the transistor M9 and the second terminal of the capacitor C3, and the terminal T63 is coupled to the fourth node n4.

[0129] In some embodiments, Figure 7 The transistor M9 in the charge pump circuit shown in (b) may be replaced by a diode, a cathode terminal of the diode being coupled to the first terminal of the capacitor C2, and an anode terminal of the diode being coupled to the fourth node n4.

[0130] In addition, Figure 7 Compared with the charge pump circuit shown in (a), Figure 7 The charge pump circuit shown in (b) further includes a subcircuit consisting of a transistor M8, a transistor M9, and a capacitor C3. In some embodiments, the charge pump circuit may include more than one such subcircuit. For example, in some embodiments, the charge pump circuit includes two subcircuits, and the connection relationship of the first subcircuit consisting of the transistor M8, the transistor M9, and the capacitor C3 is the same as Figure 7The connection relationship of the subcircuit shown in (b) is the same. For another subcircuit composed of transistor M10, transistor M11 and capacitor C3, the gate terminal of transistor M10 is coupled to the second node n10, the source terminal of transistor M10 is coupled to the source terminal of transistor M8, and the drain terminal of transistor M10 is coupled to the fifth node. The gate terminal of transistor M11 is coupled to the drain terminal of transistor M11, and the source terminal of transistor M1 is coupled to the fifth node. The first terminal of capacitor C4 is coupled to the drain terminal of transistor M11. The first terminal of capacitor C4 is coupled to the fifth node. Terminal T63 is coupled to the fifth node.

[0131] Figure 8 A schematic diagram of the output circuit is shown.

[0132] like Figure 8 As shown, the output circuit includes two transistors, namely, transistor M3 and transistor M7.

[0133] The gate terminal of transistor M3 is coupled to terminal T31 of the output circuit, the source terminal of transistor M3 is coupled to terminal T32 of the output circuit, and the drain terminal of transistor M3 is coupled to the drain terminal of transistor M7. The gate terminal of transistor M7 is coupled to terminal T34 of the output circuit, and the source terminal of transistor M7 is coupled to terminal T35 of the output circuit. Terminal T33 of the output circuit is coupled to the drain terminal of transistor M3.

[0134] In some embodiments, the first to third control signals may be three different clock signals.

[0135] In some embodiments, the first control signal is a first clock signal (hereinafter referred to as "CLK 1"), the second control signal is a second clock signal (hereinafter referred to as "CLK 2"), and the third control signal is a third clock signal (hereinafter referred to as "CLK3").

[0136] In some embodiments, the first control signal is CLK 1, the second control signal is CLK 2, and the third control signal is a fourth clock signal different from CLK 3 (hereinafter referred to as "CLK 4").

[0137] In some embodiments, the fourth control signal is the second external control signal, and the fifth control signal is the first external control signal.

[0138] In some embodiments, the first external control signal is at a constant high level. Therefore, the first external control signal can be referred to as VGH. The second external control signal is at a constant low level. Therefore, the second external control signal can be referred to as VGL.

[0139] Fig. 9 FIG. 1 shows a shift register. Fig. 9 As shown, the shift register 900 includes Figure 2 (a) shows the input circuit, Figure 3 (a) shows the bootstrap circuit, Figure 7 The charge pump circuit shown in (a) and Figure 8 The output circuit is shown.

[0140] Fig.10 FIG. 1 shows a shift register. Fig.10 As shown, the shift register 1000 includes Figure 2 (b) The input circuit shown, Figure 3 (a) shows the bootstrap circuit, Figure 7 The charge pump circuit shown in (a) and Figure 8 The output circuit is shown.

[0141] Optionally, in some embodiments of the present application, the transistor may be a thin film transistor (TFT). In some embodiments, the TFT may be manufactured by a semiconductor process, such as low temperature polysilicon (LTPS), low temperature polycrystalline oxide (LTPO), indium gallium zinc oxide (IGZO) or amorphous silicon (aSi).

[0142] Optionally, in some embodiments of the present application, the transistor may be a P-type metal oxide semiconductor (PMOS) transistor.

[0143] Optionally, in some embodiments of the present application, the transistor may be an N-type metal-oxide-semiconductor (NMOS) transistor.

[0144] Optionally, in some embodiments of the present application, Fig. 9 and Fig.10 The width of transistor M3 shown may be 50 μm to 200 μm. In some embodiments, the width of transistor M3 may be 50 μm to 120 μm. In some embodiments, the width of transistor M3 may be 60 μm to 80 μm. In some embodiments, the width of transistor M3 may be 70 μm to 80 μm, such as 72 μm, 75 μm, or 77 μm.

[0145] Optionally, in some embodiments of the present application, the width of the transistor M7 may be 10 μm to 20 μm. In some embodiments, the width of the transistor M7 may be 15 μm to 20 μm, for example, 18 μm, or 20 μm.

[0146] The length of transistors M3 and M7 is not limited. As an example and not a limitation, the length of transistor M3 or M7 may be 3 μm.

[0147] In some embodiments of the present application, Figure 1 , Figure 5 , Figure 6 , Fig. 9 and Fig.10 The shift register shown can be a unit in a GOA circuit. Therefore, the shift register shown in the above figure can be called a GOA unit.

[0148] Fig.11 Another shift register is shown. Shift register 1100 includes 9 transistors and 2 capacitors (referred to herein as "9T2C").

[0149] Fig.11 The high-side switch transistor M1 shown is biased with only a small voltage: Vgs = VGL - VGH - Vth (i.e., VGL = -5V, VGH = 7V, Vth = -2V, Vgs = -5-7+2 = -10V). The transistor on-resistance of transistor M1 during the on-state is insufficient, giving low drive capability and requiring a larger transistor width. This is a disadvantage when making narrow bezels.

[0150] However, according to the present application, the shift register according to the present application (eg, Figure 1 , Figure 6 , Fig. 9 or Fig.10 The voltage of the first node in the shift register shown in the embodiment of the present invention is determined according to both the input circuit and the bootstrap circuit. Therefore, the voltage of the first node in the shift register according to the present application can be biased to an additional boosted voltage. The voltage of the first node is used to control the output circuit. Therefore, the voltage used to control the state of the transistor in the output circuit can be biased to an additional boosted voltage.

[0151] refer to Fig.12, at point A, capacitor C1 is discharged through transistor M1. The threshold voltage (hereinafter referred to as "Vth") for turning on transistor M1 remains on the first node n1. For convenience, it is assumed that the threshold voltages of all transistors mentioned in this application are the same. Therefore, the voltage of the first node n1 is Vn1=VGL-Vth. When CLK 2 becomes a low level (see point B), the voltage of the first node n1 is further pulled down by the second node n2. The voltage of the first node n1 becomes Vn1=VGL-Vth-(VGH-VGL). When CLK 3 becomes a high level (see point C), the gate bias voltage of transistor M3 is given by Vgs=Vn1-VGH=VGL-Vth-(VGH-VGL)-VGH=2(VGL-VGH)-Vth. If VGL=-5V, VGH=7V, Vth=-2V, then Vgs=2(-5-7)+2=-22V. With Fig.11 Compared to the shift register shown in FIG. 1 , the bias voltage at the gate terminal of transistor M3 is much higher, which makes the output rise and fall times faster and allows a smaller transistor to maintain a narrower frame. According to the basic equation that gives the on-resistance of a transistor, when Vgs becomes smaller (small gate bias voltage), in order to maintain the same Ron value, the transistor channel width should become larger. Therefore, according to the present application, the size of transistor M3 can be smaller. For example, at the same voltage and output load, Fig. 9 or Fig.10 The channel width of transistor M3 shown may be Fig.11 The channel width of transistor M1 is about half of that shown. Fig. 9 or Fig.10 The size of the transistor M3 shown may be 70 μm*3 μm (width*length), Fig.11 The size of the transistor M1 shown may be 140 μm*3 μm.

[0152] In addition, if Fig.10 As shown, the output circuit includes a path-gate structure including transistors M7 and M3. Transistor M3 contributes to both charging and discharging the load. Transistor M7 only needs a small driving capability to keep G(n) at VGL during the low state. The size of transistor M7 is minimized to maintain a narrow frame.

[0153] In some embodiments of the present application, the shift register includes a charge pump circuit. The charge pump circuit can generate an additional low voltage lower than VGL to drive the low-side buffer transistor M7. The output G(n) is periodically discharged to VGL through the transistor M7. This keeps the shift register function stable in a variable refresh rate (VRR), especially in a 1Hz (ultra-low refresh rate drive).

[0154] refer to Fig.13 , at point D, the voltage of the third node n3 is pulled down. Therefore, the voltage of the third node n3 is Vn3 = VGL-Vth; at point E, the voltage of the third node n3 is further pulled down to VGL-Vth-(VGH-VEL). At point F, the gate bias voltage of transistor M7 is given by Vgs = Vn3-VGL = VGL-Vth-(VGH-VGL)-VGL = VGL-VGH-Vth. If VGH = +7V, VGL = -5V, Vth = -2V, Vgs = -5-7-2 = -14V (>Vth), transistor M7 is in the on state to discharge the output G(n) to VGL.

[0155] Fig.13 The timing diagram shown corresponds to Figure 7 (a) shows the charge pump circuit. Figure 7 The charge pump circuit shown in (b) can further pull down the voltage of the gate terminal of transistor M7. Figure 7 In the charge pump circuit shown in (b), the voltage of the third node n3, the voltage of the fourth node n4 and the bias voltage of the transistor M7 satisfy:

[0156] Vn3=VGL–Vth–(VGH–VGL),

[0157] Vn4=Vn3–Vth–(VGH–VGL)=VGL–Vth–(VGH–VGL)–Vth–(VGH–VGL)=3VGL–2Vth–2VGH

[0158] VgsM7=Vn4–VGL=2(VGL–VGH–Vth),

[0159] Wherein, Vn3 is the voltage of the third node, Vn4 is the voltage of the fourth node, and VgsM7 is the gate bias voltage of transistor M7. If VGL=–5V, VGH=7V, Vth=–2V, then VgsM=2(–5–7+2)=–20V.

[0160] Fig.13 The relationship between the control signals is further shown. Fig.12As shown, the duration of tLine is greater than the duration of tWidth1, the duration of tWidth1 is greater than the duration of tWidth2, and the duration of tWidth2 is greater than the duration of tDelay. For example: tLine = 3μs, tWidth1 = 2.6μs, tWidth2 = 1.4μs, tDelay = 0.2μs. It should be noted that the above values ​​of tLine, tWidth1, tWidth2 and tDelay are only examples, and the values ​​of these parameters can be adjusted according to display resolution, frame rate, load, etc.

[0161] Also, if GA(n–1) is from the previous shift register, the width is the same as tWidth1. If GA(0) is the start pulse, the pulse width is wider or the same as tWidth1, which is acceptable.

[0162] In some embodiments of the present application, the input circuit includes more than one transistor. Therefore, the gate bias voltage stress on each transistor can be reduced. For example, Fig. 9 The gate bias voltage of transistor M1 shown can satisfy:

[0163] VgsM1=VGH–{VGL–Vth–(VGH–VGL)}=2(VGH–VGL)+Vth.

[0164] If VGL=–5V, VGH=7V, Vth=–2V, then VgsM1=7–(–5+2–(7+5))=22V.

[0165] However, according to Fig.10 For the input circuit shown, the gate bias voltage of transistor M1 satisfies:

[0166] VgsM1=VGH–(VGL–Vth)

[0167] The gate bias voltage of transistor M8 satisfies:

[0168] VgsM8=VGL–{VGL–Vth–(VGH–VGL)}

[0169] If VGL=–5V, VGH=7V, Vth=–2V, then VgsM1=7+5–2=10V, VgsM8=–5+5–2+7+5=10V. Fig.10 The gate bias voltage stress of transistors M1 and M8 shown is only Fig. 9 The gate bias voltage stress of transistor M1 is shown to be approximately half of that.

[0170] although Figure 2An input circuit is shown comprising a maximum of 2 transistors, but in some embodiments the input circuit may comprise more than 2 transistors.

[0171] Fig.14 is a schematic diagram of the structure of another shift register according to an embodiment of the present application.

[0172] Fig.14 (a) shows a shift register 1400. Fig.14 As shown in (a), the shift register 1400 includes an input circuit 1401, a bootstrap circuit 1420 and an output circuit 1403. The input circuit 1401 outputs a first voltage control signal, a second voltage control signal and a third voltage control signal. The first voltage control signal is used to adjust the voltage of the first node n1, the second voltage control signal is used to adjust the voltage of the second node n2, and the third voltage control signal is used to adjust the voltage of the third node n3. The bootstrap circuit 1420 outputs a fourth voltage control signal for adjusting the voltage of the second node. The output circuit 1430 outputs an output signal according to the input signal (including the voltage signal from the second node and the voltage signal from the third node).

[0173] In some embodiments, input circuit 1401 includes input subcircuit 1410 and charge pump subcircuit 1440 .

[0174] like Fig.14 As shown in (B), the shift register 1400 includes an input sub-circuit 1410, a bootstrap circuit 1420, an output circuit 1430 and a charge pump sub-circuit 1440.

[0175] The input sub-circuit 1410 includes three terminals, namely, a terminal T411 , a terminal T412 , and a terminal T413 .

[0176] The terminal T411 is used to obtain the first start pulse input signal EA(n-1). The terminal T412 is used to obtain the first control signal. The terminal T413 is coupled to the first node n1.

[0177] The bootstrap circuit 1420 includes three terminals, namely, terminal T421, terminal T422 and terminal T423. Terminal T421 is coupled to the first node n1. Terminal T422 is used to obtain the third control signal. The third terminal is coupled to the second node n2. The third terminal is also used to output the third start pulse input signal EA(n).

[0178] The charge pump subcircuit 1440 includes five terminals, namely, terminal T441, terminal T442, terminal T443, terminal T444 and terminal T445. Terminal T441 is used to obtain the second start pulse input signal E(n-1), terminal T442 is used to obtain the second control signal, terminal T443 is used to obtain the first control signal, terminal T444 is coupled to the second node n2, and terminal T445 is coupled to the output circuit 1430.

[0179] Output circuit 1430 includes several terminals for obtaining control signals and a terminal for outputting output signals. More specifically, output circuit 1430 includes terminal T431, terminal T432, terminal T433, terminal T434 and terminal T435. Terminal T435 is an output terminal for outputting the fourth start pulse input signal. Terminals T431 to T434 are used to obtain control signals. Terminal T431 is coupled to the second node n2, terminal T432 is coupled to terminal T445 to obtain the fifth control signal, terminal T433 is used to obtain the second control signal, and terminal T434 is used to obtain the fourth control signal. The fifth control signal is used to adjust the voltage of the third node n3. Therefore, the fifth control signal can also be called the third voltage control signal.

[0180] The shift register 1400 may be a unit in an emission driver on array (EOA) circuit, and therefore, the shift register 1400 may be referred to as an EOA subcircuit.

[0181] In some embodiments, the first control signal and the third control signal may be different clock signals. For example, the first control signal may be a first clock signal (hereinafter referred to as "CLK 1"), and the third control signal may be a second clock signal (hereinafter referred to as "CLK 2").

[0182] In some embodiments, the second control signal and the fourth control signal may be different constant signals. For example, the second control signal may be at a constant high level (hereinafter referred to as VGH), and the fourth control signal may be at a constant low level (hereinafter referred to as VGL). In some embodiments, the second control signal and the fourth control signal may be referred to as external signals. In order to distinguish the second control signal from the fourth control signal, the second control signal may be referred to as a first external control signal, and the fourth control signal may be referred to as a second external control signal.

[0183] In some embodiments, input subcircuit 1410 may include one or more transistors. Figure 2 The input circuit shown may be input subcircuit 1410. For example, if input subcircuit 1410 includes only one transistor, then Figure 2The input circuit shown in (a) is the input subcircuit 1410. In this case, Figure 2 The terminal T11 shown in (a) is the terminal T411, Figure 2 The terminal T12 shown in (a) is the terminal T412, Figure 2 The terminal T13 shown in (a) is the terminal T413. If the input sub-circuit 1410 includes two transistors, then Figure 2 The input circuit shown in (b) is the input sub-circuit 1410 . Figure 2 The terminal T11 shown in (a) is the terminal T411, Figure 2 The terminal T13 shown in (a) is the terminal T413. The terminal T412 may include two sub-terminals, one of which is Figure 2 (b) The terminal T12-1 is shown, and the other is Figure 2 (b) The terminal T12-2 shown in FIG. 1 is used to obtain the first control signal (ie, CLK1), and the terminal T12-2 is used to obtain the fourth control signal (ie, VGL).

[0184] Figure 3 The bootstrap circuit shown may be bootstrap circuit 1420 .

[0185] Figure 8 The output circuit shown may be output circuit 1430

[0186] Fig.15 Schematic diagram of the charge pump circuit.

[0187] like Fig.15 As shown, the charge pump circuit includes a transistor M2, a transistor M4 and a capacitor C2. The source terminal of the transistor M2 is a terminal T442, and the drain terminal of the transistor M2 is a terminal T444. The gate terminal of the transistor M2 is coupled to the third node n3, the drain terminal of the transistor M4 is coupled to the third node n3, and one terminal of the capacitor C2 (hereinafter referred to as "the first terminal of the capacitor C2") is coupled to the third node n3. The terminal T445 is also coupled to the third node n3. In other words, the terminal T445 is coupled to the gate terminal of the transistor M2, the drain terminal of the transistor M4 and the first terminal of the capacitor C2. In addition, the terminal T443 is coupled to the gate terminal of the transistor M4 and the other terminal of the capacitor C2, and the source terminal of the transistor is coupled to the terminal T441.

[0188] Fig.16 Figure 2 is a schematic diagram of the structure of the EOA subcircuit. Fig.16 As shown, the EOA subcircuit 1600 includes Figure 2 (a) shows the input circuit, Figure 3 (a) shows the bootstrap circuit, Figure 8 The output circuit shown and Fig.15The charge pump circuit shown.

[0189] Fig.17 For the corresponding Fig.16 The timing diagram of the EOA subcircuit is shown.

[0190] Fig.18 Schematic diagram of the structure of the shift register circuit according to the present application.

[0191] like Fig.18 As shown, the shift register circuit 1800 includes at least one stage of a shift register. The first stage of the shift register is coupled to a start pulse input signal line, wherein the start pulse input signal line is used to provide a start pulse input signal.

[0192] Each of the remaining stages of the shift register is coupled to a start pulse output terminal of a previous stage of its corresponding shift register, wherein the start pulse output terminal is used to output a corresponding start pulse input signal. The shift register also includes a first external control signal line, a second external control signal line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line.

[0193] The first external control signal line is used to provide a first external control signal (ie, VGH) to each of the stages of the shift register, and the second external control signal line is used to provide a second external control signal (ie, VGL) to each of the stages of the shift register.

[0194] The first clock signal line is used to provide a first clock signal (i.e., CLK1) to each stage of the shift register; the second clock signal line is used to provide a second clock signal (i.e., CLK 2) to each stage of the shift register; the third clock signal line is used to provide a third clock signal (i.e., CLK 3) to the odd-numbered stages of the shift register; and the fourth clock signal line is used to provide a fourth clock signal (i.e., CLK 4) to the even-numbered stages of the shift register.

[0195] Fig.18 The shift register in the shift register circuit 1800 shown may be the above-mentioned GOA unit. Therefore, the shift register circuit 1800 may be called a GOA circuit. Fig.18 The shift register in the GOA unit shown can be Figure 1 , Figure 5 , Figure 6 , Fig. 9 and Fig.10 More specifically, Figure 1 , Figure 5 , Figure 6 , Fig. 9 and Fig.10 The shift register shown is the odd-numbered stage of the shift register. Fig.19An example of an even-numbered stage of a shift register is shown. Fig. 9 and Fig.19 As shown, the circuit of the odd-numbered unit in the GOA circuit is the same as the circuit of the even-numbered unit. The difference between the odd-numbered unit and the even-numbered unit is that the control signals to some terminals are different.

[0196] The embodiment of the present application further provides a display panel, the display panel comprising: Fig.18 The GOA circuit shown.

[0197] In some embodiments, the width of the border of the display panel may be 0.8 mm to 1.2 mm, for example 1.0 mm, or 1.1 mm.

[0198] The embodiment of the present application also provides an electronic device. The electronic device includes the above-mentioned display panel. The electronic device can be a smart phone, a tablet computer, a smart watch, a television, etc.

[0199] Fig. 20 It is a structural schematic diagram according to the present application.

[0200] like Fig. 20 As shown, the shift register circuit 2000 includes at least one stage of a shift register. The first stage of the shift register is coupled to two start pulse input signal lines, wherein the start pulse input signal lines are used to provide a start pulse input signal.

[0201] Each of the remaining stages of the shift register is coupled to a start pulse output terminal of a previous stage of its corresponding shift register, wherein the start pulse output terminal is used to output a corresponding start pulse input signal. The shift register also includes a first external control signal line, a second external control signal line, a first clock signal line, and a second clock signal line.

[0202] The first external control signal line is used to provide a first external control signal (ie, VGH) to each of the stages of the shift register, and the second external control signal line is used to provide a second external control signal (ie, VGL) to each of the stages of the shift register.

[0203] The first clock signal line is used to provide a first clock signal (ie, CLK1) to each stage of the shift register; the second clock signal line is used to provide a second clock signal (ie, CLK2) to each stage of the shift register.

[0204] The embodiment of the present application further provides a display panel, the display panel comprising: Fig. 20 The EOA circuit is shown.

[0205] In some embodiments, the width of the border of the display panel may be 0.8 mm to 1.2 mm, for example 1.0 mm, or 1.1 mm.

[0206] The embodiment of the present application also provides an electronic device. The electronic device includes the above-mentioned display panel. The electronic device can be a smart phone, a tablet computer, a smart watch, a television, etc.

[0207] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above systems, devices and units can refer to the corresponding processes in the above method embodiments, which will not be described in detail here.

[0208] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described are only examples. For example, the unit division is only a logical function division, and other divisions can be used in actual implementations. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not performed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be implemented through some interfaces. The indirect coupling or communication connection between devices or units can be implemented in electronic, mechanical or other forms.

[0209] The units described as discrete components may or may not be physically separate, and the components shown as units may or may not be physical units, may be located in one location, or may be distributed over multiple network units. Some or all of the units may be selected based on actual needs to achieve the purpose of the solution of this embodiment.

[0210] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0211] The above description is only some specific implementations of the present application and is not intended to limit the protection scope of the present application. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A shift register, characterized in that: It includes an input circuit, a bootstrap circuit and an output circuit, wherein: The input circuit is used to obtain a first input signal and output a first voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust the voltage of a first node connected to the input circuit; The bootstrap circuit is used to obtain a second input signal and output a second voltage control signal according to the second input signal, wherein the second voltage control signal is used to adjust the voltage of the first node connected to the bootstrap circuit; The output circuit is used to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal includes a voltage signal from the first node, and the voltage signal includes: a first voltage and a second voltage, wherein the second voltage is lower than a low voltage of the first input signal, and the low voltage of the first input signal is lower than the first voltage.

2. The shift register according to claim 1, characterized in that: The input circuit includes a first transistor, the first input signal includes a first start pulse input signal and a first control signal, wherein, The source terminal of the first transistor is used to obtain the first start pulse input signal; The gate terminal of the first transistor is used to obtain the first control signal; The drain terminal of the first transistor is used to output the first voltage control signal.

3. The shift register according to claim 1, characterized in that: The input circuit includes a first transistor and a second transistor, the first input signal includes a first start pulse input signal, a first control signal and a fourth control signal, wherein, The source terminal of the first transistor is used to obtain the first start pulse input signal; The gate terminal of the first transistor is used to obtain the first control signal; The gate terminal of the second transistor is used to obtain the fourth control signal; a drain terminal of the first transistor coupled to a source terminal of the second transistor; The drain terminal of the second transistor is used to output the first voltage control signal.

4. The shift register according to any one of claims 1 to 3, characterized in that: The bootstrap circuit includes a third transistor and a first capacitor, and the second input signal includes a second control signal and the voltage signal, wherein, a first terminal of the first capacitor coupled to a gate terminal of the third transistor; a second terminal of the first capacitor coupled to a drain terminal of the third transistor; The gate terminal of the third transistor is used to obtain the voltage signal; A source terminal of the third transistor is used to obtain the second control signal.

5. The shift register according to claim 4, characterized in that: The second terminal of the first capacitor is used to output a second start pulse input signal.

6. The shift register according to any one of claims 1 to 5, characterized in that: The output circuit includes a fourth transistor, and the third input signal further includes a third control signal, wherein, The gate terminal of the fourth transistor is used to obtain the voltage signal; The source terminal of the fourth transistor is used to obtain the third control signal; A drain terminal of the fourth transistor is used to output the output signal.

7. The shift register according to any one of claims 1 to 5, characterized in that: The shift register further includes a charge pump circuit, wherein: The charge pump circuit is used to obtain a fourth input signal and output a third voltage control signal according to the fourth input signal; The third input signal also includes the third voltage control signal, and the third voltage control signal includes: a third voltage and a fourth voltage, wherein the fourth voltage is lower than the low voltage of the first input signal, and the low voltage of the first input signal is lower than the third voltage.

8. The shift register according to claim 7, characterized in that: The output circuit includes a fourth transistor and a fifth transistor, and the third input signal also includes a third control signal and a fourth control signal, wherein, a drain terminal of the fourth transistor coupled to a drain terminal of the fifth transistor; The gate terminal of the fourth transistor is used to obtain the voltage signal; The source terminal of the fourth transistor is used to obtain the third control signal; The drain terminal of the fourth transistor is used to output the output signal; The gate terminal of the fifth transistor is used to obtain the third voltage control signal; A source terminal of the fifth transistor is used to obtain the fourth control signal.

9. The shift register according to claim 7 or 8, characterized in that: The charge pump circuit includes: a sixth transistor, a seventh transistor, an eighth transistor and a second capacitor, the fourth input signal includes a second start pulse input signal, a second control signal, a third control signal, a fourth control signal and a fifth control signal, wherein, The gate terminal of the seventh transistor is used to obtain the second start pulse input signal; a drain terminal of the sixth transistor coupled to the gate terminal of the seventh transistor; A source terminal of the sixth transistor and a source terminal of the seventh transistor are used to obtain the fifth control signal; The gate terminal of the eighth transistor is used to obtain the third control signal; The first terminal of the second capacitor is used to obtain the second control signal; The source terminal of the eighth transistor is used to obtain the fourth control signal; a drain terminal of the eighth transistor coupled to a drain terminal of the seventh transistor and to a second terminal of the second capacitor; The second terminal of the second capacitor is used to output the third voltage control signal.

10. A shift register, characterized in that: It includes an input circuit, a bootstrap circuit and an output circuit, wherein: The input circuit is used to obtain a first input signal, and output a first voltage control signal, a second voltage control signal and a third voltage control signal according to the first input signal, wherein the first voltage control signal is used to adjust the voltage of the first node, the second voltage control signal is used to adjust the voltage of the second node, and the third voltage control signal is used to adjust the voltage of the third node; The bootstrap circuit is used to obtain a second input signal and output a fourth voltage control signal, wherein the fourth voltage control signal is used to adjust the voltage of the second node; The output circuit is used to obtain a third input signal and output an output signal according to the third input signal, wherein the third input signal includes a voltage signal from the second node and a voltage signal from the third node.

11. The shift register according to claim 10, characterized in that: The input circuit includes an input subcircuit and a charge pump subcircuit, the first input signal includes a first start pulse input signal and a second start pulse input signal, wherein, The input subcircuit is used to output the first voltage control signal according to the first start pulse signal; The charge pump subcircuit is used to output the second voltage control signal and the third voltage control signal according to the second start pulse input signal.

12. The shift register according to claim 11, characterized in that: The input subcircuit includes a first transistor, and the first input signal also includes a first control signal, wherein, The source terminal of the first transistor is used to obtain the first start pulse input signal; The gate terminal of the first transistor is used to obtain the first control signal; The drain terminal of the first transistor is used to output the first voltage control signal.

13. The shift register according to claim 11 or 12, characterized in that: The charge pump subcircuit includes: a second transistor, a third transistor and a first capacitor, and the first input signal also includes a first control signal and a second control signal, wherein, The source terminal of the second transistor is used to obtain the second start pulse input signal; A source terminal of the third transistor is used to obtain the second control signal; The gate terminal of the second transistor is used to obtain the first control signal; The drain terminal of the third transistor is used to output the second voltage control signal; a drain terminal of the second transistor coupled to a gate terminal of the third transistor and to a first terminal of the first capacitor; The first terminal of the first capacitor is used to output the third voltage control signal; The second terminal of the first capacitor is used to obtain the first control signal.

14. The shift register according to any one of claims 11 to 13, characterized in that: The output circuit includes a fourth transistor and a fifth transistor, and the third input signal also includes a second control signal and a fourth control signal, wherein, a gate terminal of the fourth transistor coupled to the second node; a gate terminal of the fifth transistor coupled to the third node; A source terminal of the fourth transistor is used to obtain the second control signal; The source terminal of the fifth transistor is used to obtain the fourth control signal; The drain-source of the fourth transistor is coupled to the drain-source of the fifth transistor; The drain-source of the fourth transistor is used to output the output signal.

15. The shift register according to any one of claims 10 to 13, characterized in that: The bootstrap circuit includes a sixth transistor and a second capacitor, the second input signal includes a voltage signal from the first node and a third control signal, wherein, a first terminal of the second capacitor coupled to a gate terminal of the sixth transistor; a second terminal of the second capacitor coupled to a drain terminal of the sixth transistor; The gate terminal of the sixth transistor is used to obtain the voltage signal from the first node; the drain terminal of the sixth transistor is coupled to the second node; A source terminal of the sixth transistor is used to obtain the third control signal.

16. A shift register, characterized in that: include: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor; a first terminal of the first capacitor coupled to a drain terminal of the first transistor, a gate terminal of the second transistor, and a gate terminal of the third transistor; a second terminal of the first capacitor coupled to a drain terminal of the second transistor, a drain terminal of the sixth transistor, and a gate terminal of the fourth transistor; a first terminal of the second capacitor coupled to a drain terminal of the fourth transistor, a drain terminal of the fifth transistor, a gate terminal of the sixth transistor, and a gate terminal of the seventh transistor; A drain terminal of the seventh transistor is coupled to a drain terminal of the third transistor.

17. The shift register according to claim 16, characterized in that: Also included is an eighth transistor having a drain terminal coupled to a source terminal of the first transistor.

18. A shift register, characterized in that: The method comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor and a second capacitor, wherein: a first terminal of the first capacitor coupled to a drain terminal of the first transistor and a gate terminal of the third transistor; a second terminal of the first capacitor coupled to a drain terminal of the third transistor, a drain terminal of the second transistor, and a gate terminal of the fifth transistor; a first terminal of the second capacitor coupled to a gate terminal of the second transistor, a drain terminal of the fourth transistor, and a gate terminal of the sixth transistor; A drain terminal of the fifth transistor is coupled to a drain terminal of the sixth transistor.

19. A shift register circuit, characterized in that: comprising at least one stage of a shift register according to any one of claims 1 to 9, 16 or 17, wherein the first stage of the shift register is coupled to a start pulse input signal line, the start pulse input signal line being used to provide a start pulse input signal; Each of the remaining stages of the shift register is coupled to a start pulse output terminal of a previous stage of its corresponding shift register, wherein the start pulse output terminal is used to output a corresponding start pulse input signal; The shift register circuit further includes: a first external control signal line for providing a first external control signal to each of the stages of the shift register; a second external control signal line for providing a second external control signal to each of the stages of the shift register; a first clock signal line for providing a first clock signal to each of the stages of the shift register; a second clock signal line for providing a second clock signal to each of the stages of the shift register; A third clock signal line, used for providing a third clock signal to the odd-numbered stages of the shift register; The fourth clock signal line is used to provide a fourth clock signal to the even-numbered stages of the shift register.

20. A display panel, characterized in that: Comprising the shift register circuit according to claim 19.

21. An electronic device, characterized in that: Comprising the display panel according to claim 20.

22. A shift register circuit, characterized in that: comprising at least one stage of a shift register according to any one of claims 10 to 15 or 18, wherein the first stage of the shift register is coupled to a start pulse input signal line, the start pulse input signal line being used to provide a start pulse input signal; Each of the remaining stages of the shift register is coupled to a start pulse output terminal of a previous stage of its corresponding shift register, wherein the start pulse output terminal is used to output a corresponding start pulse input signal; The shift register circuit further includes: a first external control signal line for providing a first external control signal to each of the stages of the shift register; a second external control signal line for providing a second external control signal to each of the stages of the shift register; a first clock signal line for providing a first clock signal to each of the stages of the shift register; A second clock signal line is used to provide a second clock signal to each of the stages of the shift register.

23. A display panel, characterized in that: Comprising the shift register circuit according to claim 22.

24. An electronic device, characterized in that: Comprising the display panel according to claim 23.

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