A digital assisted analog off-chip capacitor-less low-dropout linear regulator

Abstract

The present application belongs to the field of power management in analog integrated circuits, and particularly relates to a digital auxiliary analog off-chip capacitor-free low-dropout linear voltage regulator; comprising a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power tube group, an analog loop and a digital loop; in a load steady state, an analog LDO is used as a main control scheme, a high-gain amplifier can obtain an accurate output voltage, and limit cycle oscillation does not occur. Only when a load transient occurs, a digital LDO is called as a main control scheme, so as to improve speed, reduce static current and suppress switching noise. On-chip integration, high-precision output voltage, wide load current range, fast transient response speed, high-efficiency power tube area utilization and low output ripple can be realized. The circuit can be applicable to SoC modular power management and digital IP load.

Description

Technical Field

[0001] This invention belongs to the field of power management in analog integrated circuits, and specifically relates to a digital-aided analog low-dropout linear regulator without external capacitors. Background Technology

[0002] As electronic systems become increasingly integrated, modern system-on-a-chip (SoC) power supply systems feature multi-voltage domain designs, leading to a growing variety of power management chips. Among these, traditional low-dropout linear regulators (LDOs) are common step-down chips, widely used in various small circuits and as on-chip regulators. Traditional analog LDOs are the most widely used, offering good noise performance, good power supply rejection ratio, and a small footprint.

[0003] However, traditional analog circuits cannot benefit from advanced CMOS processes and are incompatible with standard digital design flows. Analog LDOs, under advanced processes, suffer from drawbacks such as low intrinsic gain and small output swing due to low supply voltages, particularly with analog LDOs. To address these shortcomings, digital LDOs were proposed. Unlike traditional analog LDOs, digital LDOs can operate under low threshold voltage or subthreshold conditions, and they can be designed according to standard digital design flows and integrated with other digital modules. Digital LDOs offer low power consumption and scalability, but they suffer from poor power supply ripple suppression and lower output accuracy.

[0004] Hybrid-digital LDOs combine the technical features of analog and digital LDOs, achieving higher performance and more flexible voltage stability output. For example, Chinese patent CN117631735A proposes an analog-digital dual-loop LDO circuit, employing a dual-loop configuration of digital and analog loops, dividing the power transistors into analog and digital power transistors. This solves the loop stability problem of existing LDO circuits without external capacitors, improving performance in terms of high load current, stability, and transient response. Another example is Chinese patent CN118399966A, which proposes a hybrid-digital LDO circuit and its operating method based on a switched-capacitor integral loop. This scheme achieves high load under ultra-low voltage through the digital loop in a stable operating state, and achieves lower output ripple by replacing the locked digital loop with the analog loop in a stable operating state. However, these solutions cannot effectively address fast transient response and suffer from drawbacks such as slow transient recovery time. Summary of the Invention

[0005] This invention discloses a digital-assisted analog low-dropout linear regulator without external capacitors. By employing a dual-loop hybrid solution, it combines the advantages of both digital and analog LDOs while mitigating their respective shortcomings. It eliminates the need for large external capacitors, achieving on-chip integration, high-precision output voltage, wide load current range, fast transient response, high power transistor area utilization, and low output ripple. Addressing the various deficiencies of traditional analog and digital LDO circuits, this invention proposes a digital-assisted analog low-dropout linear regulator without external capacitors. This hybrid digital-analog LDO circuit is suitable for SoC modular power management and digital IP loads.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A digitally-assisted analog low-dropout linear regulator without external capacitors includes a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power transistor group, an analog loop, and a digital loop.

[0008] The bandgap reference circuit outputs four reference voltages VREF, VREFH, VREFL, VRFB and an enable signal EN;

[0009] The control module takes three reference voltages VREF, VREFH, and VREFL, two enable signals EN and EN3, and a clock signal CLK as inputs, and outputs four control signals VOH, VOL, COMP_OUT, and RSTN, and one enable signal.

[0010] The digital loop inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs a voltage signal VOUT.

[0011] The analog loop inputs a reference voltage VRFB and outputs a voltage signal VOUT.

[0012] The transient enhancement circuit takes input voltage signal VOUT and enable signal EN2, and outputs enable signal EN3 and control signal S.

[0013] The transient power transistor group receives a control signal S and outputs a voltage signal VOUT.

[0014] Furthermore, the analog loop includes an error amplifier EA, a PMOS transistor, load resistors R1 and R2, and a load capacitor CL; the non-inverting input of the error amplifier EA is connected to one end of resistors R1 and R2, the inverting input of the error amplifier EA is connected to the reference voltage VRFB, the output of the error amplifier EA is connected to the gate of the PMOS transistor, the source of the PMOS transistor is connected to the power supply voltage VDD, the drain of the PMOS transistor is connected to the other end of resistor R1 and one end of capacitor CL, and the other end of resistor R2 and the other end of capacitor CL are grounded to GND.

[0015] Furthermore, the digital loop includes a coarse adjustment logic circuit and a corresponding coarse adjustment power transistor group, as well as a fine adjustment logic circuit and a corresponding fine adjustment power transistor group. The coarse adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs an enable signal EN1 and a coarse adjustment control signal C. The coarse adjustment power transistor group inputs the coarse adjustment control signal C and controls the number of coarse adjustment power transistors turned on to output a voltage signal VOUT. The fine adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, RSTN, and the enable signal EN1, and outputs a control signal X. The fine adjustment power transistor group inputs the control signal X and controls the number of fine adjustment power transistors turned on to output a voltage signal VOUT.

[0016] Furthermore, the coarse-tuning power transistor group includes: power transistors with the smallest aspect ratio as one basic unit, arranged in binary and multi-unary combinations, with the number of the first N power transistor groups in a binary ratio of 2. 0 ,2 1 ,…,2 N-1 The number of power transistors in the middle K-bit group increases sequentially; the ratio of the number of power transistors in the middle K-bit group follows a binary ratio of 2. N The ratio of the number of power transistor groups in the last N bits remains unchanged, according to the binary ratio of 2. N-1 ,…,2 1 ,2 0 Decrease sequentially; K≥2, N≥2.

[0017] Furthermore, the fine-tuning logic circuit is a multi-bit shift register, and the fine-tuning power transistor group consists of power transistors with corresponding bit widths.

[0018] Further, the control module includes three comparators COMP1, COMP2, and COMP3. Comparator COMP1 compares the magnitude of the output voltage VOUT and the expected value VREF. When VOUT > VREF, COMP_OUT outputs a high level. When VOUT < VREF, COMP_OUT outputs a low level. The comparators COMP2, COMP3, and an exclusive-OR gate form a dead zone controller. When VREFH > VOUT > VREFL, VOH outputs a low level, VOL outputs a high level, and RSTN outputs a high level. When VOUT > VREFH > VREFL, VOH outputs a high level, VOL outputs a high level, and RSTN outputs a low level. When VREFH > VREFL > VOUT, VOH outputs a low level, VOL outputs a low level, and RSTN outputs a low level. When the signal EN3 is pulled from a high level to a low level, RSTN outputs a low level.

[0019] Further, the transient enhancement circuit includes resistors R11, R12, RC, capacitor Cc, NAND gate AND, power transistor M1, and power transistor M2. Among them, one end of resistor R12 is connected to the power supply voltage VDD, the other end of resistor R12 is connected to one end of RC and one end of R11, the other end of R11 is grounded to GND, the other end of resistor RC is connected to capacitor Cc and one input terminal of NAND gate AND, and the other end of capacitor Cc outputs a voltage signal VOUT. The other input terminal of the NAND gate is connected to the EN2 enable signal, the output terminal of the NAND gate is connected to the bases of power transistor M1 and power transistor M2, and the gates of power transistor M1 and power transistor M2 output a control signal S. The source of power transistor M1 is connected to the power supply voltage VDD, and the source of power transistor M2 is grounded to GND.

[0020] Further, the operation processes of the digital loop and the analog loop include:

[0021] When RSTN is pulled from a high level to a low level, the coarse adjustment logic circuit and the fine adjustment logic circuit are initialized simultaneously, and all power transistors are not conducting. The coarse adjustment logic circuit uses the successive approximation search algorithm to achieve the conduction of the coarse adjustment power transistor group according to the smooth binary increasing search step.

[0022] When VOUT > VREFL, the coarse adjustment logic circuit stops increasing the search step.

[0023] When VOUT > VREFH and EN3 is at a low level, a transient event is triggered, and the coarse adjustment logic circuit starts searching from the highest search step.

[0024] When VREF>VOUT>VREFL, the coarse adjustment logic circuit will stop the new coarse adjustment power transistor group from being turned on, and keep the already turned-on coarse adjustment power transistor group in the on state. At this time, the fine adjustment logic circuit starts to work. When the rising edge of the clock arrives at each moment, a fine adjustment power transistor is turned on by a one-element shift register search to provide fine adjustment current.

[0025] When VOUT>VREF, the fine-tuning logic circuit turns off the fine-tuning power transistor that was turned on at the rising edge of the previous clock. The fine-tuning logic circuit will maintain its current state and will not turn on the subsequent power transistors again, keeping the already turned-on fine-tuning power transistor group on. Finally, the analog loop is enabled, and the analog loop will provide compensation current to suppress ripple.

[0026] The beneficial effects of this invention are:

[0027] This invention proposes a novel dual-loop hybrid analog-digital LDO circuit with no external capacitors, employing a dual-loop hybrid solution. Under steady-state load conditions, the analog LDO is the primary control scheme, with the analog loop providing fine-tuning current. The high-gain amplifier achieves accurate output voltage without extreme cyclic oscillations. Only during load transients is the digital LDO activated as the primary control scheme. The digital loop provides coarse-tuning current and utilizes a hybrid algorithm based on successive approximation search and unary shift register search to rapidly turn the power transistor on or off within a short time to match transient load current changes. This hybrid algorithm improves speed, reduces quiescent current, and suppresses switching noise. It achieves on-chip integration, high-precision output voltage, wide load current range, fast transient response, high power transistor area utilization, and low output ripple. This circuit is suitable for SoC modular power management and digital IP loads. Attached Figure Description

[0028] Figure 1 This is an overall framework diagram of a digitally assisted analog low-dropout linear regulator without external capacitors according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the internal structure of the control module according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the transient enhancement circuit structure according to an embodiment of the present invention;

[0031] Figure 4 This is a coarse-tuned state transition diagram according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the working output states of each load in an embodiment of the present invention;

[0033] Figure 6 This is a comparison diagram of the transient process in an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] It should be noted that, since the embodiments of this invention focus on the current or voltage of signals, the description herein refers to the input / output of each module / unit / device as current or voltage. Those skilled in the art should understand that, in reality, the input / output of each module / unit / device is a signal. To facilitate understanding of the technical means and inventive features of this invention, the invention will be further described in conjunction with the accompanying drawings.

[0036] like Figure 1 As shown, a digitally assisted analog low-dropout linear regulator without external capacitors includes a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power transistor group, an analog loop, and a digital loop. The reference bandgap circuit generates four reference voltages, which are used to control the operation of the digital loop and the analog loop, respectively. The transient enhancement circuit detects the magnitude of the mixed output voltage of the digital loop and the analog loop, and outputs a signal to enable all or part of the transient enhancement power transistor group to conduct and to enable the control module to operate. The control module uses a clock signal and an enable signal combined with the reference voltage to enable all or part of the coarse-tuning power transistor group and / or the fine-tuning power transistor group to conduct. The analog loop provides compensation current to the mixed output voltage of the digital loop and the analog loop.

[0037] In this embodiment of the invention, VDD (1.2V) is the power supply for this circuit, and VOUT (0.9V) is the stable output voltage of the mixed-signal LDO.

[0038] In this embodiment of the invention, the bandgap reference circuit outputs four reference voltages VREF, VREFH, VREFL, VRFB, and an enable signal EN. The input signal of the bandgap reference circuit can be a power supply voltage VDD, which can drive the bandgap reference circuit to start, waking it from its dormant state and enabling it to begin normal operation. Alternatively, the input signal of the bandgap reference circuit can be a control signal, which may come from external circuits, such as digital or analog circuits, and is used to adjust the output voltage of the bandgap reference circuit according to specific requirements. The input signal of the bandgap reference circuit can also be a temperature sensing signal, used to monitor changes in ambient temperature in real time and compensate for the influence of temperature on the output reference voltage through adjustments to the internal circuit.

[0039] In some embodiments of the present invention, the bandgap reference module generates four reference voltages VRFB (800 mV), VREFL (870 mV), VREF (900 mV), and VREFH (930 mV). VRFB is output to the error amplifier of the analog loop as the reference voltage of the analog loop, and VREFL, VREFH, and VREF are output to the control module as the reference voltages of the digital loop. The supply voltage of the entire bandgap reference is VDD (1.2V). Only when the VDD voltage is successfully powered up to a certain voltage can these four reference voltages be normally generated. When the power supply voltage VDD reaches 1.2V, the bandgap reference module outputs a signal EN, which is pulled from low level to high level, indicating that the power-on is completed.

[0040] In an embodiment of the present invention, the control module inputs three reference voltages VREF, VREFH, VREFL, two enable signals EN, EN3, and a clock signal CLK, and outputs four control signals VOH, VOL, COMP_OUT, RSTN, and one enable signal; the CLK clock of the control module is 50 MHz, and the control module can work normally only when EN is valid.

[0041] In some embodiments of the present invention, the internal structure of the control module is as Figure 2 shown. The comparator COMP1 compares the magnitude of the output voltage VOUT and the expected value VREF. When VOUT > VREF, COMP_OUT outputs a high level; when VOUT < VREF, COMP_OUT outputs a low level. The comparator COMP2, COMP3, and an exclusive-OR gate form a dead zone controller to effectively suppress the limit cycle oscillation. When VREFH > VOUT > VREFL, VOH outputs a low level, VOL outputs a high level, and RSTN outputs a high level; when VOUT > VREFH > VREFL, VOH outputs a high level, VOL outputs a high level, and RSTN outputs a low level; when VREFH > VREFL > VOUT, VOH outputs a low level, VOL outputs a low level, and RSTN outputs a low level. In addition, when the signal EN3 is pulled from high level to low level, RSTN outputs a low level.

[0042] In some embodiments of the present invention, as Figure 3As shown, the transient enhancement circuit includes resistors R11, R12, and RC, capacitor Cc, a NAND gate, power transistors M1 and M2; one end of resistor R12 is connected to the power supply voltage VDD, the other end of resistor R12 is connected to one end of RC and one end of R11, the other end of R11 is grounded to GND, the other end of resistor RC is connected to capacitor Cc and one input terminal of the NAND gate, and the other end of capacitor Cc outputs a voltage signal VOUT; the other input terminal of the NAND gate is connected to the EN2 enable signal, the output terminal of the NAND gate is connected to the base of power transistors M1 and M2, and the gates of power transistors M1 and M2 output control signals S; the source of power transistor M1 is connected to the power supply voltage VDD, and the source of power transistor M2 is grounded to GND.

[0043] It should be noted that the transient enhancement circuit mainly provides an asynchronous undershoot detection signal to enhance transient response. When a load change causes an undershoot in the output voltage, the voltage at point FB drops below a set threshold, causing the NAND gate output to go high, turning on M2. This corresponds to the S signal changing from a high level to a low level, asynchronously triggering the transient enhancement power transistor group to turn on asynchronously to suppress changes in output voltage. EN2 is the enable signal, which is active high.

[0044] In this embodiment of the invention, the digital loop inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs a voltage signal VOUT. The digital loop includes a coarse adjustment logic circuit and a corresponding coarse adjustment power transistor group, as well as a fine adjustment logic circuit and a corresponding fine adjustment power transistor group. The coarse adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs an enable signal EN1 and a coarse adjustment control signal C. The coarse adjustment power transistor group inputs the coarse adjustment control signal C and controls the number of coarse adjustment power transistors turned on to output the voltage signal VOUT. The fine adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, RSTN, and the enable signal EN1, and outputs a control signal X. The fine adjustment power transistor group inputs the control signal X and controls the number of fine adjustment power transistors turned on to output the voltage signal VOUT.

[0045] In this embodiment of the invention, the coarse-adjustment power transistor groups are arranged in binary and multi-unary combinations, and the ratio of the number of power transistor groups in the first N bits is in binary ratio 2. 0 ,2 1 ,…,2 N-1 The number of power transistors in the middle K-bit group increases sequentially; the ratio of the number of power transistors in the middle K-bit group follows a binary ratio of 2. N The ratio of the number of power transistor groups in the last N bits remains unchanged, according to the binary ratio of 2. N-1 ,…,2 1 ,2 0 Decrease sequentially. K≥2, N≥2.

[0046] It is understood that the present invention uses binary and multi-unary arrangements to coarsely adjust the power transistor group. This method can flexibly meet the output requirements of different power levels by adjusting the number, arrangement and control strategy of the power transistors. It uses a hybrid algorithm based on successive approximation search and unary shift register search to quickly turn the power transistors on or off in a short time to match the transient changes of the load current. It solves the problems of fast transient response and slow transient recovery time.

[0047] In some embodiments of this invention, the minimum size of the power transistor is 0.8 / 0.06 μm. The coarse-tuned power transistor group arrangement scheme uses a combination of binary and multi-unary permutations. For example, if N=5, the ratio of the number of power transistor groups in the first five bits to the last five bits is 1:2:4:8:16, and the ratio of the number of power transistor groups in the middle bits is 32. In embodiments of this invention, the digital loop employs a hybrid algorithm of successive approximation search and unary shift register search to achieve an optimized trade-off between voltage accuracy and settling time. The minimum size digital power transistor can provide a current of I. LSB The current supplied by the analog loop is I. A For any given load current I L There always exists I L =I A +aI LSB +bI LSB , where aI LSB To fine-tune the current supplied to the power transistor bank, bI LSB I is used for coarse adjustment of the current supplied to the power transistor bank. A To simulate the current supplied by the loop, I A Always greater than I LSB Parameter a represents the number of bits turned on in the fine-tuning power transistor group, and parameter b represents the number of power transistors with the smallest aspect ratio turned on in the coarse-tuning power transistor group.

[0048] Among them, Successive Approximation Search and Univariate Shift Register Search are two different optimization algorithms. This hybrid algorithm combines the global search capability of Successive Approximation Search with the local search capability of Univariate Shift Register Search. This hybrid algorithm can roughly determine the corresponding power transistor in the search space using the successive approximation method, and then use the univariate shift register method to more precisely determine the corresponding power transistor, making it easier to compensate for loop current. In this embodiment of the invention, the control module and the digital loop are combined to form a digital logic control unit, which is synthesized, automatically placed, and routed according to standard digital design flow.

[0049] In this embodiment of the invention, the coarse adjustment module includes a coarse adjustment logic circuit and a corresponding coarse adjustment power transistor group, and the fine adjustment module includes a fine adjustment logic circuit and a corresponding fine adjustment power transistor group. The state transition of the coarse adjustment module (SAR logic) is as follows: Figure 4 As shown, when RSTN is pulled from high to low, the coarse adjustment module and the fine adjustment module are initialized simultaneously, and all power transistors are not turned on. The black arrows indicate that the coarse adjustment module is performing a normal successive approximation search algorithm, with a smooth binary increase in the search step size. The increase in the search step size will only stop when VOUT > VREFL. The sparse dashed arrows indicate transient event triggering transitions. A transient event will only be triggered when VOUT > VREFH and EN3 is low, and the search step size will start from the highest step size. The dense dashed arrows indicate the transition from the coarse adjustment module to the fine adjustment module. The coarse adjustment state will only switch to the fine adjustment state when VREF > VOUT > VREFL.

[0050] In some embodiments, the fine-tuning module consists of a 24-bit shift register, with 24 bits controlling 24 small-sized power transistors. When the loop enters fine-tuning mode, each rising edge of the clock will turn on a fine-tuning power transistor. When VOUT>VREF, the fine-tuning power transistor turned on by the previous clock bit will be turned off. The fine-tuning module will maintain its current state and will not turn on subsequent power transistors. The analog loop will compensate for the subsequent current to achieve accurate output voltage, thus effectively reducing output ripple.

[0051] In some embodiments of the present invention, the minimum aspect ratio power transistor is taken as one basic unit of quantity, the number of power transistor groups of each fine-tuning power transistor group is M, the number of power transistor groups of the analog power transistor group (transient enhancement power transistor group) is N (the load capacity must be greater than the load capacity of the minimum aspect ratio power transistor), and the number of power transistor groups of the transient enhancement power transistor group is K.

[0052] In some embodiments, the minimum size of the power transistor is 0.8 / 0.06, both in μm. The number of power transistors in each bit of the 24-bit fine-tuning power transistor group is 24 minimum size power transistors, the number of power transistors in the analog power transistor group is 40 minimum size power transistors, and the number of power transistors in the transient enhancement power transistor group is 40 minimum size power transistors.

[0053] It should be noted that, in the embodiments of the present invention, the power transistor controlled by the digital loop is simply referred to as the digital power transistor, and the one driven by the analog loop or the error amplifier is simply referred to as the analog power transistor. There is no essential difference between these analog power transistors and digital power transistors; they are all power transistors, only their numbers differ. By dynamically adjusting the number of power transistors turned on or off to match the transient changes in the load current, the speed is improved, the quiescent current is reduced, and the switching noise is suppressed.

[0054] In some embodiments of the present invention, the analog loop is similar to a traditional analog LDO and may include an error amplifier EA, a PMOS transistor, load resistors R1 and R2, and a load capacitor CL. The non-inverting input of the error amplifier EA is connected to one end of resistors R1 and R2, the inverting input of the error amplifier EA is connected to a reference voltage VRFB, the output of the error amplifier EA is connected to the gate of the PMOS transistor, the source of the PMOS transistor is connected to the power supply voltage VDD, the drain of the PMOS transistor is connected to the other end of resistor R1 and one end of capacitor CL, and the other end of resistor R2 and the other end of capacitor CL are grounded to GND. This analog loop automatically detects the output voltage VOUT through a resistor divider formed by resistors R1 and R2, and the error amplifier EA continuously adjusts the current source I. L This maintains the output voltage VOUT stable at the rated voltage. In addition to the traditional analog LDO circuit, this invention adds a control module, bandgap reference circuit, transient enhancement circuit, transient enhancement power transistor group, and digital loop structure. Under steady-state load conditions, the analog LDO is used as the main control scheme, allowing the high-gain amplifier to obtain an accurate output voltage without extreme cyclic oscillations. The digital LDO is only activated as the main control scheme during load transients to improve speed, reduce quiescent current, and suppress switching noise.

[0055] like Figure 5 As shown, the diagram illustrates the operating state of the entire dual-loop mixed-signal LDO circuit under different current load conditions. In the initial power-on phase, the entire digital loop is not working, and only the analog loop provides a small amount of current. When power-on is complete, the digital loop starts working and enters the coarse adjustment mode for rapid searching, resulting in large output voltage fluctuations. When entering the fine adjustment mode, the difference between the output voltage and the desired value is very small, and it can be completed in just a few clock cycles. Finally, it enters the fine adjustment mode, where the analog loop compensates for the current. The entire operating time is <2μs, and the output ripple is <2mV.

[0056] like Figure 6 As shown in the figure, the transient response process under different mechanisms is illustrated. The comparison shows that the transient enhancement circuit can significantly suppress the undershoot voltage, and the transient event triggering mechanism can improve the system stability and effectively suppress the overshoot and undershoot voltage. The above shows that the proposed dual-loop capacitorless hybrid digital-analog LDO circuit has been effectively verified.

[0057] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A digitally-aided analog low-dropout linear regulator without external capacitors, characterized in that, It includes a control module, a bandgap reference circuit, a transient enhancement circuit, a transient enhancement power transistor group, an analog loop, and a digital loop; The bandgap reference circuit outputs four reference voltages VREF, VREFH, VREFL, VRFB and an enable signal EN; The control module takes three reference voltages VREF, VREFH, and VREFL, two enable signals EN and EN3, and a clock signal CLK as inputs, and outputs four control signals VOH, VOL, COMP_OUT, and RSTN, and one enable signal EN2. The digital loop inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs a voltage signal VOUT. The analog loop inputs a reference voltage VRFB and outputs a voltage signal VOUT. The transient enhancement circuit takes input voltage signal VOUT and enable signal EN2, and outputs enable signal EN3 and control signal S. The transient power transistor group receives a control signal S and outputs a voltage signal VOUT. The digital loop includes a coarse adjustment logic circuit and a corresponding coarse adjustment power transistor group, as well as a fine adjustment logic circuit and a corresponding fine adjustment power transistor group. The coarse adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, and RSTN, and outputs an enable signal EN1 and a coarse adjustment control signal C. The coarse adjustment power transistor group inputs the coarse adjustment control signal C and controls the number of coarse adjustment power transistors turned on to output a voltage signal VOUT. The fine adjustment logic circuit inputs four control signals VOH, VOL, COMP_OUT, RSTN, and the enable signal EN1, and outputs a control signal X. The fine adjustment power transistor group inputs the control signal X and controls the number of fine adjustment power transistors turned on to output a voltage signal VOUT. The transient enhancement circuit includes resistors R11, R12, and RC; capacitor Cc; a NAND gate; and power transistors M1 and M2. One end of resistor R12 is connected to the power supply voltage VDD; the other end of resistor R12 is connected to one end of RC and one end of R11; the other end of R11 is grounded (GND); the other end of resistor RC is connected to capacitor Cc and one input of the NAND gate; the other end of capacitor Cc outputs a voltage signal VOUT; the other input of the NAND gate is connected to the EN2 enable signal; the output of the NAND gate is connected to the gates of power transistors M1 and M2; the drains of power transistors M1 and M2 output a control signal S; the source of power transistor M1 is connected to the power supply voltage VDD; and the source of power transistor M2 is grounded (GND).

2. The digital-aided analog low-dropout linear regulator without external capacitors according to claim 1, characterized in that, The analog loop includes an error amplifier EA, a PMOS transistor, load resistors R1 and R2, and a load capacitor CL. The non-inverting input of the error amplifier EA is connected to one end of resistors R1 and R2, the inverting input of the error amplifier EA is connected to the reference voltage VRFB, the output of the error amplifier EA is connected to the gate of the PMOS transistor, the source of the PMOS transistor is connected to the power supply voltage VDD, the drain of the PMOS transistor is connected to the other end of resistor R1 and one end of capacitor CL, and the other end of resistor R2 and the other end of capacitor CL are grounded to GND.

3. The digital-aided analog low-dropout linear regulator without external capacitors according to claim 1, characterized in that, The coarse-tuning power transistor group includes: power transistors with the smallest aspect ratio as one basic unit, arranged in binary and multi-unary combinations, with the number of power transistors in the first N power transistor groups arranged in a binary ratio of 2. 0 ,2 1 ,…,2 N-1 The number of power transistors in the middle K-bit group increases sequentially; the ratio of the number of power transistors in the middle K-bit group follows a binary ratio of 2. N The ratio of the number of power transistor groups in the last N bits remains unchanged, according to the binary ratio of 2. N -1 ,…,2 1 ,2 0 Decrease sequentially; K≥2, N≥2.

4. The digital-aided analog low-dropout linear regulator without external capacitors according to claim 1, characterized in that, The fine-tuning logic circuit is a multi-bit shift register, and the fine-tuning power transistor group is power transistors corresponding to the number of bits.

5. A digitally-aided analog low-dropout linear regulator without external capacitors as described in claim 1, characterized in that, The control module includes three comparators COMP1, COMP2, and COMP3. Comparator COMP1 compares the magnitude of the output voltage VOUT and the expected value VREF. When VOUT > VREF, COMP_OUT outputs a high level; when VOUT < VREF, COMP_OUT outputs a low level. The comparators COMP2, COMP3, and an exclusive-OR gate form a dead zone controller. When VREFH > VOUT > VREFL, VOH outputs a low level, VOL outputs a high level, and RSTN outputs a high level; when VOUT > VREFH > VREFL, VOH outputs a high level, VOL outputs a high level, and RSTN outputs a low level; when VREFH > VREFL > VOUT, VOH outputs a low level, VOL outputs a low level, and RSTN outputs a low level; when the signal EN3 is pulled from a high level to a low level, RSTN outputs a low level.

6. A digitally-aided analog low-dropout linear regulator without external capacitors as described in any one of claims 1-5, characterized in that, The operation processes of the digital loop and the analog loop include: When RSTN is pulled from a high level to a low level, the coarse-tuning logic circuit and the fine-tuning logic circuit are initialized simultaneously, and all power transistors are not conducting. The coarse-tuning logic circuit uses a successive approximation search algorithm to achieve the conduction of the coarse-tuning power transistor group by increasing the search step size smoothly in binary. When VOUT > VREFL, the coarse-tuning logic circuit stops increasing the search step size. When VOUT > VREFH and EN3 is at a low level, a transient event is triggered, and the coarse-tuning logic circuit starts searching from the highest step size for the search step size. When VREF > VOUT > VREFL, the coarse-tuning logic circuit stops the conduction of new coarse-tuning power transistor groups and maintains the conduction state of the already opened coarse-tuning power transistor groups. At this time, the fine-tuning logic circuit starts to work. At each rising edge of the clock, a single-bit shift register search is used to turn on a fine-tuning power transistor to provide fine-tuning current. When VOUT > VREF, the fine-tuning logic circuit turns off the fine-tuning power transistor opened at the previous rising edge of the clock. The fine-tuning logic circuit will maintain the current state and will not turn on the subsequent power transistors, maintaining the conduction state of the already opened fine-tuning power transistor group. Finally, the analog loop is enabled, and the analog loop will provide a compensation current to suppress the ripple.

Images