IF circuit linearity compensation method, system, device, storage medium and product

Abstract

The present invention discloses a method, system, device, storage medium, and product for compensating the linearity of an IF circuit. The method comprises obtaining the actual output pulse values ​​of the IF circuit under different excitation currents, and forming a first pulse sequence from the actual output pulse values; obtaining the ideal output pulse values ​​of the IF circuit under different excitation currents, and forming a second pulse sequence from the ideal output pulse values; calculating the digital quantity corresponding to the integrated voltage of each excitation current within a sampling period, and forming an AD sequence from the digital quantities; calculating a pulse ratio based on the first pulse sequence and the second pulse sequence, and forming a ratio sequence from the pulse ratio; fitting the ratio sequence and the AD sequence, and calculating a commutation discharge time based on a linearity compensation function obtained by fitting and the AD value corresponding to the actual input current; and performing commutation control based on the commutation discharge time. The present invention prevents the linearity of the IF circuit from being affected by standard voltage changes, thereby achieving linearity compensation for the IF circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit compensation, and in particular relates to an IF circuit linearity compensation method, system, device, storage medium and product based on commutation discharge time. Background Art

[0002] IF circuits (i.e., current-frequency conversion circuits) typically use a transistor switching scheme to achieve current and frequency switching. Since the voltage Uce between the collector and emitter of the transistor cannot immediately become 0 when it is turned on, while the current Ice between the collector and emitter has already started to rise from 0, there is an overlap of voltage and current at the moment the transistor is turned on, resulting in conduction loss. Similarly, there will be cutoff loss when the transistor is turned off. The higher the switching frequency of the transistor, the greater the switching loss (including conduction loss and cutoff loss). When the input current of the IF circuit increases, the commutation frequency of the IF circuit will also increase accordingly, resulting in greater switching loss, which ultimately affects the linearity of the IF circuit.

[0003] Currently, the technical solution to switching losses is to control the saturation depth of the transistors, increasing their turn-on and turn-off speeds and thus reducing switching losses. This method can only reduce switching losses, not eliminate them, and is ineffective against losses caused by factors such as leakage current. Therefore, the traditional method of varying the transistor saturation depth has very limited impact on linearity accuracy. Summary of the Invention

[0004] The purpose of the present invention is to provide an IF circuit linearity compensation method, system, device, storage medium and product to solve the problem that the traditional method of changing the saturation depth of the transistor cannot eliminate switching losses, resulting in poor effect in improving the linearity accuracy of the IF circuit.

[0005] The present invention solves the above technical problems through the following technical solutions: a method for compensating linearity of an IF circuit, comprising:

[0006] Acquiring actual output pulse values ​​of the IF circuit under different excitation currents, wherein the different excitation currents constitute a current sequence, and the actual output pulse values ​​under the different excitation currents constitute a first pulse sequence;

[0007] Acquire ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, and form a second pulse sequence by the ideal output pulse values ​​under different excitation currents;

[0008] According to different excitation currents of the current sequence, digital quantities corresponding to the integrated voltages of the corresponding excitation currents in one sampling period are calculated respectively, and an AD sequence is formed by the digital quantities corresponding to the integrated voltages of the different excitation currents in one sampling period;

[0009] Calculating pulse ratios under different excitation currents according to the first pulse sequence and the second pulse sequence, and forming a ratio sequence based on the pulse ratios under different excitation currents;

[0010] Fitting the ratio sequence and the AD sequence to obtain a linearity compensation function;

[0011] Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current;

[0012] The commutation control of the IF circuit is performed according to the commutation discharge time, thereby realizing linearity compensation of the IF circuit.

[0013] Furthermore, obtaining an ideal output pulse value of the IF circuit under different excitation currents of the current sequence includes:

[0014] Get the actual output pulse value of the IF circuit under 1mA excitation current;

[0015] The ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence are calculated according to the multiple relationship between different excitation currents of the current sequence and the 1mA excitation current and the actual output pulse value under the 1mA excitation current.

[0016] Furthermore, the calculation formula of the digital quantity corresponding to the integral voltage of the excitation current in one sampling period is:

[0017]

[0018] Among them, ΔAD j The digital value corresponding to the integrated voltage of the j-th excitation current in the current sequence within a sampling period, i j represents the jth excitation current of the current sequence, C represents the capacitance of the integral capacitor of the IF circuit, AD ref Indicates the digital value corresponding to the integrated voltage of 1V.

[0019] Furthermore, a multi-order fitting algorithm is used to fit the ratio sequence and the AD sequence, and the obtained linearity compensation function is:

[0020] y(x)=a n x n +a n-1 x n-1 +…+a1x+a0;

[0021] Where y represents the linearity compensation parameter, that is, the pulse ratio corresponding to the input current; a n ,a n-1 ,…,a1,a0 all represent fitting coefficients; x represents the digital value corresponding to the integrated voltage of the input current within one sampling period; n represents the fitting order.

[0022] Furthermore, the commutation discharge time of the IF circuit is calculated according to the linearity compensation function and the AD value corresponding to the actual input current, including:

[0023] Obtaining a reference commutation discharge time; wherein the reference commutation discharge time refers to the commutation discharge time when the input current is 1 mA;

[0024] A commutation discharge time function is obtained according to the reference commutation discharge time and the linearity compensation function; wherein the commutation discharge time function is:

[0025] t(x)=t0y(x);

[0026] Wherein, t(x) represents the commutation discharge time, t0 represents the reference commutation discharge time, y(x) represents the linearity compensation function, and x represents the digital value corresponding to the integrated voltage of the input current within one sampling period;

[0027] The AD value corresponding to the actual input current is substituted as x into the commutation discharge time function to obtain the corresponding commutation discharge time.

[0028] Based on the same concept, the present invention provides an IF circuit linearity compensation system, including a high-precision constant current source, a pulse acquisition unit, and a control processing module;

[0029] The high-precision constant current source is used to generate different excitation currents and input the different excitation currents to the IF circuit respectively;

[0030] The pulse acquisition unit is used to acquire the actual output pulse value of the IF circuit under different excitation currents;

[0031] The control processing module is used to:

[0032] Acquiring actual output pulse values ​​of the IF circuit under different excitation currents, wherein the different excitation currents constitute a current sequence, and the actual output pulse values ​​under the different excitation currents constitute a first pulse sequence;

[0033] Acquire ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, and form a second pulse sequence by the ideal output pulse values ​​under different excitation currents;

[0034] According to different excitation currents of the current sequence, digital quantities corresponding to the integrated voltages of the corresponding excitation currents in one sampling period are calculated respectively, and an AD sequence is formed by the digital quantities corresponding to the integrated voltages of the different excitation currents in one sampling period;

[0035] Calculating pulse ratios under different excitation currents according to the first pulse sequence and the second pulse sequence, and forming a ratio sequence based on the pulse ratios under different excitation currents;

[0036] Fitting the ratio sequence and the AD sequence to obtain a linearity compensation function;

[0037] Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current;

[0038] The commutation control of the IF circuit is performed according to the commutation discharge time, thereby realizing linearity compensation of the IF circuit.

[0039] Based on the same concept, the present invention also provides an electronic device, comprising a memory, a processor, and a computer program / instruction stored in the memory, wherein the processor executes the computer program / instruction to implement the IF circuit linearity compensation method as described above.

[0040] Based on the same concept, the present invention further provides a computer-readable storage medium having a computer program / instruction stored thereon. When the computer program / instruction is executed by a processor, the IF circuit linearity compensation method described above is implemented.

[0041] Based on the same concept, the present invention further provides a computer program product, comprising a computer program / instruction, which implements the above-mentioned IF circuit linearity compensation method when executed by a processor.

[0042] Beneficial effects

[0043] Compared with the prior art, the advantages of the present invention are:

[0044] The present invention measures the actual output pulses of an IF circuit under different input currents, establishes a relationship curve (i.e., a linearity compensation function) between the true value ΔAD of a digital quantity change caused by the input current and the pulse ratio, and then uses the relationship curve to calculate the commutation discharge time under different input currents. By adjusting the commutation discharge time, the change in discharge current (i.e., the various current losses during the switching process) is compensated, thereby ensuring the stability of the standard voltage, avoiding the influence of the standard voltage change on the linearity of the IF circuit, realizing the linearity compensation of the IF circuit, and improving the linearity accuracy of the IF circuit. At the same time, the pulse glitches caused by the standard voltage change when the input current is large are improved, and the accuracy of the IF circuit within the full range is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only one embodiment of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 is a flow chart of a method for compensating linearity of an IF circuit according to an embodiment of the present invention;

[0047] Figure 2 This is a pulse comparison curve when the output pulses before and after linearity compensation are converted to 1s / mA in the embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts are within the scope of protection of the present invention.

[0049] The following specific embodiments are used to describe the technical solution of the present application in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0050] Example 1

[0051] The basic principle of the IF circuit is the charge balance principle. The precise constant current generated by the constant current source is used as the input current of the IF circuit. The output pulse calculation formula of the IF circuit is:

[0052]

[0053] Among them, N p Indicates the output pulse number of the IF circuit; ΔAD indicates the digital value related to the input current; V s It represents the standard voltage, that is, the discharge voltage of the IF circuit during the commutation discharge time; a represents a constant; M represents the magnification, which is a fixed value.

[0054] According to the output pulse calculation formula (1) of the IF circuit, ΔAD, a, and M will not affect the linearity of the IF circuit. s The calculation formula is:

[0055]

[0056] Among them, Id represents the discharge current, C represents the capacitance of the integral capacitor of the IF circuit, t d Represents the commutation discharge time. When the charging voltage of the integral capacitor of the IF circuit reaches the threshold voltage, the control switch turns on the constant current source to discharge the integral capacitor. The time the switch is open is the commutation discharge time, which is also the discharge time of the integral capacitor.

[0057] According to the calculation formula (2) of the standard voltage, when the input current becomes larger, the discharge current I of the IF circuit will be caused by switching loss, leakage current, etc. d changes, so that the standard voltage V s The commutation discharge time t can be changed to change the commutation discharge time t, which will affect the linearity of the IF circuit and also cause the output pulse of the IF circuit to fluctuate when the input current is large. In order to ensure that the standard voltage of the IF circuit is a constant value within the full range, thereby improving the linearity accuracy of the IF circuit, the commutation discharge time t can be changed to change the commutation discharge time t d To compensate the discharge current I d Aiming at the problem of linearity degradation and output pulse fluctuation of IF circuit when large input current occurs, the present invention proposes an IF circuit linearity compensation method.

[0058] like Figure 1 As shown, an IF circuit linearity compensation method provided by an embodiment of the present invention includes the following steps:

[0059] Step 1: Acquire actual output pulse values ​​of the IF circuit under different excitation currents, and form a current sequence by the different excitation currents, and form a first pulse sequence by the actual output pulse values ​​under the different excitation currents.

[0060] In a specific embodiment of the present invention, a high-precision constant current source is used to generate different excitation currents, and the generated excitation current (i.e., the input current of the IF circuit) is input to the IF circuit, thereby obtaining the actual output pulse value of the IF circuit under the corresponding excitation current.

[0061] Exemplarily, the current sequence is {1mA, 2mA, 4mA, 8mA, 15mA, 20mA, 25mA, 30mA, 35mA, 40mA, 45mA}, and the first pulse sequence corresponding to the current sequence is {19999.92167, 39999.73381, 79999.36609, 159997.6604, 299993.633, 399989.6405, 499984.3324, 599979.1227, 699965.0483, 799955.9379, 899948.3509}.

[0062] Step 2: Obtain ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, and form a second pulse sequence with the ideal output pulse values ​​under different excitation currents.

[0063] In a specific embodiment of the present invention, obtaining an ideal output pulse value of the IF circuit under different excitation currents of the current sequence includes:

[0064] Step 2.1: Obtain the actual output pulse value of the IF circuit under 1mA excitation current;

[0065] Step 2.2: Calculate the ideal output pulse value of the IF circuit under different excitation currents in the current sequence based on the multiple relationship between different excitation currents in the current sequence and the 1mA excitation current and the actual output pulse value under the 1mA excitation current.

[0066] For example, the actual output pulse value corresponding to the 1mA excitation current is 19999.92167. The multiples of the other excitation currents in the current sequence (i.e., 2mA, 4mA, 8mA, 15mA, 20mA, 25mA, 30mA, 35mA, 40mA, 45mA) and the 1mA excitation current are 2, 4, 8, 15, 20, 25, 30, 35, 40, 45, respectively. Therefore, the actual output pulse value corresponding to the other excitation currents in the current sequence is 19999.92167. The ideal output pulse values ​​are 2×19999.92167, 4×19999.92167, 8×19999.92167, 15×19999.92167, 20×19999.92167, 25×19999.92167, 30×19999.92167, 35×19999.92167, 40×19999.92167, and 45×19999.92167.

[0067] Step 3: Calculate the digital quantity corresponding to the integral voltage of the corresponding excitation current in one sampling period according to the different excitation currents of the current sequence, and form an AD sequence by the digital quantities corresponding to the integral voltage of the different excitation currents in one sampling period.

[0068] In a specific embodiment of the present invention, the calculation formula of the digital quantity corresponding to the integral voltage of the excitation current in one sampling period is:

[0069]

[0070] Among them, ΔAD j The digital value corresponding to the integrated voltage of the j-th excitation current in the current sequence within a sampling period, i j represents the jth excitation current of the current sequence, C represents the capacitance of the integral capacitor of the IF circuit, AD refIndicates the digital value corresponding to the integrated voltage of 1V. In this embodiment, AD ref It is 3276.8.

[0071] Step 4: Calculate pulse ratios under different excitation currents based on the first pulse sequence and the second pulse sequence, and form a ratio sequence based on the pulse ratios under different excitation currents.

[0072] Each pulse ratio in the ratio sequence is equal to the ratio of the actual output pulse value to the ideal output pulse value under the same excitation current. Table 1 shows the sequence values ​​of a single IF circuit.

[0073] Table 1 Sequence values ​​of IF circuit

[0074] Current sequence First pulse sequence Second pulse sequence Ratio series AD sequence 1mA 19999.92167 19999.92167 1 327.68 2mA 39999.73381 39999.84334 0.999997262 655.36 4mA 79999.36609 79999.68668 0.999995992 1310.72 8mA 159997.6604 159999.3734 0.999989294 2621.44 15mA 299993.633 299998.8251 0.999982693 4915.2 20mA 399989.6405 399998.4334 0.999978018 6553.6 25mA 499984.3324 499998.0418 0.999972581 8192 30mA 599979.1227 599997.6501 0.999969121 9830.4 35mA 699965.0483 699997.2585 0.999953985 11468.8 40mA 799955.9379 799996.8668 0.999948839 13107.2 45mA 899948.3509 899996.4752 0.999946528 14745.6

[0075] Step 5: Fit the contrast sequence and AD sequence to obtain the linearity compensation function.

[0076] In order to improve the accuracy, a multi-order fitting algorithm is used to fit the contrast sequence and AD sequence, and the obtained linearity compensation function is:

[0077] y(x)=a n x n +a n-1 x n-1 +…+a1x+a0 (4)

[0078] Where y represents the linearity compensation parameter, that is, the pulse ratio corresponding to the input current; a n ,a n-1 ,…,a1,a0 all represent fitting coefficients; x represents the digital value corresponding to the integrated voltage of the input current within a sampling period, that is, the true value of the digital value change every 500us caused by the input current; n represents the fitting order.

[0079] In this embodiment, a third-order fitting algorithm is used to fit the contrast sequence and the AD sequence, and the obtained linearity compensation function is:

[0080] y(x)=a3x 3 +a2x 2 +a1x+a0 (5)

[0081] According to the data in Table 1, the fitting coefficients are as follows: a0=0.9999998683, a1=0.0000008376, a2=0.0000009928, a3=0.000000042.

[0082] Step 6: Calculate the commutation discharge time of the IF circuit based on the linearity compensation function and the AD value corresponding to the actual input current.

[0083] In a specific embodiment of the present invention, the commutation discharge time of the IF circuit is calculated according to the linearity compensation function and the AD value corresponding to the actual input current, including:

[0084] Step 6.1: Obtain the reference commutation discharge time.

[0085] The reference commutation discharge time refers to the commutation discharge time when the input current is 1 mA. In this embodiment, the reference commutation discharge time is 437 μs.

[0086] Step 6.2: Obtain a commutation discharge time function based on the reference commutation discharge time and the linearity compensation function; wherein the commutation discharge time function is:

[0087] t(x)=t0y(x)=t0a n x n +t0a n-1 x n-1 +…+t0a1x+t0a0 (6)

[0088] Where t(x) represents the commutation discharge time, t0 represents the baseline commutation discharge time, y(x) represents the linearity compensation function, and x represents the digital value corresponding to the integrated voltage of the input current within one sampling period. The compensated commutation discharge time is obtained by multiplying the baseline commutation discharge time by the linearity compensation function.

[0089] Step 6.3: Substitute the AD value corresponding to the actual input current as x into the commutation discharge time function to obtain the corresponding commutation discharge time, thereby achieving linearity compensation for the IF circuit.

[0090] Step 7: Perform commutation control of the IF circuit according to the commutation discharge time to achieve linearity compensation for the IF circuit.

[0091] The corresponding commutation discharge time is determined according to the input current of the IF circuit and formula (6), and the commutation control of the IF circuit is then performed according to the commutation discharge time. By adjusting the commutation discharge time to compensate for the change of the discharge current, the purpose of compensating linearity is achieved. At the same time, the pulse glitch problem caused by the change of the standard voltage at large input current is improved, so that the IF circuit can achieve ideal pulse output under different input currents, greatly improving the accuracy of the IF circuit within the full range.

[0092] Figure 2 The figure shows the pulse comparison curve when the output pulse is converted to 1s / mA before and after linearity compensation. Table 2 shows the linearity results within the range after linearity compensation. Figure 2It can be seen that after compensation, the linearity of the IF circuit has been significantly improved. As shown in Table 2, the linearity after compensation is improved by one order of magnitude compared with that before compensation. X / Y / Z represent the three acceleration channels respectively.

[0093] Table 2 Linearity results within the range after linearity calibration

[0094] IF measurement channel X Y Z Linearity before compensation 1.74321147847e-05 2.11032578462e-05 1.274568714544e-05 Linearity after compensation 1.32542178547e-06 1.42185751772e-06 1.205416473851e-06

[0095] Example 2

[0096] An embodiment of the present invention further provides an IF circuit linearity compensation system including a high-precision constant current source, a pulse acquisition unit, and a control processing module.

[0097] High-precision constant current source, used to generate different excitation currents and input different excitation currents to the IF circuit respectively;

[0098] Pulse acquisition unit, used to collect the actual output pulse value of the IF circuit under different excitation currents;

[0099] Control processing module, used for:

[0100] Acquiring actual output pulse values ​​of the IF circuit under different excitation currents, wherein the different excitation currents constitute a current sequence, and the actual output pulse values ​​under the different excitation currents constitute a first pulse sequence;

[0101] Acquire ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, and form a second pulse sequence by the ideal output pulse values ​​under different excitation currents;

[0102] According to different excitation currents of the current sequence, digital quantities corresponding to the integrated voltages of the corresponding excitation currents in one sampling period are calculated respectively, and an AD sequence is formed by the digital quantities corresponding to the integrated voltages of the different excitation currents in one sampling period;

[0103] Calculating pulse ratios under different excitation currents according to the first pulse sequence and the second pulse sequence, and forming a ratio sequence based on the pulse ratios under different excitation currents;

[0104] Fitting the ratio sequence and the AD sequence to obtain a linearity compensation function;

[0105] Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current;

[0106] The commutation control of the IF circuit is performed according to the commutation discharge time, thereby realizing linearity compensation of the IF circuit.

[0107] Example 3

[0108] An embodiment of the present invention further provides an electronic device comprising: a memory, a processor, and a computer program / instruction stored in the memory, wherein the processor executes the computer program / instruction to implement the IF circuit linearity compensation method in the embodiment of the present application.

[0109] Although not shown, the electronic device includes a processor that can perform various appropriate operations and processes based on the programs and / or data stored in the read-only memory (ROM) or the programs and / or data loaded from the storage portion into the random access memory (RAM). The processor can be a multi-core processor or can include multiple processors. In some embodiments, the processor can include a general-purpose main processor and one or more special coprocessors, such as a central processing unit, a graphics processing unit (GPU), a neural network processor (NPU), a digital signal processor (DSP), etc. In the RAM, there is also stored

[0110] Stores various programs and data required for device operation. The processor, ROM, and RAM are connected to each other via a bus. The input / output (I / O) interface is also connected to the bus.

[0111] The processor and memory are used together to execute the program / instructions stored in the memory. When the program / instructions are executed by the computer, the methods, steps or functions described in the above embodiments can be implemented.

[0112] Although not shown, an embodiment of the present invention further provides a computer-readable storage medium having a computer program / instruction stored thereon. When the computer program / instruction is executed by a processor, the IF circuit linearity compensation method in the embodiment of the present application is implemented.

[0113] Storage media in embodiments of the present invention include permanent and non-permanent, removable and non-removable items that can be used to store information using any method or technology. Examples of storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0114] Computer-readable storage media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves.

[0115] Although not shown, an embodiment of the present invention further provides a computer program product, including: a computer program / instruction, which, when executed by a processor, implements the IF circuit linearity compensation method in the embodiment of the present application.

[0116] The above disclosure is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or modifications within the technical scope disclosed in the present invention, and they should all be covered by the scope of protection of the present invention.

Claims

1. A method for compensating linearity of an IF circuit, characterized in that: The compensation method includes: Acquiring actual output pulse values ​​of the IF circuit under different excitation currents, wherein the different excitation currents constitute a current sequence, and the actual output pulse values ​​under the different excitation currents constitute a first pulse sequence; Acquire ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, and form a second pulse sequence by the ideal output pulse values ​​under different excitation currents; According to different excitation currents of the current sequence, digital quantities corresponding to the integrated voltages of the corresponding excitation currents in one sampling period are calculated respectively, and an AD sequence is formed by the digital quantities corresponding to the integrated voltages of the different excitation currents in one sampling period; Calculating pulse ratios under different excitation currents according to the first pulse sequence and the second pulse sequence, and forming a ratio sequence based on the pulse ratios under different excitation currents; Fitting the ratio sequence and the AD sequence to obtain a linearity compensation function; Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current; Performing commutation control of the IF circuit according to the commutation discharge time to achieve linearity compensation of the IF circuit; The ratio sequence and the AD sequence are fitted using a multi-order fitting algorithm, and the obtained linearity compensation function is: ； in, represents the linearity compensation function, that is, the pulse ratio corresponding to the input current; All represent fitting coefficients; It represents the digital value corresponding to the integrated voltage of the input current in one sampling period; n represents the fitting order; Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current includes: Obtaining a reference commutation discharge time; wherein the reference commutation discharge time refers to the commutation discharge time when the input current is 1 mA; A commutation discharge time function is obtained according to the reference commutation discharge time and the linearity compensation function; wherein the commutation discharge time function is: ； in, Indicates the commutation discharge time, Indicates the reference commutation discharge time, represents the linearity compensation function, Indicates the digital value corresponding to the integrated voltage of the input current within a sampling period; The AD value corresponding to the actual input current is used as Substitute it into the commutation discharge time function to obtain the corresponding commutation discharge time.

2. The IF circuit linearity compensation method according to claim 1, wherein: Obtaining ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, including: Get the actual output pulse value of the IF circuit under 1mA excitation current; The ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence are calculated according to the multiple relationship between different excitation currents of the current sequence and the 1mA excitation current and the actual output pulse value under the 1mA excitation current.

3. The IF circuit linearity compensation method according to claim 1, wherein: The calculation formula of the digital quantity corresponding to the integral voltage of the excitation current in one sampling period is: ； in, The first The digital value corresponding to the integral voltage of an excitation current in one sampling period, The first An excitation current, C represents the capacitance of the integrating capacitor of the IF circuit, Indicates the digital value corresponding to the integrated voltage of 1V.

4. An IF circuit linearity compensation system, characterized in that: The system includes a high-precision constant current source, a pulse acquisition unit and a control processing module; The high-precision constant current source is used to generate different excitation currents and input the different excitation currents to the IF circuit respectively; The pulse acquisition unit is used to acquire the actual output pulse value of the IF circuit under different excitation currents; The control processing module is used to: Acquiring actual output pulse values ​​of the IF circuit under different excitation currents, wherein the different excitation currents constitute a current sequence, and the actual output pulse values ​​under the different excitation currents constitute a first pulse sequence; Acquire ideal output pulse values ​​of the IF circuit under different excitation currents of the current sequence, and form a second pulse sequence by the ideal output pulse values ​​under different excitation currents; According to different excitation currents of the current sequence, digital quantities corresponding to the integrated voltages of the corresponding excitation currents in one sampling period are calculated respectively, and an AD sequence is formed by the digital quantities corresponding to the integrated voltages of the different excitation currents in one sampling period; Calculating pulse ratios under different excitation currents according to the first pulse sequence and the second pulse sequence, and forming a ratio sequence based on the pulse ratios under different excitation currents; Fitting the ratio sequence and the AD sequence to obtain a linearity compensation function; Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current; Performing commutation control of the IF circuit according to the commutation discharge time to achieve linearity compensation of the IF circuit; The ratio sequence and the AD sequence are fitted using a multi-order fitting algorithm, and the obtained linearity compensation function is: ； in, represents the linearity compensation function, that is, the pulse ratio corresponding to the input current; All represent fitting coefficients; It represents the digital value corresponding to the integrated voltage of the input current in one sampling period; n represents the fitting order; Calculating the commutation discharge time of the IF circuit according to the linearity compensation function and the AD value corresponding to the actual input current includes: Obtaining a reference commutation discharge time; wherein the reference commutation discharge time refers to the commutation discharge time when the input current is 1 mA; A commutation discharge time function is obtained according to the reference commutation discharge time and the linearity compensation function; wherein the commutation discharge time function is: ； in, Indicates the commutation discharge time, Indicates the reference commutation discharge time, represents the linearity compensation function, Indicates the digital value corresponding to the integrated voltage of the input current within a sampling period; The AD value corresponding to the actual input current is used as Substitute it into the commutation discharge time function to obtain the corresponding commutation discharge time.

5. An electronic device comprising a memory, a processor, and a computer program / instruction stored in the memory, characterized in that: The processor executes the computer program / instructions to implement the IF circuit linearity compensation method according to any one of claims 1 to 3.

6. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instruction is executed by a processor, the IF circuit linearity compensation method according to any one of claims 1 to 3 is implemented.

7. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the IF circuit linearity compensation method according to any one of claims 1 to 3 is implemented.

Images