A high-reliability high-stability high-voltage reference source

Abstract

The application discloses a high-reliability high-stability high-voltage reference source and belongs to the field of power supply circuits.In the application, Is1 is formed by the VBE of a triode Q3 and a resistor R3, the current flowing through a high-voltage NMOS tube hnmos1 is VBE3 / R3, the current is irrelevant to a high-voltage power supply VDD, and the current is relatively small with process and temperature changes; Is2 for copying the current of Is1 is used as a starting current, and the starting can be stable and reliable under any change of the power supply; the high-voltage tubes hnmos2 / hnmos3 make the triodes Q1 and Q2 not need high-voltage triodes, so that many processes can meet the generation of IPTAT current; in the same way, the triode Q1 and the low-voltage tubes pmos9 / pmos10 / nmos1 / nmos2 and the high-voltage tube hnmos4 and the resistor R5 form the Ictat current, so that the application is convenient and special devices are not needed.The reference source has the advantages of wide voltage range, stable and reliable starting, no special devices, and meeting the current source of any temperature characteristics.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and in particular to a high-reliability and high-stability high-voltage reference source. Background Art

[0002] As domestic high-voltage process technology matures and improves, high-voltage analog circuits are developing towards large-scale and high-integration. However, the most basic startup circuit of the high-voltage circuit is indeed a difficult point. Since the high voltage is over 60 or 70 volts, and the gate voltage withstand voltage of the high-voltage MOS tube is relatively low, the startup circuit design of the high-voltage reference source is relatively complicated. In addition, the startup circuit of the high-voltage reference source has the problem of unstable startup current, and will be greatly affected by changes in process and power supply. Summary of the Invention

[0003] The object of the present invention is to provide a high-reliability and high-stability high-voltage reference source to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a high-reliability and high-stability high-voltage reference source, including high-voltage PMOS tubes hpmos1~hpmos8, high-voltage NMOS tubes hnmos1~hnmos4, PMOS tubes pmos1~pmos10, NMOS tubes nmos1~nmos2, transistors Q1~Q3, and resistors R1~R6;

[0005] The source terminals of the PMOS transistors pmos1 to pmos8 are all connected to the power supply voltage Vdd, and the drain terminals of the PMOS transistors pmos1 to pmos8 are respectively connected to the source terminals of the high-voltage PMOS transistors hpmos1 to hpmos8; the gate terminal of the PMOS transistor pmos1 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS transistor pmos2; the gate terminal of the PMOS transistor pmos7 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS transistor pmos8; the gate terminals of the PMOS transistors pmos3 to pmos6 are interconnected;

[0006] The drain of the high-voltage PMOS tube hpmos1 is connected to the drain of the high-voltage NMOS tube hnmos1, the drain of the high-voltage PMOS tube hpmos2 and the drain of the high-voltage PMOS tube hpmos3 are both connected to the drain of the high-voltage NMOS tube hnmos2, and the drain of the high-voltage PMOS tube hpmos4 is connected to the drain of the high-voltage NMOS tube hnmos3 through the resistor R6; the gate of the high-voltage PMOS tube hpmos1 is simultaneously connected to its own drain and the gate of the high-voltage PMOS tube hpmos2, the gates of the high-voltage PMOS tubes hpmos3 to hpmos6 are interconnected, and the gate of the high-voltage PMOS tube hpmos4 is connected to the drain of the high-voltage NMOS tube hnmos3. The drain terminal is connected to the gate terminal of the PMOS tube pmos3 and the gate terminal of the PMOS tube pmos4 at the same time, the drain terminal of the high-voltage NMOS tube hnmos3 is connected to the gate terminal of the high-voltage PMOS tube hpmos3 and the gate terminal of the high-voltage PMOS tube hpmos4 at the same time, the drain terminal of the high-voltage PMOS tube hpmos5 is connected to the source terminal of the PMOS tube pmos9 and the source terminal of the PMOS tube pmos10 at the same time; the drain terminal current of the high-voltage PMOS tube hpmos6 and the drain terminal current of the high-voltage PMOS tube hpmos8 are added together; the drain terminal of the high-voltage PMOS tube hpmos7 is connected to the drain terminal of the high-voltage NMOS tube hnmos4;

[0007] The first end of the resistor R1 is connected to the power supply voltage Vdd, and the second end of the resistor R1 is connected to the first end of the resistor R2; the second end of the resistor R2 is connected to the gate end of the high-voltage NMOS transistor hnmos1 and the collector of the transistor Q3; the base of the transistor Q3 is connected to the source end of the high-voltage NMOS transistor hnmos1 and the first end of the resistor R3, and the emitter of the transistor Q3 and the second end of the resistor R3 are grounded to Vss; the drain end of the high-voltage NMOS transistor hnmos2 is connected to its own gate end and the gate end of the high-voltage NMOS transistor hnmos3, the source end of the high-voltage NMOS transistor hnmos2 is connected to the collector of the transistor Q1 and the gate end of the PMOS transistor pmos9, the base of the transistor Q1 is connected to its own collector and the base of the transistor Q2; the source end of the high-voltage NMOS transistor hnmos3 is connected to the transistor Q 2, the emitter of the transistor Q2 is connected to the first end of the resistor R4, and the emitter of the transistor Q1 and the second end of the resistor R4 are both grounded to Vss; the drain terminal of the PMOS transistor pmos9 is connected to the drain terminal of the NMOS transistor nmos1, and the drain terminal of the NMOS transistor nmos1 is connected to its own gate terminal and the gate terminal of the NMOS transistor nmos2; the gate terminal of the PMOS transistor pmos10 is connected to the first end of the resistor R5, the drain terminal of the PMOS transistor pmos10 is connected to the drain terminal of the NMOS transistor nmos2, and the second end of the resistor R5, the source terminal of the NMOS transistor nmos1 and the source terminal of the NMOS transistor nmos2 are all grounded to Vss; the gate terminal of the high-voltage NMOS transistor hnmos4 is connected to the drain terminal of the PMOS transistor pmos10, and the source terminal of the high-voltage NMOS transistor hnmos4 is connected to the first end of the resistor R5.

[0008] The present invention provides a high-reliability and high-stability high-voltage reference source that is easy to implement and does not require special components. The reference source is applicable to a current source with a wide voltage range, stable and reliable startup, no special components required, and meeting arbitrary temperature characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a structural schematic diagram of a high-reliability and high-stability high-voltage reference source provided by the present invention. DETAILED DESCRIPTION

[0010] The following is a detailed description of a high-reliability, high-stability, high-voltage reference source proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0011] The present invention provides a high-reliability and high-stability high-voltage reference source, comprising high-voltage PMOS tubes hpmos1-hpmos8, high-voltage NMOS tubes hnmos1-hnmos4, PMOS tubes pmos1-pmos10, NMOS tubes nmos1-nmos2, triodes Q1-Q3, and resistors R1-R6; source ends of the PMOS tubes pmos1-pmos8 are all connected to a power supply voltage Vdd, drain ends of the PMOS tubes pmos1-pmos8 are respectively connected to the source ends of the high-voltage PMOS tubes hpmos1-hpmos8; a gate end of the PMOS tube pmos1 is simultaneously connected to its own drain end and the gate end of the PMOS tube pmos2, a gate end of the PMOS tube pmos7 is simultaneously connected to its own drain end and the gate end of the PMOS tube pmos8; and the gate ends of the PMOS tubes pmos3-pmos6 are interconnected.

[0012] The drain end of the high-voltage PMOS tube hpmos1 is connected to the drain end of the high-voltage NMOS tube hnmos1, the drain end of the high-voltage PMOS tube hpmos2 and the drain end of the high-voltage PMOS tube hpmos3 are both connected to the drain end of the high-voltage NMOS tube hnmos2, and the drain end of the high-voltage PMOS tube hpmos4 is connected to the drain end of the high-voltage NMOS tube hnmos3 through the resistor R6. The gate terminal of the high-voltage PMOS tube hpmos1 is simultaneously connected to its own drain terminal and the gate terminal of the high-voltage PMOS tube hpmos2, the gate terminals of the high-voltage PMOS tubes hpmos3 to hpmos6 are interconnected, the drain terminal of the high-voltage PMOS tube hpmos4 is simultaneously connected to the gate terminal of the PMOS tube pmos3 and the gate terminal of the PMOS tube pmos4, the drain terminal of the high-voltage NMOS tube hnmos3 is simultaneously connected to the gate terminal of the high-voltage PMOS tube hpmos3 and the gate terminal of the high-voltage PMOS tube hpmos4, the drain terminal of the high-voltage PMOS tube hpmos5 is simultaneously connected to the source terminal of the PMOS tube pmos9 and the source terminal of the PMOS tube pmos10; the drain current of the high-voltage PMOS tube hpmos6 and the drain current of the high-voltage PMOS tube hpmos8 are added together; the drain terminal of the high-voltage PMOS tube hpmos7 is connected to the drain terminal of the high-voltage NMOS tube hnmos4.

[0013] A first terminal of resistor R1 is connected to a power supply voltage Vdd, and a second terminal of resistor R1 is connected to a first terminal of resistor R2. The second terminal of resistor R2 is connected to both the gate terminal of high-voltage NMOS transistor hnmos1 and the collector of transistor Q3. The base of transistor Q3 is connected to both the source terminal of high-voltage NMOS transistor hnmos1 and the first terminal of resistor R3. The emitter of transistor Q3 and the second terminal of resistor R3 are both connected to ground Vss. The drain of high-voltage NMOS transistor hnmos2 is connected to its own gate terminal and the gate terminal of high-voltage NMOS transistor hnmos3. The source of high-voltage NMOS transistor hnmos2 is connected to both the collector of transistor Q1 and the gate terminal of PMOS transistor pmos9. The base of transistor Q1 is connected to both its own collector and the base of transistor Q2. The source of high-voltage NMOS transistor hnmos3 is connected to the collector of transistor Q2. The emitter of transistor Q2 is connected to the first terminal of resistor R4. The emitter of transistor Q1 and the second terminal of resistor R4 are both connected to ground Vss. The drain of the PMOS transistor pmos9 is connected to the drain of the NMOS transistor nmos1, which in turn is connected to its own gate and the gate of the NMOS transistor nmos2. The gate of the PMOS transistor pmos10 is connected to the first end of the resistor R5, and the drain of the PMOS transistor pmos10 is connected to the drain of the NMOS transistor nmos2. The second end of the resistor R5, the source of the NMOS transistor nmos1, and the source of the NMOS transistor nmos2 are all connected to ground Vss. The gate of the high-voltage NMOS transistor hnmos4 is connected to the drain of the PMOS transistor pmos10, and the source of the high-voltage NMOS transistor hnmos4 is connected to the first end of the resistor R5.

[0014] Please continue reading Figure 1 The startup circuit is composed of resistor R1, resistor R2, transistor Q3, resistor R3, PMOS tube pmos1, PMOS tube pmos2, high-voltage PMOS tube hpmos1, and high-voltage PMOS tube hpmos2. The startup current Is2 copies Is1, and the current of Is1 is VBE3 / R3;

[0015] The positive temperature characteristic current (PTAT) is composed of PMOS tube pmos3, PMOS tube pmos4, high-voltage PMOS tube hpmos3, high-voltage PMOS tube hpmos4, resistor R6, high-voltage NMOS tube hnmos2, high-voltage NMOS tube hnmos3, transistor Q1, transistor Q2, and resistor R4. IPTAT=VTln(m*IC2 / IC1) / R4;

[0016] The negative temperature characteristic current (CTAT) is composed of transistor Q1, PMOS tube pmos9, PMOS tube pmos10, NMOS tube nmos1, NMOS tube nmos2, resistor R5, and high-voltage NMOS tube hnmos4. ICTAT=VBE1 / R5;

[0017] The current of PMOS tube pmos6 / high-voltage PMOS tube hpmos6 copies the current of PMOS tube pmos4 / high-voltage PMOS tube hpmos4, and the current of PMOS tube pmos8 / high-voltage PMOS tube hpmos8 copies the current of PMOS tube pmos7 / high-voltage PMOS tube hpmos7;

[0018] The reference current IREF is composed of the PTAT current of the PMOS tube pmos6 / high-voltage PMOS tube hpmos6 and the CTAT current of the PMOS tube pmos8 / high-voltage PMOS tube hpmos8;

[0019] In the present invention, Is1 is formed by the VBE of transistor Q3 and resistor R3. The current flowing through the high-voltage NMOS transistor hnmos1 is VBE3 / R3. This current is independent of the high-voltage power supply VDD and varies relatively little with process and temperature. By replicating Is1's current as Is2 as the startup current, stable and reliable startup is achieved regardless of power supply variations. By using the high-voltage transistors hnmos2 / hnmos3, transistors Q1 and Q2 do not require high-voltage transistors, allowing many processes to generate the IPTAT current. Similarly, the Ictat current is formed by transistor Q1 and low-voltage transistors pmos9 / pmos10 / nmos1 / nmos2, and high-voltage transistor hnmos4 and resistor R5. This facilitates implementation and does not require special components. This reference source is applicable to current sources with a wide voltage range, stable and reliable startup, no special components required, and meeting arbitrary temperature characteristics.

[0020] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high reliability and high stability high voltage reference source, characterized in that: Including high-voltage PMOS tubes hpmos1~hpmos8, high-voltage NMOS tubes hnmos1~hnmos4, PMOS tubes pmos1~pmos10, NMOS tubes nmos1~nmos2, transistors Q1~Q3, and resistors R1~R6; The source terminals of the PMOS transistors pmos1 to pmos8 are all connected to the power supply voltage Vdd, and the drain terminals of the PMOS transistors pmos1 to pmos8 are respectively connected to the source terminals of the high-voltage PMOS transistors hpmos1 to hpmos8; the gate terminal of the PMOS transistor pmos1 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS transistor pmos2; the gate terminal of the PMOS transistor pmos7 is simultaneously connected to its own drain terminal and the gate terminal of the PMOS transistor pmos8; the gate terminals of the PMOS transistors pmos3 to pmos6 are interconnected; The drain of the high-voltage PMOS tube hpmos1 is connected to the drain of the high-voltage NMOS tube hnmos1, the drain of the high-voltage PMOS tube hpmos2 and the drain of the high-voltage PMOS tube hpmos3 are both connected to the drain of the high-voltage NMOS tube hnmos2, and the drain of the high-voltage PMOS tube hpmos4 is connected to the drain of the high-voltage NMOS tube hnmos3 through the resistor R6; the gate of the high-voltage PMOS tube hpmos1 is simultaneously connected to its own drain and the gate of the high-voltage PMOS tube hpmos2, the gates of the high-voltage PMOS tubes hpmos3 to hpmos6 are interconnected, and the gate of the high-voltage PMOS tube hpmos4 is connected to the drain of the high-voltage NMOS tube hnmos3. The drain terminal is connected to the gate terminal of the PMOS tube pmos3 and the gate terminal of the PMOS tube pmos4 at the same time, the drain terminal of the high-voltage NMOS tube hnmos3 is connected to the gate terminal of the high-voltage PMOS tube hpmos3 and the gate terminal of the high-voltage PMOS tube hpmos4 at the same time, the drain terminal of the high-voltage PMOS tube hpmos5 is connected to the source terminal of the PMOS tube pmos9 and the source terminal of the PMOS tube pmos10 at the same time; the drain terminal current of the high-voltage PMOS tube hpmos6 and the drain terminal current of the high-voltage PMOS tube hpmos8 are added together; the drain terminal of the high-voltage PMOS tube hpmos7 is connected to the drain terminal of the high-voltage NMOS tube hnmos4; The first end of the resistor R1 is connected to the power supply voltage Vdd, and the second end of the resistor R1 is connected to the first end of the resistor R2; the second end of the resistor R2 is connected to the gate end of the high-voltage NMOS transistor hnmos1 and the collector of the transistor Q3; the base of the transistor Q3 is connected to the source end of the high-voltage NMOS transistor hnmos1 and the first end of the resistor R3, and the emitter of the transistor Q3 and the second end of the resistor R3 are grounded to Vss; the drain end of the high-voltage NMOS transistor hnmos2 is connected to its own gate end and the gate end of the high-voltage NMOS transistor hnmos3, the source end of the high-voltage NMOS transistor hnmos2 is connected to the collector of the transistor Q1 and the gate end of the PMOS transistor pmos9, the base of the transistor Q1 is connected to its own collector and the base of the transistor Q2; the source end of the high-voltage NMOS transistor hnmos3 is connected to the transistor Q 2, the emitter of the transistor Q2 is connected to the first end of the resistor R4, and the emitter of the transistor Q1 and the second end of the resistor R4 are both grounded to Vss; the drain terminal of the PMOS transistor pmos9 is connected to the drain terminal of the NMOS transistor nmos1, and the drain terminal of the NMOS transistor nmos1 is connected to its own gate terminal and the gate terminal of the NMOS transistor nmos2; the gate terminal of the PMOS transistor pmos10 is connected to the first end of the resistor R5, the drain terminal of the PMOS transistor pmos10 is connected to the drain terminal of the NMOS transistor nmos2, and the second end of the resistor R5, the source terminal of the NMOS transistor nmos1 and the source terminal of the NMOS transistor nmos2 are all grounded to Vss; the gate terminal of the high-voltage NMOS transistor hnmos4 is connected to the drain terminal of the PMOS transistor pmos10, and the source terminal of the high-voltage NMOS transistor hnmos4 is connected to the first end of the resistor R5.

Images