A voltage stabilizer and a control method thereof

Abstract

The present invention discloses a voltage stabilizer and a control method thereof, wherein the voltage stabilizer comprises a voltage reference circuit, a buffer circuit, a transmission circuit and an output circuit; the input end of the buffer circuit receives a reference voltage provided by the voltage reference circuit, the output end of the buffer circuit is connected to the input end of the transmission circuit; the output end of the transmission circuit is connected to the input end of the output circuit, and the output end of the output circuit is connected to a load. Through the proportional regulation of the load current and the buffer circuit current and the control method combining the awake state and the sleep state, the voltage stabilizer of the present invention obtains the beneficial effects of small area, high precision and ultra-low power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a voltage stabilizer and a control method thereof. Background Art

[0002] With the popularity of portable electronic devices, low power design has become one of the key factors in chip design. In order to adapt to different scenarios and power consumption requirements, electronic devices usually have multiple modes, such as normal working mode, sleep mode and deep sleep mode. In normal working mode, the chip needs to run at high performance to meet the needs of various applications; when not in use, the chip enters sleep mode to reduce power consumption and extend battery life.

[0003] In these modes, the voltage regulator plays an important role, especially in sleep mode and deep sleep mode. Reducing power consumption to extend battery life has become one of the main design goals. However, traditional voltage regulator design is difficult to meet the requirements of power consumption, chip area and output voltage accuracy at the same time.

[0004] In order to achieve extremely low bias currents at the nanoampere level, designers usually use high-value resistors, which occupy a large amount of chip area. In addition, under low current working conditions, the mismatch problem of the device is more prominent. In order to suppress the impact of mismatch, designers usually need to increase the size of the device, which further aggravates the increase in chip area.

[0005] In addition, loop compensation of low-power regulators also faces challenges. Due to the reduction of bias current, frequency compensation becomes difficult. The traditional solution is to use large-sized compensation capacitors or complex compensation networks, but this not only increases the complexity of the design, but also increases the chip area.

[0006] In summary, it is difficult to strike a balance between power consumption, area and accuracy in existing voltage regulator designs. Summary of the invention

[0007] In order to solve the problem in the prior art that it is difficult to strike a balance between power consumption, area and accuracy of a voltage stabilizer, the present invention provides a voltage stabilizer.

[0008] A voltage stabilizer proposed in the present invention comprises a voltage reference circuit, a buffer circuit, a transmission circuit and an output circuit; the output end of the voltage reference circuit is connected to the input end of the buffer circuit; the output end of the buffer circuit is connected to the input end of the transmission circuit; the output end of the transmission circuit is connected to the input end of the output circuit, and the output circuit outputs a stable voltage VCCD;

[0009] Specifically, the buffer circuit includes an operational amplifier, a first NMOS tube, a second NMOS tube and a first PMOS tube; the non-inverting input terminal of the operational amplifier is connected to the output terminal of the voltage reference circuit, and the inverting input terminal of the operational amplifier is connected to the source of the first NMOS tube and the drain of the second NMOS tube; the output terminal of the operational amplifier outputs a first signal VNG and is directly connected to the gate of the first NMOS tube; the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the gate of the first NMOS tube is connected to the transmission circuit; the source of the first PMOS tube is connected to the power supply voltage VDDA, and the gate of the first PMOS tube is connected to the second signal ENB_REG; the source of the second NMOS tube is grounded VSSA, and the gate of the second NMOS tube is connected to the third signal VBN.

[0010] Specifically, the transmission circuit includes a second PMOS tube and a third NMOS tube, the source of the second PMOS tube is connected to the drain of the third NMOS tube and the output end of the buffer circuit, and the drain of the second PMOS tube is connected to the source of the third NMOS tube and the input end of the output circuit; the gate of the second PMOS tube is connected to the fourth signal ENB_TG, and the gate of the third NMOS tube is connected to the fifth signal ENI_TG.

[0011] Specifically, the voltage reference circuit includes third to sixteenth PMOS tubes, fourth to thirteenth NMOS tubes, first to third PNP-type transistors and first to third resistors; the source of the third PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the source of the fourth PMOS tube, and the gate is connected to the gate of the fifth PMOS tube, the drain of the sixth PMOS tube, the drain of the sixth NMOS tube, the drain of the fifteenth PMOS tube and the gate of the eleventh PMOS tube; the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the seventh NMOS tube and the drain of the twelfth NMOS tube, and the gate is connected to the gate of the sixth PMOS tube, the drain of the eighth PMOS tube, the drain of the seventh NMOS tube and the drain of the twelfth NMOS tube, and the gate is connected to the gate of the sixth PMOS tube, the drain of the eighth PMOS tube, the drain of the eighth NMOS tube, the drain of the fifteenth PMOS tube and the drain of the twelfth NMOS tube. The gate of the tenth PMOS tube, the gate of the twelfth PMOS tube and the gate of the fourteenth PMOS tube; the source of the fifth PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the sixth PMOS tube; the source of the seventh PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the source of the eighth PMOS tube, and the gate is connected to the gate of the ninth PMOS tube, the drain of the tenth PMOS tube, the drain of the tenth NMOS tube, the drain of the sixteenth PMOS tube and the gate of the thirteenth PMOS tube; the drain of the eighth PMOS tube is connected to the drain of the eighth NMOS tube, the gate of the ninth NMOS tube, the gate of the eleventh NMOS tube and the drain of the thirteenth NMOS tube; The source of the ninth PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the tenth PMOS tube; the source of the eleventh PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the twelfth PMOS tube; the drain of the twelfth PMOS tube is connected to the first end of the third resistor, the drain of the fourteenth PMOS tube and the input end of the buffer circuit; the source of the thirteenth PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the fourteenth PMOS tube; the source of the fifteenth PMOS tube is connected to the power supply voltage VDDA, and the gate is connected to the sixth signal ENI_REG; the source of the sixteenth PMOS tube is connected to the power supply voltage VDDA, and the gate is connected to the sixth signal ENI_REG. The electrode of the fourth NMOS tube is connected to the drain of the fifth NMOS tube, and the gate is connected to the gate of the sixth NMOS tube, the gate of the eighth NMOS tube and the gate of the tenth NMOS tube; the source of the fifth NMOS tube is connected to the emitter of the first PNP type transistor; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is connected to the first end of the first resistor; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; the source of the ninth NMOS tube is connected to the emitter of the third PNP type transistor; the source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube;The source of the eleventh NMOS transistor is connected to the first end of the second resistor; the source of the twelfth NMOS transistor is connected to the ground VSSA, and the gate is connected to the second signal ENB_REG; the source of the thirteenth NMOS transistor is connected to the ground VSSA, and the gate is connected to the second signal ENB_REG; the emitter of the second PNP transistor is connected to the second end of the first resistor; the bases and collectors of the first PNP transistor, the second PNP transistor and the third PNP transistor are all connected to the ground VSSA; the second end of the second resistor and the second end of the third resistor are both connected to the ground VSSA. ;

[0012] Further, the gate of the third PMOS tube, the gate of the fifth PMOS tube and the gate of the eleventh PMOS tube are connected to the seventh signal VBP1; the gate of the seventh PMOS tube, the gate of the ninth PMOS tube and the gate of the thirteenth PMOS tube are connected to the eighth signal VBP2; the gate of the fourth NMOS tube, the gate of the sixth NMOS tube, the gate of the eighth NMOS tube and the gate of the tenth NMOS tube are connected to the ninth signal VCN; the gate of the fifth NMOS tube and the gate of the seventh NMOS tube are connected to the tenth signal VBN1; the gate of the ninth NMOS tube and the eleventh NMOS tube are connected to the eleventh signal VBN2.

[0013] Specifically, the output circuit includes a capacitor, a seventeenth PMOS tube and a fourteenth NMOS tube; the first end of the capacitor is connected to the output end of the transmission circuit and the gate of the fourteenth NMOS tube, and the second end is grounded; the source of the seventeenth PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the drain of the fourteenth NMOS tube, and the gate is connected to the twelfth signal TIEL; the source of the fourteenth NMOS tube outputs a stable voltage VCCD.

[0014] More specifically, the fourteenth NMOS tube and the first NMOS tube are devices of the same type, and the drain current of the fourteenth NMOS tube is and the drain current of the first NMOS tube The ratio of the width to length of the fourteenth NMOS tube and the width-to-length ratio of the first NMOS tube The ratio is equal, that is The stable voltage VCCD is equal to the source voltage of the first NMOS tube and is also equal to the reference voltage.

[0015] The present invention also proposes a control method for a voltage stabilizer, which is used to control the voltage stabilizer as described above, and comprises the following steps:

[0016] Generate a periodic clock signal;

[0017] Generate control signals for controlling wake-up and sleep states;

[0018] According to the control signal, the working states of the voltage reference circuit, the buffer circuit and the transmission circuit are controlled, wherein:

[0019] In the awake state, activating the voltage reference circuit and the buffer circuit, and turning on the transmission circuit for one or more clock cycles;

[0020] In the sleep state, the voltage reference circuit and the buffer circuit are turned off, and the transmission circuit is disconnected.

[0021] Specifically, the duration of the awake state is controlled to be a first preset duration, and the duration of the sleep state is controlled to be a second preset duration, wherein the second preset duration is greater than the first preset duration.

[0022] More specifically, the method further includes the following steps: generating a first enable signal for controlling the voltage reference circuit and the buffer circuit; generating a second enable signal for controlling the transmission circuit; and generating an inverted signal of the first enable signal and the second enable signal through an inverter.

[0023] Furthermore, by adjusting the width-to-length ratio of the second NMOS tube to control the ratio of the drain current of the first NMOS tube to the load current of the output circuit, the gate-source voltages of the first NMOS tube and the fourteenth NMOS tube are made equal, and the stable voltage VCCD of the regulator is made equal to the reference voltage of the voltage reference circuit.

[0024] The present invention has the following beneficial effects:

[0025] The present invention proposes a novel voltage stabilizer, which achieves low power consumption while ensuring output voltage accuracy through the design and combination of a voltage reference circuit, a buffer circuit, a transmission circuit and an output circuit, and has advantages and application prospects.

[0026] The buffer circuit in the voltage stabilizer of the present invention comprises an operational amplifier, a first NMOS tube, a second NMOS tube and a first PMOS tube. The in-phase input terminal of the operational amplifier is connected to the output terminal of the voltage reference circuit, the inverting input terminal is connected to the source of the first NMOS tube and the drain of the second NMOS tube, and the output terminal is connected to the gate of the first NMOS tube. Such a connection method utilizes the feedback regulation function of the operational amplifier to stabilize the source voltage of the first NMOS tube at a level equal to the voltage reference.

[0027] By designing the width-to-length ratio of the second NMOS tube, the drain current of the first NMOS tube can be adjusted to be close to, equal to, or proportional to the load current, so that the gate-source voltages of the first NMOS tube and the fourteenth NMOS tube are close to or equal to each other, thereby making the output voltage close to or equal to the reference voltage. In addition, when the load current is small, the width-to-length ratio of the first NMOS tube and the fourteenth NMOS tube can be designed to be 1:1, at which time the drain current of the first NMOS tube is equivalent to the load current, and the static power consumption of the buffer circuit is low; when the load current is large, the width-to-length ratio of the first NMOS tube can be set to 1 / 10 or 1 / 100 of that of the fourteenth NMOS tube, so that the drain current of the first NMOS tube is only 1 / 10 or 1 / 100 of the load current, thereby reducing the static power consumption of the buffer circuit.

[0028] In addition, the buffer circuit of the present invention has a simple structure and does not require a complex frequency compensation network, thereby reducing design complexity, reducing the size of the compensation capacitor, saving chip area, and reducing power consumption.

[0029] Based on the above designs, the buffer circuit in the voltage stabilizer of the present invention achieves low static power consumption while ensuring the output voltage accuracy, laying the foundation for the low power operation of the entire voltage stabilizer. Combined with the stable reference voltage provided by the voltage reference circuit, the working mode control of the transmission circuit and the load driving capability of the output circuit, the voltage stabilizer of the present invention has good comprehensive performance, and while meeting the requirements of different applications, it prolongs the battery life and has application prospects.

[0030] The design idea and method of the present invention provide a new idea for solving the contradiction between power consumption, area and accuracy faced by the design of low-power regulators, and are of great significance for promoting the development of low-power circuit design technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A circuit diagram of a voltage stabilizer in one embodiment of the present invention;

[0032] Figure 2 FIG. 1 is a timing control diagram of a voltage regulator in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the described embodiments are only used to explain the technical principles of the present invention, rather than to limit the scope of protection thereof. Those skilled in the art should understand that, without departing from the spirit and scope of the present invention, various changes, modifications or equivalent substitutions may be made to these embodiments. These changes, modifications or equivalent substitutions shall all be deemed to fall within the scope of protection defined by the claims of the present invention.

[0034] like Figure 1As shown, MNAT1 is the first NMOS tube, MN2 is the second NMOS tube, MN3 is the third NMOS tube, MN4 is the fourth NMOS tube, MN5 is the fifth NMOS tube, MN6 is the sixth NMOS tube, MN7 is the seventh NMOS tube, MN8 is the eighth NMOS tube, MN9 is the ninth NMOS tube, MN10 is the tenth NMOS tube, MN11 is the eleventh NMOS tube, MN12 is the twelfth NMOS tube, MN13 is the thirteenth NMOS tube, and MNAT2 is the fourteenth NMOS tube; MP1 is the first PMOS tube, MP2 is the second PMOS tube, MP3 is the third PMOS tube, and MP4 is the fourth PMOS tube. OS tube, MP5 is the fifth PMOS tube, MP6 is the sixth PMOS tube, MP7 is the seventh PMOS tube, MP8 is the eighth PMOS tube, MP9 is the ninth PMOS tube, MP10 is the tenth PMOS tube, MP11 is the eleventh PMOS tube, MP12 is the twelfth PMOS tube, MP13 is the thirteenth PMOS tube, MP14 is the fourteenth PMOS tube, MP15 is the fifteenth PMOS tube, MP16 is the sixteenth PMOS tube, and MP17 is the seventeenth PMOS tube; Q1, Q2, and Q3 are the first, second, and third PNP type triodes respectively; R1, R2, and R3 are the first, second, and third resistors respectively; C1 is a capacitor.

[0035] The input end of the buffer circuit receives the reference voltage VREF provided by the voltage reference circuit, the output end VNG of the buffer circuit is connected to the input end of the transmission circuit, the output end of the transmission circuit is connected to the input end of the output circuit, and the output end of the output circuit is connected to the load to provide a stable output voltage VCCD.

[0036] Specifically, the buffer circuit includes an operational amplifier, MNAT1, MN2 and MP1. The non-inverting input terminal of the operational amplifier is connected to the output terminal of the voltage reference circuit, and the inverting input terminal is connected to the source of MNAT1 and the drain of MN2. The output terminal of the operational amplifier is connected to the gate of MNAT1. The drain of MNAT1 is connected to the drain of MP1, and the gate of MNAT1 is connected to the transmission circuit. The width-to-length ratios of MN2 and MNAT1 are adjustable to optimize the power consumption of the buffer circuit.

[0037] The transmission circuit includes MP2 and MN3, the source of MP2 is connected to the drain of MN3 and the output terminal VNG of the buffer circuit, and the drain of MP2 is connected to the source of MN3 and the input terminal VNG_TG of the output circuit.

[0038] The voltage reference circuit includes MP3~MP16, MN4~MN13, Q1~Q3 and R1~R3. Among them, the source of MP3 is connected to VDDA, the drain of MP3 is connected to the source of MP4, the gate of MP3 is connected to the gate of MP5, the drain of MP6, the drain of MN6, the drain of MP15 and the gate of MP11; the drain of MP4 is connected to the drain of MN4, the gate of MN5, the gate of MN7 and the drain of MN12, the gate of MP4 is connected to the gate of MP6, the gate of MP8, the gate of MP10, the gate of MP12 and the gate of MP14; the source of MP5 is connected to VDDA, The drain of MP5 is connected to the source of MP6; the source of MP7 is connected to VDDA, the drain of MP7 is connected to the source of MP8, the gate of MP7 is connected to the gate of MP9, the drain of MP10, the drain of MN10, the drain of MP16 and the gate of MP13; the drain of MP8 is connected to the drain of MN8, the gate of MN9, the gate of MN11 and the drain of MN13; the source of MP9 is connected to VDDA, the drain of MP9 is connected to the source of MP10; the source of MP11 is connected to VDDA, The drain of P11 is connected to the source of MP12; the source of MP13 is connected to VDDA, and the drain of MP13 is connected to the source of MP14; the sources of MP15 and MP16 are connected to VDDA, and the gates are connected to the ENI_REG signal; the source of MN4 is connected to the drain of MN5, and the gate of MN4 is connected to the gates of MN6, MN8, and MN10; the drain of MN5 is connected to the emitter of Q1; the source of MN6 is connected to the drain of MN7; the source of MN7 is connected to the emitter of Q2 via R1. The source of MN8 is connected to the drain of MN9; the source of MN9 is connected to the emitter of Q3; the source of MN10 is connected to the drain of MN11; the source of MN11 is connected to the ground VSSA via R2; the sources of MN12 and MN13 are connected to the ground VSSA, and the gates are connected to the ENB_REG signal; the drain of MP12 is connected to the drain of MP14 and is connected to the ground VSSA via R3, and the output VREF signal is connected to the buffer circuit; the bases and collectors of Q1, Q2, and Q3 are all connected to the ground VSSA.

[0039] The output circuit includes capacitor C1, MP17 and MNAT2. One end of capacitor C1 is connected to the output end of the transmission circuit and the gate of MNAT2, and the other end is grounded. The source of MP17 is connected to the power supply voltage VDDA, the drain is connected to the drain of MNAT2, and the gate is connected to the twelfth signal TIEL. The source of MNAT2 provides a stable output voltage VCCD.

[0040] In the voltage regulator, the voltage reference circuit provides a reference voltage VREF for the buffer circuit, and the voltage is connected to the non-inverting input terminal of the operational amplifier. After passing through the buffer circuit, the output voltage of the operational amplifier is VNG, that is, the gate voltage of MNAT1. Since the inverting input terminal of the operational amplifier is connected to the source of MNAT1 and the drain of MN2, according to the virtual short and virtual open characteristics of the operational amplifier, it can be known that the voltage V S，MNAT1 When the transmission circuit is turned on, the gate voltage VNG_TG of MNAT2 is equal to VNG, and the source output voltage VCCD of MNAT2 is equal to VREF.

[0041] VCCD = VNG - V GS，MNAT2 = V S，MNAT1 + V GS，MNAT1 -V GS，MNAT2 = VREF + V GS，MNAT1 -V GS，MNAT2 .

[0042] Among them, V GS，MNAT1 and V GS，MNAT2 are the gate-source voltages of MNAT1 and MNAT2 respectively. The output voltage VCCD of the voltage regulator is not only related to the reference voltage VREF, but also affected by the gate-source voltage difference between MNAT1 and MNAT2. In order to stabilize the output voltage VCCD at VREF, it is necessary to reasonably design the circuit parameters so that V GS，MNAT1 and V GS，MNAT2 Similar or equal.

[0043] Specifically, the width-to-length ratio of MN2 can be adjusted to make the current flowing through the drain of MNAT1 close to, equal to, or proportional to the current flowing through the drain of MNAT2 (i.e., the load current). According to the characteristics of MOSFET devices, when the ratio of the drain currents of the two tubes is close to or equal to the ratio of the width-to-length ratios of the two tubes, their gate-source voltages are also close to or equal, i.e., V GS，MNAT1 ≈V GS，MNAT2 Substituting this condition into the above expression, we get:

[0044] VCCD=VREF+V GS，MNAT1 -V GS，MNAT2 ≈ VREF+0= VREF.

[0045] It can be seen that when the drain currents of MNAT1 and MNAT2 are similar, equal or proportional, the output voltage VCCD of the voltage regulator is approximately equal to the reference voltage VREF, which is the core principle of the voltage regulator to achieve the voltage stabilization function.

[0046] In order to make the drain currents of MNAT1 and MNAT2 similar, equal or proportional, the width-to-length ratio of MN2 needs to be reasonably designed. According to the characteristics of MOSFET devices, the drain current of the tube is proportional to its width-to-length ratio. Therefore, by adjusting the width-to-length ratio of MN2, the current flowing through MNAT1 can be controlled to make it similar, equal or proportional to the load current flowing through MNAT2. This process can be optimized through simulation or testing to obtain the best voltage regulation performance.

[0047] In addition to adjusting the width-to-length ratio of MN2, the ratio of the width-to-length ratio of MNAT1 and MNAT2 will also affect the performance of the regulator. The drain current of MNAT1 and MNAT2 satisfies the following relationship:

[0048] .

[0049] in, is the drain current of the MNAT1, is the drain current of the MNAT2, is the width-to-length ratio of the MNAT1, is the MNAT2 width-to-length ratio.

[0050] In order to reduce the power consumption of the buffer circuit, the width-to-length ratio of MNAT1 and MNAT2 needs to be reasonably designed. At the same time, the capacitor C1 in the output circuit also plays a role, especially in maintaining the stability of the gate voltage of MNAT2 in the sleep mode.

[0051] When the load current is small (e.g., 0-1 microampere), the ratio of the width-to-length ratio of MNAT1 and MNAT2 can be designed to be 1:1. This is because under low load current, even if the width-to-length ratios of MNAT1 and MNAT2 are equal, by adjusting the width-to-length ratio of MN2, the current flowing through MNAT1 is equal to the load current, and the static power consumption of the buffer circuit is also low.

[0052] However, when the load current is large (e.g., 1 to 100 microamperes or greater), if the width-to-length ratio of MNAT1 and MNAT2 is still 1:1, the current flowing through MNAT1 will be equivalent to the load current, resulting in a significant increase in the power consumption of the buffer circuit. Even though the gate connection of MNAT1 and MNAT2 can be disconnected by the transmission circuit in sleep mode to reduce average power consumption, in wake-up mode, the drain current of MNAT1 is equal to the load current, and the static power consumption of the buffer circuit is still high.

[0053] To solve this problem, the width-to-length ratio of MNAT1 can be designed to be 1 / 10 or 1 / 100 of the width-to-length ratio of MNAT2. According to the characteristics of MOSFET devices, the drain current of the tube is proportional to its width-to-length ratio. Therefore, when the width-to-length ratio of MNAT2 is 10 times that of MNAT1, the current flowing through MNAT2 will be 10 times the current flowing through MNAT1. Since MNAT2 is connected to a load, its drain current is equal to the load current, so the current flowing through MNAT1 will be 1 / 10 of the load current. Similarly, when the area of ​​MNAT2 is 100 times that of MNAT1, the current flowing through MNAT1 will be 1 / 100 of the load current. By reasonably designing the ratio of the width-to-length ratios of MNAT1 and MNAT2, the drain current of MNAT1 can be made significantly smaller than the drain current of MNAT2 (i.e., the load current), and the static power consumption of the buffer circuit is significantly reduced.

[0054] In wake-up mode, capacitor C1 is charged to the voltage of the gate of MNAT1, i.e., VNG. When entering sleep mode and the transmission circuit is disconnected, capacitor C1 will provide a stable voltage for the gate of MNAT2, so that it continues to conduct and provide current to the load. The size of capacitor C1 needs to be reasonably designed according to factors such as load current and sleep time to ensure the stability of the gate voltage of MNAT2 during sleep.

[0055] In summary, the ratio design of the width-to-length ratio of MNAT1 and MNAT2, as well as the introduction of capacitor C1, together achieve low-power operation of the regulator in different working modes. The reasonable ratio of the width-to-length ratio significantly reduces the drain current of MNAT1 and reduces the static power consumption of the buffer circuit; while capacitor C1 maintains the gate voltage of MNAT2 in sleep mode to make it conductive, ensuring the basic function of the regulator. The combination of the two enables the regulator to achieve ultra-low power operation while meeting the accuracy requirements, and has good application prospects.

[0056] like Figure 2 As shown, the present invention provides a control method for a low power consumption voltage regulator. In a specific embodiment, the specific implementation steps are as follows:

[0057] 1. Generate a periodic clock signal CLK_OSC. This signal is used as the basic clock of the entire circuit to synchronize the operation of each circuit.

[0058] 2. Generate a control signal SLEEP to control the wake-up and sleep states. When the SLEEP signal is at a low level, the circuit is in the wake-up state; when the SLEEP signal is at a high level, the circuit is in the sleep state.

[0059] 3. According to the SLEEP signal, control the working status of the voltage reference circuit, buffer circuit and transmission circuit. This is achieved by generating EN_REG and EN_TG signals:

[0060] a) generating a first enable signal EN_REG that controls a voltage reference circuit and a buffer circuit;

[0061] b) generating a second enable signal EN_TG for controlling the transmission circuit;

[0062] c) Generate ENB_REG, ENI_REG, ENB_TG and ENI_TG signals through inverters:

[0063] ENB_REG is the signal of EN_REG after one-stage inversion;

[0064] ENI_REG is the signal of ENB_REG after one-stage inversion;

[0065] ENB_TG is the signal of EN_TG after one-stage inversion;

[0066] ENI_TG is the signal of ENB_TG after one stage of inversion.

[0067] 4. In the awake state:

[0068] EN_REG is high level, activating the voltage reference circuit and buffer circuit so that their operating current reaches a preset value (eg, 30 μA).

[0069] EN_TG is high, turning on the transmission circuit.

[0070] 5. In dormant state:

[0071] EN_REG is low level, turning off the voltage reference circuit and buffer circuit, reducing their operating current to 0.

[0072] EN_TG is low, disconnecting the transmission circuit.

[0073] 6. Control the duration of the awake state to be a first preset duration (eg, 0.2 mS), and control the duration of the sleep state to be a second preset duration (eg, 20 mS).

[0074] By periodically switching between the wake-up and sleep states, the average operating current of the circuit can be reduced to about 0.3μA, calculated as follows:

[0075] (30μA*0.2mS+0*20mS) / (0.2mS+20mS)≈0.3μA

[0076] This design approach not only ensures the circuit's accuracy and small area during operation (through a 30μA wake-up operating current), but also achieves overall low power consumption (the average current is only 0.3μA). This is particularly valuable for battery-powered devices that need to work for a long time, and can significantly extend the use time of the device.

[0077] Regarding a voltage stabilizer proposed by the present invention, in a specific embodiment, when the resistance of the first resistor R1 reaches several hundred kilo-ohms and the resistance of the second resistor R2 reaches the order of magnitude of mega-ohms, the current flowing through the two resistors can be reduced to a level of several tens of nano-amperes. Since the bias current of the buffer circuit is mainly provided by the voltage reference circuit, the static power consumption of the buffer circuit can also be reduced to the order of nano-amperes. This design scheme further significantly reduces the overall power consumption of the voltage stabilizer while ensuring the output voltage accuracy of the voltage stabilizer.

[0078] In summary, the voltage regulator proposed in the present invention achieves ultra-low power consumption at the nanoampere level while ensuring the output voltage accuracy by adopting a combination design of a voltage reference circuit, a buffer circuit, a transmission circuit and an output circuit, and reasonably selecting circuit parameters.

[0079] In addition, the voltage regulator has a simple circuit structure, flexible design, and is easy to integrate and expand. It has good portability and scalability, and can be applied to the design of voltage regulators with different processes and different voltage ranges, providing ideas and references for low-power voltage regulators.

[0080] The voltage stabilizer and control method thereof embodied in the present invention represent the current development trend of low-power voltage stabilizers, and have a positive role in promoting and referencing the technological progress in related fields. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A voltage stabilizer, characterized in that: It includes a voltage reference circuit, a buffer circuit, a transmission circuit and an output circuit; the output end of the voltage reference circuit is connected to the input end of the buffer circuit; the output end of the buffer circuit is connected to the input end of the transmission circuit; the output end of the transmission circuit is connected to the input end of the output circuit, and the output circuit outputs a stable voltage VCCD; The buffer circuit includes an operational amplifier, a first NMOS tube, a second NMOS tube and a first PMOS tube; the non-inverting input terminal of the operational amplifier is connected to the output terminal of the voltage reference circuit, the inverting input terminal of the operational amplifier is connected to the source of the first NMOS tube and the drain of the second NMOS tube, the output terminal of the operational amplifier outputs a first signal VNG and is directly connected to the gate of the first NMOS tube; the drain of the first NMOS tube is connected to the drain of the first PMOS tube, and the gate of the first NMOS tube is connected to the transmission circuit; the source of the first PMOS tube is connected to the power supply voltage VDDA, and the gate of the first PMOS tube is connected to the second signal ENB_REG; the source of the second NMOS tube is grounded VSSA, and the gate of the second NMOS tube is connected to the third signal VBN; The transmission circuit includes a second PMOS tube and a third NMOS tube, the source of the second PMOS tube is connected to the drain of the third NMOS tube and the output end of the buffer circuit, and the drain of the second PMOS tube is connected to the source of the third NMOS tube and the input end of the output circuit; the gate of the second PMOS tube is connected to the fourth signal ENB_TG, and the gate of the third NMOS tube is connected to the fifth signal ENI_TG; The output circuit includes a capacitor, a seventeenth PMOS tube and a fourteenth NMOS tube; the first end of the capacitor is connected to the output end of the transmission circuit and the gate of the fourteenth NMOS tube, and the second end is connected to the ground VSSA; the source of the seventeenth PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the drain of the fourteenth NMOS tube, and the gate is connected to the twelfth signal TIEL; the source of the fourteenth NMOS tube outputs a stable voltage VCCD.

2. The voltage stabilizer according to claim 1, characterized in that: The voltage reference circuit includes third to sixteenth PMOS tubes, fourth to thirteenth NMOS tubes, first to third PNP-type triodes and first to third resistors; the source of the third PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the source of the fourth PMOS tube, and the gate is connected to the gate of the fifth PMOS tube, the drain of the sixth PMOS tube, the drain of the sixth NMOS tube, the gate of the eleventh PMOS tube and the drain of the fifteenth PMOS tube; the source of the fourth PMOS tube is connected to the drain of the third PMOS tube, and the drain is connected to the drain of the fourth NMOS tube, the gate of the fifth NMOS tube, the gate of the seventh NMOS tube and the drain of the fifteenth PMOS tube. The drain of the second NMOS tube is connected to the gate of the sixth PMOS tube, the gate of the eighth PMOS tube, the gate of the tenth PMOS tube, the gate of the twelfth PMOS tube and the gate of the fourteenth PMOS tube; the source of the fifth PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the sixth PMOS tube; the source of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain is connected to the drain of the sixth NMOS tube, the gate of the third PMOS tube and the gate of the fifth PMOS tube; the source of the seventh PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the source of the eighth PMOS tube, and the gate is connected to the The gate of the ninth PMOS tube, the drain of the tenth PMOS tube, the drain of the tenth NMOS tube and the gate of the thirteenth PMOS tube are connected; the source of the eighth PMOS tube is connected to the drain of the seventh PMOS tube, and the drain is connected to the drain of the eighth NMOS tube, the gate of the ninth NMOS tube, the gate of the eleventh NMOS tube and the drain of the thirteenth NMOS; the source of the ninth PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the tenth PMOS tube; the source of the tenth PMOS tube is connected to the drain of the ninth PMOS tube, and the drain is connected to the gate of the seventh PMOS tube, the gate of the ninth PMOS tube and the drain of the tenth NMOS tube. the drain of the eleventh PMOS tube; the source of the eleventh PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the twelfth PMOS tube; the source of the twelfth PMOS tube is connected to the drain of the eleventh PMOS tube, and the drain is connected to the first end of the third resistor, the drain of the fourteenth PMOS tube and the input end of the buffer circuit; the source of the thirteenth PMOS tube is connected to the power supply voltage VDDA, and the drain is connected to the source of the fourteenth PMOS tube; the source of the fourteenth PMOS tube is connected to the drain of the thirteenth PMOS tube, and the drain is connected to the first end of the third resistor, the drain of the twelfth PMOS tube and the input end of the buffer circuit;The source of the fifteenth PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the gate of the third PMOS tube, the gate of the fifth PMOS tube, the drain of the sixth PMOS tube and the drain of the sixth NMOS tube, and the gate is connected to the sixth signal ENI_REG; the source of the sixteenth PMOS tube is connected to the power supply voltage VDDA, the drain is connected to the gate of the seventh PMOS tube, the gate of the ninth PMOS tube, the drain of the tenth PMOS tube and the drain of the tenth NMOS tube, and the gate is connected to the sixth signal ENI_REG; the source of the fourth NMOS tube is connected to the gate of the fifth NMOS tube The drain of the sixth NMOS tube is connected to the gate of the eighth NMOS tube, the gate of the tenth NMOS tube, and the gate of the sixth NMOS tube; the source of the fifth NMOS tube is connected to the emitter of the first PNP-type triode, and the gate is connected to the gate of the seventh NMOS tube and the drain of the twelfth NMOS tube; the source of the sixth NMOS tube is connected to the drain of the seventh NMOS tube; the source of the seventh NMOS tube is connected to the first end of the first resistor; the source of the eighth NMOS tube is connected to the drain of the ninth NMOS tube; the source of the ninth NMOS tube is connected to the emitter of the third PNP-type triode; The source of the tenth NMOS tube is connected to the drain of the eleventh NMOS tube; the source of the eleventh NMOS tube is connected to the first end of the second resistor; the source of the twelfth NMOS tube is connected to the ground VSSA, and the gate is connected to the second signal ENB_REG; the source of the thirteenth NMOS tube is connected to the ground VSSA, and the gate is connected to the second signal ENB_REG; the emitter of the first PNP transistor is connected to the source of the fifth NMOS tube; the emitter of the second PNP transistor is connected to the second end of the first resistor; the emitter of the third PNP transistor is connected to The first end of the first resistor is connected to the source of the seventh NMOS tube, and the second end is connected to the emitter of the second PNP transistor; the first end of the second resistor is connected to the source of the eleventh NMOS tube, and the second end is connected to the ground VSSA; the first end of the third resistor is connected to the drain of the twelfth PMOS tube, the drain of the fourteenth PMOS tube and the input end of the buffer circuit, and the second end is connected to the ground VSSA. ; 3. The voltage stabilizer according to claim 2, characterized in that: The gate of the third PMOS tube, the gate of the fifth PMOS tube and the gate of the eleventh PMOS tube are connected to the seventh signal VBP1; the gate of the seventh PMOS tube, the gate of the ninth PMOS tube and the gate of the thirteenth PMOS tube are connected to the eighth signal VBP2; the gate of the fourth NMOS tube, the gate of the sixth NMOS tube, the gate of the eighth NMOS tube and the gate of the tenth NMOS tube are connected to the ninth signal VCN; the gate of the fifth NMOS tube and the gate of the seventh NMOS tube are connected to the tenth signal VBN1; the gate of the ninth NMOS tube and the eleventh NMOS tube are connected to the eleventh signal VBN2.

4. The voltage stabilizer according to claim 3, characterized in that: The drain current of the fourteenth NMOS tube is and the drain current of the first NMOS tube The ratio of the width to length of the fourteenth NMOS tube and the width-to-length ratio of the first NMOS tube The ratio is equal, that is The stable voltage VCCD is equal to the source voltage of the first NMOS tube and is also equal to the reference voltage provided by the voltage reference circuit.

5. A control method for a voltage stabilizer, used for controlling the voltage stabilizer according to any one of claims 1 to 4, characterized in that: The following steps are involved: Generates a periodic clock signal; generates a control signal to control the wake-up and sleep states; According to the control signal, the working state of the voltage reference circuit, the buffer circuit and the transmission circuit is controlled, wherein: in the awake state, the voltage reference circuit and the buffer circuit are activated, and the transmission circuit is turned on for one or more clock cycles; In the sleep state, the voltage reference circuit and the buffer circuit are turned off, and the transmission circuit is disconnected.

6. The method according to claim 5, characterized in that: The duration of the awake state is controlled to be a first preset duration, and the duration of the sleep state is controlled to be a second preset duration, wherein the second preset duration is greater than the first preset duration.

7. The method according to claim 5, characterized in that The method further includes the following steps: generating a first enable signal for controlling the voltage reference circuit and the buffer circuit; generating a second enable signal for controlling the transmission circuit; and generating an inverted signal of the first enable signal and the second enable signal through an inverter.

8. The method according to claim 5, characterized in that The ratio of the drain current of the first NMOS tube to the load current of the output circuit is controlled by adjusting the width-to-length ratio of the second NMOS tube, so that the gate-source voltages of the first NMOS tube and the fourteenth NMOS tube are equal, and the stable voltage VCCD of the regulator is equal to the reference voltage of the voltage reference circuit.

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