Device and method for generating clock signal, chip and electronic equipment
By designing the master clock module and multi-stage slave clock module in the touch and display driver integration chip, and using sub-clock units and control units to achieve refined control of clock signals, the problem that other module clocks cannot be turned off after the microcontroller is working is solved. , saving power consumption and improving system stability.
Patent Information
- Application Number
- CN202411328609.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-31
AI Technical Summary
In the touch and display driver integrated chip, after the microcontroller is completed, the clocks of other modules remain on, resulting in increased power consumption and lack of refined control.
Design a device including a master clock module and a multi-stage slave clock module, and realize refined control of the clock signal through the sub-clock unit and the control unit, automatically close the corresponding clock module according to the effectiveness of the sub-clock signal, and finally all sub-clocks are Stops the generation of the main clock signal when invalid.
It realizes refined control of clock signals, saves power consumption, and ensures that the clock is easy to turn on and difficult to turn off, and prevents circuit errors caused by the inability to turn on.
Smart Images
Figure CN119225474A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of digital circuits, and more specifically, to a device and method for generating a clock signal, a chip and an electronic device. Background Art
[0002] Touch and Display Driver Integration (TDDI) chip is a touch display integrated chip. In TDDI chip, the touch function and display function work alternately. In order to save power consumption, the microcontroller (MCU) often turns off the total clock of the touch circuit after processing the data and before the display function starts, so as to save power consumption.
[0003] The basis for MCU to turn off the main clock is that the work of MCU itself has been completed, and then decide to turn off the main clock; but before the work of MCU is completed, other modules in the circuit may no longer need the clock. If the clock is still turned on at this time, the power consumption will increase.
[0004] Therefore, it is desirable to provide a device for generating a clock signal to achieve fine control of the clock. Summary of the invention
[0005] In view of the above problems, an object of the present invention is to provide a device and method, a chip and an electronic device for generating a clock signal, so as to achieve refined control of the clock and save power consumption.
[0006] According to a first aspect of the present invention, there is provided an apparatus for generating a clock signal, comprising:
[0007] A master clock module, configured to generate a master clock signal; and
[0008] A multi-stage slave clock module generates multiple output clock signals according to the master clock signal, each stage of the slave clock module includes at least one sub-module, each of the sub-modules includes at least one clock unit for providing a sub-clock signal, in the non-last stage of the slave clock module, the sub-clock signal provided by the clock unit in the first stage of the slave clock module is used as the input signal of the next stage of the slave clock module, and in the last stage of the slave clock module, the sub-clock signal provided by the clock unit is used as the output clock signal,
[0009] Wherein, when the sub-clock signals provided by all the clock units in one of the sub-modules in the slave clock module of the first stage are invalid, the sub-clock signals provided by the corresponding clock units in the slave clock module of the previous stage are controlled to be invalid,
[0010] When the sub-clock signals provided by all the clock units of each sub-module in the first-stage slave clock module are invalid, the master clock module is controlled to stop generating the master clock signal.
[0011] Optionally, it also includes:
[0012] A slave control module provides a corresponding switch signal to each of the clock units in at least one level of the slave clock module to control each of the sub-clock signals respectively; and
[0013] A main control module controls the main clock module according to the switch signal provided by the control unit corresponding to each clock unit in the first-level slave clock module,
[0014] When the sub-clock signals provided by all the clock units in one of the sub-modules in the slave clock module of the first stage are invalid, the slave control module controls the sub-clock signals provided by the corresponding clock units in the slave clock module of the previous stage to be invalid.
[0015] Optionally, the slave control module includes:
[0016] A plurality of control units corresponding one to one to the plurality of clock units, each of the control units being controlled by an enable signal and providing the switch signal,
[0017] Wherein, in each level of the slave clock module, one of the multiple clock units corresponds to the first control unit, and control units other than the first control unit are also connected to the first control unit and provide the switch signal to the first control unit to control the first control unit, and the first control unit is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level,
[0018] When the enable signals received by multiple control units connected to the multiple clock units corresponding to the control units other than the first control unit all indicate that the sub-clock signal is invalid, the control units other than the first control unit provide the switching signal to the first control unit; when the switching signals received by the first control unit are all invalid and the received enable signals indicate that the sub-clock signal is invalid, the first control unit provides the switching signal and controls the control unit corresponding to the corresponding clock unit in the previous level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous level slave clock module is invalid.
[0019] Optionally, the slave control module includes:
[0020] A plurality of control units corresponding one to one to the plurality of clock units, each of the control units being controlled by an enable signal and providing the switch signal,
[0021] Wherein, the control unit corresponding to each clock unit in the submodule of the slave clock module of the first level is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level,
[0022] When the enable signals received by the multiple control units connected to all the clock units in the sub-module of the first-level slave clock module all indicate that the sub-clock signal is invalid, the multiple control units provide the switching signal and control the control units corresponding to the corresponding clock units in the previous-level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous-level slave clock module is invalid.
[0023] Optionally, each of the control units comprises:
[0024] A first conduction signal receiving end, used for receiving a first conduction signal source;
[0025] A first conduction enable terminal, used to receive a first conduction enable signal to control whether the first conduction signal source is received;
[0026] A first shutdown signal receiving end, used for receiving a first shutdown signal source;
[0027] A first shutdown enable terminal is used to receive a first shutdown enable signal to control whether the first shutdown signal source is received,
[0028] When the first conduction enable signal is valid, the control unit receives the first conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
[0029] Optionally, each of the control units further comprises:
[0030] A second conduction signal receiving end, used for receiving a second conduction signal source;
[0031] A second conduction enable terminal, used to receive a second conduction enable signal to control whether the second conduction signal source is received;
[0032] A second shutdown signal receiving end, used for receiving a second shutdown signal source;
[0033] A second shutdown enable terminal is used to receive a second shutdown enable signal to control whether the second shutdown signal source is received,
[0034] When the first conduction enable signal and / or the second conduction enable signal are valid, the control unit receives the first conduction signal source and / or the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
[0035] When both the first shutdown enable signal and the second shutdown enable signal are valid, the control unit stops receiving the first conduction signal source and the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be invalid.
[0036] Optionally, each level of the slave clock module further includes a frequency division module for performing frequency division processing on the input signal.
[0037] Among them, in the first-level slave clock module, the frequency division module divides the frequency of the master clock signal and sends it to each of the sub-modules.
[0038] In the non-first-stage slave clock module, the frequency division module divides the sub-clock signal provided by the previous-stage slave clock module and sends the divided sub-clock signal to each of the sub-modules.
[0039] Optionally, each of the clock units includes a clock input terminal, an enable terminal, and an output terminal, wherein the clock input terminal is used to receive the input signal after frequency division processing, the enable terminal is used to receive the switch signal, and the output terminal is used to provide the sub-clock signal.
[0040] When the switch signal is valid, the clock unit converts the input signal after frequency division into the sub-clock signal and outputs it.
[0041] According to a second aspect of the present invention, a chip is provided, comprising the apparatus for generating a clock signal as described above.
[0042] According to a third aspect of the present invention, there is provided an electronic device comprising the chip as described above.
[0043] Optionally, the electronic device has a display panel, and the electronic device is any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, an electronic door lock, and a vehicle-mounted terminal.
[0044] According to a fourth aspect of the present invention, there is provided a method for generating a clock signal, comprising:
[0045] Generate a master clock signal;
[0046] Generate a multi-level clock signal according to the main clock signal, each level of the clock signal includes at least one sub-clock signal divided into at least one group of clock signals, for non-last level clock signals, each of the sub-clock signals is used as an input signal for generating a next level of clock signal, and for the last level clock signal, each of the sub-clock signals is used as an output clock signal; and
[0047] When all the sub-clock signals of a group of clock signals in a first-level clock signal are invalid, the sub-clock signals corresponding to the group of clock signals of the previous-level clock signal are controlled to be invalid.
[0048] When all the sub-clock signals of the first stage are invalid, the generation of the main clock signal is stopped.
[0049] According to a fourth aspect of the present invention, there is provided a method for generating a clock signal, comprising:
[0050] generating a master clock signal; and
[0051] A plurality of output clock signals are generated according to the master clock signal by using a multi-stage slave clock module, wherein each stage of the slave clock module comprises at least one sub-module, and each of the sub-modules comprises at least one clock unit for providing a sub-clock signal. In the non-last stage of the slave clock module, the sub-clock signal provided by the clock unit in the first stage of the slave clock module serves as an input signal of the next stage of the slave clock module, and in the last stage of the slave clock module, the sub-clock signal provided by the clock unit serves as the output clock signal.
[0052] Wherein, when the sub-clock signals provided by all the clock units in one of the sub-modules in the slave clock module of the first stage are invalid, the sub-clock signals provided by the corresponding clock units in the slave clock module of the previous stage are controlled to be invalid,
[0053] When the sub-clock signals provided by all the clock units of each sub-module in the first-stage slave clock module are invalid, the master clock module is controlled to stop generating the master clock signal.
[0054] Optionally, it also includes:
[0055] Providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module to control each of the sub-clock signals respectively; and
[0056] Whether to generate the master clock signal is controlled according to the switch signals corresponding to the clock units in the first-level slave clock module.
[0057] Optionally, providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module to respectively control each of the sub-clock signals comprises:
[0058] The plurality of clock units are controlled respectively by a plurality of control units corresponding to the plurality of clock units, each of the control units is controlled by an enable signal and provides the switch signal,
[0059] Wherein, in each of the submodules, one of the multiple clock units corresponds to a first control unit, and control units other than the first control unit are also connected to the first control unit and provide the switch signal to the first control unit to control the first control unit, and the first control unit is also connected to a control unit corresponding to a corresponding clock unit in the slave clock module of the previous stage to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous stage,
[0060] When the enable signals received by multiple control units connected to the multiple clock units corresponding to the control units other than the first control unit all indicate that the sub-clock signal is invalid, the control units other than the first control unit provide the switching signal to the first control unit; when the switching signals received by the first control unit are all invalid and the received enable signals indicate that the sub-clock signal is invalid, the first control unit provides the switching signal and controls the control unit corresponding to the corresponding clock unit in the previous level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous level slave clock module is invalid.
[0061] Optionally, providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module to respectively control each of the sub-clock signals comprises:
[0062] The plurality of clock units are controlled respectively by a plurality of control units corresponding to the plurality of clock units, each of the control units is controlled by an enable signal and provides the switch signal,
[0063] Wherein, the control unit corresponding to each clock unit in the submodule of the slave clock module of the first level is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level,
[0064] When the enable signals received by the multiple control units connected to all the clock units in the sub-module of the first-level slave clock module all indicate that the sub-clock signal is invalid, the multiple control units provide the switching signal and control the control units corresponding to the corresponding clock units in the previous-level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous-level slave clock module is invalid.
[0065] Optionally, using a plurality of control units corresponding one-to-one to the plurality of clock units to respectively control the plurality of clock units comprises:
[0066] receiving a first conduction signal source;
[0067] receiving a first conduction enable signal to control whether the first conduction signal source is received;
[0068] receiving a first shutdown signal source;
[0069] receiving a first shutdown enable signal to control whether the first shutdown signal source is received,
[0070] When the first conduction enable signal is valid, the control unit receives the first conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
[0071] Optionally, using a plurality of control units corresponding one-to-one to the plurality of clock units to respectively control the plurality of clock units further comprises:
[0072] receiving a second conduction signal source;
[0073] receiving a second conduction enable signal to control whether the second conduction signal source is received;
[0074] receiving a second shutdown signal source;
[0075] receiving a second shutdown enable signal to control whether the second shutdown signal source is received,
[0076] When the first conduction enable signal and / or the second conduction enable signal are valid, the control unit receives the first conduction signal source and / or the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
[0077] When both the first shutdown enable signal and the second shutdown enable signal are valid, the control unit stops receiving the first conduction signal source and the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be invalid.
[0078] Optionally, generating a plurality of output clock signals according to the master clock signal further comprises: performing frequency division processing on the input signal,
[0079] Wherein, in the first-level slave clock module, the master clock signal is divided and then sent to each of the sub-modules.
[0080] In the non-first-stage slave clock module, the sub-clock signal provided by the previous-stage slave clock module is divided and sent to each of the sub-modules.
[0081] When the switch signal is valid, the clock unit converts the input signal after frequency division into the sub-clock signal and outputs it.
[0082] The device and method, chip and electronic device for generating clock signals provided by the present invention, when the control unit sends a switch signal representing the turning off of the sub-clock signal, the sub-clock signal is turned off, and when the control units corresponding to all the clock units in the sub-module have sent switch signals representing the turning off of the sub-clock signal, the control unit corresponding to the corresponding previous-stage clock unit sends a switch signal representing the turning off of the sub-clock signal to turn off the corresponding sub-clock signal / main clock; when all slave control modules send switch signals representing the turning off of the sub-clock signal, the main clock signal is turned off. Each digital circuit in the embodiment of the present invention can determine the clock switch of each module by itself, and does not need to be turned off together with the main clock, thereby realizing refined control of the clock signal, so that other modules can turn off the corresponding clock to save power consumption during the operation of the microcontroller.
[0083] Furthermore, the first on-signal source, the second on-signal source, the first off-signal source and the second off-signal source of the control unit all have enable bits, and a suitable signal source can be selected. When one on-signal source is enabled, the switch signal is valid, and the clock unit provides a valid sub-clock signal; when all off-signal sources are enabled, the switch signal is invalid, and the clock unit stops providing the sub-clock signal. Such a setting can ensure that the clock is relatively easy to turn on and relatively difficult to turn off, and prevent the circuit from failing due to the inability to turn on the clock. BRIEF DESCRIPTION OF THE DRAWINGS
[0084] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0085] Figure 1 A schematic diagram of a clock signal according to an embodiment of the present invention is shown;
[0086] Figure 2 A schematic diagram showing an apparatus for generating a clock signal according to a first embodiment of the present invention is shown;
[0087] Figure 3 A schematic diagram showing an apparatus for generating a clock signal according to a second embodiment of the present invention is shown;
[0088] Figure 4 A schematic diagram of a control unit according to an embodiment of the present invention is shown;
[0089] Figure 5 A flow chart of a method for generating a clock signal according to a first embodiment of the present invention is shown;
[0090] Figure 6 A flow chart of a method for generating a clock signal according to a second embodiment of the present invention is shown. DETAILED DESCRIPTION
[0091] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.
[0092] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.
[0093] It should be understood that the connection / coupling of A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiment of the present application is not limited to this.
[0094] Embodiments of the device and method, chip, and electronic device for generating a clock signal provided by the present application will be described below in conjunction with the accompanying drawings.
[0095] An embodiment of the present invention provides a device for generating a clock signal, the device comprising a master clock module and at least one level of slave clock modules (for example, N levels of slave clock modules, N is a natural number greater than or equal to 1). The master clock module is used to generate a master clock signal; the multi-level slave clock modules are used to generate multiple output clock signals according to the master clock signal, each level of the slave clock module comprises at least one sub-module, and each sub-module comprises at least one clock unit for providing a sub-clock signal, wherein, in the first level of the slave clock module, the master clock signal is used as the input signal, in the non-first level of the slave clock module, the sub-clock signal provided by the clock unit in the previous level of the slave clock module is used as the input signal, and in the last level of the slave clock module, the sub-clock signal provided by the clock unit is used as the output clock signal, and when the sub-clock signals provided by all the clock units in the first level of the slave clock module are invalid, the input signal of the slave clock module of this level is controlled to be invalid.
[0096] In the first-level slave clock module, the master clock signal is used as the input signal of the first-level slave clock module. If N is 1, the sub-clock signal provided by each clock unit in the first-level slave clock module is used as the output clock signal; if N is greater than 1, the sub-clock signal provided by each clock unit in the first-level slave clock module is used as the input signal of the second-level slave clock module, and the sub-clock signal provided by the clock unit in the Nth-level slave clock module is used as the output clock signal.
[0097] If N is greater than 2, the n-th level slave clock module uses the sub-clock signal provided by the n-1-th level slave clock module as the input signal, and the sub-clock signal provided by each clock unit in the n-th level slave clock module is used as the input signal of the n+1-th level slave clock module, where n is a natural number greater than 1 and less than N. When the sub-clock signals provided by all the clock units in a sub-module in the n+1-th level slave clock module are invalid, the sub-clock signals provided by the corresponding clock units in the n-th level slave clock module are controlled to be invalid.
[0098] In an embodiment of the present invention, the main clock signal and the sub-clock signal have a valid state and an invalid state, respectively. In the valid state, the main clock signal / sub-clock signal switches between the first level and the second level at a stable frequency. The first level is, for example, a high level, and the high level can be set differently according to the requirements of the circuit. The second level is, for example, a low level, and the low level is usually a zero potential, or other levels of non-zero potential (having a positive voltage amplitude or a negative voltage amplitude). In the invalid state, the main clock signal / sub-clock signal can be maintained at a zero potential or other levels of non-zero potential, and the level can be the same as the aforementioned second level, or different from the aforementioned second level, as long as it is stable and has no timing effect. It can be seen that when the main clock signal / sub-clock signal is valid, it switches between the first level and the second level at a stable frequency, and when the main clock signal / sub-clock signal is invalid, it is maintained at the second level or other levels.
[0099] Therefore, in the embodiment of the present invention, the main clock signal / sub-clock signal is invalid, which means that the main clock signal / sub-clock signal is maintained at zero potential or other levels other than zero potential. For example, the main clock signal / sub-clock signal is maintained at zero potential by controlling the clock unit to be turned off, or a pull-down circuit is set inside or outside the clock unit to pull the main clock signal / sub-clock signal down to zero potential or other levels other than zero potential, and the main clock signal / sub-clock signal at a non-zero potential has no timing effect.
[0100] Figure 1 The schematic diagram of the clock signal according to the embodiment of the present invention is shown. The waveform schematic diagram shows, for example, a working flag Working_flag, a first module working waveform Modul_1, a second module working waveform Modul_2 and a microcontroller (MCU) working waveform MCU.
[0101] like Figure 1 As shown, during the microcontroller sleep period, the microcontroller clock MCU_clk is turned off; during the microcontroller operation period, the microcontroller clock MCU_clk is turned on.
[0102] When the working flag Working_flag is pulled high, the digital circuit starts the main work. At this time, the main clock Main_clk is turned on and the sub-clock Sub_clk is also turned on; when the working flag Working_flag is pulled low, the digital circuit basically does not work, and only the secondary module is retained for timing / waking up the next main work, so the main clock Main_clk is turned off and the sub-clock Sub_clk is turned on.
[0103] It can be seen from the waveform diagram that the device for generating a clock signal provided by the embodiment of the present invention realizes fine control of the clock signal, so that other modules can turn off the corresponding clocks to save power consumption during the operation of the microcontroller.
[0104] Figure 2 A schematic diagram of a device for generating a clock signal according to a first embodiment of the present invention is shown.
[0105] As shown in FIG2 , the apparatus 100 for generating a clock signal includes a master clock module 110 and at least one slave clock module 120. Figure 2 For the sake of simplicity, only one level of slave clock module 120 is shown, and the first level slave clock module 120 includes a frequency division module 121 and four sub-modules 122, and each sub-module 122 includes four clock units 1221. It should be understood that the number of levels of the slave clock module and the number of sub-modules and clock units it contains can be set according to actual conditions.
[0106] The master clock module 110 is used to generate a master clock signal. The master clock module 110 can be any type of clock generator, for example, the master clock module 110 is selected from any one of a crystal oscillator, a ring oscillator, a phase-locked loop, a microprocessor clock generator, a high-frequency clock generator, a low-frequency clock generator, and a programmable clock generator.
[0107] The slave clock module 120 includes a frequency division module 121 and at least one sub-module 122, and is configured to generate a plurality of output clock signals according to the master clock signal.
[0108] The frequency division module 121 is used to divide the input signal received from the clock module 120 and send it to each sub-module 122. In this embodiment, the input signal of the clock module 120 is the main clock signal. In an alternative embodiment, when the number of levels of the clock module is greater than 1, the input signal of the n-th level clock module is the sub-clock signal output by the previous level clock module. The frequency division module 121 can be various types of digital frequency dividers, for example, the frequency division module 121 is selected from any one of a binary frequency divider, a D flip-flop frequency divider, a Johnson frequency divider, a programmable frequency divider, an asynchronous frequency divider, and a synchronous frequency divider.
[0109] Each submodule 122 includes at least one clock unit 1221. After receiving the input signal after the frequency division processing provided by the frequency division module 121, each clock unit 1221 determines whether to output the sub-clock signal according to the switch signal it receives. Each clock unit 1221 includes, for example, a clock input terminal, an enable terminal, and an output terminal. The clock input terminal is used to receive the input signal after the frequency division processing, the enable terminal is used to receive the switch signal, and the output terminal is used to provide the sub-clock signal. When the switch signal is valid, the clock unit 1221 converts the input signal after the frequency division processing into a sub-clock signal and outputs it.
[0110] In this embodiment, the apparatus 100 for generating a clock signal further includes a main control module 130 and a slave control module 140, and the slave control module 140 includes at least one control unit 141. The slave control module 140 provides a corresponding switch signal to at least each clock unit 1221 in the first-stage slave clock module 120 to respectively control whether to generate each sub-clock signal. The main control module 130 controls the master clock module 110 according to the switch signal provided by the control unit 141 corresponding to each clock unit 1221 in the first-stage slave clock module 120.
[0111] In this embodiment, when the sub-clock signals provided by all the clock units 1221 in a sub-module 122 in a first-stage slave clock module 120 are invalid, the slave control module 140 controls the sub-clock signals provided by the corresponding clock units 1221 in the previous-stage slave clock module 120 to be invalid.
[0112] Optionally, the slave control module 140 includes a plurality of control units 141 corresponding to the plurality of clock units 1221 one by one, each control unit 141 is controlled by an enable signal and provides a switch signal. In the submodule 122, one of the plurality of clock units 1221 corresponds to the first control unit 141 (each first control unit adopts Figure 2 As shown in the dashed box in FIG. 1 ), the control units 141 other than the first control unit 141 are also connected to the first control unit 141, and provide a switch signal to the first control unit 141 to control the first control unit 141, and the first control unit 141 is also connected to the control unit 141 corresponding to the corresponding clock unit 1221 in the previous stage slave clock module 120 to provide a switch signal and control the control unit 141 corresponding to the corresponding clock unit 1221 in the previous stage slave clock module 120,
[0113] When the enable signals received by the multiple control units 141 connected to the multiple clock units 1221 corresponding to the control units 141 other than the first control unit 141 all indicate that the sub-clock signal is invalid, the control units 141 other than the first control unit 141 provide a switching signal to the first control unit 141; when the switching signals received by the first control unit 141 are all invalid and the received enable signals indicate that the sub-clock signal is invalid, the first control unit 141 provides a switching signal and controls the control unit 141 corresponding to the corresponding clock unit 1221 in the previous stage slave clock module 120, so that the sub-clock signal provided by the corresponding clock unit 1221 in the previous stage slave clock module 120 is invalid.
[0114] In the first-stage slave clock module 120 , when the sub-clock signals provided by all the clock units 1221 of all the sub-modules 122 are invalid, the main control module 130 is controlled to generate an invalid switch signal to control the master clock module 110 to stop generating the master clock signal.
[0115] The control process from the last-stage slave clock module 120 to the first-stage clock module 120 described above realizes the back pressure from the secondary to the primary, thereby shutting down the submodule 122. Similarly, the shut-down conditions of the other three submodules 122 can be obtained. Finally, when the sub-clock signals provided by all the clock units 1221 in the first-stage slave clock module 120 are invalid, the main control module 130 is controlled to generate an invalid switch signal to control the main clock module 110 to stop generating the main clock signal, thus completing the final back pressure mechanism and shutting down the main clock signal to reduce power consumption.
[0116] Figure 3 FIG. 1 is a schematic diagram of a device for generating a clock signal according to a second embodiment of the present invention. In this embodiment, the connection mode of the master clock module 110 and at least one level of the slave clock module 120 is the same as that of FIG. Figure 2 The same, no further elaboration here.
[0117] In this embodiment, the slave control module 140 includes a plurality of control units 141 corresponding one-to-one to the plurality of clock units 1221, each control unit 141 is controlled by an enable signal and provides a switch signal, wherein the control unit 141 corresponding to each clock unit 1221 in a submodule 122 in a first-level slave clock module 120 is also connected to the control unit 141 corresponding to the corresponding clock unit 1221 in the previous-level slave clock module 120 to provide a switch signal and control the control unit 141 corresponding to the corresponding clock unit 1221 in the previous-level slave clock module 120; when the enable signals received by the plurality of control units 141 connected to all the clock units 1221 in a submodule 122 in a first-level slave clock module 120 all indicate that the sub-clock signal is invalid, the plurality of control units 141 provide a switch signal and control the control unit 141 corresponding to the corresponding clock unit 1221 in the previous-level slave clock module 120, so that the sub-clock signal provided by the corresponding clock unit 1221 in the previous-level slave clock module 120 is invalid.
[0118] Figure 4 A schematic diagram of a control unit according to an embodiment of the present invention is shown.
[0119] like Figure 4 As shown, the signal terminals of each control unit 141 include: a first on-signal receiving terminal turn_on_0, used for receiving a first on-signal source; a first on-en enable terminal on_0_en, used for receiving a first on-enable signal to control whether the first on-signal source is received; a first off-signal receiving terminal turn_off_0, used for receiving a first off-signal source; a first off-enable terminal off_0_en, used for receiving a first off-enable signal to control whether the first off-signal source is received, wherein, when the first on-enable signal is valid, the control unit 141 receives the first on-signal source to control the sub-clock signal provided by the clock unit 1221 corresponding to the control unit 141 to be valid.
[0120] Optionally, each control unit 141 also includes: a second on-signal receiving terminal turn_on_1, used to receive a second on-signal source; a second on-en enable terminal on_1_en, used to receive a second on-enable signal to control whether the second on-signal source is received; a second off-signal receiving terminal turn_off_1, used to receive a second off-signal source; a second off-enable terminal off_1_en, used to receive a second off-enable signal to control whether the second off-signal source is received, wherein, when the first on-enable signal and / or the second on-enable signal is valid, the control unit 141 receives the first on-signal source and / or the second on-signal source to control the sub-clock signal provided by the clock unit 1221 corresponding to the control unit 141 to be valid, and when the first off-enable signal and the second off-enable signal are both valid, the control unit 141 stops receiving the first on-signal source and the second on-signal source to control the sub-clock signal provided by the clock unit 1221 corresponding to the control unit 141 to be invalid.
[0121] The circuit elements of each control unit 141 include a first AND gate AND1 , a second AND gate AND2 , a third AND gate AND3 , a fourth AND gate AND4 , a fifth AND gate AND5 , a first OR gate OR1 , and a second OR gate OR2 . Among them, the input end of the first AND gate AND1 is respectively connected to the first conduction signal receiving terminal turn_on_0 and the first conduction enable terminal on_0_en, the input end of the second AND gate AND2 is respectively connected to the second conduction signal receiving terminal turn_on_1 and the second conduction enable terminal on_1_en, the input end of the third AND gate AND3 is respectively connected to the first shut-down signal receiving terminal turn_off_0 and the first shut-down enable terminal off_0_en, the input end of the fourth AND gate AND4 is respectively connected to the second shut-down signal receiving terminal turn_off_1 and the second shut-down enable terminal off_1_en, the input end of the fifth AND gate AND5 is respectively connected to the output end of the third AND gate AND3 and the fourth AND gate AND4, the input end of the first OR gate OR1 is respectively connected to the output end of the first AND gate AND1 and the second AND gate AND2, the input end of the second OR gate OR2 is respectively connected to the output end of the fifth AND gate AND5 and the first OR gate OR1, and the output end of the second OR gate OR2 provides a switching signal.
[0122] The first on-signal source, the second on-signal source, the first off-signal source and the second off-signal source of the control unit 141 all have enable bits, and a suitable signal source can be selected. When one on-signal source is enabled, the switch signal is valid, and the clock unit provides a valid sub-clock signal; when all off-signal sources are enabled, the switch signal is invalid, and the clock unit stops providing the sub-clock signal. Such a setting can ensure that the clock is relatively easy to turn on and relatively difficult to turn off, and prevent the circuit from failing due to the inability to turn on the clock.
[0123] In addition, the present invention also provides a chip (not shown), comprising: Figure 2-4 Optionally, the chip further comprises a plurality of digital circuits connected to the device for generating a clock signal, wherein the device for generating a clock signal generates a plurality of output clock signals respectively, and provides the plurality of output clock signals to the plurality of digital circuits respectively, and the device for generating a clock signal independently controls each output clock signal.
[0124] The embodiment of the present invention subdivides the clock signals of each module / digital circuit according to the function. Even if multiple modules use the same clock, different output clock signals will be used according to the different application times and scenarios.
[0125] In addition, the present invention designs an asynchronous switch circuit (i.e., a control unit) to supply a switch signal to the clock unit, which is used to receive the switch signals sent by all digital circuit modules on a certain clock path, and each switch signal is equipped with an enable bit to ensure that only the desired switch signal source is received. When one of the on-signal sources is enabled, the switch signal is valid, and the clock unit provides a valid sub-clock signal; when all the off-signal sources are enabled, the switch signal is invalid, and the clock unit stops providing the sub-clock signal.
[0126] In the embodiment of the present invention, a control unit is provided for each clock unit to ensure that each clock path can be automatically switched on and off. At the same time, a primary sub-clock signal can be used as a switch signal source for a previous sub-clock signal. When all sub-clock signals of a previous sub-clock signal output "0", the previous sub-clock signal will also be turned off, thereby realizing a clock back pressure mechanism.
[0127] When the microcontroller sends a SLEEP command to enter sleep mode after completing its work, it also serves as a shutdown enable signal source to the control unit to turn off the clock. Other digital circuit modules also send corresponding shutdown enable signal sources to turn off their own clocks after completing their work. When the microcontroller and all other digital circuits do not need the clock, the overall clock will be turned off and wait for the wake-up source.
[0128] The present invention enables each digital circuit module inside the chip to automatically switch the clock on and off according to their own needs, and after the sub-clocks at each level are turned off, they can be reversed to the upper clock level to finally turn off the main clock, and no longer rely on the microcontroller to switch the main clock. The clocks at each level achieve the effect of refined control, and the opening and closing are completely determined by demand, which further saves power consumption.
[0129] The chip and the device for generating a clock signal according to the embodiment of the present invention can be applied to various digital circuit systems, for example, to electronic devices including display screens, capacitive touch screens, etc. For example, the electronic devices in this embodiment include but are not limited to desktop computers, televisions, mobile devices with display screens such as mobile phones, tablet computers, and other common electronic devices.
[0130] Exemplarily, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, an electronic door lock, and a vehicle-mounted terminal.
[0131] The electronic device may also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. For example, some terminals are: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile Internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control (Industrial Control), a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid (Smart Grid), a wireless terminal in transportation safety (Transportation Safety), a wireless terminal in smart city (Smart City), a wireless terminal in smart home (Smart Home), a wireless terminal in Internet of Vehicles, etc. For example, the server may be a local server or a cloud server.
[0132] Figure 5 A flow chart of a method for generating a clock signal according to a first embodiment of the present invention is shown.
[0133] In step S101 , a master clock signal is generated.
[0134] In step S102, a multi-level clock signal is generated according to the main clock signal, and each level of the clock signal includes at least one sub-clock signal divided into at least one group of clock signals. For non-last level clock signals, each sub-clock signal serves as an input signal for generating a next level of clock signal. For the last level clock signal, each sub-clock signal serves as an output clock signal.
[0135] In step S103, when all sub-clock signals of a group of clock signals in a first-level clock signal are invalid, the sub-clock signals corresponding to the previous-level clock signal and the group of clock signals are controlled to be invalid. When all first-level sub-clock signals are invalid, the generation of the main clock signal is stopped.
[0136] Figure 6 A flowchart showing a method for generating a clock signal according to a second embodiment of the present invention is shown.
[0137] In step S201 , a master clock signal is generated.
[0138] In step S202, multiple levels of slave clock modules are used to generate multiple output clock signals according to the master clock signal. Each level of the slave clock module includes at least one sub-module, and each sub-module includes at least one clock unit for providing a sub-clock signal. In non-last-level slave clock modules, the sub-clock signal provided by the clock unit in one level of the slave clock module serves as the input signal of the next level of the slave clock module. In the last-level slave clock module, the sub-clock signal provided by the clock unit serves as the output clock signal.
[0139] In step S203, when the sub-clock signals provided by all the clock units in a sub-module in a first-level slave clock module are invalid, the sub-clock signals provided by the corresponding clock units in the previous-level slave clock module are controlled to be invalid; when the sub-clock signals provided by all the clock units in each sub-module in the first-level slave clock module are invalid, the master clock module is controlled to stop generating the master clock signal.
[0140] Optionally, it also includes: providing a corresponding switching signal to each clock unit in at least one level of the slave clock module to control each sub-clock signal respectively; and controlling whether to generate a master clock signal according to the switching signals corresponding to each clock unit in the first level slave clock module.
[0141] Optionally, providing a corresponding switch signal to at least each clock unit in a first-level slave clock module to respectively control each sub-clock signal includes: using a plurality of control units corresponding to the plurality of clock units one by one to respectively control the plurality of clock units, each control unit is controlled by an enable signal and provides a switch signal, wherein, in each sub-module, one of the plurality of clock units corresponds to a first control unit, a control unit other than the first control unit is also connected to the first control unit, and provides a switch signal to the first control unit to control the first control unit, the first control unit is also connected to a control unit corresponding to a corresponding clock unit in a previous-level slave clock module to provide a switch signal and control a control unit corresponding to a corresponding clock unit in the previous-level slave clock module, when the enable signals received by the plurality of control units connected to the plurality of clock units corresponding to the control unit other than the first control unit all indicate that the sub-clock signal is invalid, the control unit other than the first control unit provides a switch signal to the first control unit, and when the switch signals received by the first control unit are all invalid and the received enable signal indicates that the sub-clock signal is invalid, the first control unit provides a switch signal and controls the control unit corresponding to the corresponding clock unit in the previous-level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous-level slave clock module is invalid.
[0142] Optionally, providing a corresponding switch signal to at least each clock unit in a first-level slave clock module to respectively control each sub-clock signal includes: using multiple control units corresponding to the multiple clock units one by one to respectively control the multiple clock units, each control unit is controlled by an enable signal and provides a switch signal, wherein the control unit corresponding to each clock unit in the sub-module of the first-level slave clock module is also connected to the control unit corresponding to the corresponding clock unit in the previous-level slave clock module to provide a switch signal and control the control unit corresponding to the corresponding clock unit in the previous-level slave clock module, when the enable signals received by the multiple control units connected to all the clock units in a sub-module in the first-level slave clock module indicate that the sub-clock signal is invalid, the multiple control units provide switch signals and control the control units corresponding to the corresponding clock units in the previous-level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous-level slave clock module is invalid.
[0143] Optionally, using multiple control units corresponding to multiple clock units one by one to respectively control the multiple clock units includes: receiving a first on-signal source; receiving a first on-enable signal to control whether the first on-signal source is received; receiving a first off-signal source; receiving a first off-enable signal to control whether the first off-signal source is received, wherein when the first on-enable signal is valid, the control unit receives the first on-signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
[0144] Optionally, using multiple control units corresponding to multiple clock units one by one to control the multiple clock units respectively also includes: receiving a second on-signal source; receiving a second on-enable signal to control whether the second on-signal source is received; receiving a second off-signal source; receiving a second off-enable signal to control whether the second off-signal source is received, wherein when the first on-enable signal and / or the second on-enable signal is valid, the control unit receives the first on-signal source and / or the second on-signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid, and when the first off-enable signal and the second off-enable signal are both valid, the control unit stops receiving the first on-signal source and the second on-signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be invalid.
[0145] Optionally, generating multiple output clock signals based on the main clock signal also includes: performing frequency division processing on the input signal, wherein, in the first-level slave clock module, the main clock signal is divided and sent to each sub-module, and in the non-first-level slave clock module, the sub-clock signal provided by the previous level slave clock module is divided and sent to each sub-module, and when the switch signal is valid, the clock unit converts the input signal after frequency division processing into a sub-clock signal and outputs it.
[0146] The device and method, chip and electronic device for generating clock signals provided by the present invention, when the control unit sends a switch signal representing the turning off of the sub-clock signal, the sub-clock signal is turned off, and when the control units corresponding to all the clock units in the sub-module have sent switch signals representing the turning off of the sub-clock signal, the control unit corresponding to the corresponding previous-stage clock unit sends a switch signal representing the turning off of the sub-clock signal to turn off the corresponding sub-clock signal / main clock; when all slave control modules send switch signals representing the turning off of the sub-clock signal, the main clock signal is turned off. Each digital circuit in the embodiment of the present invention can determine the clock switch of each module by itself, and does not need to be turned off together with the main clock, thereby realizing refined control of the clock signal, so that other modules can turn off the corresponding clock to save power consumption during the operation of the microcontroller.
[0147] Furthermore, the first on-signal source, the second on-signal source, the first off-signal source and the second off-signal source of the control unit all have enable bits, and a suitable signal source can be selected. When one on-signal source is enabled, the switch signal is valid, and the clock unit provides a valid sub-clock signal; when all off-signal sources are enabled, the switch signal is invalid, and the clock unit stops providing the sub-clock signal. Such a setting can ensure that the clock is relatively easy to turn on and relatively difficult to turn off, and prevent the circuit from failing due to the inability to turn on the clock.
[0148] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0149] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A device for generating a clock signal, comprising: A master clock module, used for generating a master clock signal; as well as A multi-stage slave clock module generates a plurality of output clock signals according to the master clock signal, each stage of the slave clock module comprises at least one sub-module, each of the sub-modules comprises at least one clock unit for providing a sub-clock signal, Among them, in the first-level slave clock module, the master clock signal is used as the input signal, in the non-first-level slave clock module, the sub-clock signal provided by the clock unit in the previous-level slave clock module is used as the input signal, and in the last-level slave clock module, the sub-clock signal provided by the clock unit is used as the output clock signal. When the sub-clock signals provided by all the clock units in a slave clock module of a stage are invalid, the input signal of the slave clock module of this stage is controlled to be invalid.
2. The device according to claim 1, wherein: Also includes: A slave control module, providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module, so as to control each of the sub-clock signals respectively; as well as The main control module controls the main clock module according to the switch signal provided by the control unit corresponding to each clock unit in the first-level slave clock module.
3. The device according to claim 2, wherein: The slave control module comprises: A plurality of control units corresponding one to one to the plurality of clock units, each of the control units being controlled by an enable signal and providing the switch signal, Wherein, in each level of the slave clock module, one of the multiple clock units corresponds to the first control unit, and control units other than the first control unit are also connected to the first control unit and provide the switch signal to the first control unit to control the first control unit, and the first control unit is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level, When the enable signals received by multiple control units connected to the multiple clock units corresponding to the control units other than the first control unit all indicate that the sub-clock signal is invalid, the control units other than the first control unit provide the switching signal to the first control unit; when the switching signals received by the first control unit are all invalid and the received enable signals indicate that the sub-clock signal is invalid, the first control unit provides the switching signal and controls the control unit corresponding to the corresponding clock unit in the previous level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous level slave clock module is invalid.
4. The device according to claim 2, wherein: The slave control module comprises: A plurality of control units corresponding one to one to the plurality of clock units, each of the control units being controlled by an enable signal and providing the switch signal, Wherein, the control unit corresponding to each clock unit in the submodule of the slave clock module of the first level is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level, When the enable signals received by the multiple control units connected to all the clock units in the sub-module of the first-level slave clock module all indicate that the sub-clock signal is invalid, the multiple control units provide the switching signal and control the control units corresponding to the corresponding clock units in the previous-level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous-level slave clock module is invalid.
5. The device according to claim 3 or 4, wherein: Each of the control units comprises: A first conduction signal receiving end, used for receiving a first conduction signal source; A first conduction enable terminal, used to receive a first conduction enable signal to control whether the first conduction signal source is received; A first shutdown signal receiving end, used for receiving a first shutdown signal source; A first shutdown enable terminal is used to receive a first shutdown enable signal to control whether the first shutdown signal source is received, When the first conduction enable signal is valid, the control unit receives the first conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
6. The device according to claim 5, wherein: Each of the control units further comprises: A second conduction signal receiving end, used for receiving a second conduction signal source; A second conduction enable terminal, used to receive a second conduction enable signal to control whether the second conduction signal source is received; A second shutdown signal receiving end, used for receiving a second shutdown signal source; A second shutdown enable terminal is used to receive a second shutdown enable signal to control whether the second shutdown signal source is received, When the first conduction enable signal and / or the second conduction enable signal are valid, the control unit receives the first conduction signal source and / or the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid. When both the first shutdown enable signal and the second shutdown enable signal are valid, the control unit stops receiving the first conduction signal source and the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be invalid.
7. The device according to claim 2, wherein: Each level of the slave clock module also includes a frequency division module for performing frequency division processing on the input signal. Among them, in the first-level slave clock module, the frequency division module divides the frequency of the master clock signal and sends it to each of the sub-modules. In the non-first-stage slave clock module, the frequency division module divides the sub-clock signal provided by the previous-stage slave clock module and sends the divided sub-clock signal to each of the sub-modules.
8. The device according to claim 7, wherein: Each of the clock units comprises a clock input terminal, an enable terminal, and an output terminal, wherein the clock input terminal is used to receive the input signal after frequency division processing, the enable terminal is used to receive the switch signal, and the output terminal is used to provide the sub-clock signal. When the switch signal is valid, the clock unit converts the input signal after frequency division into the sub-clock signal and outputs it.
9. A chip, comprising the device for generating a clock signal according to any one of claims 1 to 8.
10. An electronic device comprising the chip according to claim 9.
11. The electronic device according to claim 10, wherein: The electronic device has a display panel, and the electronic device is any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, an electronic door lock, and a vehicle-mounted terminal.
12. A method for generating a clock signal, comprising: Generate a master clock signal; A multi-level clock signal is generated according to the main clock signal, each level of the clock signal includes at least one sub-clock signal divided into at least one group of clock signals, for the first level clock signal, the main clock signal is used as an input signal, for non-first level clock signals, the sub-clock signal in the previous level clock signal is used as an input signal, and for the last level clock signal, the sub-clock signal is used as the output clock signal, When the sub-clock signal in a stage of clock signal is invalid, the input signal controlling the stage of clock signal is invalid.
13. A method for generating a clock signal, comprising: Generate a master clock signal; as well as Using multiple levels of slave clock modules, multiple output clock signals are generated according to the master clock signal, each level of the slave clock module includes at least one sub-module, and each of the sub-modules includes at least one clock unit for providing a sub-clock signal, Among them, in the first-level slave clock module, the master clock signal is used as the input signal, in the non-first-level slave clock module, the sub-clock signal provided by the clock unit in the previous-level slave clock module is used as the input signal, and in the last-level slave clock module, the sub-clock signal provided by the clock unit is used as the output clock signal. When the sub-clock signals provided by all the clock units in a slave clock module of a stage are invalid, the input signal of the slave clock module of this stage is controlled to be invalid.
14. The method according to claim 13, wherein: Also includes: Providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module to control each of the sub-clock signals respectively; as well as Whether to generate the master clock signal is controlled according to the switch signals corresponding to the clock units in the first-level slave clock module.
15. The method according to claim 14, wherein: Providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module to control each of the sub-clock signals respectively includes: The plurality of clock units are controlled respectively by a plurality of control units corresponding to the plurality of clock units, each of the control units is controlled by an enable signal and provides the switch signal, Wherein, in each level of the slave clock module, one of the multiple clock units corresponds to the first control unit, and control units other than the first control unit are also connected to the first control unit and provide the switch signal to the first control unit to control the first control unit, and the first control unit is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level, When the enable signals received by multiple control units connected to the multiple clock units corresponding to the control units other than the first control unit all indicate that the sub-clock signal is invalid, the control units other than the first control unit provide the switching signal to the first control unit; when the switching signals received by the first control unit are all invalid and the received enable signals indicate that the sub-clock signal is invalid, the first control unit provides the switching signal and controls the control unit corresponding to the corresponding clock unit in the previous level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous level slave clock module is invalid.
16. The method according to claim 14, wherein: Providing a corresponding switch signal to each of the clock units in at least one level of the slave clock module to control each of the sub-clock signals respectively includes: The plurality of clock units are controlled respectively by a plurality of control units corresponding to the plurality of clock units, each of the control units is controlled by an enable signal and provides the switch signal, Wherein, the control unit corresponding to each clock unit in the submodule of the slave clock module of the first level is also connected to the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level to provide the switch signal and control the control unit corresponding to the corresponding clock unit in the slave clock module of the previous level, When the enable signals received by the multiple control units connected to all the clock units in the sub-module of the first-level slave clock module all indicate that the sub-clock signal is invalid, the multiple control units provide the switching signal and control the control units corresponding to the corresponding clock units in the previous-level slave clock module, so that the sub-clock signal provided by the corresponding clock unit in the previous-level slave clock module is invalid.
17. The method according to claim 15 or 16, wherein: Using a plurality of control units corresponding one-to-one to the plurality of clock units to control the plurality of clock units respectively comprises: receiving a first conduction signal source; receiving a first conduction enable signal to control whether the first conduction signal source is received; receiving a first shutdown signal source; receiving a first shutdown enable signal to control whether the first shutdown signal source is received, When the first conduction enable signal is valid, the control unit receives the first conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid.
18. The method according to claim 15 or 16, wherein: Using a plurality of control units corresponding one-to-one to the plurality of clock units to control the plurality of clock units respectively also includes: receiving a second conduction signal source; receiving a second conduction enable signal to control whether the second conduction signal source is received; receiving a second shutdown signal source; receiving a second shutdown enable signal to control whether the second shutdown signal source is received, When the first conduction enable signal and / or the second conduction enable signal are valid, the control unit receives the first conduction signal source and / or the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be valid. When both the first shutdown enable signal and the second shutdown enable signal are valid, the control unit stops receiving the first conduction signal source and the second conduction signal source to control the sub-clock signal provided by the clock unit corresponding to the control unit to be invalid.
19. The method according to claim 14, wherein: Generating a plurality of output clock signals according to the master clock signal further comprises: performing frequency division processing on the input signal, Wherein, in the first-level slave clock module, the master clock signal is divided and then sent to each of the sub-modules. In the non-first-stage slave clock module, the sub-clock signal provided by the previous-stage slave clock module is divided and sent to each of the sub-modules. When the switch signal is valid, the clock unit converts the input signal after frequency division into the sub-clock signal and outputs it.