Clock tree synthesis method and related device

Abstract

The application discloses a clock tree synthesis method and related equipment, including: dividing a plurality of timing units needing to receive a clock signal from a clock source into clustering clusters of different levels, wherein the load capacitances of each clustering cluster of the same level are balanced; according to the level order of the clustering cluster starting from the clock source, taking each clustering cluster as a node of a clock tree, recursively constructing the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; analyzing the delay and offset of the constructed clock tree to obtain an analysis result; if the analysis result indicates that the delay and offset of the clock tree do not satisfy a preset constraint condition, adjusting the clock tree until the delay and offset of the adjusted clock tree satisfy the preset constraint condition. The technical scheme of the embodiment of the application can effectively reduce power consumption and offset, improve computing efficiency and design reliability, and is suitable for high-performance chip design under advanced process.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and more specifically, to a clock tree synthesis method and related equipment. Background Art

[0002] With the development of FinFET technology and the introduction of technologies such as multiple masks and FinTrack, traditional clock tree construction methods have exposed multiple shortcomings under the new process: on the one hand, the need to balance multi-dimensional parameters such as delay, offset, and power consumption has increased exponentially in solution complexity, resulting in low computational efficiency; on the other hand, the clock tree logical topology is disconnected from the physical layout of the buffer, and the calculation of the convergence point coordinates cannot be optimized in conjunction with the tree structure, which often leads to layout violations or a surge in secondary adjustment costs.

[0003] Therefore, how to implement clock tree synthesis under FinFET process has become an urgent problem to be solved. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In a first aspect, the present application proposes a clock tree synthesis method, comprising:

[0006] Divide multiple sequential units that need to receive clock signals from a clock source into clusters at different levels, where the load capacitance of each cluster at the same level is balanced;

[0007] According to the hierarchical order of the clusters starting from the clock source, each cluster is regarded as a node of the clock tree, the clock tree is recursively constructed, and a target buffer is inserted at the position of each node for driving the corresponding node;

[0008] Analyze the delay and offset of the constructed clock tree to obtain analysis results;

[0009] If the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint conditions, the clock tree is adjusted until the delay and offset of the adjusted clock tree meet the preset constraint conditions.

[0010] In a feasible implementation, multiple timing units that need to receive clock signals from a clock source are divided into clusters of different levels, including: determining the number of division levels and the number of clusters corresponding to each level based on the input branching factor vector; and dividing the multiple timing units into clusters of different levels layer by layer based on the number of division levels and the number of clusters corresponding to each level.

[0011] In a feasible embodiment, the method also includes: in the process of hierarchical division, if the number of timing units in each clustering cluster corresponding to the current level is greater than a preset threshold, then the global clustering method is used to determine the timing unit clustering scheme in each clustering cluster corresponding to the current level; if the number of timing units in each clustering cluster corresponding to the current level is less than or equal to the preset threshold, then the local clustering method is used to determine the timing unit clustering scheme in each clustering cluster corresponding to the current level.

[0012] In a feasible embodiment, the method further includes: using the global clustering method to determine the sequential unit clustering scheme within each cluster corresponding to the current level to satisfy the minimum first objective function and to satisfy the load capacitance constraint of each cluster within an allowable range, wherein the first objective function is:

[0013]

[0014] in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster Each time series unit in the cluster The maximum distance from the center position, is the weighting coefficient.

[0015] In a feasible embodiment, the method further includes: using the local clustering method to determine the sequential unit clustering scheme within each cluster corresponding to the current level to satisfy the minimum second objective function and to satisfy the total load capacitance constraint of each cluster within an allowable range, wherein the second objective function is:

[0016]

[0017] in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster The semi-perimeter of the bounding box of is the weighting coefficient.

[0018] In a feasible implementation, inserting a target buffer at the position of each node includes: determining the coordinate position of each node based on the weighted center of the cluster corresponding to each node; if there is no obstacle at the coordinate position, inserting the target buffer at the coordinate position; if there is an obstacle at the coordinate position, inserting the target buffer on at least one side of the left, right, bottom, or top of the obstacle.

[0019] In a feasible implementation, the coordinate position of each node is determined according to the weighted center of the cluster corresponding to each node, including: establishing a linear programming model according to the weighted center of the cluster corresponding to each node, solving the linear programming model to obtain the coordinate position of each node; wherein the linear programming model takes minimizing the maximum distance between the node and the weighted center as the objective function, takes the distance between adjacent nodes as a fixed value as the first constraint condition, and takes the preset distance relationship between the node and the weighted center as the second constraint condition.

[0020] In a feasible embodiment, the method further includes: performing preliminary screening in a preset buffer list based on the metal wire length and load capacitance corresponding to each node to obtain multiple candidate buffers; based on the power consumption values ​​corresponding to the multiple candidate buffers, again screening out the buffer with the smallest power consumption value from the multiple candidate buffers, and using the buffer screened out again as the target buffer.

[0021] In a feasible embodiment, the preset buffer list is established in the following manner: based on the target process library, circuit simulation is performed on different types of buffers connected to metal wires of different lengths, and the electrical characteristic parameters corresponding to the different types of buffers are recorded; a buffer list is established with metal wire length and buffer type as indexes, and the electrical characteristic parameters under each combination are stored.

[0022] In a second aspect, the present application proposes a clock tree synthesis device, comprising:

[0023] a dividing unit configured to divide a plurality of sequential units that need to receive clock signals from a clock source into clusters at different levels, wherein the load capacitance of each cluster at the same level is balanced;

[0024] a construction unit configured to recursively construct the clock tree according to the hierarchical order of the clusters starting from the clock source, taking each cluster as a node of the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node;

[0025] an analyzing unit, configured to analyze the delay and offset of the clock tree to obtain an analysis result;

[0026] The adjustment unit is configured to adjust the multi-layer clock tree until the delay and offset of the adjusted multi-layer clock tree meet the preset constraint conditions if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint conditions.

[0027] In a third aspect, the present application proposes a clock tree synthesis system, comprising:

[0028] a solution vector construction module configured to use the clock tree to be constructed as a solution of the clock tree, wherein the solution of the clock tree is represented as a parameter vector including a buffer type, an insertion coordinate, a line length allocation, and a drive capability;

[0029] a space establishment module configured to establish a multi-dimensional index space with clock tree depth, convergence area, number of convergence point areas, maximum clock delay, minimum clock delay, and input capacitance as dimensions;

[0030] The storage and retrieval module is configured to store the parameter vector in the multidimensional index space to form a parameterized result set for retrieving a solution of the clock tree that meets preset constraints.

[0031] In a fourth aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the clock tree synthesis method of any one of the first aspects described above when executing the computer program stored in the memory.

[0032] In a fifth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the clock tree synthesis method of any one of the first aspects is implemented.

[0033] In summary, the technical solution proposed in this application divides the timing units into clusters of the same level with balanced load capacitance, recursively constructs the clock tree hierarchically and inserts the adapted target buffer, while iteratively optimizing based on the delay and offset analysis results. Through hierarchical load-balanced clustering, the multi-dimensional parameter optimization problem is transformed into a layer-by-layer iterative solution, reducing the complexity from exponential to polynomial level, improving computational efficiency, and accurately matching the buffer driving capability with the node requirements, realizing the coordinated optimization of the logic topology and buffer layout, and significantly reducing the secondary adjustment cost. The overall solution can effectively reduce power consumption and offset, and is suitable for high-performance, high-integration chip design. In particular, it can effectively cope with complex layout constraints at advanced process nodes, improving the overall chip performance and design reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present description. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0035] Figure 1 A flowchart of a clock tree synthesis method provided in an embodiment of the present application.

[0036] Figure 2 A flowchart of a clock tree synthesis method provided in an embodiment of the present application.

[0037] Figure 3 A flowchart of a clock tree synthesis method provided in an embodiment of the present application.

[0038] Figure 4 A flowchart of a clock tree synthesis method provided in an embodiment of the present application.

[0039] Figure 5 A flowchart of a clock tree synthesis method provided in an embodiment of the present application.

[0040] Figure 6 A schematic diagram of the structure of a clock tree synthesis device provided in an embodiment of the present application.

[0041] Figure 7 A schematic diagram of the structure of a clock tree integrated electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments.

[0043] First, some nouns or terms that appear in the process of describing the embodiments of the present application are subject to the following explanations.

[0044] FinFET process: FinFET is an advanced semiconductor manufacturing process. FinFET (Fin Field-Effect Transistor) refers to fin-shaped field-effect transistors. In this process, a raised fin-shaped structure is created on the substrate to serve as the transistor's channel, with the gate surrounding three sides of the fin. This unique three-dimensional structure more effectively controls the current in the channel, reduces leakage, and significantly improves device performance and integration. It is widely used in advanced manufacturing processes and is one of the key process technologies for achieving smaller size, higher performance, and lower power consumption in modern integrated circuit manufacturing.

[0045] Clock tree: A clock tree is a circuit structure that distributes clock signals from one or more clock sources to multiple timing units efficiently and evenly.

[0046] Clock Tree Synthesis (CTS): It is a key step in the physical design of digital integrated circuits. It is mainly used to build and optimize the chip's clock distribution network to ensure that the clock signal can reach all timing units (such as flip-flops, registers, etc.) synchronously with minimal skew and latency.

[0047] Skew: refers to the time difference between the arrival of the same clock signal at different nodes. Ideally, all sequential units should receive the clock signal at the same time.

[0048] Latency: refers to the time it takes for a clock signal to travel from the clock source through the clock tree to each sequential unit.

[0049] Buffers are key elements in clock tree synthesis, used to drive clock signals. They compensate for signal attenuation and optimize timing metrics such as delay and skew. Buffer types are selected based on drive capability and are subject to layout constraints such as spacing and density.

[0050] See also Figure 1 , is a flow chart of a clock tree synthesis method provided in an embodiment of the present application, the method comprising steps S110 to S140:

[0051] Step S110: Divide the plurality of sequential units that need to receive clock signals from a clock source into clusters at different levels, wherein the load capacitance of each cluster at the same level is balanced;

[0052] Step S120: recursively construct the clock tree according to the hierarchical order of the clusters starting from the clock source, taking each cluster as a node of the clock tree, and inserting a target buffer at the position of each node to drive the corresponding node;

[0053] Step S130: Analyze the delay and offset of the constructed clock tree to obtain analysis results;

[0054] Step S140: If the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint conditions, the clock tree is adjusted until the delay and offset of the adjusted clock tree meet the preset constraint conditions.

[0055] These steps are described in detail below.

[0056] In step S110 , a plurality of sequential units that need to receive clock signals from a clock source are divided into clusters at different levels, wherein the load capacitance of each cluster at the same level is balanced.

[0057] During clock tree synthesis, multiple sequential cells that need to receive clock signals from a clock source can first be divided into clusters at different levels, with the load capacitance of each cluster at the same level balanced. This step provides a structured and balanced foundation for subsequent clock tree construction, ensuring that clock signals can be transmitted to each sequential cell with minimal delay and skew.

[0058] Sequential cells are essential components in integrated circuits that rely on clock signals for synchronous operation, primarily including flip-flops and latches. These components store, transmit, or process data under the control of clock signals, ensuring that the entire circuit system operates in accordance with predetermined timing logic. The clock source, typically a high-precision oscillator or phase-locked loop (PLL), is the starting point of the entire clock network. It generates a stable clock signal and distributes it to each sequential cell through the clock tree. Sequential cells are organized into hierarchical clusters, grouping them according to their location and function in the clock tree. Each cluster corresponds to a specific level in the clock tree, starting from the clock source and extending downward. For example, the top cluster might be located near the clock source, receiving the initial clock signal and then distributing it to the next lower cluster. The bottom cluster connects directly to each sequential cell. This hierarchical structure helps optimize clock signal transmission paths, reducing latency and power consumption.

[0059] The size of the load capacitance directly affects the transmission delay of the clock signal; larger capacitance increases the delay. Load capacitance balancing aims to keep the load capacitance of clusters at the same level as close as possible. This ensures consistent transmission delay of the clock signal across branches, reducing clock skew and improving circuit timing stability. If the load capacitance of clusters at the same level varies significantly, the clock signal will propagate at different speeds in different branches, resulting in inconsistent arrival times at each timing unit, impacting circuit operation.

[0060] In step S120 , the clock tree is recursively constructed according to the hierarchical order of the clusters starting from the clock source, with each cluster as a node of the clock tree, and a target buffer is inserted at the position of each node to drive the corresponding node.

[0061] After the hierarchical division is performed, the clock tree can be recursively constructed based on the hierarchical order of the clusters.

[0062] Specifically, each cluster is treated as a node in the clock tree, following a hierarchical order starting from the clock source. That is, starting from the top level (the level closest to the clock source) and expanding downwards. For example, the top-level cluster becomes a direct child of the root node, the middle-level cluster becomes a child of the top-level node, and so on, until all sequential units at the bottom level are connected. This hierarchical order ensures that the clock signal is transmitted in an orderly manner from the source through each node to the final destination.

[0063] During the construction process, the physical location of each cluster (typically its geometric center) is treated as a node in the clock tree. Recursive construction means that for each node, the algorithm repeatedly performs the following operations: determining the node's child nodes (i.e., the clusters at the next level) and establishing connections. This process is repeated until all clusters are integrated into the clock tree. For example, a top-level cluster may be divided into multiple subclusters, each of which becomes a child of the node, forming a branch of the tree structure.

[0064] The target buffer is inserted at each node to ensure that the clock signal can effectively drive all timing units in the corresponding cluster. It amplifies signal strength to compensate for attenuation during transmission, preventing insufficient signal energy due to excessive load capacitance. It adjusts its own delay characteristics to match global timing requirements and reduce clock skew between different branches. At the same time, it supports the expansion of lower-level nodes with its specific fan-out capabilities, ensuring reliable signal transmission to all child nodes, thereby achieving low-latency and low-skew operation for the entire clock network.

[0065] In step S130 , the delay and offset of the constructed clock tree are analyzed to obtain an analysis result.

[0066] The key step in evaluating the timing performance of a constructed clock tree focuses on analyzing the clock signal's delay and skew. Latency refers to the total transmission time it takes for a clock signal to travel from the clock source, through various buffers and interconnects, to the timing unit. This metric directly affects the chip's operating frequency. If the delay is too long, data may not be transmitted within the specified clock cycle, thereby limiting chip performance. Skew refers to the difference in delay between different clock paths, or the inconsistency in the time at which each timing unit receives the clock signal. Even if the delay of each path is within an acceptable range, excessive skew can still lead to poor synchronization between timing units, potentially causing data sampling errors or logical function anomalies.

[0067] During the analysis process, it's necessary to comprehensively consider the impact of multiple factors on delay and skew. For delay, it's important to consider not only the delay characteristics of the buffer itself (such as differences in drive capability between buffers of different sizes) but also the parasitic effects of interconnects (such as signal attenuation and delay caused by resistance and capacitance). For skew, it's necessary to compare the delays of all clock paths, especially those that traverse different layers or regions, as these paths are more susceptible to layout and process variations. By accurately calculating the delay and overall skew of each path, a comprehensive assessment of the clock tree's timing performance can be achieved.

[0068] In practice, static timing analysis (STA) tools are often used to calculate delay and skew. Based on the physical parameters of the circuit and timing constraints, these tools use algorithms to simulate the propagation of clock signals throughout the network, resulting in accurate delay and skew values. Simplified methods such as linear delay models can also be used for preliminary estimates, quickly identifying potentially problematic path areas and conducting targeted, detailed analysis. This approach allows for efficient identification of timing bottlenecks, providing a basis for subsequent optimization.

[0069] In step S140 , if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint conditions, the clock tree is adjusted until the delay and offset of the adjusted clock tree meet the preset constraint conditions.

[0070] When analysis finds that the delay or offset of the clock tree exceeds the preset constraints, such as the maximum delay threshold or the maximum offset threshold, it means that the current clock tree structure cannot guarantee stable operation of the chip and must be adjusted to optimize timing performance.

[0071] The adjustment process can start with buffer configuration and tree structure optimization. Regarding buffer configuration, this may involve replacing a buffer type with one with stronger drive capability or lower latency, adjusting buffer size to match load requirements, or reallocating buffer insertion positions to shorten the signal transmission path. For example, if a path has excessive latency, a buffer with stronger drive capability can be replaced to accelerate signal transmission. If the skew between different paths is too large, the buffer positions can be fine-tuned to keep the latency of each path as close as possible.

[0072] In terms of tree structure optimization, the branching factor or topology of the clock tree can be adjusted. By enumerating different branching factors and re-dividing the clusters, the clock tree hierarchy and number of branches are changed to achieve more even signal distribution and reduce latency differences caused by load imbalance. Furthermore, the load capacitance of each node is checked for balance. If a cluster is overloaded, the timing unit ownership may be reallocated and the cluster division may be adjusted to optimize the overall load distribution.

[0073] The technical solution of the embodiment of the present application divides the timing units into the same-level clusters with balanced load capacitance, recursively constructs the clock tree hierarchically and inserts the adapted target buffer, and iteratively optimizes based on the delay and offset analysis results. It can be well adapted to the FinFET process characteristics, effectively reduce power consumption and offset, improve timing convergence efficiency, and significantly improve the comprehensive performance and design automation level of the clock tree.

[0074] In some embodiments, clock tree synthesis can be understood as solving a multidimensional solution space within a multidimensional solution space. In clock tree synthesis design, multiple spatial parameters are defined to construct a multidimensional space to accurately describe and store design solutions. These parameters include clock tree depth (D), which determines the level of clock signal transmission from source to destination; the area of ​​the sink region (width w, height h) and the number of sink regions (n), which reflect the distribution and density of timing cells on the chip; the maximum and minimum clock delays (Lmax / Lmin), which measure the time constraints for clock signal transmission; and input capacitance (C), a key factor influencing buffer drive capability selection. Each clock tree design solution, or "solution," includes information such as buffer type, insertion coordinates, wire length allocation, and drive capability. These solutions are indexed by these parameters and stored in a result set (R). Think of the result set (R) as a massive database, where each record corresponds to a clock tree design solution and can be quickly located and retrieved using these spatial parameters.

[0075] The space formed by the result set (R) is a multi-dimensional solution space. This means that the input is multi-dimensional parameters (such as clock tree depth and area), and the output is also multi-dimensional design solutions (buffer type, insertion location, etc.). In this complex space, achieving the ideal clock synthesis solution requires finding the optimal balance between power consumption, skew, and delay.

[0076] In other embodiments, in addition to the above parameters, additional parameters may be added from multiple dimensions to optimize the design. For example, parameters related to physical layout constraints (such as wiring resource density) and process characteristics (such as buffer threshold voltage) may also be included.

[0077] In this embodiment, by defining spatial parameters such as clock tree depth and convergence area, each clock tree design solution, or "solution," including information such as buffer type and insertion coordinates, is indexed and stored in a result set using these parameters. This acts like a massive database, enabling rapid location and retrieval of design solutions based on parameters. This transforms the complex combinatorial optimization problem into an efficient parameter matching process, significantly improving solution efficiency and significantly reducing clock tree synthesis time for million-gate chips.

[0078] The multidimensional solution space, formed by the result set, maps multidimensional parameters into a multidimensional design solution. Finding the optimal balance between power consumption, offset, and latency in this space changes the traditional trial-and-error design approach. For example, when specific process requirements or performance indicators are met, matching solutions can be directly retrieved based on the parameters, making multi-objective optimization more precise and avoiding the losses associated with multiple iterations.

[0079] In one embodiment of the present application, Figure 2 As shown, step S110 may specifically include steps S210 to S220, which are described in detail as follows:

[0080] Step S210: Determine the number of division levels and the number of clusters corresponding to each level according to the input branching factor vector.

[0081] The branching factor vector is a key parameter guiding clock tree structure design. It is an ordered sequence, with each element corresponding to a different level of the clock tree. For example, the branching factor vector [2, 3, 2] indicates that the first level of the clock tree (near the clock source) is divided into two branches, the second level into three branches, and the third level into two branches. This vector essentially defines the expansion rules for each level of the clock tree and directly determines the tree's topology and complexity.

[0082] The number of levels is automatically determined based on the length of the branching factor vector. Since each element in the vector corresponds to the number of branches in a level, the length of the vector is equal to the number of levels in the clock tree. For example, a branching factor vector of [2,3,2] contains three elements, meaning the clock tree will be divided into three levels. This step specifies how many "stages" a signal must pass through from the clock source to reach the final sequential unit.

[0083] The number of clusters at each level is determined by the values ​​of the branching factor vector. The number of clusters at each level is equal to the branching factor value for that level. For example, in the branching factor vector [2, 3, 2], there are two clusters at the first level, three clusters at the second level, and two clusters at the third level. These clusters serve as the basis for constructing clock tree nodes in subsequent steps. Each cluster contains a set of sequential cells, with buffers inserted in their place to drive the signals.

[0084] Step S220 : Divide the multiple time series units into clusters of different levels according to the number of division levels and the number of clusters corresponding to each level.

[0085] After the number of division levels and the number of clusters corresponding to each level are determined, the multiple time series units can be divided into clusters of different levels layer by layer according to the number of division levels and the number of clusters corresponding to each level.

[0086] For example, if step S210 determines that the clock tree has three levels based on the branching factor vector, and there are two clusters in the first level, three clusters in the second level, and two clusters in the third level, then the sequential units can be allocated layer by layer starting from the top level. This hierarchical order ensures that the clock signal can be transmitted from the clock source to each sequential unit along the preset path.

[0087] In one embodiment of the present application, Figure 3 As shown, the clock tree synthesis method may further include steps S310 to S320, which are described in detail as follows:

[0088] Step S310 : During the level-by-level division process, if the number of sequential units in each cluster corresponding to the current level is greater than a preset threshold, a global clustering method is used to determine a clustering scheme for the sequential units in each cluster corresponding to the current level.

[0089] In the process of dividing the time series units into clusters hierarchically, if the number of time series units in each cluster corresponding to the current level is greater than a preset threshold, a global clustering method can be used to determine the clustering scheme of the time series units in each cluster corresponding to the current level.

[0090] The preset threshold is a pre-set quantity threshold. Global clustering refers to an algorithm that groups cells based on overall layout information. This can be implemented using integer linear programming (ILP), K-means clustering, or support vector machines (SVM). It is suitable for global optimization of large-scale cell collections.

[0091] In some embodiments, the sequential unit clustering scheme within each cluster corresponding to the current level determined by the global clustering method satisfies the minimum first objective function and satisfies the load capacitance constraint of each cluster within an allowable range. The first objective function is:

[0092]

[0093] in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster Each time series unit in the cluster The maximum distance from the center position, is the weighting coefficient.

[0094] In this embodiment, the timing unit clustering scheme within each cluster corresponding to the current level determined by the global clustering method must meet two conditions. The first condition is that the first objective function must be minimized, and the second condition is that the load capacitance constraint of each cluster must be within the allowable range. In addition, each timing unit must belong to only one cluster.

[0095] Specifically, during the global clustering process, the initial cluster centers are calculated based on the coordinate distribution of the sequential cells. Then, the cluster assignments are adjusted through an iterative optimization algorithm to gradually reduce the first objective function, F1. In each iteration, the weights of the total distance and the maximum distance are dynamically balanced by adjusting the α value. At the same time, the load capacitance of each cluster is checked to ensure it is within the allowable range. If the load capacitance exceeds the allowable range, some cells are reallocated to adjacent clusters to balance the capacitance distribution.

[0096] In the formula for the first objective function, ∑Disti represents the sum of the distances from all sequential cells within each cluster to the cluster center. It reflects the compactness of the cell distribution within the cluster. A smaller value indicates more concentrated cells and shorter interconnect lengths. Distmax focuses on the sequential cells farthest from the cluster center to avoid the problem of a sequential cell being "too far from the cluster" and causing excessively long wiring. The weighting coefficient α acts as a "lever." By adjusting the value of α, the importance of the sum of distances and the maximum distance can be flexibly balanced. A larger α prioritizes reducing the distance to the farthest cell, preventing extreme situations.

[0097] The load capacitance of each cluster here is primarily the sum of the input capacitances of all sequential units (such as registers and flip-flops) within the cluster. The sequential unit clustering scheme within each cluster at the current level, determined using the global clustering method, must not only minimize the first objective function but also ensure that the load capacitance of each cluster is within an allowable range. This allowable range defines the upper and lower limits of the load capacitance, and the load capacitance of each cluster must be within these limits, meaning it cannot exceed the upper limit or fall below the lower limit.

[0098] Step S320 : If the number of sequential units in each cluster corresponding to the current level is less than or equal to a preset threshold, a local clustering method is used to determine a clustering scheme for the sequential units in each cluster corresponding to the current level.

[0099] On the contrary, if the number of sequential units in each cluster corresponding to the current level is less than or equal to the preset threshold, a local clustering method may be used to determine a clustering scheme for the sequential units in each cluster corresponding to the current level.

[0100] In some embodiments, the sequential unit clustering scheme within each cluster corresponding to the current level determined by the local clustering method satisfies the minimum second objective function and satisfies the total load capacitance constraint of each cluster within an allowable range. The second objective function is:

[0101]

[0102] in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster The semi-perimeter of the bounding box of is the weighting coefficient.

[0103] The core of the local clustering method is to determine the optimal clustering solution by minimizing the second objective function F2 while satisfying the total load capacitance constraint. F2 is composed of two key indicators:

[0104] ∑Disti (distance sum): Similar to the global clustering method, it measures the compactness of the timing units within the cluster to the cluster center. The smaller the distance sum, the shorter the interconnection line and the lower the signal delay.

[0105] HPWL (Bounding Box Half Perimeter): This value determines the minimum bounding rectangle of all sequential cells within a cluster based on their coordinates. The half perimeter reflects the physical coverage of the cluster. A smaller HPWL value indicates a more concentrated distribution of cells, which facilitates efficient buffer placement and short routing distances, reducing the risk of signal interference.

[0106] The weighting coefficient β is used to balance the priority between sum of distances and region compactness. For example, when β is large, the algorithm prioritizes compressing the bounding box size of clusters to avoid overly dispersed groups; when β is small, it prioritizes compact arrangement of units within clusters.

[0107] Thanks to HPWL calculations, smaller buffers can be accurately calculated, allowing for precise allocation of their placement coordinates within the cluster's semi-perimeter. The clustering solution with the lowest HPWL value identifies areas with compact node distribution, short connections, and relatively concentrated loads, which is highly compatible with small buffer applications. Therefore, based on the selected clustering solution with the lowest HPWL value, it is possible to precisely locate areas suitable for small buffers. Placing small buffers in these locations allows them to operate efficiently despite limited drive capacity, ensuring stable and timely signal transmission while leveraging the low power consumption and small footprint of small buffers to reduce overall chip power consumption and area, improving chip performance and competitiveness.

[0108] In this embodiment, the bounding box of a cluster can be determined based on the coordinates of the sequential cells within the cluster. Specifically, in some embodiments, determining the bounding box based on the coordinates can involve traversing the coordinates of all sequential cells within the cluster. In a two-dimensional plane (chip layout is typically based on an XY coordinate system), each sequential cell has a corresponding horizontal coordinate (X value) and vertical coordinate (Y value). During the traversal process, the minimum horizontal coordinate Xmin, maximum horizontal coordinate Xmax, minimum vertical coordinate Ymin, and maximum vertical coordinate Ymax of all cell coordinates are recorded.

[0109] After obtaining these four extreme values, the rectangle defined by (Xmin, Ymin) is used as the lower-left corner, and (Xmax, Ymax) as the upper-right corner is used as the bounding box for the cluster. The horizontal length of this rectangle is Xmax - Xmin, and the vertical length is Ymax - Ymin. This bounding box ensures complete coverage of all sequential cells within the cluster while minimizing size. This can be used to calculate the HPWL (half perimeter of the bounding box) and guide buffer placement and interconnect planning.

[0110] In terms of load capacitance constraints, the total load capacitance of each cluster consists of two parts: one is the sum of the input capacitance of the sequential units, that is, the sum of the input capacitance of all sequential units such as registers and triggers in the cluster; the other is the line capacitance, which is calculated as line capacitance Number of timing units ,in, is a constant. By controlling the total load capacitance within the allowable range, we ensure load balancing across clusters, guaranteeing stable clock signal transmission and laying a solid foundation for subsequent clock tree construction. This allowable range defines the upper and lower limits of the total load capacitance, and the load capacitance of each cluster must fall within these limits, meaning it cannot exceed the upper limit or fall below the lower limit.

[0111] In one embodiment of the present application, Figure 4 As shown, inserting the target buffer at the position of each node may specifically include steps S410 to S430, which are detailed as follows:

[0112] Step S410: Determine the coordinate position of each node according to the weighted center of the cluster corresponding to each node.

[0113] In this embodiment, the weighted center of the cluster corresponding to each node can be averaged according to the position of the time series unit, and the horizontal coordinate x of the weighted center is k w and the vertical coordinate y k w The average value of xi and yi of all sequential units is directly obtained, that is, x k w =mean(xi),y k w =mean(yi), for example, if a cluster contains three units with coordinates (1,2), (3,4), and (5,6), then its weighted center is (3,4).

[0114] The weighted center determined by this mean calculation method can intuitively reflect the distribution center of the timing units within the cluster. Placing the clock tree node here helps shorten the average connection length from the node to each unit, reducing the total parasitic capacitance and resistance of the interconnect, thereby reducing signal transmission delay.

[0115] In some embodiments, after determining the weighted center of the cluster corresponding to each node, determining the coordinate position of each node according to the weighted center of the cluster corresponding to each node may specifically include:

[0116] According to the weighted center of the cluster corresponding to each node, a linear programming model is established and solved to obtain the coordinate position of each node;

[0117] Among them, the linear programming model takes minimizing the maximum distance between the node and the weighted center as the objective function, the distance between adjacent nodes as a fixed value as the first constraint condition, and the preset distance relationship between the node and the weighted center as the second constraint condition.

[0118] Specifically, the coordinate position (x k b ,y k b ), so that the node and the corresponding cluster weighted center (x k w ,y k w ) is minimized. The “maximum distance” here is usually measured by Manhattan distance, that is, the objective function is: The goal is to place the nodes as close to the weighted center as possible, thereby shortening the average connection length to each timing unit in the cluster and reducing the time difference (offset) between the clock signal reaching different units.

[0119] To ensure the regularity of the clock tree topology (such as a symmetrical tree structure), the linear programming model introduces the first constraint of a fixed distance between adjacent nodes: .in, is the adjacent node, Dist b It is a preset fixed value.

[0120] In addition to the first constraint, the linear programming model also introduces a second constraint on the distance between the node and the weighted center through a slack variable: ; .

[0121] Among them, x k Δ and y k Δare the slack variables in the horizontal and vertical directions, representing the maximum allowable deviation between the node and the weighted center in the corresponding direction. By minimizing the Distmax in the objective function Δ (i.e., the maximum value of the slack variables in each direction), the model forces the nodes to move closer to the weighted center while allowing moderate deviation under the fixed spacing constraint.

[0122] By solving this linear programming model, the closest compliant coordinates to the weighted center can be found under the constraint of a fixed spacing between adjacent nodes. For example, if the weighted center coordinates are (100, 100) and the spacing between adjacent nodes is required to be 80μm, the model will select the point that minimizes the deviation between the node and the weighted center among all possible positions where the sum of the absolute values ​​of the horizontal and vertical coordinate deviations is equal to 80μm. This method transforms the node positioning problem into a mathematical optimization problem and automatically solves it with the help of an algorithm. This ensures that the clock tree topology conforms to physical design rules, optimizes timing performance by aligning closely with the load center of gravity, and improves the automation and accuracy of clock tree design. It is suitable for complex chip design scenarios with high clock synchronization requirements.

[0123] Step S420: If there is no obstacle at the coordinate position, insert a target buffer at the coordinate position.

[0124] Obstacle checking is a prerequisite for buffer insertion. In chip physical design, obstacles may include already laid out standard cells, macroblocks, power networks, or other fixed circuit components. These areas prohibit the insertion of new buffers. Therefore, a geometric check is performed against the layout database (e.g., LEF / DEF files) to determine whether an obstacle exists at the target coordinates. If so, the subsequent buffer position adjustment mechanism (e.g., step S430) is triggered. If not, the insertion proceeds directly.

[0125] The target buffer is selected and inserted based on the clustering scheme determined in steps S310 / S320. The load capacitance of each node's cluster has been optimized using global or local clustering methods. A buffer type with matching drive capability (e.g., buffers with different drive strengths, such as BUF_X1 and BUF_X2 in the standard cell library) is selected based on this load capacitance. During insertion, the buffer's center position is precisely aligned with the coordinates calculated in step S410 to ensure optimal connection lengths from its output to each sequential cell within the cluster.

[0126] The physical purpose of buffer insertion is to establish a relay point for the clock signal. Buffers not only amplify signal strength to drive subsequent loads, but also, through appropriate selection of type and location, compensate for latency differences along different paths in the clock tree. For example, inserting high-drive buffers in heavily loaded clusters can reduce signal attenuation. For branches with long paths, inserting multiple buffers can segment transmission and reduce latency. This precise, position-based insertion lays the foundation for achieving low-skew, low-latency clock networks.

[0127] After inserting the buffer, immediately check for design rule violations (such as minimum spacing and layer stacking constraints) to ensure compliance with physical implementation. If violations exist, iteratively adjust the buffer parameters or position until all constraints are met.

[0128] Step S430: If there is an obstacle at the coordinate position, insert a target buffer at least on the left, right, bottom, or top side of the obstacle.

[0129] If an obstacle (such as a placed macro or I / O unit) is detected at the target coordinates in step S420, an alternative location search mechanism is initiated. The presence of an obstacle may stem from hard constraints in the physical design (such as fixed macro placement) or timing optimization requirements (such as avoiding crossing high-noise areas). Directly inserting a buffer in this situation would result in DRC violations or signal interference, necessitating a relocation.

[0130] To ensure that the buffer is as close to the original coordinates as possible while avoiding obstacles, the binary variable ψj , q Make sure the buffer is not inside the bounding box of the obstacle and introduce further constraints: ψj , q left + ψj , q right + ψj , q below + ψj , q above ≥1.

[0131] This constraint requires the buffer to be located in at least one of the four directions: left, right, bottom, or top of the obstacle, avoiding deviations from the original coordinates or complex detours. This allows the buffer to be inserted only close to the edge of the obstacle, avoiding obstruction while remaining as close to the original location as possible, minimizing impact on the clock signal path.

[0132] In one embodiment of the present application, Figure 5As shown, the clock tree synthesis method may further include steps S510 to S520, which are specifically described as follows:

[0133] Step S510 : Based on the metal wire length and load capacitance corresponding to each node, a preliminary screening is performed in a preset buffer list to obtain a plurality of candidate buffers.

[0134] In the process of selecting a target buffer, a preliminary screening may first be performed in a preset buffer list based on the metal wire length and load capacitance corresponding to each node to obtain a plurality of candidate buffers.

[0135] The preset buffer list is an index database created after electrical characteristic simulation of the buffers. In some embodiments, the preset buffer list is created by: performing circuit simulations based on a target process library for different types of buffers connected to metal wires of different lengths, recording the electrical characteristic parameters corresponding to the different types of buffers; and creating a buffer list indexed by metal wire length and buffer type, storing the electrical characteristic parameters for each combination.

[0136] Specifically, first, based on the target process library, various types of buffers are selected from the library. These buffers differ in driving capability, size, power consumption, etc., such as BUF_X1, BUF_X2 and other buffer types with different driving strengths.

[0137] Next, we enter the circuit simulation phase. For each buffer type, metal wires of different lengths are connected for simulation. The metal wire length will cover various possible values ​​from shorter to longer, simulating the different situations of actual wiring in the chip. During the simulation process, the electrical characteristic parameters corresponding to each "buffer-metal wire length" combination are recorded in detail, including but not limited to transmission delay, rise / fall time, power consumption, maximum drive load capacitance, etc. These parameters directly reflect the working performance of the buffer under a specific metal wire length. For example, the transmission delay determines the time required for the signal to go from the buffer input to the output, and the maximum drive load capacitance indicates the upper limit of the load that the buffer can normally drive.

[0138] Finally, in the data integration phase, a buffer list is created, indexed by metal line length and buffer type. In this list, metal line length is one dimension, and different buffer types are another. Each intersection corresponds to a set of electrical characteristic parameters. For example, when the metal line length is 500μm and the buffer type is BUF_X2, this location stores specific parameters such as delay and power consumption for this combination. Through this structured approach, the large amount of simulated data is stored in an orderly manner, thus establishing a buffer list. Pre-generating the buffer list provides input for the next optimization algorithm. This allows for rapid evaluation of candidate solutions during the optimization process, quickly finding the target buffer, avoiding repeated circuit simulations, and significantly improving efficiency.

[0139] Schematically, with the metal line length as the row index and different buffer types as the column index, the established buffer list can be shown in Table 1 below.

[0140] Table 1 Buffer list

[0141]

[0142] Please continue to see Figure 5 In step S520, based on the power consumption values ​​corresponding to the multiple candidate buffers, a buffer with the smallest power consumption value is screened out from the multiple candidate buffers again, and the buffer screened out again is used as the target buffer.

[0143] Based on the metal wire length and load capacitance corresponding to the node, multiple candidate buffers with suitable electrical performance have been selected from the preset buffer list. Although these candidate buffers can all meet the basic driving capability and timing requirements, there are differences in power consumption. Each candidate buffer has its own corresponding power consumption value in a specific working scenario (i.e., the metal wire length and load conditions of the corresponding node). This value comes from the electrical characteristic parameters stored in the preset buffer list and reflects the energy consumed by the buffer when driving the signal.

[0144] The essence of this second screening process is to compare the power consumption of candidate buffers. By extracting the power consumption value of each candidate buffer one by one and comparing the values, the buffer with the lowest power consumption is found.

[0145] Selecting the buffer with the lowest power consumption as the target buffer can, on the one hand, reduce the buffer power consumption of a single node and reduce dynamic power consumption at the overall chip level, which is crucial for power-sensitive application scenarios such as portable devices. On the other hand, this screening process is based on meeting electrical performance standards, ensuring that the selected buffer optimizes energy consumption while meeting core requirements such as driving load and controlling signal delay, which helps to improve the chip's energy efficiency and overall performance.

[0146] In one embodiment of the present application, an automatic layout algorithm may be called to perform normalization processing on the generated buffer coordinates to ensure that the moving distance of the buffer is minimized to ensure that the generated optimal solution has the smallest jitter.

[0147] Specifically, in the clock tree synthesis process, automatic layout algorithms and buffer coordinate normalization are key steps to improve design stability and manufacturability. Their core goal is to minimize the physical movement distance of the buffer while ensuring timing performance, thereby reducing timing jitter caused by layout changes.

[0148] After completing the clock tree logic topology design (such as determining the clusters and buffer types at each level), these logical nodes need to be mapped to the physical chip layout. The automatic layout algorithm considers multiple factors, such as logical hierarchical relationships, signal transmission delays, and process regulations. Using complex mathematical models and optimization strategies, it calculates the theoretically optimal coordinates for each buffer.

[0149] However, the buffer coordinates generated by the automatic layout algorithm may exhibit slight fluctuations or deviate from the standard position. These subtle differences, in advanced processes, can lead to variations in signal transmission delay, increased routing complexity, and even affect the overall timing stability of the clock tree. Therefore, the buffer coordinates need to be normalized. Normalization essentially adjusts the buffer coordinates to a position that meets process standards or design specifications. For example, this can be achieved by forcing the coordinates to align with a grid point of a specific size or to move them closer to the center of a cluster. This ensures the regularity of the buffer layout while reducing signal delay uncertainty caused by positional variations.

[0150] The core goal of normalization is to ensure that the buffer's movement distance is minimized to ensure the generated optimal de-jitter is minimized. If the buffer movement distance is too large, it may not only destroy the clock tree topology designed in the early stage, resulting in a decrease in timing performance, but also increase the cost of back-end physical verification and modification. By limiting the buffer's movement distance, the buffer position can be made more reasonable and stable while retaining the original design advantages as much as possible. "Minimum optimal de-jitter" means that the normalized buffer layout has higher stability and repeatability while ensuring that key indicators such as signal transmission delay and offset meet the standards, avoiding large fluctuations in clock tree performance due to slight changes in coordinates, thereby improving the success rate and reliability of chip design. It is especially suitable for high-performance chip design scenarios with strict timing requirements.

[0151] In the second aspect, the present application also proposes a clock tree synthesis device, such as Figure 6 As shown, the clock tree synthesis device includes a dividing unit 601 , a constructing unit 602 , an analyzing unit 603 and an adjusting unit 604 .

[0152] Among them, the division unit 601 is configured to divide multiple timing units that need to receive clock signals from a clock source into clusters of different levels, wherein the load capacitance of each cluster at the same level is balanced; the construction unit 602 is configured to recursively construct the clock tree according to the hierarchical order of the clusters starting from the clock source, taking each cluster as a node of the clock tree, and inserting a target buffer at the position of each node to drive the corresponding node; the analysis unit 603 is configured to analyze the delay and offset of the constructed clock tree to obtain an analysis result; the adjustment unit 604 is configured to adjust the clock tree if the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraints, until the delay and offset of the adjusted clock tree meet the preset constraints.

[0153] In some embodiments of the present application, the division unit 601 is further configured to determine the number of division levels and the number of clusters corresponding to each level based on the input branching factor vector; and divide the multiple timing units into clusters of different levels layer by layer based on the number of division levels and the number of clusters corresponding to each level.

[0154] In some embodiments of the present application, the division unit 601 is also configured to, in the process of hierarchical division, if the number of timing units in each clustering cluster corresponding to the current level is greater than a preset threshold, then use the global clustering method to determine the timing unit clustering scheme in each clustering cluster corresponding to the current level; if the number of timing units in each clustering cluster corresponding to the current level is less than or equal to the preset threshold, then use the local clustering method to determine the timing unit clustering scheme in each clustering cluster corresponding to the current level.

[0155] In some embodiments of the present application, the sequential unit clustering scheme within each cluster corresponding to the current level determined by the global clustering method satisfies the minimum first objective function and satisfies the load capacitance constraint of each cluster within an allowable range. The first objective function is:

[0156]

[0157] in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster Each time series unit in the cluster The maximum distance from the center position, is the weighting coefficient.

[0158] In some embodiments of the present application, the sequential unit clustering scheme within each cluster corresponding to the current level determined by the local clustering method satisfies the minimum second objective function and satisfies the total load capacitance constraint of each cluster within an allowable range. The second objective function is:

[0159]

[0160] in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster The semi-perimeter of the bounding box of is the weighting coefficient.

[0161] In some embodiments of the present application, the construction unit 602 is also configured to determine the coordinate position of each node based on the weighted center of the cluster corresponding to each node; if there is no obstacle at the coordinate position, the target buffer is inserted at the coordinate position; if there is an obstacle at the coordinate position, the target buffer is inserted on at least one side of the left, right, bottom, and top of the obstacle.

[0162] In some embodiments of the present application, the construction unit 602 is further configured to establish a linear programming model based on the weighted center of the cluster corresponding to each node, solve the linear programming model, and obtain the coordinate position of each node; wherein, the linear programming model takes minimizing the maximum distance between the node and the weighted center as the objective function, takes the distance between adjacent nodes as a fixed value as the first constraint condition, and takes the preset distance relationship between the node and the weighted center as the second constraint condition.

[0163] In some embodiments of the present application, the construction unit 602 is further configured to perform preliminary screening in a preset buffer list based on the metal wire length and load capacitance corresponding to each node to obtain multiple candidate buffers; based on the power consumption values ​​corresponding to the multiple candidate buffers, the buffer with the smallest power consumption value is again screened out from the multiple candidate buffers, and the buffer screened out again is used as the target buffer.

[0164] In some embodiments of the present application, the preset buffer list is established in the following manner: based on the target process library, circuit simulation is performed on different types of buffers connected to metal wires of different lengths, and the electrical characteristic parameters corresponding to the different types of buffers are recorded; a buffer list is established with metal wire length and buffer type as indexes, and the electrical characteristic parameters under each combination are stored.

[0165] In a third aspect, the present application proposes a clock tree synthesis system, comprising: a solution vector construction module, a space establishment module and a storage retrieval module.

[0166] Among them, the solution vector construction module is configured to use the clock tree to be constructed as the solution of the clock tree, and the solution of the clock tree is represented as a parameter vector including buffer type, insertion coordinates, line length allocation, and driving capability; the space establishment module is configured to establish a multidimensional index space with clock tree depth, convergence area, number of convergence point areas, maximum clock delay, minimum clock delay, and input capacitance as dimensions; the storage and retrieval module is configured to store the parameter vector in the multidimensional index space to form a parameterized result set for retrieving the solution of the clock tree that meets the preset constraints.

[0167] like Figure 7 As shown, an embodiment of the present application also provides an electronic device 700, including a memory 710, a processor 720, and a computer program 711 stored in the memory 710 and executable on the processor. When the processor 720 executes the computer program 711, the steps of any of the above-mentioned clock tree synthesis methods are implemented.

[0168] Since the electronic device introduced in this embodiment is a device used to implement a clock tree synthesis device in the embodiment of the present application, based on the method introduced in the embodiment of the present application, technical personnel in this field can understand the specific implementation of the electronic device of this embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application will not be described in detail here. As long as the equipment used by technical personnel in this field to implement the method in the embodiment of the present application falls within the scope of protection to be protected by this application.

[0169] In a specific implementation process, the computer program 711 can be implemented when executed by the processor Figures 1 to 5 Any implementation manner in the corresponding embodiments.

[0170] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0171] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0172] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0173] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0174] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0175] An embodiment of the present application further provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes the clock tree synthesis process in the corresponding embodiment.

[0176] A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, they fully or partially produce the processes or functions according to the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be stored by a computer, or a data storage device such as a server or data center that integrates one or more available media. Available media can include magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0177] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0178] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0179] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0180] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0181] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0182] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A clock tree synthesis method, characterized in that: include: Divide multiple sequential units that need to receive clock signals from a clock source into clusters at different levels, where the load capacitance of each cluster at the same level is balanced; According to the hierarchical order of the clusters starting from the clock source, each cluster is regarded as a node of the clock tree, the clock tree is recursively constructed, and a target buffer is inserted at the position of each node for driving the corresponding node; Analyze the delay and offset of the constructed clock tree to obtain analysis results; If the analysis result indicates that the delay and offset of the clock tree do not meet the preset constraint conditions, adjusting the clock tree until the delay and offset of the adjusted clock tree meet the preset constraint conditions; The method of dividing multiple timing units that need to receive clock signals from a clock source into clusters of different levels includes: determining the number of division levels and the number of clusters corresponding to each level based on the input branching factor vector; dividing the multiple timing units into clusters of different levels level by level based on the number of division levels and the number of clusters corresponding to each level; in the level-by-level division process, if the number of timing units in each cluster corresponding to the current level is greater than a preset threshold, then using a global clustering method to determine the clustering scheme of the timing units in each cluster corresponding to the current level; if the number of timing units in each cluster corresponding to the current level is less than or equal to the preset threshold, then using a local clustering method to determine the clustering scheme of the timing units in each cluster corresponding to the current level.

2. The method according to claim 1, characterized in that The method further comprises: The sequential unit clustering scheme within each cluster corresponding to the current level determined by the global clustering method satisfies the minimum first objective function and satisfies the load capacitance constraint of each cluster within an allowable range. The first objective function is: in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster Each time series unit in the cluster The maximum distance from the center position, is the weighting coefficient.

3. The method according to claim 1, characterized in that The method further comprises: The sequential unit clustering scheme within each cluster corresponding to the current level determined by the local clustering method satisfies the minimum second objective function and satisfies the total load capacitance constraint of each cluster within an allowable range. The second objective function is: in, Cluster Each time series unit in the cluster The sum of the distances to the center positions, Cluster The semi-perimeter of the bounding box of is the weighting coefficient.

4. The method according to claim 1, wherein Insert the target buffer at each node location, including: Determining the coordinate position of each node according to the weighted center of the cluster corresponding to each node; If no obstacle exists at the coordinate position, inserting the target buffer at the coordinate position; If the obstacle exists at the coordinate position, the target buffer is inserted at least one side of the left, right, bottom, and top of the obstacle.

5. The method according to claim 4, characterized in that Determining the coordinate position of each node according to the weighted center of the cluster corresponding to each node includes: Establishing a linear programming model according to the weighted center of the cluster corresponding to each node, and solving the linear programming model to obtain the coordinate position of each node; The linear programming model takes minimizing the maximum distance between the node and the weighted center as the objective function, takes the distance between adjacent nodes as a fixed value as the first constraint, and takes the preset distance relationship between the node and the weighted center as the second constraint.

6. The method according to claim 1, characterized in that The method further comprises: Based on the metal wire length and load capacitance corresponding to each node, a preliminary screening is performed in a preset buffer list to obtain a plurality of candidate buffers; Based on the power consumption values ​​respectively corresponding to the multiple candidate buffers, a buffer with the smallest power consumption value is screened out again from the multiple candidate buffers, and the buffer screened out again is used as the target buffer.

7. The method according to claim 6, characterized in that The preset buffer list is established in the following manner: Based on the target process library, circuit simulation is performed on different types of buffers connected to metal wires of different lengths, and electrical characteristic parameters corresponding to the different types of buffers are recorded; A buffer list is created with metal line length and buffer type as indexes, and electrical characteristic parameters under each combination are stored.

8. A clock tree synthesis device, characterized in that: include: a dividing unit configured to divide a plurality of sequential units that need to receive clock signals from a clock source into clusters at different levels, wherein the load capacitance of each cluster at the same level is balanced; a construction unit configured to recursively construct the clock tree according to the hierarchical order of the clusters starting from the clock source, taking each cluster as a node of the clock tree, and inserting a target buffer at the position of each node for driving the corresponding node; an analysis unit configured to analyze the delay and offset of the constructed clock tree to obtain an analysis result; an adjusting unit, configured to, if the analysis result indicates that the delay and offset of the clock tree do not satisfy a preset constraint, adjust the clock tree until the delay and offset of the adjusted clock tree satisfy the preset constraint; The division unit is further configured to: determine the number of division levels and the number of clusters corresponding to each level based on the input branching factor vector; divide the multiple timing units into clusters of different levels level by level based on the number of division levels and the number of clusters corresponding to each level; in the level-by-level division process, if the number of timing units in each cluster corresponding to the current level is greater than a preset threshold, then use a global clustering method to determine the timing unit clustering scheme in each cluster corresponding to the current level; if the number of timing units in each cluster corresponding to the current level is less than or equal to the preset threshold, then use a local clustering method to determine the timing unit clustering scheme in each cluster corresponding to the current level.

9. A clock tree synthesis system, characterized in that: The clock tree synthesis system is used to execute the clock tree synthesis method according to any one of claims 1 to 7, comprising: a solution vector construction module configured to use the clock tree to be constructed as a solution of the clock tree, wherein the solution of the clock tree is represented as a parameter vector including a plurality of parameters of a buffer type, an insertion coordinate, a line length allocation, and a driving capability; a space establishment module configured to establish a multi-dimensional index space with multiple dimensions of clock tree depth, convergence area, number of convergence point areas, maximum clock delay, minimum clock delay, and input capacitance; The storage and retrieval module is configured to store the parameter vector in the multidimensional index space to form a parameterized result set for retrieving a solution of the clock tree that meets preset constraints.

10. An electronic device comprising: A memory and a processor, wherein the processor is configured to implement the clock tree synthesis method according to any one of claims 1 to 7 when executing a computer program stored in the memory.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the clock tree synthesis method according to any one of claims 1 to 7 is implemented.

Images