Calibration circuit and method

Abstract

The present invention provides a calibration circuit and method. It relates to the field of high-speed signal processing technology. The calibration circuit includes: a first calibration subcircuit, which is used to detect whether each control signal in the control bus has a rising edge or a falling edge; when the control signal in the control bus has a rising edge or a falling edge, a target pulse signal is generated; a second calibration subcircuit, which is used to generate a set of differential delay control buses based on the control bus; the differential delay control bus is used to retain the first bus state of the control bus; a third calibration subcircuit, which is used to generate a low window signal based on the target pulse signal; a fourth calibration subcircuit, which is used to synchronize the first bus state to the second bus state in response to the low window signal; the fourth calibration subcircuit is also used to send the control signal in the control bus in the second bus state to the target circuit. The embodiment of the present disclosure can eliminate the clock offset between the control bus signals with low power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed signal processing, and in particular to a calibration circuit and method. Background Art

[0002] There are a large number of control buses between the digital circuits and analog circuits of the chip. Usually, the control bus is updated at some time points according to a clock or state machine. However, due to the different circuit paths and driving capabilities of the control bus, different locations of the control bus will show different delays when reaching the target circuit, resulting in bus delay clock offset. Therefore, a low-power calibration circuit design is urgently needed to eliminate the clock offset between control bus signals. Summary of the invention

[0003] The present disclosure provides a calibration circuit and method.

[0004] According to a first aspect of the present disclosure, a calibration circuit is provided for eliminating clock offsets between control bus signals, the circuit comprising: a first calibration subcircuit, a second calibration subcircuit, a third calibration subcircuit and a fourth calibration subcircuit; wherein an input end of the first calibration subcircuit is connected to the control bus, and an output end of the first calibration subcircuit is connected to the second calibration subcircuit and the third calibration subcircuit; an input end of the second calibration subcircuit is connected to the control bus or the first calibration subcircuit, and an output end of the second calibration subcircuit is connected to the fourth calibration subcircuit; an output end of the third calibration subcircuit is connected to the fourth calibration subcircuit; and an output end of the fourth calibration subcircuit is connected to a target circuit;

[0005] The first calibration subcircuit is used to detect whether each control signal in the control bus has a rising edge or a falling edge; when the control signal in the control bus has a rising edge or a falling edge, a target pulse signal is generated;

[0006] A second calibration subcircuit is used to generate a set of differential delay control buses based on the control bus; wherein the differential delay control bus is used to retain a first bus state of the control bus; the first bus state is a bus state in which the clock offset between the control signals in the control bus is not eliminated;

[0007] A third calibration subcircuit is used to generate a low window signal based on the target pulse signal; wherein the low window signal is a control signal that is high in a first time period and low in only one second time period; the first time period is greater than the second time period;

[0008] a fourth calibration subcircuit, configured to synchronize the first bus state to a second bus state in response to the low window signal; wherein the second bus state is a bus state in which a clock offset between control signals in the control bus signal has been eliminated;

[0009] The fourth calibration sub-circuit is further configured to send the control signal in the control bus in the second bus state to the target circuit.

[0010] According to a second aspect of the present disclosure, a calibration method is provided for calibrating a clock offset of a control bus, comprising:

[0011] Detecting whether each control signal in the control bus has a rising edge or a falling edge, and generating a target pulse signal when the control signal in the control bus has a rising edge or a falling edge;

[0012] A set of differential delay control buses is generated based on the control bus; wherein the differential delay control bus is used to retain a first bus state of the control bus; the first bus state is a bus state in which the clock offset between the control signals in the control bus is not eliminated;

[0013] Generate a low window signal based on the target pulse signal; wherein the low window signal is a control signal that is high level in a first time period and low level in only one second time period; the first time period is greater than the second time period;

[0014] Synchronizing the first bus state to a second bus state in response to the low window signal; wherein the second bus state is a bus state in which a clock offset between control signals in the control bus signal has been eliminated;

[0015] The control signal in the control bus in the second bus state is sent to the target circuit.

[0016] According to the technical solution disclosed in the present invention, the clock offset between control bus signals can be eliminated with low power consumption, thereby improving the stability and reliability of high-speed signal transmission.

[0017] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of eliminating control bus delay in the prior art;

[0019] Figure 2 A schematic diagram of a calibration circuit according to an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of the connection of the calibration circuit provided in the embodiment of the present invention Figure 1 ;

[0021] Figure 4 Waveform diagram of the calibration control bus provided by the embodiment of the present invention Figure 1 ;

[0022] Figure 5 A schematic diagram of the connection of the calibration circuit provided in the embodiment of the present invention Figure 2 ;

[0023] Figure 6 Waveform diagram of the calibration control bus provided by the embodiment of the present invention Figure 2 ;

[0024] Figure 7 A schematic diagram of a flow chart of a calibration method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The present disclosure will be further described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0026] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

[0027] The term "and / or" herein means that there may be three relationships. For example, A and / or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The term "at least one" herein means any combination of at least two of any one or more of a plurality of. For example, at least one of A, B, and C may mean any one or more elements selected from the set consisting of A, B, and C. The terms "first" and "second" herein refer to and distinguish a plurality of similar technical terms. They do not mean to limit the order or to limit the meaning to only two. For example, the first feature and the second feature refer to two types / two features. The first feature may be one or more, and the second feature may also be one or more.

[0028] In the related art, there are a large number of control buses (or data buses) between the digital logic circuit and the analog signal circuit of the chip. The control bus can be from the digital logic circuit to the analog signal circuit, or from the analog signal circuit to the digital logic circuit. Usually, the control bus is continuously updated at some time points according to a clock or a state machine. However, due to the differences in the circuit paths generated by different bus bits of the control bus, the number of added buffers, the driving capability, the number of layers and length of metal wiring, etc., the control bus bits will show different delays when reaching the target circuit, resulting in bus delay skew. The sensitivity or tolerance of various circuits on the chip to the control bus delay skew is different. Some circuits can withstand a large bus delay skew, such as greater than 500 picoseconds (Picosecond, PS), but some circuits cannot even withstand a control bus delay skew of 100PS, resulting in a decrease in circuit performance or even failure.

[0029] Figure 1 A schematic diagram of eliminating control bus delay in the prior art is shown. Figure 1 As shown, the working principle of the control bus delay elimination method is to use a synchronous clock to resample or re-time all the control bits of the control bus at the target module end to remove the delay difference of each control bit of the control bus. This method can indeed achieve the function of eliminating the offset (Deskew). However, the method of the prior art has the following disadvantages: First, the method requires a clock signal for synchronization. Because it is difficult to dynamically switch the clock signal in practical applications, the clock signal needs to work continuously; but this will increase the power consumption of the circuit. Secondly, the method will generate additional noise, which will interfere with other sensitive modules in the circuit system and affect the electromagnetic compatibility (EMC) performance of the system; for example, the noise of the clock signal will propagate through the power supply and ground. Finally, each bit signal of the method requires a sampling device (such as a D flip-flop), which will increase the circuit area, especially when a chip needs to deskew hundreds or thousands of control bus signals. In addition, if there is a delay in the clock distribution (Distribution) to each flip-flop (Flip-Flop, FF), this will increase the remaining bus residual clock skew (Skew).

[0030] In order to at least partially solve one or more of the above problems and other potential problems, the present disclosure proposes a control circuit and method for eliminating Skew between control bus signals, the circuit comprising: a first calibration subcircuit for detecting whether each control signal in the control bus has a rising edge or a falling edge; a second calibration subcircuit for generating a set of differential delay control buses based on the control bus; the differential delay control bus is used to retain the first bus state of the control bus; a third calibration subcircuit for generating a target signal based on a target pulse signal; a fourth calibration subcircuit for synchronizing the first bus state to the second bus state in response to the target signal. In this way, the clock offset between the control bus signals can be eliminated with low power consumption, thereby improving the stability and reliability of high-speed signal transmission.

[0031] Figure 2 is a schematic diagram of a calibration circuit according to an embodiment of the present disclosure, such as Figure 2 As shown, the circuit may include: a first calibration subcircuit 210, a second calibration subcircuit 220, a third calibration subcircuit 230 and a fourth calibration subcircuit 240; wherein the input end of the first calibration subcircuit 210 is connected to the control bus, and the output end of the first calibration subcircuit 210 is connected to the second calibration subcircuit 220 and the third calibration subcircuit 230; the input end of the second calibration subcircuit 220 is connected to the control bus or the first calibration subcircuit 210, and the output end of the second calibration subcircuit 220 is connected to the fourth calibration subcircuit 240; the output end of the third calibration subcircuit 230 is connected to the fourth calibration subcircuit 240; and the output end of the fourth calibration subcircuit 240 is connected to the target circuit;

[0032] The first calibration sub-circuit 210 is used to detect whether each control signal in the control bus has a rising edge or a falling edge; when the control signal in the control bus has a rising edge or a falling edge, a target pulse signal is generated;

[0033] The second calibration subcircuit 220 is used to generate a set of differential delay control buses based on the control bus; wherein the differential delay control bus is used to retain the first bus state of the control bus; the first bus state is a bus state in which the clock offset between the control signals in the control bus is not eliminated;

[0034] The third calibration subcircuit 230 is used to generate a low window signal based on the target pulse signal; wherein the low window signal is a control signal that is high in a first time period and low in only one second time period; the first time period is greater than the second time period;

[0035] The fourth calibration subcircuit 240 is used to synchronize the first bus state to a second bus state in response to the low window signal; wherein the second bus state is a bus state in which the clock offset between the control signals in the control bus signal has been eliminated;

[0036] The fourth calibration sub-circuit 240 is further configured to send the control signal in the control bus in the second bus state to the target circuit.

[0037] Here, the calibration circuit is placed before the target circuit to calibrate the clock offset of the control bus before the control bus reaches the target circuit.

[0038] In some embodiments, the control bus is used to transmit various control signals; the control signals are used to instruct the target circuit to perform specific operations or functions; the control signals may include: start, stop, read, write, etc. The above instructions may be generated by a system controller (such as a central processing unit (CPU)) and sent to the target circuit via the control bus.

[0039] In some embodiments, the first calibration subcircuit is used to detect whether each control signal in the control bus has a rising edge or a falling edge; if the control signal in the control bus has a rising edge or a falling edge, a target pulse signal is generated; wherein the target pulse signal is a high narrow pulse signal (OS), and the OS[K:0] signal is used to generate a low window signal; the rising edge refers to the process of the control signal jumping from a low level (usually 0V or logic 0) to a high level (usually 1V or logic 1); the falling edge refers to the process of the control signal jumping from a high level (1V or logic 1) to a low level (0V or logic 0). The first calibration subcircuit is also used to generate a group of delay control buses CTL_DELAY[K:0] by adding a delay to each control signal in the control bus; a group of differential delay control buses is generated based on a group of delay control buses; wherein the synchronization signal samples the group of delay control buses to implement the Deskew function. The first calibration sub-circuit includes: a first detection unit, used to detect whether each control signal in the control bus has a rising edge or a falling edge; the input end of the first detection unit is connected to the control bus, the first output end of the first detection unit is connected to the first inverter and the transmission gate of the second calibration sub-circuit, and the second output end of the first calibration sub-circuit is connected to the first transistor of the third calibration sub-circuit.

[0040] In some embodiments, the second calibration subcircuit is used to generate a group of differential delay control buses based on the control bus; the differential delay control bus is used to retain the first bus state of the control bus. The group of differential delay control buses and the delay control bus are used to reset K+1 latch (LATCH) units to retain the first bus state and the second bus state of the control bus; wherein K is a positive integer; the first bus state is a bus state in which the clock offset between the control bus signals is not eliminated, and the second bus state is a bus state in which the clock offset between the control bus signals is eliminated. LATCH is a basic storage unit for storing one bit of binary information (0 or 1); the basic function of LATCH is to store data without the control of a clock signal; LATCH can change state under the action of a specific input pulse level, thereby temporarily storing the signal to maintain a certain level state.

[0041] In some embodiments, the third calibration subcircuit is used to generate a low window signal based on the target pulse signal. Wherein, when the third calibration subcircuit includes: a first transistor, a second transistor, a target resistor, a target capacitor, a fourth inverter and a fifth inverter, the third calibration subcircuit is used to generate a low window signal based on the target pulse signal. When the third calibration subcircuit includes: a first transistor, a second transistor, a target resistor, a target capacitor, a fourth inverter, a fifth inverter and a second detection unit, the third calibration subcircuit is used to respond to a rising edge of the low window signal and output a synchronization pulse signal.

[0042] In some embodiments, the fourth calibration subcircuit is used to synchronize the first bus state to the second bus state in response to the low window signal. The fourth calibration subcircuit is also used to retain the first control bus state; and after all the control signals of the control bus have completed the jump, the second bus state is given to all LATCH units, and the second bus state is output. In this way, the clock offset between the control signals of the control bus is eliminated. Specifically, due to the large resistance of the target resistor (R_WIN), the low window signal (OSB_GATE) is pulled high within the interval time of each two groups of signal jumps. When a new group of jumps comes, since the impedance of each pull-down CMOS is much smaller than R_WIN, the low window signal OSB_GATE signal will be pulled down relatively quickly by each target pulse signal (OS). When all signal jumps at the same time point are completed, the low window signal (OSB_GATE) will be pulled up relatively slowly, and at this time, each control signal of the control bus will be released from the fourth calibration subcircuit at the same time.

[0043] In some embodiments, generating a differential delay control bus may include: directly generating a group of differential delay control buses based on the control bus; or generating a group of delay control buses by adding a delay to each control signal in the control bus; generating a group of differential delay control buses based on a group of delay control buses. The differential delay control bus is used to retain the first bus state of the control bus.

[0044] In some embodiments, the first bus state refers to a bus state in which clock offsets between control bus signals are not eliminated, and the second bus state refers to a bus state in which clock offsets between control bus signals are eliminated.

[0045] The solution of the embodiment of the present disclosure provides a calibration circuit including a first calibration subcircuit, a second calibration subcircuit, a third calibration subcircuit and a fourth calibration subcircuit. The calibration circuit can eliminate the clock offset between control bus signals with low power consumption, thereby improving the stability and reliability of high-speed signal transmission.

[0046] In an embodiment of the present disclosure, a group of differential delay control buses are generated based on the control bus, including: adding a delay to each control signal in the control bus to generate a group of delay control buses; generating a group of differential delay control buses based on the group of delay control buses.

[0047] In some embodiments, adding a delay to each control signal in the control bus means adding a delay of a preset time during the transmission of the control signal. The delay can be fixed or variable. The delay can be set according to demand and circuit design.

[0048] In some embodiments, the delay control bus is obtained by adding a delay to each control signal in the control bus. Each control signal in the delay control bus has a delay of a preset time.

[0049] In this way, the clock offset between bus signals can be effectively eliminated, thereby improving the accuracy of signal transmission.

[0050] In some embodiments, the first calibration sub-circuit includes: a first detection unit, used to detect whether each control signal in the control bus has a rising edge or a falling edge; the input end of the first detection unit is connected to the control bus, the first output end of the first detection unit is connected to the first inverter and the transmission gate of the second calibration sub-circuit, and the second output end of the first calibration sub-circuit is connected to the first transistor of the third calibration sub-circuit.

[0051] In some embodiments, the first detection unit (EDGE DET) is used to detect whether each control signal in the control bus has a rising edge or a falling edge. In the first detection unit, the implementation of edge detection usually relies on registers and logical operations. A common method is to use two-level registers to latch the state of the input signal, the first-level register latches the current state, and the second-level register latches the state of the next clock cycle; by comparing the values ​​of the two registers, the rising edge or falling edge of the signal can be detected. Specifically, if the value of the first-level register is low (0) and the value of the second-level register is high (1), the rising edge is detected; on the contrary, if the value of the first-level register is high (1) and the value of the second-level register is low (0), the falling edge is detected. This logical operation can be implemented by simple "AND", "OR" and "NOT" operations.

[0052] In this way, the first detection unit can accurately detect the rising edge and the falling edge of the control signal in the control bus, providing strong support for the stable transmission of high-speed signals.

[0053] In an embodiment of the present disclosure, synchronizing the first bus state to the second bus state in response to a low window signal includes: synchronizing the first bus state to the second bus state in response to the end of the low window signal; wherein the length of the low window signal is greater than the length of each control signal jump completion of the control bus.

[0054] In some embodiments, the low window signal is a control signal that is high in a first time period and low in only a second time period; the first time period is much longer than the second time period. For example, the first time period is 1 second and the second time period is 1 millisecond. The length of the low window signal is greater than the length of each control signal jump of the control bus. The length of the low window signal can be set according to the estimated maximum Skew of the control bus.

[0055] In this way, it can be ensured that before the first bus state is synchronized to the second bus state, it will not be affected by the incomplete signal transition, thereby helping to maintain the consistency and stability of the bus state.

[0056] In the disclosed embodiment, the second calibration sub-circuit includes: a transmission gate, a first inverter, a second inverter, and a third inverter; wherein, one end of the first inverter is connected to the input end or the first output end of the first calibration sub-circuit, and the other end is connected to the second inverter; one end of the second inverter is connected to the first inverter, and the other end is connected to the fourth transistor of the fourth calibration sub-circuit; one end of the transmission gate is connected to the first output end of the first detection unit, and the other end is connected to the third inverter; one end of the third inverter is connected to the transmission gate, and the other end is connected to the sixth transistor of the fourth calibration sub-circuit.

[0057] In some embodiments, a transmission gate is a controllable switch circuit used to provide a flexible selective path during digital signal transmission. The transmission gate is usually composed of complementary P-channel and N-channel field effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) in parallel to achieve bidirectional transmission characteristics. The working principle of the transmission gate is based on the switching characteristics of MOSFET. When the control signal is high, the P-channel MOSFET is turned off and the N-channel MOSFET is turned on, allowing the digital signal to be transmitted from the input to the output; conversely, when the control signal is low, the P-channel MOSFET is turned on and the N-channel MOSFET is turned off; at this time, although the signal cannot be directly transmitted from the input to the output, due to the parallel structure of the P-channel and N-channel, if the output is originally high, it can be maintained at a high level through the P-channel MOSFET, and vice versa. However, this is not true signal transmission, but state retention.

[0058] In some embodiments, an inverter is a circuit that can reverse the phase of an input signal by 180 degrees. Specifically, when the input signal is at a high level, the inverter outputs a low level; and when the input signal is at a low level, the inverter outputs a high level. The working principle of the inverter is based on the principle of negative feedback. In an electronic circuit, an inverter is usually composed of a transistor or an operational amplifier and a feedback resistor. The transistor or operational amplifier is used as an amplifier to amplify the level of the input signal; and the feedback resistor is used to provide a feedback path so that the output signal and the input signal form an inverse relationship in level.

[0059] In this way, a group of differential delay control buses are generated based on the control bus by the second calibration sub-circuit, so as to achieve the first bus state of the control bus being retained and the second bus state of the control bus being overwritten.

[0060] In the embodiment of the present disclosure, the third calibration subcircuit includes: a first transistor, a second transistor, a target resistor, a target capacitor, a fourth inverter and a fifth inverter; wherein, the second end and the control end of the first transistor are grounded, and the first end of the first transistor is connected to the target resistor; the second end of the second transistor is grounded, the control end of the second transistor is connected to the second output end of the first detection unit, and the first end of the second transistor is connected to the target resistor; one end of the target capacitor is grounded, and the other end is connected to the fourth inverter; one end of the fourth inverter is connected to the target capacitor, and the other end is connected to the fifth inverter; one end of the fifth inverter is connected to the fourth inverter, and the other end is connected to the third transistor and the fifth transistor respectively.

[0061] In some embodiments, a complementary metal oxide semiconductor (CMOS) transistor is an important semiconductor device. It is composed of a P-type semiconductor and an N-type semiconductor, which are used alternately in CMOS circuits to form a complementary structure. The working principle of the transistor is based on the field effect principle, and the conductive state between the second end and the first end is controlled by changing the control terminal voltage. In CMOS circuits, P-type metal oxide semiconductor tubes (positive channel Metal Oxide Semiconductor, PMOS) and N-type metal oxide semiconductor tubes (N-Metal-Oxide-Semiconductor, NMOS) appear in pairs, and they work in a complementary manner, that is, when the PMOS tube is turned on, the NMOS tube is turned off; when the NMOS tube is turned on, the PMOS tube is turned off. This complementary characteristic makes CMOS circuits have the advantages of low power consumption, high integration, high noise suppression ratio and strong radiation resistance.

[0062] Figure 3 shows the connection diagram of the calibration circuit Figure 1 ,like Figure 3As shown, the calibration circuit includes: a first calibration subcircuit, a second calibration subcircuit, a third calibration subcircuit and a fourth calibration subcircuit. The first calibration subcircuit includes: a first detection unit; the input end of the first detection unit is connected to the control bus, the first output end of the first detection unit is connected to the first inverter and the transmission gate of the second calibration subcircuit, and the second output end of the first calibration subcircuit is connected to the first transistor of the third calibration subcircuit. The second calibration subcircuit includes: a transmission gate, a first inverter, a second inverter, and a third inverter; one end of the first inverter is connected to the input end or the first output end of the first calibration subcircuit, and the other end is connected to the second inverter; one end of the second inverter is connected to the first inverter, and the other end is connected to the fourth transistor of the fourth calibration subcircuit; one end of the transmission gate is connected to the first output end of the first detection unit, and the other end is connected to the third inverter; one end of the third inverter is connected to the transmission gate, and the other end is connected to the sixth transistor of the fourth calibration subcircuit. The third calibration subcircuit includes: a first transistor, a second transistor, a target resistor, a target capacitor, a fourth inverter and a fifth inverter; the second end and the control end of the first transistor are grounded, and the first end of the first transistor is connected to the target resistor; the second end of the second transistor is grounded, the control end of the second transistor is connected to the second output end of the first detection unit, and the first end of the second transistor is connected to the target resistor; one end of the target capacitor is grounded, and the other end is connected to the fourth inverter; one end of the fourth inverter is connected to the target capacitor, and the other end is connected to the fifth inverter; one end of the fifth inverter is connected to the fourth inverter, and the other end is connected to the third transistor and the fifth transistor respectively. The fourth calibration subcircuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a sixth inverter, a seventh inverter, an eighth inverter and a ninth inverter; the second end of the third transistor is grounded, the control end of the third transistor is connected to the fifth inverter or the second detection unit, and the first end of the third transistor is connected to the fourth transistor; the second end of the fourth transistor is connected to the third transistor, the control end of the fourth transistor is connected to the second inverter, and the first end of the fourth transistor is connected to the sixth inverter or the ninth inverter; the second end of the fifth transistor is grounded, the control end of the fifth transistor is connected to the fifth inverter or the second detection unit The first end of the fifth transistor is connected to the sixth transistor; the second end of the sixth transistor is connected to the fifth transistor, the control end of the sixth transistor is connected to the third inverter, and the first end of the sixth transistor is connected to the eighth inverter or the seventh inverter; one end of the sixth inverter is connected to the fourth transistor, and the other end is connected to the seventh inverter; one end of the seventh inverter is connected to the sixth inverter, and the other end is the first output end of the fourth calibration sub-circuit; one end of the eighth inverter is connected to the sixth transistor, and the other end is connected to the ninth inverter; one end of the ninth inverter is connected to the eighth inverter, and the other end is the second output end of the fourth calibration sub-circuit.

[0063] In some embodiments, the first transistor is a P-type metal-oxide-semiconductor field effect transistor (PMOS); when the first transistor is a PMOS, the control end is a gate, the first end is a source, and the second end is a drain. The second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type metal-oxide-semiconductor field effect transistors (NMOS); when the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS, the control end is a gate, the first end is a source, and the second end is a drain. The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, and the ninth inverter are composed of two complementary transistors (i.e., an NMOS tube and a PMOS tube).

[0064] Figure 4 The waveform diagram of the calibration control bus is shown in Figure 1 ,like Figure 4 As shown, the first group of waveforms assumes a group of two control signals CTL[n] and CTL[m] with skew; the second group of waveforms is the target pulse signal (OS[K:0]) generated based on CTL[n] and CTL[m]; the third group of waveforms CTL_DELAY[n] and CTL_DELAY[m] are the delayed control buses obtained by adding delay to each control signal of CTL[n] and CTL[m]; wherein, the jump of each control signal of the delayed control bus is placed within the low window signal to ensure that the new bus state will not be output to the second bus state in advance; the fourth group of waveforms is the low window signal generated based on the target pulse signal; in response to the last target pulse signal OS[m] changing from high to low, when PMOS and R_WIN start to pull the time window signal from low to high, all the signals that have jumped in the control bus will simultaneously overwrite the second bus state to the corresponding LATCH; in this way, the final output synchronous control bus signal CTL_SYNC[K:0] is generated. Since LATCH and subsequent inverters or buffers may have intrinsic pulse skew that appears in the final synchronous bus signal, there may be a residual skew of less than 10ps in actual implementation. If the intrinsic pulse skew of LATCH and subsequent inverters or buffers can be optimized to close to 0, the final residual skew will also be close to 0. In this case, the target pulse signal will be generated regardless of whether CTL[n] and CTL[m] have a rising edge or a falling edge.

[0065] In this way, the clock offset between control bus signals can be eliminated through a simple digital circuit; at the same time, a simple calibration circuit can help reduce the power consumption of calibration.

[0066] In the embodiment of the present disclosure, the third calibration sub-circuit also includes: a second detection unit, used to detect whether a rising edge occurs in the low window signal; if a rising edge occurs in the low window signal, a synchronization pulse signal is output; one end of the second detection unit is connected to the fifth inverter, and the other end is connected to the fifth transistor of the fourth calibration sub-circuit.

[0067] In some embodiments, the second detection unit (RISE EDGE DET) is used to detect whether a rising edge occurs in the low window signal. If a rising edge occurs in the low window signal, a synchronization pulse signal is output. Specifically, the second detection unit receives a low window signal from an upstream circuit; when the level of the low window signal reaches a preset threshold (i.e., transitions from a low level to a high level), the trigger is activated; when the trigger is activated, the second detection unit recognizes that a rising edge occurs in the low window signal. The second detection unit includes a plurality of comparators or triggers.

[0068] Figure 5 shows the connection diagram of the calibration circuit Figure 2 ,like Figure 5As shown, the calibration circuit includes: a first calibration subcircuit, a second calibration subcircuit, a third calibration subcircuit and a fourth calibration subcircuit. The first calibration subcircuit includes: a first detection unit; the input end of the first detection unit is connected to the control bus, the first output end of the first detection unit is connected to the first inverter and the transmission gate of the second calibration subcircuit, and the second output end of the first calibration subcircuit is connected to the first transistor of the third calibration subcircuit. The second calibration subcircuit includes: a transmission gate, a first inverter, a second inverter, and a third inverter; one end of the first inverter is connected to the input end or the first output end of the first calibration subcircuit, and the other end is connected to the second inverter; one end of the second inverter is connected to the first inverter, and the other end is connected to the fourth transistor of the fourth calibration subcircuit; one end of the transmission gate is connected to the first output end of the first detection unit, and the other end is connected to the third inverter; one end of the third inverter is connected to the transmission gate, and the other end is connected to the sixth transistor of the fourth calibration subcircuit. The third calibration sub-circuit includes: a first transistor, a second transistor, a target resistor, a target capacitor, a fourth inverter, a fifth inverter and a second detection unit; the second end and the control end of the first transistor are grounded, and the first end of the first transistor is connected to the target resistor; the second end of the second transistor is grounded, the control end of the second transistor is connected to the second output end of the first detection unit, and the first end of the second transistor is connected to the target resistor; one end of the target capacitor is grounded, and the other end is connected to the fourth inverter; one end of the fourth inverter is connected to the target capacitor, and the other end is connected to the fifth inverter; one end of the fifth inverter is connected to the fourth inverter, and the other end is respectively connected to the second detection unit; one end of the second detection unit is connected to the fifth inverter, and the other end is connected to the third transistor and the fifth transistor of the fourth calibration sub-circuit.The fourth calibration subcircuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a sixth inverter, a seventh inverter, an eighth inverter and a ninth inverter; the second end of the third transistor is grounded, the control end of the third transistor is connected to the fifth inverter or the second detection unit, and the first end of the third transistor is connected to the fourth transistor; the second end of the fourth transistor is connected to the third transistor, the control end of the fourth transistor is connected to the second inverter, and the first end of the fourth transistor is connected to the sixth inverter or the ninth inverter; the second end of the fifth transistor is grounded, the control end of the fifth transistor is connected to the fifth inverter or the second detection unit The first end of the fifth transistor is connected to the sixth transistor; the second end of the sixth transistor is connected to the fifth transistor, the control end of the sixth transistor is connected to the third inverter, and the first end of the sixth transistor is connected to the eighth inverter or the seventh inverter; one end of the sixth inverter is connected to the fourth transistor, and the other end is connected to the seventh inverter; one end of the seventh inverter is connected to the sixth inverter, and the other end is the first output end of the fourth calibration sub-circuit; one end of the eighth inverter is connected to the sixth transistor, and the other end is connected to the ninth inverter; one end of the ninth inverter is connected to the eighth inverter, and the other end is the second output end of the fourth calibration sub-circuit.

[0069] In some embodiments, the first transistor is a PMOS; when the first transistor is a PMOS, the control end is a gate, the first end is a source, and the second end is a drain. The second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type metal-oxide-semiconductor field effect transistors NMOS; when the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are NMOS, the control end is a gate, the first end is a source, and the second end is a drain. The first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter, the eighth inverter, and the ninth inverter are composed of two complementary transistors (i.e., an NMOS tube and a PMOS tube).

[0070] Figure 6 The waveform diagram of the calibration control bus is shown in Figure 2 ,like Figure 6 As shown, the first group of waveforms assumes a group of two control signals CTL[n] and CTL[m] with skew; the second group of waveforms is the target pulse signal (OS[K:0]) generated based on CTL[n] and CTL[m]; the third group of waveforms is the low window signal generated based on the target pulse signal; in response to the rising edge of the low window signal, a synchronization pulse signal is generated; when the synchronization pulse signal is at a low level, the first bus state of the control bus is retained; when the synchronization pulse signal is at a high level, the first bus state is synchronized to the second bus state. When the synchronization pulse signal returns to a low level again, this module begins to retain the second bus state.

[0071] In this way, the clock offset between the control bus signals can be eliminated through a simple digital circuit; at the same time, a simple calibration circuit can help reduce the power consumption of calibration and reduce the area occupied by the chip.

[0072] In an embodiment of the present disclosure, synchronizing the first bus state to the second bus state in response to a low window signal includes: outputting a synchronization pulse signal in response to a rising edge of the low window signal; and synchronizing the first bus state to the second bus state in response to detecting the synchronization pulse signal.

[0073] In some embodiments, the synchronization pulse signal is generated when the second detection unit detects a rising edge of the low window signal. The synchronization pulse signal is used to synchronize the first bus state of the control bus to the second bus state.

[0074] In this way, by detecting whether a rising edge occurs in the low window signal to generate a synchronization pulse signal, it helps to reduce false triggering caused by signal fluctuations or noise interference; at the same time, synchronizing the first bus state to the second bus state also enhances the stability of high-speed signal transmission.

[0075] In the embodiment of the present disclosure, the fourth calibration subcircuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a sixth inverter, a seventh inverter, an eighth inverter and a ninth inverter; wherein the second end of the third transistor is grounded, the control end of the third transistor is connected to the fifth inverter or the second detection unit, and the first end of the third transistor is connected to the fourth transistor; the second end of the fourth transistor is connected to the third transistor, the control end of the fourth transistor is connected to the second inverter, and the first end of the fourth transistor is connected to the sixth inverter or the ninth inverter; the second end of the fifth transistor is grounded, the control end of the fifth transistor is connected to the fifth inverter or the ninth inverter The second detection unit is connected, the first end of the fifth transistor is connected to the sixth transistor; the second end of the sixth transistor is connected to the fifth transistor, the control end of the sixth transistor is connected to the third inverter, and the first end of the sixth transistor is connected to the eighth inverter or the seventh inverter; one end of the sixth inverter is connected to the fourth transistor, and the other end is connected to the seventh inverter; one end of the seventh inverter is connected to the sixth inverter, and the other end is the first output end of the fourth calibration sub-circuit; one end of the eighth inverter is connected to the sixth transistor, and the other end is connected to the ninth inverter; one end of the ninth inverter is connected to the eighth inverter, and the other end is the second output end of the fourth calibration sub-circuit.

[0076] In this way, a simple calibration circuit consisting of the first calibration sub-circuit, the second calibration sub-circuit, the third calibration sub-circuit and the fourth calibration sub-circuit helps to reduce power consumption of high-speed signal transmission and reduce the area occupied by the chip.

[0077] Figure 7is a schematic diagram of a calibration process according to an embodiment of the present disclosure, such as Figure 7 As shown, the method comprises at least the following steps:

[0078] S701: Detect whether each control signal in the control bus has a rising edge or a falling edge, and generate a target pulse signal when the control signal in the control bus has a rising edge or a falling edge;

[0079] S702: Generate a group of differential delay control buses based on the control bus; wherein the differential delay control bus is used to retain a first bus state of the control bus; the first bus state is a bus state in which the clock offset between the control signals in the control bus is not eliminated;

[0080] S703: Generate a low window signal based on the target pulse signal; wherein the low window signal is a control signal that is high in a first time period and low in only one second time period; the first time period is greater than the second time period;

[0081] S704: synchronizing the first bus state to a second bus state in response to the low window signal; wherein the second bus state is a bus state in which a clock offset between control signals in the control bus signal has been eliminated;

[0082] S705: Send the control signal in the control bus in the second bus state to the target circuit.

[0083] In some embodiments, the target circuit is a circuit that performs corresponding operations according to the received control signal. For example, if the control bus sends a command of a read signal, the target circuit (such as a memory module or an I / O device) will read data from the specified address according to the command and send the data back to the processor through the data bus.

[0084] Thus, compared with the method of calibration through clock driving, the calibration circuit can avoid the impact on sensitive circuits, which helps to improve the stability and reliability of high-speed signal transmission.

[0085] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A calibration circuit, characterized in that: Used to eliminate clock offsets between control signals in a control bus, the calibration circuit comprises: a first calibration subcircuit, a second calibration subcircuit, a third calibration subcircuit and a fourth calibration subcircuit; wherein the input end of the first calibration subcircuit is connected to the control bus, and the output end of the first calibration subcircuit is connected to the second calibration subcircuit and the third calibration subcircuit; the input end of the second calibration subcircuit is connected to the control bus or the first calibration subcircuit, and the output end of the second calibration subcircuit is connected to the fourth calibration subcircuit; the output end of the third calibration subcircuit is connected to the fourth calibration subcircuit; and the output end of the fourth calibration subcircuit is connected to a target circuit; The first calibration subcircuit is used to detect whether each control signal in the control bus has a rising edge or a falling edge; when the control signal in the control bus has a rising edge or a falling edge, generate a target pulse signal; The second calibration subcircuit is used to generate a set of differential delay control buses based on the control bus; wherein the differential delay control bus is used to retain a first bus state of the control bus; the first bus state is a bus state in which the clock offset between the control signals in the control bus is not eliminated; The third calibration subcircuit is used to generate a low window signal based on the target pulse signal; wherein the low window signal is a control signal that is high in a first time period and low in only one second time period; the first time period is greater than the second time period; The fourth calibration subcircuit is used to synchronize the first bus state to a second bus state in response to the low window signal; wherein the second bus state is a bus state in which a clock offset between control signals in a control bus signal has been eliminated; The fourth calibration sub-circuit is further configured to send a control signal in the control bus in the second bus state to the target circuit.

2. The calibration circuit according to claim 1, characterized in that: The generating a set of differential delay control buses based on the control bus comprises: Adding a delay to each of the control signals in the control bus to generate a set of delayed control buses; A group of the differential delay control buses is generated based on a group of the delay control buses.

3. The calibration circuit according to claim 1, characterized in that: The first calibration subcircuit comprises: a first detection unit, configured to detect whether a rising edge or a falling edge occurs on each of the control signals in the control bus; The input end of the first detection unit is connected to the control bus, the first output end of the first detection unit is connected to the first inverter and the transmission gate of the second calibration subcircuit, and the second output end of the first calibration subcircuit is connected to the first transistor of the third calibration subcircuit.

4. The calibration circuit according to claim 3, characterized in that: Synchronizing the first bus state to a second bus state in response to the low window signal, comprising: In response to the end of the low window signal, the first bus state is synchronized to the second bus state; wherein the length of the low window signal is greater than the length of each control signal jump completion of the control bus.

5. The calibration circuit according to claim 3, characterized in that: The second calibration sub-circuit includes: a transmission gate, the first inverter, a second inverter, and a third inverter; wherein, one end of the first inverter is connected to the input end or the first output end of the first calibration sub-circuit, and the other end is connected to the second inverter; one end of the second inverter is connected to the first inverter, and the other end is connected to the fourth transistor of the fourth calibration sub-circuit; one end of the transmission gate is connected to the first output end of the first detection unit, and the other end is connected to the third inverter; one end of the third inverter is connected to the transmission gate, and the other end is connected to the sixth transistor of the fourth calibration sub-circuit.

6. The calibration circuit according to claim 5, characterized in that: The third calibration subcircuit includes: a first transistor, a second transistor, a target resistor, a target capacitor, a fourth inverter and a fifth inverter; wherein, the second end and the control end of the first transistor are grounded, and the first end of the first transistor is connected to the target resistor; the second end of the second transistor is grounded, the control end of the second transistor is connected to the second output end of the first detection unit, and the first end of the second transistor is connected to the target resistor; one end of the target capacitor is grounded, and the other end is connected to the fourth inverter; one end of the fourth inverter is connected to the target capacitor, and the other end is connected to the fifth inverter; one end of the fifth inverter is connected to the fourth inverter, and the other end is connected to the third transistor and the fifth transistor respectively.

7. The calibration circuit according to claim 6, characterized in that: The third calibration sub-circuit also includes: a second detection unit, used to detect whether a rising edge occurs in the low window signal; if a rising edge occurs in the low window signal, a synchronization pulse signal is output; one end of the second detection unit is connected to the fifth inverter, and the other end is connected to the fifth transistor of the fourth calibration sub-circuit.

8. The calibration circuit according to claim 7, characterized in that: The step of synchronizing the first bus state to a second bus state in response to the low window signal comprises: In response to a rising edge of the low window signal, outputting the synchronization pulse signal; In response to detecting the synchronization pulse signal, the first bus state is synchronized to a second bus state.

9. The calibration circuit according to claim 7, characterized in that: The fourth calibration subcircuit includes: the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the sixth inverter, the seventh inverter, the eighth inverter and the ninth inverter; wherein the second end of the third transistor is grounded, the control end of the third transistor is connected to the fifth inverter or the second detection unit, and the first end of the third transistor is connected to the fourth transistor; the second end of the fourth transistor is connected to the third transistor, the control end of the fourth transistor is connected to the second inverter, and the first end of the fourth transistor is connected to the sixth inverter or the ninth inverter; the second end of the fifth transistor is grounded, the control end of the fifth transistor is connected to the fifth inverter or the second detection unit, and the first end of the fourth transistor is connected to the sixth inverter or the ninth inverter; the second end of the fifth transistor is grounded, the control end of the fifth transistor is connected to the fifth inverter or the second detection unit, and the first end of the fourth transistor is connected to the sixth inverter or the ninth inverter. The first end of the fifth transistor is connected to the sixth transistor; the second end of the sixth transistor is connected to the fifth transistor, the control end of the sixth transistor is connected to the third inverter, and the first end of the sixth transistor is connected to the eighth inverter or the seventh inverter; one end of the sixth inverter is connected to the fourth transistor, and the other end is connected to the seventh inverter; one end of the seventh inverter is connected to the sixth inverter, and the other end is the first output end of the fourth calibration sub-circuit; one end of the eighth inverter is connected to the sixth transistor, and the other end is connected to the ninth inverter; one end of the ninth inverter is connected to the eighth inverter, and the other end is the second output end of the fourth calibration sub-circuit.

10. A calibration method, characterized in that: For calibrating a clock offset of a control bus, the method comprises: Detecting whether each control signal in the control bus has a rising edge or a falling edge, and generating a target pulse signal when the control signal in the control bus has a rising edge or a falling edge; A set of differential delay control buses is generated based on the control bus; wherein the differential delay control bus is used to retain a first bus state of the control bus; the first bus state is a bus state in which the clock offset between the control signals in the control bus is not eliminated; Generate a low window signal based on the target pulse signal; wherein the low window signal is a control signal that is high in a first time period and low in only a second time period; the first time period is greater than the second time period; Synchronizing the first bus state to a second bus state in response to the low window signal; wherein the second bus state is a bus state in which a clock offset between control signals in a control bus signal has been eliminated; The control signal in the control bus in the second bus state is sent to the target circuit.

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