Memory system, storage device, operating method, storage medium, and program product

Abstract

The embodiment of the invention provides a memory system, a storage device, an operation method, a computer readable storage medium and a computer program product, and relates to the technical field of semiconductors. The method comprises the steps that an operation command from a storage controller is received, and the operation command comprises a first physical address; based on the second physical address, operation corresponding to the operation command is executed, the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address. According to the method, the system performance is improved, and the occupied system space is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a memory system, a storage device, an operating method, a computer-readable storage medium, and a computer program product. Background Art

[0002] In the memory system, NAND memory is a non-volatile memory with the advantages of low cost, high capacity and fast rewrite speed. During the use of NAND memory, bad blocks (BB) may be generated. In order to ensure the normal use of NAND memory, bad block management (BBM) is required. In the related art, the bad block information is managed by the firmware (FW) of the storage controller. Summary of the invention

[0003] Embodiments of the present disclosure provide a memory system, a storage device, an operating method, a computer-readable storage medium, and a computer program product.

[0004] According to one aspect of an embodiment of the present disclosure, a memory system is provided, comprising: a storage controller configured to send an operation command; and a storage device coupled to the storage controller, the storage device comprising a plurality of storage blocks and a peripheral circuit; the storage device stores a bad block table, and the peripheral circuit is configured to: receive the operation command from the storage controller, wherein the operation command comprises a first physical address; and perform an operation corresponding to the operation command based on a second physical address, wherein the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address.

[0005] In one embodiment, the bad block table includes the block address of the bad block; the peripheral circuit is also configured to: determine the first block address of the first physical address; when the first block address of the first physical address exists in the bad block table, determine that the block corresponding to the first physical address is the bad block.

[0006] In one embodiment, the bad block table includes a bad block remapping table, which includes the block address of the bad block and the block address of the replacement block corresponding to the bad block; the peripheral circuit is also configured to: obtain the block address of the replacement block corresponding to the first block address based on the bad block remapping table; and determine the second physical address based on the block address of the replacement block.

[0007] In one embodiment, the peripheral circuit is further configured to: determine a first available block according to a set order; and determine the second physical address based on the first available block.

[0008] In one embodiment, the peripheral circuit is further configured to: receive a set feature command from the storage controller to enable a bad block management function of the storage device.

[0009] In one embodiment, the operation command includes a multi-plane read command (read multi-plane) or a multi-plane program command (page program multi-plane), and the first physical address includes multiple first block addresses, and the multiple first block addresses are the same except for the plane bits.

[0010] In one embodiment, the operation command includes a multi-plane block erase command (multi-plane Block Erase), the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for plane bits.

[0011] In one embodiment, the peripheral circuit is further configured to: update the bad block table when a new bad block is found.

[0012] In one embodiment, the storage controller is configured to: determine whether to enable the bad block management function of the storage device through a Get Feature command; if the bad block management function of the storage device is not enabled, the storage controller performs bad block management on the first physical address in the operation command; if the bad block management function of the storage device is enabled, the storage device performs bad block management of the first physical address in the operation command.

[0013] According to another aspect of the present disclosure, a storage device is provided, comprising: a storage cell array; and a peripheral circuit coupled to the storage cell array; the storage device stores a bad block table, and the peripheral circuit is configured to: receive an operation command from a storage controller, wherein the operation command comprises a first physical address; based on a second physical address, perform an operation corresponding to the operation command, wherein the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address.

[0014] In one embodiment, the bad block table includes the block address of the bad block; the peripheral circuit is also configured to: determine the first block address of the first physical address; when the first block address of the first physical address exists in the bad block table, determine that the block corresponding to the first physical address is the bad block.

[0015] In one embodiment, the bad block table includes a bad block remapping table, which includes the block address of the bad block and the block address of the replacement block corresponding to the bad block; the peripheral circuit is also configured to: obtain the block address of the replacement block corresponding to the first block address based on the bad block remapping table; and determine the second physical address based on the block address of the replacement block.

[0016] In one embodiment, the peripheral circuit is further configured to: determine a first available block according to a set order; and determine the second physical address based on the first available block.

[0017] In one embodiment, the peripheral circuit is further configured to: receive a set feature command from the storage controller to enable a bad block management function of the storage device.

[0018] In one embodiment, the operation command includes a multi-plane read command or a multi-plane program command, and the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

[0019] In one embodiment, the operation command includes a multi-plane block erase command, the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

[0020] In one embodiment, the peripheral circuit is further configured to: update the bad block table when a new bad block is found.

[0021] According to another aspect of the present disclosure, there is provided a method for operating a memory system, which is applied to a storage device, wherein the storage device stores a bad block table, the method comprising: receiving an operation command from a storage controller, wherein the operation command comprises a first physical address; based on a second physical address, executing an operation corresponding to the operation command, wherein a block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address.

[0022] In one embodiment, the bad block table includes the block address of the bad block; the method also includes: determining the first block address of the first physical address; when the first block address of the first physical address exists in the bad block table, determining that the block corresponding to the first physical address is the bad block.

[0023] In one embodiment, the bad block table includes a bad block remapping table, and the bad block remapping table also includes the block address of the bad block and the block address of the replacement block corresponding to the bad block; the method also includes: based on the bad block remapping table, obtaining the block address of the replacement block corresponding to the first block address; determining the second physical address based on the block address of the replacement block.

[0024] In one embodiment, the method further includes: determining a first available block according to a set order; and determining the second physical address based on the first available block.

[0025] In one embodiment, the method further includes: receiving a set feature command from the storage controller to enable a bad block management function of the storage device.

[0026] In one embodiment, the operation command includes a multi-plane read command or a multi-plane program command, and the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

[0027] In one embodiment, the operation command includes a multi-plane block erase command, the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

[0028] In one embodiment, the method further comprises: when a new bad block is found, updating the bad block table.

[0029] According to another aspect of the present disclosure, a computer-readable storage medium is provided. When control instructions in the computer-readable storage medium are executed by a controller processor, the controller processor is enabled to execute the operation method as described above.

[0030] According to another aspect of the present disclosure, a computer program product is provided, including a computer program / instruction, wherein the computer program / instruction implements the method described above when executed by a processor.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0033] Figure 1 A block diagram showing an exemplary system with a storage device according to an embodiment of the present disclosure;

[0034] Figure 2A A block diagram of a memory system is exemplarily shown;

[0035] Figure 2B A block diagram of another memory system is shown by way of example;

[0036] Figure 2C A block diagram of yet another memory system is exemplarily shown;

[0037] Figure 3 A schematic circuit diagram showing a storage device including a peripheral circuit provided by an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram showing a peripheral circuit provided by an embodiment of the present disclosure;

[0039] Figure 5A A flowchart showing a method for operating a memory system in one embodiment of the present disclosure is shown;

[0040] Figure 5B A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0041] Figure 6 A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0042] Fig. 7A A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0043] Figure 7B A schematic diagram showing a column address in one embodiment of the present disclosure;

[0044] Figure 8 Schematic diagrams showing different memory system operation methods;

[0045] Fig.9A A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0046] Fig. 9B A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0047] Fig. 9C A schematic diagram showing bad block mapping in one embodiment of the present disclosure is shown;

[0048] Fig.10 A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0049] Fig.11 A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0050] Fig.12 A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0051] Fig.13A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown;

[0052] Fig.14 A sequence diagram showing multi-plane programming commands in one embodiment of the present disclosure;

[0053] Fig.15 A sequence diagram showing a multi-plane block erase command in one embodiment of the present disclosure; and

[0054] Fig.16 A sequence diagram of a multi-plane read command in one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0056] The features, structures or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0057] The accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some block diagrams shown in the accompanying drawings do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in at least one hardware module or integrated circuit, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0058] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and steps, nor must they be executed in the order described. For example, some steps can be decomposed, and some steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0059] In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of at least one element / component / etc.; the terms "comprising", "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0060] Figure 1 A schematic diagram showing an exemplary system having a storage device according to an embodiment of the present disclosure is shown. Figure 1 As shown, the system 100 may be a mobile phone, a desktop computer, a portable computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102 having one or more storage devices 104 and a storage controller 106 .

[0061] The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be coupled to the storage controller 106 and configured to send data to the storage device 104 or receive data from the storage device 104 through the storage controller 106. For example, the host 108 may send program data in a programming operation or receive read data in a read operation. The host 108 is configured to receive instructions and commands from the storage controller 106 of the memory system 102 and send instructions and commands to the storage controller 106 of the memory system 102, and perform or implement a plurality of functions and operations provided in the present disclosure, which will be described below.

[0062] The storage device 104 may be any memory disclosed in the present disclosure, for example, a NAND flash memory including a page buffer having a plurality of sections. Note that for illustrative purposes, NAND flash memory is only one example of a memory. The storage device 104 may include any suitable non-volatile memory, for example, NOR flash memory, ferroelectric random access memory (FeRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), spin-transfer torque random access memory (STT-RAM), or resistive random access memory (RRAM). In some implementations, the storage device 104 includes a three-dimensional (3D) NAND flash memory.

[0063] The storage controller 106 may be implemented by: a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic device (Programmable Logic Device, PLD), a state machine, gating logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0064] According to some implementations, the storage controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The storage controller 106 can manage data stored in the storage device 104 and communicate with the host 108. In some implementations, the storage controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, the storage controller 106 is designed to operate an SSD in a high duty cycle environment or as an embedded MultiMedia Card (eMMC) used as a data storage device for mobile devices (e.g., smart phones, tablet computers, laptop computers, etc.) and an enterprise storage array. The storage controller 106 can be configured to control the operation of the storage device 104, such as read, erase, and program operations, by providing instructions such as read instructions to the storage device 104. For example, the storage controller 106 may be configured to provide read instructions to the peripheral circuits of the storage device 104 to control the read operation. The storage controller 106 may also be configured to manage various functions regarding data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection (GC), logical to physical address conversion, wear leveling, etc. In some implementations, the storage controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the storage device 104. The storage controller 106 may also perform any other suitable functions, such as formatting the storage device 104.

[0065] The storage controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the storage controller 106 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC (Multi Media Card) protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-E (Peripheral Component Interconnect Express) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, and the like.

[0066] The storage controller 106 and the one or more storage devices 104 can be integrated into various types of memories, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0067] Figure 2A A block diagram of a memory system is shown as an example. Figure 2A As shown, the storage controller 106 and the storage device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA (Personal Computer Memory Card International Association) card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC), an SD card, a UFS, etc. The memory card 202 may also include a memory card that connects the memory card to a host (e.g., Figure 1 A memory card connector 204 is coupled to the host 108 in the memory card connector.

[0068] Figure 2B FIG. 1 is a block diagram of another memory system. Figure 2BAs shown, the storage controller 106 and the plurality of storage devices 104 may be integrated into an SSD (solid state drive) 206. The SSD 206 may also include a processor that connects the SSD 206 to a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0069] Figure 2C FIG. 1 is a schematic diagram showing an exemplary storage controller having a memory system in an embodiment of the present disclosure. Figure 2C As shown, the storage controller 106 is coupled to the host 108 and one or more storage devices 104, respectively, and is used to control the host 108 to send data to the storage device 104 or read data from the storage device 104 and return it to the host 108. The storage controller 106 at least includes: a controller processor 210, a host interface controller 211, a flash memory controller 212, a controller memory 213, a buffer memory 214 and an ECC (Error Correction Code) module 215.

[0070] The controller processor 210 is used to execute the control logic and algorithm of the storage controller and is responsible for processing functions such as address mapping, garbage collection, wear leveling, etc. The controller processor 210 can be implemented by an embedded processor or FPGA.

[0071] The host interface controller 211 is coupled to the host 108 and the controller processor 210, respectively, and is a communication interface component between the host and the storage controller, responsible for data transmission between the host and the storage controller, including reading and writing data, and receiving and sending commands. It generally supports various interfaces (such as SATA (Serial Advanced Technology Attachment), PCIe) and protocols (such as AHCI (Advanced Host Controller Interface), NVMe (Non-Volatile Memory Express)), and provides data transmission functions.

[0072] The flash memory controller 212 is coupled to the storage device 104 and the controller processor 210 respectively, and is a communication interface component between the storage device and the storage controller.

[0073] The controller memory 213 is coupled to the controller processor 210 and is a storage area for storing instructions and data. The controller memory 213 can be a storage medium such as NOR flash, NAND flash or RAM.

[0074] The buffer memory 214 is coupled to the controller processor 210 and is a component for temporarily storing data and can also be used to cache instructions and data. It can use high-speed storage devices such as DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory).

[0075] The ECC module 215 is used for error detection and correction of data read from the storage device. The ECC check data can be stored in the reserved space of the storage device 104 for data verification.

[0076] Figure 3 A schematic circuit diagram of a memory including a peripheral circuit provided by an embodiment of the present disclosure is shown. The storage device 300 may be Figure 1 3. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein the memory cells 306 are provided in the form of an array of memory strings 308 of the NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0077] In some embodiments, the peripheral circuit 302 is configured to execute the operating method provided by the embodiment of the present disclosure. It is understood that the peripheral circuit 302 can be configured to execute the operating method provided by the embodiment of the present disclosure according to the instruction received from the storage controller 106.

[0078] In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0079] In some embodiments, each storage cell 306 can store 1 bit of data or 2 bits of data or more bits of data, that is, it can be a single-level cell (SLC) type, a multi-level cell (MLC) type, a triple-level cell (TLC) type, a quad-level cell (QLC) type, or a higher level type. The p (p is a positive integer) layer cell can have 2 pstates (for example, one state corresponds to one threshold voltage distribution interval), so it can store p bits of data. Among them, an SLC type storage cell can have 2 states, so it can store 1 bit of data; an MLC type storage cell can have 4 states, so it can store 2 bits of data; a TLC type storage cell can have 8 states, so it can store 3 bits of data; a QLC type storage cell can have 16 states, so it can store 4 bits of data, and so on. p states, including an erase state and 2 p -1 programming state. The p-layer cell type NAND flash memory can program and / or read data page by page. During the programming operation, the p-layer cell type NAND flash memory cell is programmed to have 2 p states, a memory cell is programmed to 2 p When a state is in the target state among the states, it is said to be in the target programming state. Figure 3 As shown, each memory string 308 may include a source select gate (SSG) 310 at its source terminal and a drain select gate (DSG) 312 at its drain terminal. SSG 310 and DSG 312 may be configured to activate the selected memory string 308 during read and program operations.

[0080] In some embodiments, the sources of the memory strings 308 in the same block 304 are coupled through the same source line (Source Line, SL) 314 (e.g., a common SL). For example, all memory strings 308 in the same block 304 have an array common source (Array Common Source, ACS). Figure 3 As shown, the memory string 308 can be organized into a plurality of blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time.

[0081] In some embodiments, the transistors of the DSG 312 of each memory string 308 are coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). Each memory string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0082] like Figure 3 As shown, the memory cells 306 of the memory string 308 may be coupled via a word line (WL) 318, which selects which row of memory cells 306 are affected by read and program operations. The peripheral circuit 302 may be coupled to the memory cell array 301 via a bit line 316, a word line 318, a source line 314, an SSG line 315, and a DSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each memory cell 306 that is the target of the operation and sensing a voltage signal and / or a current signal from each memory cell 306 that is the target of the operation via the bit line 316, the word line 318, the source line 314, the SSG line 315, and the DSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology.

[0083] Figure 4 Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the peripheral circuit 302 may include a page buffer / sense amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, an input / output (I / O) circuit 416, and a data bus 418. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 4 Additional peripheral circuits not shown.

[0084] In some embodiments, the page buffer / sense amplifier 404 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 412. For example, the page buffer / sense amplifier 404 can store a page of programming data (write data) to be programmed into the memory cell array 301. For another example, the page buffer / sense amplifier 404 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / BL driver 406 can be configured to be controlled by the control logic unit 412, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0085] The row decoder / WL driver 408 may be configured to be controlled by the control logic unit 412, and select / deselect the block 304 of the memory cell array 301 and select / deselect the word line 318 of the block 304. The row decoder / WL driver 408 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 410. In some embodiments, the row decoder / WL driver 408 may also select / deselect and drive the SSG line 314 and the DSG line 313. The voltage generator 410 may be configured to be controlled by the control logic unit 412, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, a source line voltage, etc. to be supplied to the memory cell array 301.

[0086] The control logic unit 412 may be coupled to each portion of the peripheral circuit 302 and configured to control the operation of each portion. The register 414 may be coupled to the control logic unit 412 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The input / output circuit 416 may be coupled to the control logic unit 412 and act as a control buffer to buffer the input / output information from the host ( Figure 4 The input / output circuit 416 may also be coupled to the column decoder / bit line driver 406 via the data bus 418 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0087] Figure 5A A flowchart showing a method for operating a memory system in one embodiment of the present disclosure is shown.

[0088] like Figure 5A As shown, S501, the storage controller receives an operation command request, parses the operation command request, converts the logical address in the operation command request into a first physical address, and generates an operation command, wherein the operation command includes the first physical address.

[0089] S503, the storage controller sends an operation command to the storage device, wherein the operation command includes a first physical address. The operation command may include a read command, a program command, an erase command, and the like.

[0090] In the above embodiment, the operation command sent by the storage controller to the storage device includes a first physical address, which is a physical address converted by the storage controller from a logical address in the operation command request, and the corresponding block may be a bad block. In the memory system, the operation command sent by the storage controller to the storage device can be detected, and the physical address included in the operation command can be obtained by parsing; in addition, the bad block table in the memory system can be obtained by technical means, and by comparing the physical address with the bad block address in the bad block table, it can be detected whether the physical address corresponds to a bad block.

[0091] In one embodiment of the present disclosure, the storage controller 106 does not perform bad block processing, so the blocks corresponding to the physical addresses contained in the operation command sent by the storage controller 106 include normal blocks and may also include bad blocks. Through the above technical solution, the firmware of the storage controller 106 can save the extra operations caused by bad block management when running, and the storage controller 106 omits a large number of operations related to bad blocks, thereby improving system performance, reducing the complexity of the firmware of the storage controller, and saving the storage space of the storage controller 106 occupied by the bad block information.

[0092] Figure 5B A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown.

[0093] like Figure 5B As shown, S502, the storage device receives an operation command from a storage controller, wherein the operation command includes a first physical address.

[0094] S504, the storage device performs the operation corresponding to the operation command based on the second physical address, wherein the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address. The block corresponding to the second physical address is a normal block, not a bad block. In one embodiment, the storage device determines that the block corresponding to the first physical address is a bad block by searching a bad block table, and determines the second physical address corresponding to the replacement block.

[0095] In the above embodiment, after receiving the operation command, the storage device performs bad block processing, and does not execute the operation command on the bad block corresponding to the first physical address, but executes the operation command on the normal block based on the second physical address. The bad block information is managed in the storage device, so that the firmware of the storage controller can save the operation caused by managing the bad block when running. The storage controller can ignore the bad block table and send the operation command to the storage device. After receiving the operation command, the storage device determines the correct block position where the operation command is executed. The storage controller omits a large number of operations related to bad block management, which can reduce the storage space occupied by the bad block information in the storage controller, reduce the complexity of the firmware of the storage controller, and improve the system performance.

[0096] Figure 6 A flowchart showing a method for operating a memory system in another embodiment of the present disclosure is shown.

[0097] like Figure 6 As shown, S602, the storage controller performs command decoding (CommandDecoder) processing on the received operation command request, converts the logical address in the command request into a physical address, generates an operation command, and sends the generated operation command to the storage device. In one embodiment, the storage controller receives an operation command request from a host.

[0098] S604: The storage device receives an operation command including a first physical address, and searches for the first physical address in a bad block table.

[0099] S606, determine whether the first physical address belongs to a bad block, if yes, proceed to step S608, otherwise, proceed to step S612.

[0100] S608: The storage device determines a replacement block and a second physical address corresponding to the first physical address.

[0101] S610: The storage device executes an operation command based on the second physical address.

[0102] S612: The storage device executes the operation command based on the first physical address.

[0103] Fig. 7A A flowchart of a memory system operation method in another embodiment of the present disclosure is shown. In this embodiment, the storage device stores a bad block table, which includes block addresses of bad blocks. The method is executed by the storage device, for example, by a peripheral circuit of the storage device.

[0104] S702: The storage device receives an operation command, where the operation command includes a first physical address.

[0105] S704: The storage device determines a first block address of the first physical address. Figure 7BFIG. 2 is a schematic diagram showing a column address in one embodiment of the present disclosure. Figure 7B As shown, the physical address in the operation command includes three parts: LUN number part 71, block number part 72 and page address part 73. Among them, the lowest bit of the block number part 72 is the plane address bit 721. The first block address consists of the LUN number part 71 and the block number part 72.

[0106] S706: When the first block address of the first physical address exists in the bad block table, determine that the block corresponding to the first physical address is a bad block.

[0107] In the above embodiment, the storage device searches the bad block table according to the first block address of the first physical address, and there is no need to send the bad block table to the storage controller for processing, which reduces operation instructions, simplifies the firmware logic of the storage controller, improves system performance, saves system space, reduces errors (bugs), and improves product competitiveness.

[0108] Figure 8 Schematic diagram showing different memory system operation methods. Figure 8 As shown in A on the left side of the figure, in the related art, after receiving the operation request, the storage controller remaps the bad block based on the bad block table, converts the physical address of the corresponding bad block into the physical address of the corresponding normal block, and then sends the operation command to the storage device, and the storage device does not need to perform bad block processing. In one embodiment of the present disclosure, Figure 8 As shown in B, after receiving the operation command request, the storage controller converts the logical address into a physical address without remapping the bad block. The operation command containing the physical address is sent to the storage device, which remaps the bad block based on the bad block table, converts the physical address of the corresponding bad block into the physical address of the corresponding normal block, and then executes the operation command.

[0109] When the memory system reads and writes data, the target block may have been mapped, so it needs to look up the bad block table to obtain the correct block location before issuing a command. Read and write performance is an important performance indicator of the product. The operation of bad blocks is on the critical path of the system and brings additional logical judgments and path branches that affect performance. Using the technical solution of the present disclosure, the firmware of the storage controller does not need to judge whether block mapping is required when issuing commands, and directly issues commands. The storage device side searches the bad block table by itself to operate on the correct block. In the related art, bad blocks are managed by the firmware of the storage controller. When bad blocks are encountered in the read and write path, additional operations will occur, causing performance jitter and instability. The management of this information will also increase the complexity of the firmware and increase the use of system space. In the embodiment of the present disclosure, the management of bad blocks is implemented inside the storage device, and the use of this information is transparent to the upper-level logic, reducing the branch path of the firmware of the storage controller, improving system performance, and reducing system space occupancy.

[0110] Bad block management strategies include Skip strategy and Replace strategy. Figure 9A-9C Provide explanation.

[0111] Fig.9A A flowchart of a memory system operation method in another embodiment of the present disclosure is shown. In this embodiment, a storage device stores a bad block table, which includes the block address of the bad block. When a bad block is found, a skip strategy is used to determine a new block.

[0112] like Fig.9A As shown, S902, the storage controller sends a set feature command to the storage device, where the set feature command includes a first parameter, and the first parameter indicates to enable the bad block management function of the storage device.

[0113] S904: The storage device receives the set feature command, where the set feature command includes a first parameter and enables a bad block management function of the storage device.

[0114] S906: The storage device receives an operation command from the storage controller, where the operation command includes the first physical address.

[0115] S908: The storage device determines a first block address of the first physical address, and when the first block address exists in the bad block table, determines that the block corresponding to the first physical address is a bad block.

[0116] S910, the storage device determines the first available block according to the set order. In one embodiment, the storage device determines the available blocks according to the order of different dies. For example, there are 4 dies, die 0, die 1, die 2, and die 3. When writing block A on die0 and continuing to write block B on die 1, it is found that block B is a bad block, then the bad block skipping strategy is adopted to skip block B and write to block C on die2.

[0117] S912: The storage device determines a second physical address based on the first available block.

[0118] S914: The storage device executes the operation command based on the second physical address.

[0119] In the above embodiment, the storage device determines the bad block based on the bad block table, and then determines the available block in a certain order, thereby determining the second physical address, which realizes simple logic and high space utilization.

[0120] Fig. 9BA flowchart of a memory system operation method in another embodiment of the present disclosure is shown. In this embodiment, the bad block table includes a bad block remapping table, and the storage device stores the bad block remapping table. The bad block remapping table includes a block address of the bad block and a block address of a replacement block corresponding to the bad block. When a bad block is found, a replacement strategy is used to determine a new block.

[0121] like Fig. 9B As shown, S901, the storage controller sends a set feature command to the storage device, including a first parameter, where the first parameter indicates to enable the bad block management function of the storage device.

[0122] S903: The storage device receives the setting feature command and enables the bad block management function of the storage device.

[0123] S905: The storage device receives an operation command from a storage controller, where the operation command includes a first physical address, and determines a first block address of the first physical address.

[0124] S907: When the first block address exists in the bad block remapping table, the storage device determines that the block corresponding to the first physical address is a bad block.

[0125] S909: The storage device obtains a block address of a replacement block corresponding to the first block address based on the bad block remapping table.

[0126] S911: The storage device determines a second physical address based on the block address of the replacement block.

[0127] S913: The storage device executes the operation command based on the second physical address.

[0128] In the above embodiment, the storage device determines the bad block based on the bad block remapping table, and determines the replacement block of the bad block, thereby determining the second physical address, and the execution efficiency is high.

[0129] Combine the following Fig. 9C The implementation of a replacement block in one embodiment of the present disclosure is described.

[0130] Fig. 9C FIG. 2 is a schematic diagram showing bad block mapping in one embodiment of the present disclosure. Fig. 9C As shown, the storage device includes multiple dies, such as die 0 and die 1; each die includes multiple planes, such as plane 0, plane 1 and plane 2; each plane includes multiple storage blocks, and the multiple storage blocks are divided into different areas: storage area and hidden area. The storage area includes block 1 to block n, and the hidden area includes block n+1, block n+2, ... When a bad block appears in the storage area, such as Fig. 9C If block 2 in face 1 is shown in FIG, a replacement block is determined from the hidden area, for example, block n+1 of face 1.

[0131] Fig.10 A flowchart showing a method for operating a memory system in yet another embodiment of the present disclosure is shown.

[0132] like Fig.10 As shown, S1002, the storage controller determines whether the bad block management function of the storage device is enabled by obtaining a characteristic command. For example, the storage controller can set a flag bit for the information obtained by obtaining the characteristic command.

[0133] S1004: The storage controller converts the received operation command request from a logical address to a physical address to generate an operation command.

[0134] S1006, the storage controller determines whether the bad block management function of the storage device is enabled. If yes, proceed to S1012, otherwise proceed to step S1008. For example, the bad block management function is enabled by setting a flag bit.

[0135] S1008: The storage controller performs bad block processing of the operation command.

[0136] S1010: The storage controller sends an operation command to the storage device. The operation command does not include a physical address corresponding to the bad block.

[0137] S1012: The storage controller sends an operation command to the storage device, wherein the operation command includes a physical address corresponding to the bad block.

[0138] S1014: The storage device performs bad block processing on the operation command.

[0139] S1016: The storage device executes the operation command.

[0140] In the above embodiment, whether the bad block management function of the storage device is enabled is determined by obtaining a feature command. If the storage device supports and enables the bad block management function, the bad block management is performed by the storage device. Otherwise, the bad block management is performed by a storage controller, thereby increasing the compatibility and application scope of the technical solution.

[0141] Fig.11 A flowchart showing a method for operating a memory system in yet another embodiment of the present disclosure is shown.

[0142] like Fig.11 As shown, S1102, the storage controller receives a write request, where the write request includes a first logical address.

[0143] S1104, the storage controller converts the logical address of the write request into a physical address, obtains a first physical address corresponding to the first logical address, and generates a programming command.

[0144] S1106, the storage controller sends a program command to the storage device, where the program command includes a first physical address.

[0145] S1108, the storage device performs bad block processing on the received programming command, determines that the first physical address is located in the bad block, and replaces the first physical address with a second physical address located in a normal block.

[0146] S1110 , the storage device executes a program command based on the second physical address.

[0147] S1112: The storage controller receives a read request, where the read request includes a first logical address.

[0148] S1114, the storage controller converts the logical address of the read request into a physical address, obtains a first physical address corresponding to the first logical address, and generates a read command.

[0149] S1116: The storage controller sends a read command to the storage device, where the read command includes the first physical address.

[0150] S1118, the storage device performs bad block processing on the received read command, determines that the first physical address is located in the bad block, replaces the first physical address with a second physical address, and the second physical address is located in a normal block.

[0151] S1120: The storage device executes a read command based on the second physical address and returns the read data to the storage controller.

[0152] In the above embodiments, the writing and reading process based on the technical solution disclosed in the present invention is described. In the whole process, the storage controller does not need to perform bad block management, nor does it need to load the bad block table from the storage device to the cache of the storage controller. All of this is done inside the NAND, which simplifies the FW logic, saves system space, reduces the probability of errors, and improves product competitiveness.

[0153] Fig.12 A flowchart showing a method for operating a memory system in yet another embodiment of the present disclosure is shown.

[0154] like Fig.12 As shown, S1202, the storage device receives an operation command, and the operation command includes a first physical address.

[0155] S1204: The storage device determines a first block address of the first physical address.

[0156] S1206: The storage device compares the first block address with the block address in the bad block table.

[0157] S1208: If the same block address is matched, determine that the block corresponding to the first physical address is a bad block.

[0158] S1210: The storage device determines a replacement block, and determines a second physical address based on the replacement block.

[0159] S1212: The storage device executes the operation command based on the second physical address.

[0160] The sources of bad blocks of storage devices include bad blocks existing at the factory and bad blocks that become bad during use. The reasons for bad blocks include erasure, write wear, etc. The detected bad blocks will be marked. For example, a non-0xFF value is written to the first byte of the first page and the last page of the block and the first byte of the reserved area.

[0161] Fig.13 A flowchart of a memory system operation method in another embodiment of the present disclosure is shown. In this embodiment, the processing of bad blocks and the maintenance of a bad block table are described.

[0162] like Fig.13 As shown, S1302, the storage device executes the operation command.

[0163] S1304, the storage device receives data indicating that the operation command failed, for example, reading UECC (Uncorrectable Error Correction Code), erasing failure, writing failure, etc.

[0164] S1306: The storage device tests the block corresponding to the operation command.

[0165] S1308: The storage device determines that the block is a bad block.

[0166] S1310: The storage device updates a bad block table and adds the newly determined bad block to the bad block table.

[0167] In the above embodiment, when the storage device is executing an operation command, it receives failed data, determines the bad block through testing, and updates the bad block table, so that no instruction from the storage controller is required, the efficiency is high, and the system performance is improved.

[0168] In one embodiment, the operation command sent by the storage controller includes a multi-plane program command, and the first physical address in the multi-plane program command includes multiple first block addresses, and the multiple first block addresses are the same except for the plane bits. Fig.14 FIG. 2 shows a sequence diagram of multi-plane programming commands in one embodiment of the present disclosure. Fig.14 As shown, the first physical address in the multi-plane programming command includes the addresses of multiple pages (page A and page B), and the multi-plane programming command sequence starts with 80h, C1 A -C2 A Indicates the column address of page A, R1 A -R3A Indicates the row address of page A, D0 A -Dn A Indicates the data of page A, PRG can use 80h or 81h; C1 B -C2 B Indicates the column address of page B, R1 B -R3 B Indicates the row address of page B, D0 B -Dn B Indicates the data of page B. The row addresses of page A and page B have different plane address bits. The first block address corresponding to page A and the first block address corresponding to page B are obtained from the row addresses of page A and page B, respectively. The multi-plane programming command ends with 10h. Fig.14 The command sequence diagram only shows two pages, and those skilled in the art should understand that three or more pages may be included.

[0169] In one embodiment, the operation command sent by the storage controller includes a multi-plane block erase command (Multi-plane Block Erase command), and the first physical address in the command includes multiple first block addresses, and the multiple first block addresses are identical in bits except for the plane bits. Fig.15 FIG. 2 shows a sequence diagram of a multi-plane block erase command in one embodiment of the present disclosure. Fig.15 As shown, the multi-plane block erase command sequence starts with 60h, R1 A -R3 A Indicates the row address of block A, R1 B -R3 B Indicates the row address of block B. The first block address corresponding to block A and the first block address corresponding to block B are obtained from the row addresses of block A and block B, respectively. The multi-plane block erase command ends with D0h. Fig.15 The command sequence diagram only shows two blocks, and those skilled in the art should understand that it may include three or more blocks.

[0170] In one embodiment, the operation command sent by the storage controller includes a multi-plane read command, and the first physical address in the command includes multiple first block addresses, and the multiple first block addresses are identical in bits except for the plane bits. Fig.16 FIG. 2 shows a sequence diagram of a multi-plane read command in one embodiment of the present disclosure. Fig.16 As shown, the multi-plane read command sequence starts with 00h, C1 A -C2 A Indicates the column address of page A, R1 A -R3 A Indicates the row address of page A; C1 B-C2 B Indicates the column address of page B, R1 B -R3 B Indicates the row address of page B. The row addresses of page A and page B have different plane address bits. The first block address corresponding to page A and the first block address corresponding to page B are obtained from the row addresses of page A and page B, respectively. The multi-plane read command ends with 30h. Fig.16 The command sequence diagram only shows two pages, and those skilled in the art should understand that three or more pages may be included.

[0171] exist Figure 14-16 In the illustrated embodiment, the difference between the technical solution of the present application and other technical solutions can be reflected by detecting the operation command between the storage controller and the storage device, and detecting the physical address contained in the operation command. Specifically, when the storage controller sends a Multi-plane program command, a Multi-plane read command or a Multi-plane Block Erase command to the storage device, when the ALE (Address Latch Enable) pin of the flash memory chip is valid, it can be determined whether the block number of a certain plane (plane) of the address sent to the storage device through the IOx pin of the flash memory chip is inconsistent with that of other planes.

[0172] In one embodiment, the bad block table includes a bad block remapping table, which is recorded on the storage device side, and the storage device searches the bad block remapping table to find the correct block position; the firmware of the storage controller does not need to consider the remapping of the bad block when processing the operation command. Therefore, when the storage controller starts, it is not necessary to load the bad block remapping table to the storage controller, which improves the startup speed, and the firmware of the storage controller does not need to search the bad block remapping table, which improves system performance, saves system space, simplifies the firmware logic of the storage controller, and improves system stability.

[0173] Bad block information management is a very important module in SSD and is on the critical performance path. The optimization of this module in the embodiments of the present disclosure can improve the competitiveness of the product.

[0174] In an exemplary embodiment, a computer-readable storage medium including instructions is also provided, such as a controller memory including instructions, and the above instructions can be executed by a controller processor of a storage controller to complete the above method. Optionally, the computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0175] In an exemplary embodiment, a computer program product is also provided, including a computer program / instruction, and when the computer program / instruction is executed by a processor, the method in the above embodiment is implemented.

[0176] It should be understood that the "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0177] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0178] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0179] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0180] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0181] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: include: A storage controller configured to send an operation command; as well as a memory device coupled to the memory controller, the memory device comprising a plurality of memory blocks and peripheral circuits; The storage device stores a bad block table, and the peripheral circuit is configured as follows: receiving the operation command from the storage controller, wherein the operation command includes a first physical address; Based on the second physical address, the operation corresponding to the operation command is executed, wherein the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address.

2. The memory system according to claim 1, wherein: The bad block table includes block addresses of bad blocks; the peripheral circuit is further configured to: determining a first block address of the first physical address; When the first block address of the first physical address exists in the bad block table, the block corresponding to the first physical address is determined to be the bad block.

3. The memory system according to claim 2, wherein: The bad block table includes a bad block remapping table, and the bad block remapping table includes a block address of the bad block and a block address of a replacement block corresponding to the bad block; The peripheral circuit is further configured as: Based on the bad block remapping table, obtaining a block address of the replacement block corresponding to the first block address; The second physical address is determined based on a block address of the replacement block.

4. The memory system according to claim 2, wherein: The peripheral circuit is further configured as: Determine the first available block in the set order; The second physical address is determined based on the first available block.

5. The memory system according to claim 1, wherein: The peripheral circuit is further configured as: A setting characteristic command is received from the storage controller to enable a bad block management function of the storage device.

6. The memory system according to claim 5, characterized in that: The operation command includes a multi-plane read command or a multi-plane program command, and the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

7. The memory system according to claim 5, characterized in that: The operation command includes a multi-plane block erase command, the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

8. The memory system according to claim 1, wherein: The peripheral circuit is further configured as: When a new bad block is found, the bad block table is updated.

9. The memory system according to claim 1, wherein: The storage controller is configured to: Determine whether to enable the bad block management function of the storage device by obtaining a characteristic command; If the bad block management function of the storage device is not enabled, the storage controller performs bad block management on the first physical address in the operation command; If the bad block management function of the storage device is enabled, the storage device executes the bad block management of the first physical address in the operation command.

10. A storage device, characterized in that: include: A memory cell array; as well as a peripheral circuit coupled to the memory cell array; The storage device stores a bad block table, and the peripheral circuit is configured as follows: receiving an operation command from a storage controller, wherein the operation command includes a first physical address; Based on the second physical address, the operation corresponding to the operation command is executed, wherein the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address.

11. The storage device according to claim 10, characterized in that: The bad block table includes block addresses of bad blocks; the peripheral circuit is further configured to: determining a first block address of the first physical address; When the first block address of the first physical address exists in the bad block table, the block corresponding to the first physical address is determined to be the bad block.

12. The storage device according to claim 11, characterized in that: The bad block table includes a bad block remapping table, and the bad block remapping table includes a block address of the bad block and a block address of a replacement block corresponding to the bad block; The peripheral circuit is further configured as: Based on the bad block remapping table, obtaining a block address of the replacement block corresponding to the first block address; The second physical address is determined based on a block address of the replacement block.

13. The storage device according to claim 11, characterized in that: The peripheral circuit is further configured as: Determine the first available block in the set order; The second physical address is determined based on the first available block.

14. The storage device according to claim 10, characterized in that: The peripheral circuit is further configured as: A set feature command is received from the storage controller to enable a bad block management function of the storage device.

15. The storage device according to claim 14, characterized in that: The operation command includes a multi-plane read command or a multi-plane program command, and the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

16. The storage device according to claim 14, characterized in that: The operation command includes a multi-plane block erase command, the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

17. The storage device according to claim 10, characterized in that: The peripheral circuit is further configured as: When a new bad block is found, the bad block table is updated.

18. A method for operating a memory system, characterized in that: Applied to a storage device, the storage device stores a bad block table, the method comprising: receiving an operation command from a storage controller, wherein the operation command includes a first physical address; Based on the second physical address, the operation corresponding to the operation command is executed, wherein the block corresponding to the first physical address is a bad block, and the second physical address corresponds to the first physical address.

19. The operating method according to claim 18, characterized in that: The bad block table includes block addresses of bad blocks; the method further includes: determining a first block address of the first physical address; When the first block address of the first physical address exists in the bad block table, the block corresponding to the first physical address is determined to be the bad block.

20. The operating method according to claim 19, characterized in that: The bad block table includes a bad block remapping table, and the bad block remapping table also includes a block address of the bad block and a block address of a replacement block corresponding to the bad block; The method further comprises: Based on the bad block remapping table, obtaining a block address of a replacement block corresponding to the first block address; The second physical address is determined based on a block address of the replacement block.

21. The operating method according to claim 19, characterized in that: The method further comprises: Determine the first available block in the set order; The second physical address is determined based on the first available block.

22. The operating method according to claim 18, characterized in that: Also includes: A set feature command is received from the storage controller to enable a bad block management function of the storage device.

23. The operating method according to claim 22, characterized in that: The operation command includes a multi-plane read command or a multi-plane program command, and the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

24. The operating method according to claim 22, characterized in that: The operation command includes a multi-plane block erase command, the first physical address includes a plurality of first block addresses, and the plurality of first block addresses are identical in bits except for the plane bits.

25. The operating method according to claim 18, characterized in that: Also includes: When a new bad block is found, the bad block table is updated. 26 . A computer-readable storage medium, when the control instructions in the computer-readable storage medium are executed by a controller processor, the controller processor is enabled to perform the operating method according to any one of claims 18 to 25.

27. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method according to any one of claims 18 to 25 is implemented.

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