Multiply-adder group, product accumulation method and device

Abstract

The invention provides a multiply-adder group, a multiply-adder accumulation method and a multiply-adder accumulation device, and relates to the field of chips. The multiplier-adder group comprises n functional circuits, m first adder circuits and m second adder circuits. The output end of each functional circuit is connected with the input end of at least one first addition circuit, and the input end of at least one m first addition circuit is connected with the output ends of the plurality of functional circuits. The output ends of the m first addition circuits are connected with the input end of the second addition circuit. Wherein n is a positive integer greater than 2, and m is a positive integer greater than 1. And the functional circuit is used for outputting a code to obtain a partial product after the multiplicand and the multiplier are input. And the first summing circuit is used for summing the partial products to obtain a first summing result and outputting the first summing result. And the second summing circuit is used for summing the first summing result to obtain a second summing result and outputting the second summing result. The invention is used for reducing the power consumption of the multiplier-adder group.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a multiplier-accumulator group, a multiply-accumulate method and a device. Background Art

[0002] A multiplier-accumulator group (MACG) refers to a circuit device used to accumulate the product results of n multiplication operations.

[0003] At present, with the rapid development of artificial intelligence (AI) technology, neural network algorithms have also evolved rapidly. In the operation of neural networks, a large number of multiplier-adder groups are needed to perform massive multiplication and accumulation operations. Therefore, the performance of the multiplier-adder group has an important impact on the overall performance of the neural network operation.

[0004] Therefore, how to improve the performance of the multiplier-accumulator group is a problem that needs to be solved at present. Summary of the invention

[0005] The present application provides a multiplier-adder group, a multiplier-accumulation method and a device for improving the performance of the multiplier-accumulator group.

[0006] In a first aspect, a multiplier-adder group is provided, comprising: n functional circuits, m first adding circuits and second adding circuits. The output end of each functional circuit is connected to the input end of at least one first adding circuit, wherein at least one first adding circuit is connected to a plurality of functional circuits. The output ends of the m first adding circuits are connected to the input end of the second adding circuit. n is a positive integer greater than 2, and m is a positive integer greater than 1. The functional circuit is used to output the encoded partial product after inputting the multiplicand and the multiplier. The first adding circuit is used to sum the partial products to obtain a first summation result, and output the first summation result. The second adding circuit is used to sum the first summation result to obtain a second summation result, and output the second summation result.

[0007] In the above method provided by the present application, the multiplier-adder group, which is different from the related art, first uses the multiplier to calculate the multiplication results of each multiplication operation respectively (specifically, in each multiplier, the multiplicand and the multiplier can be first encoded to obtain partial products, and then the obtained partial products are summed to obtain the multiplication results), and then the product results of each multiplier are added to obtain the final multiplication and accumulation result. In the above method provided by the present application, after the n functional circuits obtain the partial products of each multiplication operation, the partial products of multiple multiplication operations are input into the same first addition circuit for addition by connecting the output ends of multiple functional circuits to the same first addition circuit (that is, the input ends of at least one first addition circuit are connected to the output ends of multiple functional circuits) to obtain a first summation result. Then, the first summation results output by each first addition circuit are added through the second addition circuit to obtain a second summation result (that is, the multiplication and accumulation result). In this way, the partial products of each multiplication operation can be combined first and then summed according to the characteristics of the processed data. For example, when the data input to the multiplier-adder group includes data with a fast signal level change speed (which can be referred to as fast-changing data) and data with a slow signal level change speed (which can be referred to as slowly changing data), on the one hand, the partial products corresponding to the fast-changing data from different functional circuits can be put together and input to a part of the first adding circuits for summing; on the other hand, the partial products corresponding to the slowly changing data from different functional circuits can be put together and input to another part of the first adding circuits for summing; and then the summation results of each first adding circuit are added together to obtain the final multiplication and accumulation result. In this way, the flipping of the full adder can be concentrated in part of the first adding circuits, so that the state of the full adder in the first adding circuit is concentrated in the two states of "no flipping" (part of the slowly changing data) and "multiple bit flipping" (part of the fast changing data), reducing the frequency of occurrence of the state of "single bit flipping", thereby reducing the power of the multiplier-adder group.

[0008] In one implementation, the n functional circuits include p functional circuits, and an output terminal of each of the p functional circuits is connected to input terminals of a plurality of first adding circuits, wherein p is a positive integer.

[0009] In the above implementation, by making the output end of the functional circuit connectable to the input ends of multiple first adding circuits, the partial product output by a functional circuit can be split into multiple parts and output to different first adding circuits respectively. For example, when the data input to a functional circuit includes fast-changing digits and slowly-changing digits, on the one hand, the partial products corresponding to the fast-changing digits can be put together and input to a part of the first adding circuits for summing; on the other hand, the partial products corresponding to the slowly-changing digits can be put together and input to another part of the first adding circuits for summing, so that the flipping of the full adder is concentrated in some of the first adding circuits, thereby reducing the power of the multiplier-adder group.

[0010] In one implementation, p functional circuits are used to output partial products obtained by encoding the multipliers and multiplicands at different digits in the partial products to different first adding circuits.

[0011] In the above implementation, it is considered that in the actual application process, there is a certain regularity in the positions of the fast-changing digits and the slowly-changing digits in the data for multiplication and addition operations. For example, the regularity may be: the high-order bit is the slowly-changing digit, and the low-order bit is the fast-changing digit. In this way, the partial products obtained by encoding the multipliers and multiplicands at different digits in the partial products can be output to different first addition circuits, so that the flipping of the full adder is concentrated in some of the first addition circuits, thereby reducing the power of the multiplier-adder group.

[0012] In one implementation, the p functional circuits are used to output a first set of partial products in the partial products to m1 first adding circuits, and to output a second set of partial products in the partial products to m2 first adding circuits. The m1 first adding circuits are different from the m2 first adding circuits, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

[0013] In the above implementation, the first adding circuit is divided into two parts (i.e., m1 first adding circuits and m2 first adding circuits). The m1 first adding circuits are used to process partial products with faster signal level changes, and the m2 first adding circuits are used to process partial products with slower signal level changes. In this way, the flipping of the full adder can be concentrated in the m1 first adding circuits, thereby reducing the power of the multiplier-adder group.

[0014] In one implementation, the p functional circuits are used to divide the partial product into q parts according to the signal level change speed, and output them to different first adding circuits, where q is a positive integer greater than 1.

[0015] In the above implementation, by dividing the first adding circuit into q parts, the q part first adding circuits are respectively used to process partial products with different signal level change speeds. In this way, the flipping of the full adder can be concentrated in some of the first adding circuits, thereby reducing the power of the multiplier-adder group.

[0016] In one implementation, the second adding circuit includes a first subcircuit and a second subcircuit. The first subcircuit and the second subcircuit are respectively used to sum the data from the first adding circuit. The output ends of the m first adding circuits are respectively connected to the input end of the first subcircuit and the input end of the second subcircuit. The m first adding circuits are specifically used to output the first data set in the first summation result to the first subcircuit, and output the second data set in the first summation result to the second subcircuit, and the signal level of the data in the first data set changes faster than that of the data in the second data set.

[0017] In the above implementation, the second adding circuit is divided into two parts (i.e., a first subcircuit and a second subcircuit). The first subcircuit is used to process a first data set with a faster signal level change speed, and the second subcircuit is used to process a second data set with a faster signal level change speed. In this way, the flipping of the full adder can be concentrated in the second subcircuit, thereby reducing the power of the multiplier-adder group.

[0018] In one implementation, the second adding circuit includes s subcircuits, the s subcircuits being respectively used to sum the data from the first adding circuit. The m first adding circuits are specifically used to divide the first summation result into s output data according to the signal level change speed, and output the s output data to the s subcircuits respectively.

[0019] In the above implementation, by dividing the second adding circuit into s sub-circuits, the s sub-circuits are respectively used to process output data with different signal level change speeds. In this way, the flipping of the full adder can be concentrated in some sub-circuits, thereby reducing the power of the multiplier-adder group.

[0020] In one implementation, n functional circuits are respectively encoded in a radix-2 manner to obtain partial products, or n functional circuits are respectively encoded in a radix-4 manner to obtain partial products, or n functional circuits are respectively encoded in a radix-8 manner to obtain partial products.

[0021] In a second aspect, a multiplication accumulation method is provided, which is applied to a multiplier-adder group, and the method includes: encoding n groups of multiplicands and multipliers to obtain n groups of partial products. The n groups of partial products are divided into m parts of partial products for summing, and m first summation results are obtained, wherein at least one part of the partial product includes partial products from different groups; n is a positive integer greater than 2, and m is a positive integer greater than 1. The m first summation results are summed to obtain a second summation result.

[0022] In one implementation, the n groups of partial products include p groups of partial products, and each group of partial products in the p groups of partial products is divided into a plurality of partial products in the m groups of partial products, where p is a positive integer.

[0023] In one implementation, partial products obtained by encoding the multipliers and multiplicands at different digits in the p groups of partial products are divided into different portions of partial products in the m portions of partial products.

[0024] In one implementation, a first set of partial products in p groups of partial products is divided into m1 sets of partial products in m groups of partial products, and a second set of partial products in p groups of partial products is divided into m2 sets of partial products in m groups of partial products; wherein the m1 sets of partial products are different from the m2 sets of partial products, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

[0025] In one implementation, each group of partial products in the p groups of partial products is divided into q parts according to a signal level change speed, and is divided into q partial products in the m partial products.

[0026] In one implementation, m first summation results are summed to obtain a second summation result, including: summing a first data set in the m first summation results to obtain a third summation result; summing a second data set in the m first summation results to obtain a fourth summation result; and the signal level of the data in the first data set changes faster than that of the data in the second data set.

[0027] In one implementation, summing the m first summation results to obtain a second summation result includes: dividing the m first summation results into s portions of data according to a signal level change rate, and summing the s portions of data respectively to obtain s summation results.

[0028] In one implementation, n groups of multiplicands and multipliers are encoded to obtain n groups of partial products, including: encoding the n groups of multiplicands and multipliers in a radix-2 manner to obtain n groups of partial products; or, encoding the n groups of multiplicands and multipliers in a radix-4 manner to obtain n groups of partial products; or, encoding the n groups of multiplicands and multipliers in a radix-8 manner to obtain n groups of partial products.

[0029] In a third aspect, a chip is provided, comprising a processor and a multiplier-adder group as in the first aspect or any implementation of the first aspect.

[0030] In one implementation, the processor is a neural network processor NPU.

[0031] In a fourth aspect, an electronic device is provided, comprising a printed circuit board and a chip as in the third aspect or the implementation method of the third aspect; the chip is electrically connected to the printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 One of the structural schematic diagrams of a multiplier-adder group provided in an embodiment of the present application;

[0033] Figure 2 A schematic diagram of a full adder provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of the probability of change of each bit of adjacent eigenvalues ​​in a eigenimage of a neural network provided in an embodiment of the present application;

[0035] Figure 4 A second structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0036] Figure 5 A third structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0037] Figure 6 One of the flowcharts of data compression provided in the embodiment of the present application;

[0038] Figure 7 A fourth structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0039] Figure 8 One of the structural schematic diagrams of an addition tree provided in an embodiment of the present application;

[0040] Fig. 9 A fifth structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0041] Fig.10 A second structural diagram of an addition tree provided in an embodiment of the present application;

[0042] Fig.11 A sixth structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0043] Fig.12 A seventh structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0044] Fig.13A A second schematic diagram of a data compression process provided in an embodiment of the present application;

[0045] Fig. 13B A third schematic diagram of a data compression process provided in an embodiment of the present application;

[0046] Fig.14 An eighth structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0047] Fig.15 A fourth flowchart of a data compression method provided in an embodiment of the present application;

[0048] Fig.16 A ninth structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0049] Fig.17 A third structural diagram of an addition tree provided in an embodiment of the present application;

[0050] Fig.18 A tenth structural diagram of a multiplier-adder group provided in an embodiment of the present application;

[0051] Fig.19 A flowchart of a multiplication and accumulation method provided in an embodiment of the present application;

[0052] Fig. 20 One of the structural schematic diagrams of a chip provided in an embodiment of the present application;

[0053] Fig.21 A second schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0054] Fig. 22 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0056] First, in order to facilitate understanding of the technical solutions provided in the embodiments of the present application, the relevant technologies involved in the embodiments of the present application are first introduced:

[0057] 1. Multiplier-adder group (mul_add component group, MACG)

[0058] The multiplier-accumulator group refers to a circuit device used to accumulate the product results of n multiplication operations.

[0059] At present, in order to realize the multiplication and accumulation operation, the related technology (for example, in the hardware design of the neural process unit (NPU)) often adopts a method of forming a multiplier-accumulator group with multiple multipliers so as to perform the multiplication and accumulation operation using the multiplier-accumulator group.

[0060] Specifically, Figure 1The structure diagram of the multiplier-adder group in the related art is shown. Among them, a multiplier-adder group includes multiple multipliers (such as multiplier M1-multiplier Mn in the figure). Each multiplier is used to output the result of the multiplication operation after inputting the multiplicand and the multiplier (A0-An in the figure represents the multiplicand input to each multiplier, and B0-Bn represents the multiplier input to each multiplier). Then, the results of each multiplication operation are added together through an adder (as shown in "A1" in the figure) to obtain the final product accumulation result.

[0061] In the process of calculating the multiplication operation, each multiplier first obtains the partial product of the multiplication operation through encoding, and then accumulates the partial products to obtain the result of the multiplication operation.

[0062] by Figure 1 Taking the multiplier Mn in the example, after the multiplicand An and the multiplier Bn are input, the multiplier Mn first obtains the partial product through the corresponding encoding circuit. When taking the radix-4 method as an example, Figure 1 The partial products obtained by the multiplier Mn shown include PPn-0, PPn-1, ..., PPn-x. Exemplarily, PPn-0 can be understood as the partial product obtained by encoding the first bit (bit) from the low order, the multiplier of the second bit, and the supplementary bit (usually the supplementary bit is 0), and the multiplicand; PPn-1 can be understood as the partial product obtained by encoding the first bit (bit) from the low order, the multiplier of the second bit and the third bit, and the multiplicand; and so on, PPn-1 can be understood as the partial product obtained by encoding the multiplier of the xth bit (bit), the x+1th bit and the x+3th bit from the low order, and the multiplicand (where the multiplier has a total of x+3 bits). Among them, each row of partial products also includes 1 bit below, which is used to represent +1 when taking the complement code. Figure 1 Indicated by black dots.

[0063] After encoding to obtain each partial product, each partial product can be input into a corresponding full adder in the multiplier Mn for addition. This process can also be called data compression. Figure 1 In the example of full adder FA, after inputting three bits of the same weight (also called the same digit), full adder FA will output a sum bit S and a carry bit C. This is equivalent to compressing the original 3-bit data into 2-bit data through a full adder.

[0064] like Figure 1As shown, in the process of compression of the first layer, the multiplier Mn inputs the partial products into the corresponding full adder for addition to obtain the compression result of the first layer. Then, the multiplier Mn inputs the compression result of the first layer into the full adder of the next layer of compression to obtain the compression result of the second layer. And so on, until the compression result is obtained. Among them, since the full adder needs to input 3 bits each time, after compressing two rows of data, the full adder cannot be used to compress data. Therefore, the two rows of data can be used as the output result Fn of the multiplier Mn.

[0065] Then, each multiplier outputs the result F0-Fn and inputs it into adder A1, which further compresses the data. Specifically, the function of adder A1 can be realized by a combination of a full adder and a half adder.

[0066] 2. Full adder

[0067] A full adder adds three input bits to obtain the sum S and the carry C. Figure 2 As shown in (a) in the figure, after the full adder inputs three bits x, y and z, it obtains the sum S and the carry C.

[0068] Among them, the three bits input to the full adder can include two local bits and a carry from the lower bit. In this way, a one-bit full adder can process the lower bit carry and output the local addition carry. Multiple one-bit full adders can be cascaded to obtain a multi-bit full adder.

[0069] Currently, in the full adder using 7nm process, the power consumption statistics of the full adder are shown in Table 1 below.

[0070] Table 1

[0071]

[0072] Among them, when there is no signal level change (i.e., 0 bit flip) in the three bits input to the full adder in this calculation cycle and the three bits input to the full adder in the previous calculation cycle, the power consumption of the full adder is 0.0102uW; when 1 bit flips, the power consumption of the full adder is 0.3971uW, which is equivalent to 0.3971uW per bit flip; when 2 bits flip, the power consumption of the full adder is 0.2202uW, which is equivalent to 0.1101uW per bit flip; when 3 bits flip, the power consumption of the full adder is 0.4410uW, which is equivalent to 0.1470uW per bit flip. It can be seen that when there is 1 bit flip in the data input to the full adder, the power consumption of the full adder per bit flip is the largest.

[0073] The following is an introduction to the technical solution provided by the embodiment of the present application with reference to examples:

[0074] First, with respect to the power consumption characteristics of the full adder described above, the present application embodiment considers that during addition operations, if the flipped bits can be concentrated in a portion of the full adders, the flipping of the other portion of the full adders can be avoided as much as possible, thereby reducing the power consumption of the addition operations.

[0075] Take the example of using a full adder to add 9 single bits. Figure 2 As shown in (b) and (c) in the figure, PP0-PP8 represent the data input to the full adder. The data input from PP0, PP3 and PP6 will have a signal level flip, that is, the data input from PP0, PP3 and PP6 in the previous calculation cycle and the data input from PP0, PP3 and PP6 in the current calculation cycle have a signal level flip; the remaining 6 input data will not have a signal level flip. Then, when according to Figure 2 When adding as shown in (b), the power consumption of the three full adders in the current calculation cycle is 1.1913uW (i.e. 0.3971uW+0.3971uW+0.3971uW); Figure 2 When adding as shown in (c), the power consumption of the three full adders in the current calculation cycle is 0.4614uW (i.e. 0.4410uW+0.0102uW+0.0102uW). Figure 2 When adding as shown in (c), the power consumption of the full adder is significantly lower.

[0076] Furthermore, in the embodiment of the present application, it is considered that when performing multiplication and addition operations, the data (including multiplicand and multiplier) input to the multiplier-adder group in adjacent calculation cycles may have some digits that are the same. In this way, when the partial products obtained by each code are input to the full adder for addition, since the bits corresponding to some of the partial products in the partial products have a signal level flip, and some have no signal level flip, the frequency of 1-bit flip in the full adder is high.

[0077] Take the neural network calculation process as an example: in the feature map of the neural network, the feature value usually has the characteristics of low change rate of high-order bits and high change rate of low-order bits. Figure 3 The figure shows the change rate of each bit in the adjacent eigenvalues ​​of a feature image. It can be seen that the change rate of the high-order bit (i.e., bit7 side) is low (approaching 0), and the change rate of the low-order bit (i.e., bit0 side) is high (exceeding 0.6). In other words, for adjacent eigenvalues, the probability of the high-order bits being the same is high, and the probability of the low-order bits being the same is low.

[0078] Furthermore, in the neural network calculation process, when the eigenvalue is used as the multiplier and the preset parameter is used as the multiplicand, the input Figure 1 When performing multiplication and accumulation operations in the multiplier-accumulator group shown, Figure 1 The processing of the multiplier Mn includes:

[0079] In one calculation cycle, the multiplier Mn receives the multiplicand (preset parameter e) and the multiplier (eigenvalue FM-1), and then the multiplier Mn encodes the preset parameter e and the eigenvalue FM-1 to obtain the partial product. Then, according to the process shown above, the partial product is compressed to obtain the compressed result and output to the adder A1. Next, the adder A1 will further compress the compressed results of each multiplier to obtain the final product accumulation result.

[0080] In the next calculation cycle, the multiplier Mn receives the multiplicand (preset parameter e) and the multiplier (eigenvalue FM-2), and then the multiplier Mn encodes the preset parameter e and the eigenvalue FM-2 to obtain a partial product. At this point, it can be found that since the multiplicands received by the multiplier Mn in the two calculation cycles are the same (both are preset parameters e), and the high bits of the multipliers (eigenvalue FM-1 and eigenvalue FM-2) are also very likely to be the same, only the low bits of the multipliers are very likely to be different. In other words, in the partial products obtained in the two calculation cycles, the partial products obtained by encoding the high bits of the multiplier and multiplicand may be the same. Figure 1 For example, in the addition tree T1 corresponding to the two calculation cycles, the partial products obtained by encoding the multiplier and multiplicand on the high bit (i.e., the partial products on the PPn-x side) are very likely to be the same, and the partial products obtained by encoding the multiplier and multiplicand on the low bit (i.e., the partial products on the PPn-0 side) are very likely to be different. In this way, when the addition tree T1 is compressed in the second calculation cycle, the signal level of the bits corresponding to some partial products is flipped, while the signal level of some bits is not flipped, which makes the frequency of 1bit flipping in the full adder higher.

[0081] In view of the above problems, an embodiment of the present application provides a multiplier-adder group. The multiplier-adder group includes three or more functional circuits (hereinafter referred to as n functional circuits for ease of description, where n is a positive integer greater than 2), two or more first adding circuits (hereinafter referred to as m first adding circuits for ease of description, where m is a positive integer greater than 1), and a second adding circuit.

[0082] The output end of each functional circuit is connected to the input end of at least one first adding circuit, the input end of at least one first adding circuit is connected to the output ends of multiple functional circuits, and the output ends of the other m first adding circuits are connected to the input end of the second adding circuit.

[0083] Each functional circuit is used to output a code to obtain a partial product after inputting a multiplicand and a multiplier.

[0084] It can be seen that, since the output terminal of each functional circuit is connected to the input terminal of at least one first adding circuit, each functional circuit can output the obtained partial product to the first adding circuit.

[0085] Each first adding circuit is used to sum the partial products obtained by the functional circuits (hereinafter the summation result of each first adding circuit is referred to as "first summation result") to obtain a first summation result, and output the first summation result.

[0086] It can be seen that, since the input terminal of the at least one first adding circuit is connected to the output terminals of the plurality of functional circuits, the at least one first adding circuit in the multiplier-adder group can sum the partial products from the plurality of functional circuits.

[0087] In addition, the second adding circuit is used to sum the first summing result (hereinafter the summing result of the second adding circuit is referred to as "second summing result") to obtain a second summing result.

[0088] It can be seen that since the output ends of the m first adding circuits are connected to the input ends of the second adding circuit, the second adding circuit can sum the first summation results from the m first adding circuits, and the second summation result obtained can be understood as the multiplication and accumulation result output by the multiplier-adder group, thereby completing the multiplication and accumulation operation.

[0089] In the multiplier-adder group provided in the embodiment of the present application, since the output ends of multiple functional circuits are connected to the same first adding circuit (i.e., the input end of at least one first adding circuit is connected to the output ends of multiple functional circuits), the partial products corresponding to multiple multiplication operations can be input into the same first adding circuit for addition. Compared with the method of adding partial products in units of multiplication operations in the related art, after obtaining the partial products of each multiplication operation, the partial products corresponding to different multiplication operations can be added in the embodiment of the present application. In this way, when the partial products include both partial products with fast signal level changes (hereinafter referred to as "fast changes") and partial products with slow signal level changes (hereinafter referred to as "slow changes"), on the one hand, the fast-changing partial products from different functional circuits can be put together and input into a part of the first adding circuit for summation; on the other hand, the slow-changing partial products from different functional circuits can be put together and input into another part of the first adding circuit for summation; and then the summation results of each first adding circuit are added to obtain the final multiplication accumulation result.

[0090] In this way, the flipping of the full adder can be concentrated in part of the first adding circuit, which is equivalent to concentrating the state of the full adder as much as possible in the two states of "0 bit flipping" and "multiple bit flipping", reducing the frequency of occurrence of the state of "1 bit flipping", thereby reducing power consumption.

[0091] It is understandable that, in the embodiments of the present application, for the convenience of description, the circuits included in the multiplier-adder group that implement the corresponding functions are respectively referred to as "functional circuits", "first addition circuits" and "second addition circuits". In actual application, other names can also be used to represent the various circuits in the multiplier-adder group. For example, the "functional circuit" in the embodiments of the present application can be referred to as "encoding circuits" or "partial product generation circuits", etc. For another example, the "first addition circuit" and "second addition circuit" in the embodiments of the present application can be respectively referred to as "primary addition circuits" and "secondary addition circuits". In the embodiments of the present application, there is no restriction on the names of the circuits that implement the corresponding functions in the multiplier-adder group.

[0092] The following is an introduction to the multiplier-adder group provided in the embodiment of the present application with reference to an example:

[0093] like Figure 4 , which is a schematic diagram of the structure of a multiplier-adder group 10 provided in an embodiment of the present application. The multiplier-adder group 10 includes 8 functional circuits (i.e., functional circuits 110 to 117), 2 first adding circuits (i.e., first adding circuit 120 and first adding circuit 121) and a second adding circuit 130.

[0094] The output ends of the eight functional circuits are connected to the input ends of the two first adding circuits respectively. In addition, the input end of the first adding circuit 120 is connected to the output ends of the eight functional circuits, and the input end of the first adding circuit 121 is connected to the output ends of the eight functional circuits. In addition, the output ends of the two first adding circuits are connected to the input end of the second adding circuit 130.

[0095] In one implementation, when, among the partial products generated by each functional circuit, the signal level of the partial product obtained by encoding the high-bit multiplier and the multiplicand changes slowly, and the signal level of the partial product obtained by encoding the low-bit multiplier and the multiplicand changes quickly, the partial products generated by each functional circuit can refer to Figure 5 The partial products PP7-0, PP7-1, PP7-2 and PP7-1 generated by the function circuit 117 are: wherein the partial products obtained by encoding the low-bit multiplier and the multiplicand (i.e. Figure 5 PP7-0 and PP7-1) change quickly, and the high-bit multiplier and multiplicand are encoded to obtain the partial product (i.e. Figure 5 PP7-2 and PP7-3) in the middle changed slowly.

[0096] It should be noted that, in the embodiments of the present application, each functional circuit mainly takes the partial product obtained by encoding the multiplicand and the multiplier in a radix-4 manner as an example to introduce the operation process of the multiplier-adder group 10. Figure 5 The partial products of each row in PP7-0, PP7-1, PP7-2 and PP7-1 are all 10 bits, including 8 bits of data, 1 bit of sign bit extension and 1 bit of +1 when taking the complement code. Unless otherwise specified below, the bits included in the partial products of each row can be understood by referring to the above 10 bits.

[0097] In addition, in the actual application process, each functional circuit can also be based on the multiplier and multiplicand of other digits. In addition, each functional circuit can also obtain partial products according to different types of encoding methods. Specifically, each functional circuit can be encoded in a base 2 manner to obtain partial products, or each functional circuit can be encoded in a base 4 manner to obtain partial products, or each functional circuit can be encoded in a base 8 manner to obtain partial products, etc. For the number of digits of the multiplier and multiplicand used by each functional circuit, and the type of encoding method used by each functional circuit, there is no restriction in the embodiments of the present application.

[0098] Further, in Figure 5 In the example shown, each functional circuit outputs a partial product obtained by encoding the low-bit multiplier and multiplicand to the first adding circuit 120 , and outputs a partial product obtained by encoding the high-bit multiplier and multiplicand to the first adding circuit 121 .

[0099] The partial product received by the first adding circuit 120 is as follows: Figure 5 The addition tree T-1 is shown in FIG. The addition tree T-1 includes two rows of partial products (i.e., PP0-0 and PP0-1) obtained by encoding the low-bit multiplier and multiplicand output by the function circuit 110, two rows of partial products (i.e., PP1-0 and PP1-1) obtained by encoding the low-bit multiplier and multiplicand output by the function circuit 111, and so on until two rows of partial products (i.e., PP7-0 and PP7-1) obtained by encoding the low-bit multiplier and multiplicand output by the function circuit 117.

[0100] The partial product received by the first adding circuit 121 is as follows: Figure 5The addition tree T-2 is shown in FIG. The addition tree T-2 includes two rows of partial products (i.e., PP0-2 and PP0-3) obtained by encoding the high-bit multiplier and multiplicand output by the function circuit 110, two rows of partial products (i.e., PP1-2 and PP1-3) obtained by encoding the high-bit multiplier and multiplicand output by the function circuit 111, and so on until two rows of partial products (i.e., PP7-2 and PP7-3) obtained by encoding the high-bit multiplier and multiplicand output by the function circuit 117.

[0101] The first adding circuit 121 compresses the adding tree T-2 as follows: Figure 6 As shown. In the first adding circuit 121, the partial product of every three bits with the same weight in the adding tree T-2 is first input into the full adder to obtain the first layer compression result. Figure 6 For example, after receiving 3 bits of data, the full adder FA outputs a sum S and a carry C. S and C are used as two bits in the first layer of compression results. After that, the partial product of every three bits with the same weight in the first layer of compression results is input into the next batch of full adders to obtain the second layer of compression results. And so on, the first sum result is finally obtained.

[0102] Since the partial products input to the first adding circuit 121 are all slowly varying data, the adding tree corresponding to the first adding circuit 121 in the next calculation cycle and the adding tree T-2 corresponding to the first adding circuit 121 in the current calculation cycle have a large amount of identical data. In this way, when the adding tree is compressed in the next calculation cycle, the input data of some full adders in the first adding circuit 121 will not change, and thus the signal levels of these full adders will not change (i.e., 0 bit flip), thereby making each full adder in a low power consumption state.

[0103] On the other hand, the first adding circuit 120 compresses the adding tree T-1. Figure 6 The compression process of the addition tree T-2 by the first addition circuit 121 is similar, and the repetitive parts are not repeated here. It can be understood that in the process of compressing the partial product by the first addition circuit 120, since the partial product input to the first addition circuit 120 in two adjacent calculation cycles includes a large amount of changing data, the signal level change probability of the full adder in the first addition circuit 121 is relatively large, so that these full adders are in a low power consumption state of multiple bit flips (i.e., 2-bit flips and 3-bit flips) as much as possible.

[0104] In summary, in the above implementation, the first adding circuit 120 and the first adding circuit 121 integrate and compress the signal level changes quickly and the signal level changes slowly, thereby reducing the power consumption of the multiplier-adder group.

[0105] Above Figure 5 and Figure 6 In the example shown, the operation process of the multiplier-adder group 10 is introduced by taking the case where the signal level of the partial product obtained by encoding the high-bit multiplier and multiplicand in the partial product generated by each functional circuit changes slowly (for ease of description, hereinafter the "signal level of the partial product obtained by encoding the high-bit multiplier and multiplicand changes slowly" is referred to as "high-bit slow change") and the signal level of the partial product obtained by encoding the low-bit multiplier and multiplicand changes quickly (hereinafter the "signal level of the partial product obtained by encoding the low-bit multiplier and multiplicand changes quickly" is referred to as "low-bit fast change") as an example.

[0106] In another implementation provided below, the operation process of the multiplier-adder group 10 provided in the embodiment of the present application is described by taking as an example that among multiple functional circuits, there is a part of the functional circuits that generates a partial product in which the "high bit changes slowly" and the "low bit changes quickly", and another part of the functional circuits that generates a partial product in which the opposite is true, that is, the "low bit changes slowly" and the "high bit changes quickly" as the example:

[0107] For example Figure 7 As shown, in the multiplier-accumulator group 10, the "low-order bits change slowly" and the "high-order bits change quickly" in the partial products generated by the functional circuits 110 to 113, and the "high-order bits change slowly" and the "low-order bits change quickly" in the partial products generated by the functional circuits 114 to 117.

[0108] The function circuits 110 to 113 output the partial product obtained by encoding the low-bit multiplier and the multiplicand to the first adding circuit 120, and output the partial product obtained by encoding the high-bit multiplier and the multiplicand to the first adding circuit 121. The function circuits 114 to 117 output the partial product obtained by encoding the low-bit multiplier and the multiplicand to the first adding circuit 121, and output the partial product obtained by encoding the high-bit multiplier and the multiplicand to the first adding circuit 120.

[0109] Furthermore, the partial product received by the first adding circuit 120 is as follows: Figure 8 The addition tree T-1 is shown in FIG. Figure 8The addition tree T-1 includes: two rows of partial products (i.e., PP0-0 and PP0-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 110, two rows of partial products (i.e., PP1-0 and PP1-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 111, two rows of partial products (i.e., PP2-0 and PP2-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 112, and two rows of partial products (i.e., PP3-0 and PP3-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 113. In addition, the addition tree T-1 also includes: two rows of partial products (i.e., PP4-2 and PP4-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 114, two rows of partial products (i.e., PP5-2 and PP5-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 115, two rows of partial products (i.e., PP6-2 and PP6-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 116, and two rows of partial products (i.e., PP7-2 and PP7-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 117.

[0110] In addition, the partial product received by the first adding circuit 121 is as follows Figure 8 The addition tree T-2 is shown in FIG. Figure 8 The middle addition tree T-2 includes: two rows of partial products (i.e., PP0-2 and PP0-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 110, two rows of partial products (i.e., PP1-2 and PP1-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 111, two rows of partial products (i.e., PP2-2 and PP2-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 112, and two rows of partial products (i.e., PP3-2 and PP3-3) obtained by encoding the high-bit multiplier and multiplicand output by the functional circuit 113. In addition, the addition tree T-1 also includes: two rows of partial products (i.e., PP4-0 and PP4-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 114, two rows of partial products (i.e., PP5-0 and PP5-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 115, two rows of partial products (i.e., PP6-0 and PP6-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 116, and two rows of partial products (i.e., PP7-0 and PP7-1) obtained by encoding the low-bit multiplier and multiplicand output by the functional circuit 117.

[0111] Among them, for the first adding circuit 120 and the first adding circuit 121 Figure 8The compression process of the addition tree T-1 and the addition tree T-2 can refer to the first addition circuit 121 for the compression process of the addition tree T-1 and the addition tree T-2. Figure 6 The compression process of the addition tree T-2 is repeated here.

[0112] exist Figure 7-Figure 8 In the multiplier-adder group shown, the first adding circuit 120 and the first adding circuit 121 are used to compress the partial integral of the signal level that changes quickly and the signal level that changes slowly, thereby reducing the power consumption of the multiplier-adder group.

[0113] In another implementation, among the multiple functional circuits, some of the partial products generated by some of the functional circuits are data with fast signal level changes, while some of the partial products generated by other functional circuits are data with slow signal level changes.

[0114] For example Fig. 9 As shown, in the multiplier-adder group 10, the partial products generated by the functional circuits 110 to 113 are data with slow signal level changes, and the partial products generated by the functional circuits 114 to 117 are data with fast signal level changes.

[0115] At this time, the output ends of the functional circuits 110 - 113 may be connected only to the input end of the first adding circuit 120 , and the output ends of the functional circuits 114 - 117 may be connected only to the input end of the first adding circuit 121 .

[0116] The function circuits 110 to 113 output the encoded partial products to the first adding circuit 120. The function circuits 114 to 117 output the encoded partial products to the first adding circuit 121.

[0117] Furthermore, the partial product received by the first adding circuit 120 is as follows: Fig.10 The addition tree T-1 is shown in FIG. Fig.10 The addition tree T-1 includes: the partial products output by the functional circuit 110 (i.e., PP0-0, PP0-1, PP0-2, and PP0-3), the partial products output by the functional circuit 111 (i.e., PP1-0, PP1-1, PP1-2, and PP1-3), the partial products output by the functional circuit 112 (i.e., PP2-0, PP2-1, PP2-2, and PP2-3), and the partial products output by the functional circuit 113 (i.e., PP3-0, PP3-1, PP3-2, and PP3-3).

[0118] The partial product received by the first adding circuit 121 is as follows: Fig.10 The addition tree T-2 is shown in FIG. Fig.10The addition tree T-2 includes: the partial products output by the functional circuit 114 (i.e., PP4-0, PP4-1, PP4-2, and PP4-3), the partial products output by the functional circuit 115 (i.e., PP5-0, PP5-1, PP5-2, and PP5-3), the partial products output by the functional circuit 116 (i.e., PP6-0, PP6-1, PP6-2, and PP6-3), and the partial products output by the functional circuit 117 (i.e., PP7-0, PP7-1, PP7-2, and PP7-3).

[0119] Among them, for the first adding circuit 120 and the first adding circuit 121 Fig.10 The compression process of the addition tree T-1 and the addition tree T-2 can refer to the first addition circuit 121 for the compression process of the addition tree T-1 and the addition tree T-2. Figure 6 The compression process of the addition tree T-2 is repeated here.

[0120] exist Figure 9-10 In the multiplier-adder group shown, the first adding circuit 120 and the first adding circuit 121 are used to compress the partial integral of the signal level that changes quickly and the signal level that changes slowly, thereby reducing the power consumption of the multiplier-adder group.

[0121] In addition, it is understandable that, in actual application, not every first adding circuit in the multiplier adder group 10 must be connected to multiple functional circuits. In some application scenarios, the multiplier adder group 10 may also include a first adding circuit connected to only one functional circuit. Fig.11 As shown, the multiplier-adder group 10 includes: functional circuits 110 to 118 , first adding circuits 120 to 122 , and a second adding circuit 130 .

[0122] The connection relationship between the functional circuit 110-functional circuit 117 and the first adding circuit 120-first adding circuit 121, and the operation process of the functional circuit 110-functional circuit 117 and the first adding circuit 120-first adding circuit 121 can be referred to. Fig. 9 FIG. 1 is an operation process of the functional circuit 110 - the functional circuit 117 and the first adding circuit 120 - the first adding circuit 121 .

[0123] In addition, the output terminal of the functional circuit 118 is connected to the input terminal of the first adding circuit 122. At this time, it can be understood that the first adding circuit is used to output the product result of A8 and B8 (ie, the multiplicand and the multiplier received by the functional circuit 118).

[0124] Above Figure 4-10The operation process of the multiplier adder group 10 is mainly introduced by taking the multiplier adder group 10 including two first adding circuits as an example. In other application scenarios, the multiplier adder group 10 may include a larger number of first adding circuits.

[0125] For example Fig.12 As shown, the multiplier-adder group 10 includes eight functional circuits (ie, functional circuits 110 to 117 ), four first adding circuits (ie, first adding circuits 120 to 123 ) and a second adding circuit 130 .

[0126] In one implementation, the four first adding circuits included in the multiplier-adder group 10 can be divided into two groups, one of which is used to process partial products with fast signal level changes, and the other is used to process partial products with slow signal level changes.

[0127] For example Fig.12 In the embodiment, when the partial products output by each functional circuit are "high-order bits change slowly" and "low-order bits change quickly", the partial products obtained by encoding the multipliers and multiplicands at the low bits in the partial products of each functional circuit can be output to the first adding circuit 120 and the first adding circuit 121, and the partial products obtained by encoding the multipliers and multiplicands at the high bits in the partial products of each functional circuit can be output to the first adding circuit 122 and the first adding circuit 123. That is, at this time, the first adding circuit 120 and the first adding circuit 121 are used to process partial products with fast signal level changes; the first adding circuit 122 and the first adding circuit 123 are used to process partial products with slow signal level changes.

[0128] Exemplarily, the partial products received by each of the first adding circuits 120 to 123 can be expressed as follows: Fig.13A and Fig. 13B shown.

[0129] Among them, the partial products received by the first adding circuit 120 include: the partial products obtained by encoding the low-bit multipliers and multiplicands output by the functional circuits 110-113 (i.e., PP0-0, PP0-1, PP1-0, PP1-1, PP2-0, PP2-1, PP3-0 and PP3-1).

[0130] The partial products received by the first adding circuit 121 include: partial products obtained by encoding the low-bit multipliers and multiplicands output by the functional circuits 114-117 (i.e., PP4-0, PP4-1, PP5-0, PP5-1, PP6-0, PP6-1, PP7-0 and PP7-1).

[0131] The partial products received by the first adding circuit 122 include: partial products obtained by encoding the high-bit multipliers and multiplicands output by the functional circuits 110-113 (i.e., PP0-2, PP0-3, PP1-2, PP1-3, PP2-2, PP2-3, PP3-2 and PP3-3).

[0132] The partial products received by the first adding circuit 123 include: partial products obtained by encoding the high-bit multipliers and multiplicands output by the functional circuits 114-117 (i.e., PP4-2, PP4-3, PP5-2, PP5-3, PP6-2, PP6-3, PP7-2 and PP7-3).

[0133] Fig.13A and Fig. 13B The specific process of the first adding circuit 120-the first adding circuit 123 compressing the partial products to obtain the first summation results can refer to the first adding circuit 121 above. Figure 6 The compression process of the addition tree T-2 is repeated here.

[0134] exist Fig.12 , Fig.13A and Fig. 13B In the multiplier-adder group 10 shown, the power consumption of the multiplier-adder group is reduced by using the first adding circuit 120 and the first adding circuit 121 to compress the partial integration of the signal level that changes quickly and the signal level that changes slowly.

[0135] Further, in Fig.12 In the process of summing the first summation results from each first summation circuit by the second addition circuit 130 in the multiplier-adder group 10, it is considered that each first summation result may also include data with a fast signal level change and data with a slow signal level change. Therefore, by arranging multiple sub-circuits in the second addition circuit 130, on the one hand, the data with a fast signal level change from the first addition circuit can be put together and input to a part of the sub-circuits for summation; on the other hand, the data with a slow signal level change from the first addition circuit can be put together and input to another part of the sub-circuits for summation.

[0136] For example, Fig.14 As shown, the second adding circuit 130 may include a first sub-circuit 1301 and a second sub-circuit 1302 .

[0137] The input end of the first sub-circuit 1301 is connected to the first adding circuit 120 and the first adding circuit 121 , and the input end of the second sub-circuit 1302 is connected to the first adding circuit 122 and the first adding circuit 123 .

[0138] like Fig.15As shown, the data received by the first sub-circuit 1301 includes the first summation result a from the first adding circuit 120 and the first summation result b from the first adding circuit 121. The data received by the first sub-circuit 1302 includes the first summation result c from the first adding circuit 122 and the first summation result d from the first adding circuit 123.

[0139] The specific process of the first subcircuit 1301 and the second subcircuit 1302 compressing the first summation result to obtain the third summation result and the fourth summation result can be referred to the above-mentioned first adding circuit 121 compressing the first summation result. Figure 6 The compression process of the addition tree T-2 in the middle, the repeated contents are not repeated here. After the first subcircuit 1301 and the second subcircuit 1302 obtain the third summation result and the fourth summation result, the third summation result and the fourth summation result can be directly output as the operation result of the second addition circuit (in this case, the third summation result and the fourth summation result can be used together as the second summation result). Or the second addition circuit can also include a subcircuit for summing the third summation result and the fourth summation result, so that the second addition circuit can output the summation result of the third summation result and the fourth summation result as the operation result of the second addition circuit (i.e., the second summation result).

[0140] As mentioned above Fig.12 As described above, since the partial products compressed by the first adding circuit 120 and the first adding circuit 121 are partial products with fast signal level changes, the first summation results a and the first summation results b are also data with fast signal level changes. Since the partial products compressed by the first adding circuit 122 and the first adding circuit 123 are partial products with slow signal level changes, the first summation results c and the first summation results d are also data with slow signal level changes.

[0141] Therefore, in the above implementation, the first sub-circuit 1301 compresses the first summation result a and the first summation result b, and the first sub-circuit 1302 compresses the first summation result c and the first summation result d, so that the data with fast signal level changes and the data with slow signal level changes can be compressed separately, thereby further reducing the power consumption of the multiplier group 10.

[0142] In addition, the above Fig.12In the example shown, the plurality of first adding circuits are mainly divided into two groups, one of which is used to process partial products with fast signal level changes, and the other is used to process partial products with slow signal level changes. In some other implementations, the plurality of first adding circuits may be divided into three or more groups (hereinafter referred to as dividing the plurality of first adding circuits into q groups). Furthermore, each functional circuit may divide the partial product into q parts according to the signal level change speed, wherein each part of the partial product is output to a different first adding circuit.

[0143] For example Fig.16 Among the partial products output by each functional circuit, the signal level of the partial product obtained by encoding the lowest-order multiplier and the multiplicand changes the fastest. In addition, as the number of bits of the corresponding multiplier increases, the signal level change of the partial product gradually decreases until the signal level of the partial product obtained by encoding the highest-order multiplier and the multiplicand changes the slowest. In this case, the four rows of partial products output by the functional circuit can be output to different first adding circuits respectively.

[0144] Specifically, in Fig.16 In the embodiment, each functional circuit encodes the lowest-order multiplier and multiplicand in the four-row partial product and outputs the partial product (including: the partial product PP0-0 output by the functional circuit 110, the partial product PP1-0 output by the functional circuit 111, ... until the partial product PP7-0 output by the functional circuit 117) to the first adding circuit 120; each functional circuit encodes the second lowest-order multiplier and multiplicand in the four-row partial product and outputs the partial product (including: the partial product PP0-1 output by the functional circuit 110, the partial product PP1-1 output by the functional circuit 111, ... until the partial product PP7-1 output by the functional circuit 117) to the first adding circuit 121. ; Each functional circuit encodes the partial products obtained by encoding the second highest multiplier and multiplicand in the four rows of partial products (including: the partial products PP0-2 output by the functional circuit 110, the partial products PP1-2 output by the functional circuit 111... until the partial product PP7-2 output by the functional circuit 117) to the first adding circuit 122; each functional circuit encodes the partial products obtained by encoding the highest multiplier and multiplicand in the four rows of partial products (including: the partial products PP0-3 output by the functional circuit 110, the partial products PP1-3 output by the functional circuit 111... until the partial product PP7-3 output by the functional circuit 117) to the first adding circuit 123.

[0145] Furthermore, the partial products received by each of the first adding circuits 120 to 123 can be expressed as follows: Fig.17 shown.

[0146] Fig.17The specific process of the first adding circuit 120-the first adding circuit 123 compressing the partial products to obtain the first summation results can refer to the first adding circuit 121 above. Figure 6 The compression process of the addition tree T-2 in , the repeated content will not be repeated here. Fig.17 In order to simplify the information in the diagram, the complement codes corresponding to the partial products of each row are added with 1, and are uniformly represented by black dots in the last row of each addition tree.

[0147] exist Figure 16-Figure 17 In the multiplier-adder group 10 shown, each functional circuit can divide the partial product into four parts according to the different speeds of signal level changes, and output the partial product to four first adding circuits, thereby further reducing the power consumption of the multiplier-adder group.

[0148] In addition, the above Fig.14 In the example shown, the operation process of the multiplier group 10 is mainly introduced by arranging two sub-circuits in the second adding circuit, one of which is used to process data with a fast signal level change from the first adding circuit, and the other is used to process data with a slow signal level change from the first adding circuit. In some other implementations, the second adding circuit may also include three or more sub-circuits. In addition, each first adding circuit may divide the first summation result into s output data according to the signal level change speed, wherein each output data is output to a different sub-circuit in the second adding circuit.

[0149] For example Fig.18 As shown, the multiplier-adder group 10 may include: 8 functional circuits (i.e., functional circuits 110 to 117), 6 first adding circuits (i.e., first adding circuits 120 to 125), and a second adding circuit 130. The second adding circuit 130 includes a first sub-circuit 1301, a second sub-circuit 1302, and a third sub-circuit 1303.

[0150] The eight functional circuits are respectively used to divide the partial products into six parts according to the speed of signal level change, and output them to the six first adding circuits respectively. Among them, the signal level of the partial product received by the first adding circuit 120 changes the fastest, the signal level of the partial product received by the first adding circuit 121 changes the second fastest, and so on, the signal level of the partial product received by the first adding circuit 125 changes the slowest.

[0151] The six first adding circuits are respectively used to sum the received partial products to obtain a first summation result, and divide the first summation result into three output data according to the signal level change speed, and output the three output data to the first sub-circuit 1301, the second sub-circuit 1302 and the third sub-circuit 1303 respectively.

[0152] Specifically, since the signal level of the partial product received by the first adding circuit 120 among the first adding circuits changes the fastest, the signal level of the partial product received by the first adding circuit 121 changes second, until the signal level of the partial product received by the first adding circuit 125 changes the slowest, the signal level of the first summation result obtained by the first adding circuit 120 and the first adding circuit 121 changes the fastest, the signal level of the first summation result obtained by the first adding circuit 122 and the first adding circuit 123 changes second, and the signal level of the first summation result obtained by the first adding circuit 124 and the first adding circuit 125 changes the slowest.

[0153] Therefore, the first summation result obtained by the first addition circuit 120 and the first addition circuit 121 is output to the first sub-circuit 1301; the first summation result obtained by the first addition circuit 122 and the first addition circuit 123 is output to the first sub-circuit 1302; and the first summation result obtained by the first addition circuit 124 and the first addition circuit 125 is output to the first sub-circuit 1303.

[0154] The specific operation process of the first sub-circuit 1301, the second sub-circuit 1302 and the third sub-circuit 1303 can be referred to the above description. Fig.15 The description of the first sub-circuit 1301 and the second sub-circuit 1302 in the figure will not be repeated here.

[0155] In addition, it can be understood that, in the actual application process, when each functional circuit in the above example outputs the partial product to the first addition circuit, on the one hand, when there is a certain regularity in the changes of the multiplicand and the multiplier of the input multiplier adder group, these regularities can be used to determine the partial products output to different first addition circuits. For example, when the multiplicand and the multiplier of the input multiplier adder group have the following regularity: the multiplicand is a constant preset parameter, only a part of the digits of the multiplier change faster, and the other part of the digits change slower, then the partial products with different signal level change speeds can be output to different first addition circuits by encoding the multipliers and multiplicands with different digits and outputting them to different first addition circuits. In this case, each functional circuit does not need to detect the change speed of the signal level of each partial product, but only needs to output the partial product to different first addition circuits according to the digits of the multiplier corresponding to the partial product. For example, in Figure 16-Figure 17In the example shown, each functional circuit does not need to detect the change speed of the signal level of each partial product. It only needs to output the partial product obtained by encoding the lowest digit multiplier and multiplicand in the partial product to the first addition circuit 120, the partial product obtained by encoding the second lowest digit multiplier and multiplicand to the first addition circuit 121, the partial product obtained by encoding the second highest digit multiplier and multiplicand to the first addition circuit 122, and the partial product obtained by encoding the highest digit multiplier and multiplicand to the first addition circuit 123. In this way, partial products with different signal level change speeds can be output to different first addition circuits.

[0156] On the other hand, each functional circuit can also monitor the signal level change speed of each partial product, and determine to output the partial product to a different first adding circuit according to the monitoring result. Figure 16-Figure 17 For example, each functional circuit can monitor each partial product obtained by encoding. When it is monitored that the signal level change speed of a partial product is very fast (for example, the signal level change speed is greater than the first speed threshold), the partial product is output to the first adding circuit 123; when it is monitored that the signal level change speed of a partial product is slightly faster (for example, the signal level change speed is greater than the second speed threshold and less than the first speed threshold), the partial product is output to the first adding circuit 122; when it is monitored that the signal level change speed of a partial product is slightly slower (for example, the signal level change speed is greater than the third speed threshold and less than the second speed threshold), the partial product is output to the first adding circuit 121; when it is monitored that the signal level change speed of a partial product is very slow (for example, the signal level change speed is greater than the fourth speed threshold and less than the third speed threshold), the partial product is output to the first adding circuit 120. In this case, each functional circuit may include a controller for monitoring the signal level change speed of each partial product and controlling the output partial product. The function of the controller can be implemented by software or hardware.

[0157] Combined with the above Figure 4-18 In the example shown, the present application embodiment provides a multiplication and accumulation method, which is applied to a multiplier-accumulator group. Fig.19 As shown, the method may include:

[0158] S201, a multiplier-adder group encodes n groups of multiplicands and multipliers to obtain n groups of partial products, where n is a positive integer greater than 2.

[0159] For example, when n is 8, Figure 4 , Figure 5 , Figure 7 , Fig. 9 , Fig.12 , Fig.14 , Fig.16 and Fig.18In the embodiment, the eight functional circuits in the multiplier-adder group 10 encode eight groups of multiplicands and multipliers respectively to obtain eight groups of partial products.

[0160] For another example, when n is 9, Fig.11 In the embodiment, the 9 functional circuits in the multiplier-adder group 10 encode 9 groups of multiplicands and multipliers respectively to obtain 9 groups of partial products.

[0161] S202, the multiplier-adder group divides n groups of partial products into m groups of partial products for summing, and obtains m first summation results.

[0162] Wherein at least one of the partial products includes partial products from different groups. m is a positive integer greater than 1.

[0163] For example, when m is 2, Figure 4 , Figure 5 , Figure 7 and Fig. 9 The eight functional circuits divide the eight groups of partial products into two partial products, and output them to two first adding circuits for summing, respectively, to obtain two first summing results.

[0164] For another example, when m is 3, Fig.11 In the embodiment, the nine functional circuits divide the nine groups of partial products into three partial products, and output them to three first adding circuits for summing, respectively, to obtain three first summing results.

[0165] For another example, when m is 4, Fig.12 , Fig.14 and Fig.16 In the embodiment, 8 functional circuits divide 8 groups of partial products into 4 partial products, and output them to 4 first adding circuits for summing, thereby obtaining 4 first summation results.

[0166] For another example, when m is 6, Fig.18 In the embodiment, 8 functional circuits divide 8 groups of partial products into 6 partial products, and output them to 6 first adding circuits for summing, thereby obtaining 6 first summation results.

[0167] S203, the multiplier-adder group sums the m first summation results to obtain a second summation result.

[0168] For example, Figure 4 , Figure 5 , Figure 7 and Fig. 9 In the embodiment, the second adding circuit 130 adds the two first summing results from the two first adding circuits to obtain a second summing result.

[0169] For another example, Fig.11 In the embodiment, the second adding circuit 130 adds the three first summing results from the three first adding circuits to obtain a second summing result.

[0170] For another example, Fig.12 , Fig.14 and Fig.16 In the embodiment, the second adding circuit 130 adds the four first summing results from the four first adding circuits to obtain a second summing result.

[0171] For another example, Fig.18 In the embodiment, the second adding circuit 130 adds the six first summing results from the six first adding circuits to obtain a second summing result.

[0172] In one implementation, the n groups of partial products include p groups of partial products. Each group of partial products in the p groups of partial products is divided into a plurality of partial products in the m groups of partial products, where p is a positive integer.

[0173] For example, Fig.11 Among the 8 groups of partial products generated by the functional circuits 110-117 in the 9 groups of partial products, each group of partial products is divided into 2 partial products out of 3 partial products (i.e., 1 partial product received by the first adding circuit 120, and 1 partial product received by the first adding circuit 121).

[0174] In one implementation, the partial products obtained by encoding the multipliers and multiplicands on the same digits in the p groups of partial products are divided into the same partial product among the m partial products.

[0175] For example, Figure 5 Among the 8 groups of partial products generated by the functional circuits 110-127, the partial products obtained by encoding the multipliers and multiplicands on the lower bits are all divided into one portion of partial products received by the first addition circuit 120; the partial products obtained by encoding the multipliers and multiplicands on the higher bits are all divided into one portion of partial products received by the first addition circuit 121.

[0176] For another example, Fig.16 Among the 8 groups of partial products generated by the functional circuits 110-127, the partial products obtained by encoding the multiplier and the multiplicand at the lowest digit are divided into one of the 4 partial products received by the first adding circuit 120; the partial products obtained by encoding the multiplier and the multiplicand at the second lowest digit are divided into one of the 4 partial products received by the first adding circuit 121; the partial products obtained by encoding the multiplier and the multiplicand at the second highest digit are divided into one of the 4 partial products received by the first adding circuit 122; the partial products obtained by encoding the multiplier and the multiplicand at the highest digit are divided into one of the 4 partial products received by the first adding circuit 123.

[0177] In one implementation, the partial products of the p groups of partial products with fast signal level changes are divided into m1 partial products of the m partial products, and the partial products of the p groups of partial products with slow signal level changes are divided into m2 partial products of the m partial products. The m1 partial products are different from the m2 partial products.

[0178] For example, Figure 5 Among the 8 groups of partial products, the partial products with faster signal level changes are divided into one partial product received by the first adding circuit 120, and the partial products with slower signal level changes are divided into one partial product received by the first adding circuit 121.

[0179] For another example, Figure 7 , Figure 8 , Fig. 9 and Fig.10 Among the 8 groups of partial products, the partial products with slow signal level changes are divided into one partial product received by the first adding circuit 120, and the partial products with fast signal level changes are divided into one partial product received by the first adding circuit 121.

[0180] For another example, Fig.12 , Fig.13A , Fig. 13B and Fig.14 Among the 8 groups of partial products, the partial products with faster signal level changes are divided into two partial products received by the first adding circuit 120 and the first adding circuit 121, and the partial products with slower signal level changes are divided into two partial products received by the first adding circuit 122 and the first adding circuit 123.

[0181] In one implementation, each group of partial products in the p groups of partial products is divided into q parts according to a signal level change speed, and is divided into q partial products in the m partial products.

[0182] For example, Fig.16 In the embodiment, each of the 8 groups of partial products is divided into 4 parts according to the signal level change speed, and is divided into 4 parts of partial products corresponding to the 4 first adding circuits respectively.

[0183] In one implementation, S203 specifically includes:

[0184] S203a1. Sum the data with the fastest signal level change speed in the m first summation results to obtain a third summation result.

[0185] S203a2, summing up the data with slow signal level change speed in the m first summation results to obtain a fourth summation result.

[0186] For example, Fig.14In the embodiment, the first sub-circuit 1301 sums the data with the fastest signal level change speed among the four first summation results output by the first adding circuit (ie, the first summation result a output by the first adding circuit 120 and the first summation result b output by the first adding circuit 121) to obtain a third summation result.

[0187] The second subcircuit 1302 sums the data with slow signal level change speed among the four first summation results output by the first adding circuit (ie, the first summation result c output by the first adding circuit 122 and the first summation result d output by the first adding circuit 123) to obtain a fourth summation result.

[0188] In one implementation, S203 specifically includes:

[0189] S203b, dividing the m first summation results into s data portions according to the signal level change speed, and summing the s data portions respectively to obtain s summation results.

[0190] For example, Fig.18 In the example, the first subcircuit 1301, the second subcircuit 1302 and the third subcircuit 1303 respectively sum the three pieces of data to obtain three summation results.

[0191] In one implementation, S201 includes:

[0192] The n groups of multiplicands and multipliers are encoded in a base 2 manner to obtain n groups of partial products. Alternatively, the n groups of multiplicands and multipliers are encoded in a base 4 manner to obtain n groups of partial products. Alternatively, the n groups of multiplicands and multipliers are encoded in a base 8 manner to obtain n groups of partial products.

[0193] The present application also provides a chip, such as Fig. 20 As shown, the chip 30 includes a processor 301 and a multiplier-accumulator group 302 .

[0194] Specifically, the processor 301 may include a general-purpose central processing unit (CPU) and a memory, and the processor 301 may also be a microprocessor, a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), etc. In the scenario where the processor 301 includes a CPU and a memory, the CPU may execute computer instructions stored in the memory.

[0195] In one implementation, the processor 301 may be an NPU.

[0196] The multiplier-adder group 302 is used to perform multiplication-addition operations according to the operation process of the multiplier-adder group 10 described above in the embodiment of the present application when called by the processor 301.

[0197] In addition, the chip 30 may further include: a memory 303. The memory 303 stores computer instructions, and the processor 301 may execute the computer instructions stored in the memory.

[0198] Specifically, the memory 303 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0199] In addition, the chip 30 may further include: an interface 304. The interface 304 may be used to receive and send data. The interface 304 may be a communication interface or a transceiver.

[0200] In addition, the chip 30 may further include a communication line 305. For example, the communication line 305 may be a data bus for transmitting information between the above components.

[0201] like Fig.21 FIG. 4 is a schematic diagram of the structure of another chip provided in an embodiment of the present application. The chip 40 includes a processor 401 .

[0202] The processor 401 includes a multiplier-adder group 4011. The multiplier-adder group 4011 is used to perform a multiplication-accumulation operation according to the operation process of the multiplier-adder group 10 in the embodiment of the present application when called.

[0203] Specifically, the processor 401 may include a general-purpose central processing unit (CPU) and a memory, and the processor 301 may also be a microprocessor, a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), etc. In the scenario where the processor 401 includes a CPU and a memory, the CPU may execute computer instructions stored in the memory.

[0204] In one implementation, the processor 401 may be an NPU.

[0205] In addition, the chip 40 may further include a memory 402. The memory 402 stores computer instructions, and the processor 401 may execute the computer instructions stored in the memory.

[0206] Specifically, the memory 402 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage devices, or any other medium that can be used to carry or store program codes in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0207] In addition, the chip 40 may further include: an interface 403. The interface 403 may be used to receive and send data. The interface 403 may be a communication interface or a transceiver.

[0208] In addition, the chip 40 may further include a communication line 404. For example, the communication line 404 may be a data bus for transmitting information between the above components.

[0209] In addition, the present application also provides an electronic device. Fig. 22As shown, the electronic device 50 includes: a printed circuit board (PCB) 501 and a chip 502. The chip 502 is electrically connected to the printed circuit board 501.

[0210] The chip 502 may specifically be the chip 30 or the chip 40 mentioned above.

[0211] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0212] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0213] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical business division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0214] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A multiplier-adder group, characterized in that: include: n functional circuits, m first adding circuits and m second adding circuits; The output end of each of the functional circuits is connected to the input end of at least one of the first adding circuits, wherein at least one of the first adding circuits is connected to a plurality of the functional circuits; the output ends of the m first adding circuits are connected to the input end of the second adding circuit; n is a positive integer greater than 2, and m is a positive integer greater than 1; The functional circuit is used to output the encoded partial product after inputting the multiplicand and the multiplier; The first adding circuit is used to sum the partial products to obtain a first summation result, and output the first summation result; The second adding circuit is used to sum the first summing results to obtain a second summing result, and output the second summing result.

2. The multiplier-adder group according to claim 1, characterized in that: The n functional circuits include p functional circuits, and the output end of each functional circuit in the p functional circuits is connected to the input ends of multiple first adding circuits, wherein p is a positive integer.

3. The multiplier-adder group according to claim 2, characterized in that: The p functional circuits are used to output partial products obtained by encoding the multipliers and multiplicands at different digits in the partial products to different first adding circuits.

4. The multiplier-adder group according to claim 2, characterized in that: The p functional circuits are used to output a first set of partial products in the partial products to m1 first adding circuits, and to output a second set of partial products in the partial products to m2 first adding circuits, the m1 first adding circuits are different from the m2 first adding circuits, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

5. The multiplier-adder group according to claim 2, characterized in that: The p functional circuits are used to divide the partial product into q parts according to the signal level change speed, and output them to different first adding circuits, where q is a positive integer greater than 1.

6. The multiplier-adder group according to any one of claims 1 to 5, characterized in that: The second adding circuit comprises a first subcircuit and a second subcircuit; the first subcircuit and the second subcircuit are respectively used to sum the data from the first adding circuit; the output ends of the m first adding circuits are respectively connected to the input end of the first subcircuit and the input end of the second subcircuit; The m first adding circuits are specifically used to output the first data set in the first summation result to the first sub-circuit, and output the second data set in the first summation result to the second sub-circuit, and the signal level of the data in the first data set changes faster than the signal level of the data in the second data set.

7. The multiplier-adder group according to any one of claims 1 to 5, characterized in that: The second adding circuit includes s sub-circuits, and the s sub-circuits are respectively used to sum the data from the first adding circuit; The m first adding circuits are specifically used to divide the first summation result into s output data according to the signal level change speed, and output the s output data to the s sub-circuits respectively.

8. The multiplier-adder group according to any one of claims 1 to 7, characterized in that: The n functional circuits are respectively encoded in a radix-2 manner to obtain partial products, or the n functional circuits are respectively encoded in a radix-4 manner to obtain partial products, or the n functional circuits are respectively encoded in a radix-8 manner to obtain partial products.

9. A multiply-accumulate method, applied to a multiplier-accumulator group, characterized in that: The method comprises: Encode n groups of multiplicands and multipliers to obtain n groups of partial products; Dividing the n groups of partial products into m partial products for summing, to obtain m first summation results, wherein at least one partial product includes partial products from different groups; n is a positive integer greater than 2, and m is a positive integer greater than 1; The m first summation results are summed to obtain a second summation result.

10. The method according to claim 9, characterized in that The n groups of partial products include p groups of partial products, and each group of partial products in the p groups of partial products is divided into multiple partial products in the m groups of partial products, where p is a positive integer.

11. The method according to claim 10, characterized in that The partial products obtained by encoding the multipliers and multiplicands at different digits in the p groups of partial products are divided into different parts of the m partial products.

12. The method according to claim 10, characterized in that The first set of partial products in the p groups of partial products is divided into m1 sets of partial products in the m groups of partial products, and the second set of partial products in the p groups of partial products is divided into m2 sets of partial products in the m groups of partial products; wherein the m1 sets of partial products are different from the m2 sets of partial products, and the signal levels of the partial products in the first set of partial products change faster than those of the partial products in the second set of partial products.

13. The method according to claim 10, characterized in that Each group of partial products in the p groups of partial products is divided into q parts according to a signal level change speed, and is divided into q parts of partial products in the m parts of partial products.

14. The method according to any one of claims 9 to 13, characterized in that: The step of summing the m first summation results to obtain a second summation result includes: Summing the first data sets in the m first summation results to obtain a third summation result; The second data sets in the m first summation results are summed to obtain a fourth summation result; the signal level of the data in the first data set changes faster than the signal level of the data in the second data set.

15. The method according to any one of claims 9 to 13, characterized in that: The step of summing the m first summation results to obtain a second summation result includes: The m first summation results are divided into s portions of data according to the signal level change speed, and the s portions of data are summed respectively to obtain s summation results.

16. The method according to any one of claims 9 to 15, characterized in that: The encoding of n groups of multiplicands and multipliers to obtain n groups of partial products includes: Encode n groups of multiplicands and multipliers in a radix-2 manner to obtain n groups of partial products; or, encode n groups of multiplicands and multipliers in a radix-4 manner to obtain n groups of partial products; or, encode n groups of multiplicands and multipliers in a radix-8 manner to obtain n groups of partial products.

17. A chip, characterized in that: The chip comprises a processor and a multiplier-accumulator group as claimed in any one of claims 1 to 8.

18. The chip according to claim 17, characterized in that: The processor is a neural network processor NPU.

19. An electronic device, characterized in that: It comprises a printed circuit board and the chip as claimed in claim 17 or 18; the chip is electrically connected to the printed circuit board.

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