Control method, device and equipment of hard disk state indicator lamp and storage medium

Abstract

The embodiment of the invention provides a hard disk state indicator lamp control method and device, equipment and a storage medium. The method comprises the following steps: after a CPLD (Complex Programmable Logic Device) receives data through an SGPIO (Serial General Purpose Input / Output) interface, determining a hard disk state indication signal according to an effective flag bit and an overtime detection flag bit generated in a receiving process; wherein the effective flag bit is generated on the basis that the number of falling edges of a clock signal obtained in the data receiving process meets the number of clocks generated when the SGPIO interface sends a frame of data, and the overtime detection flag bit is used for indicating whether the SGPIO interface is suspended or not. The method is used for achieving the effect that when the Raid card is restarted to cause the SGPIO interface to be suspended, the CPLD is prevented from mistakenly reporting that a certain hard disk breaks down, so that the hard disk state indicator lamp is correct in indication.

Description

Technical Field

[0001] The present application relates to the technical field of computer hard disks, and in particular to a control method, device, equipment and storage medium for a hard disk status indicator light. Background Art

[0002] Hard disk indicator lights are commonly used in the server industry to indicate the working status of the server's hard disk, thereby helping users to promptly identify and resolve potential problems.

[0003] The server backplane is connected to the built-in disk array card (Redundant Array of IndependentDisks Card, referred to as Raid card) through a connecting line. The Raid card collects the status information of each hard disk on the backplane, and sends the hard disk status information in the form of SGPIO bus signals through the serial general purpose input / output (Serial General Purpose Input / Output, referred to as SGPIO) interface to the complex programmable logic device (Complex Programmable Logic Device, referred to as CPLD) or field programmable gate array (Field Programmable Gate Array, referred to as FPGA) for analysis. The CPLD or FPGA then controls the high and low levels of the output port according to the analysis results to achieve control of the hard disk indicator light.

[0004] However, when the Raid card restarts and causes the SGPIO interface to hang, the CPLD will mistakenly determine that a hard disk has failed, resulting in incorrect hard disk indicator indication. Summary of the invention

[0005] The embodiments of the present application provide a control method, device, equipment and storage medium for a hard disk status indicator light, so as to avoid the CPLD from falsely reporting a hard disk failure when the SGPIO interface is hung due to the restart of the Raid card, thereby making the hard disk status indicator light indicate the correct effect.

[0006] In a first aspect, an embodiment of the present application provides a method for controlling a hard disk status indicator light, comprising:

[0007] After receiving data through the SGPIO interface, the hard disk status indication signal is determined according to the valid flag bit and the timeout detection flag bit generated during the receiving process; wherein the valid flag bit is generated when the number of falling edges of the clock signal obtained during the data receiving process meets the number of clocks generated by the SGPIO interface to send a frame of data, and the timeout detection flag bit is used to indicate whether the SGPIO interface is hung;

[0008] The hard disk status indicator light is controlled according to the hard disk status indication signal.

[0009] In a possible implementation, in combination with the first aspect, the method further includes:

[0010] Each time a falling edge of the Load signal of the SGPIO interface is detected, starting to count the falling edges of the clock signal of the SGPIO interface;

[0011] The counting is stopped when it is detected that the Load signal of the SGPIO interface is at a high level, and the valid flag is generated when the number of falling edges of the clock signal obtained by this counting is consistent with the number of clocks that should be generated for each frame of data.

[0012] In a possible implementation, in combination with the first aspect, the method further includes:

[0013] Determine whether the SGPIO interface is hung according to a preset timeout parameter value;

[0014] If it is determined that the SGPIO interface is hung, the preset timeout detection flag is set to a low level to indicate that the SGPIO interface is hung.

[0015] In a possible implementation, in combination with the first aspect, the method for determining whether the SGPIO interface is hung according to a preset timeout parameter value further includes:

[0016] When a falling edge of the Load signal of the SGPIO interface is detected, the timeout detection flag is set, and the timeout detection flag is combined with the timeout parameter value to obtain a target value;

[0017] After the falling edge of the Load signal, each time the system clock undergoes a periodic change, the target value is subtracted by one to obtain a new target value, and this step is repeated until the new target value reaches the timeout parameter value, and it is determined that the SGPIO interface is hung.

[0018] In a possible implementation, in combination with the first aspect, the method for determining whether the SGPIO interface is hung according to a preset timeout parameter value further includes:

[0019] If the new target value has not reached the timeout parameter value when the rising edge of the Load signal of the SGPIO interface is detected after the falling edge of the Load signal, it is determined that the SGPIO interface is not hung.

[0020] In a possible implementation, in combination with the first aspect, the method for determining the hard disk status indication signal according to the valid flag bit and the timeout detection flag bit generated during the receiving process further includes:

[0021] If the valid flag is valid, and the timeout detection flag indicates that the SGPIO interface is not hung, determining the hard disk status indication signal according to the latched data;

[0022] If the valid flag is invalid, or the timeout detection flag indicates that the SGPIO interface is hung, all latched data are set to 0, and the hard disk status indication signal is determined.

[0023] In a possible implementation, in combination with the first aspect, the method further includes:

[0024] The timeout parameter value is determined according to the time size of each frame of data.

[0025] In a possible implementation, in combination with the first aspect, the method for determining the timeout parameter value according to the time size of each frame of data further includes:

[0026] The time size of each frame of data is multiplied by a preset coefficient to obtain the timeout parameter value.

[0027] In a second aspect, an embodiment of the present application provides a control device for a hard disk status indicator light, comprising:

[0028] A processing module is used to determine the hard disk status indication signal according to the valid flag bit and the timeout detection flag bit generated during the receiving process after receiving the data through the SGPIO interface. The valid flag bit is generated when the number of falling edges of the clock signal obtained during the data receiving process meets the number of clocks generated by the SGPIO interface to send a frame of data, and the timeout detection flag bit is used to indicate whether the SGPIO interface is hung;

[0029] The control module is used to control the hard disk status indicator light according to the hard disk status indication signal.

[0030] In a third aspect, an embodiment of the present application provides a controller device, including: a memory, a processor;

[0031] The memory stores computer-executable instructions;

[0032] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0033] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.

[0034] The control method, device, equipment and storage medium of the hard disk status indicator provided in the embodiment of the present application, after receiving data through the SGPIO interface, determines the hard disk status indication signal according to the valid flag bit and the timeout detection flag bit generated during the receiving process, and then controls the hard disk status indicator according to the hard disk status indication signal. Through the above means, when the SGPIO interface is hung due to the restart of the Raid card, the CPLD is prevented from falsely reporting that a hard disk has failed, so that the hard disk status indicator indicates the correct effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 A schematic diagram of a scenario of a hard disk status indicator light control method, device, equipment, and storage medium provided in the present application;

[0037] Figure 2 A flowchart of a first embodiment of a method for controlling a hard disk status indicator light provided in the present application;

[0038] Figure 3 A logic block diagram of Embodiment 1 of a method for controlling a hard disk status indicator light provided in the present application;

[0039] Figure 4 A flowchart of a second embodiment of a method for controlling a hard disk status indicator light provided in the present application;

[0040] Figure 5 A flowchart of a third embodiment of a method for controlling a hard disk status indicator light provided in the present application;

[0041] Figure 6 A schematic diagram of the structure of the control device for the hard disk status indicator light provided in this application;

[0042] Figure 7 A schematic diagram of the structure of the controller device provided in this application.

[0043] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0044] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0045] First, the terms involved in this application are explained:

[0046] Disk array card: Redundant Array of Independent Disks Card, referred to as Raid card, is used to manage and control the work of multiple hard disks and can be used to collect hard disk status information.

[0047] Complex Programmable Logic Device: CPLD is a programmable logic device used to implement digital circuit systems. In the server environment, CPLD is used to implement various complex logic control functions, such as interface management, signal processing, etc. It implements specific logic functions through programming, thereby coordinating the work of various components inside the server, including communication with hard disks and RAID cards.

[0048] Hard disk status indicator: It is an LED light used to indicate the hard disk read / write status, usually located in the hard disk area on the front panel of the server chassis. When the hard disk is reading or writing, the indicator light will flash or change color to indicate the working status of the hard disk, mainly to indicate the hard disk read / write status, diagnose hard disk failures, and monitor hard disk activities.

[0049] Serial General Purpose Input / Output, referred to as SGPIO, is a method of serial general purpose IO signals, usually used for communication between an initiator (such as a host bus adapter) and a target (such as a backplane). The target usually converts the output serial signal into multiple parallel signals and provides input signals through GPIO. SGPIO is usually used in high-speed storage interfaces such as Serial Advanced Technology Attachment (SATA), and contains four groups of interface signals, namely SClock signal, SLoad signal, SDataOut signal, and SDataIn signal. These signals are used for data transmission and signal control through specific timing and protocols. Specifically, the target uses the falling edge of SClock to lock SLoad and SDataOut, while the initiator uses the same SClock falling edge to lock SDataIn to ensure correct data transmission and accurate signal control. The SGPIO bus specification is defined by SFF-8485, which is an industry standard developed by the SFF committee, providing a common definition suitable for system manufacturers, system integrators, and suppliers.

[0050] Clock signal: refers to the SClock signal, referred to as the Clock signal in this application, which is the basic clock signal in SGPIO communication and is used to synchronize the start and end of data transmission.

[0051] Loading signal: refers to the SLoad signal, which is referred to as the Load signal in this application. It is usually used to indicate the loading status of data, indicating when a frame of data ends and restarts. It can be high-level valid or low-level valid, depending on the specific hardware implementation. When the SLoad signal is high-level valid, the SLoad signal is high to indicate that no data is loaded, and the SLoad signal is low to indicate that data is loaded; when SLoad is low-level valid, SLoad is low to indicate that no data is loaded, and the SLoad signal is high to indicate that data is loaded. In practical applications, the SLoad signal is usually detected through a circuit or an input pin of a microcontroller. When a change in the SLoad signal is detected, the microcontroller can take corresponding measures, such as starting to read data or preparing to receive new data.

[0052] Serial data output signal: refers to the SDataOut signal, which is referred to as the Data signal in this application. It is generally used to send data in SGPIO communication. The initiator controls the high and low levels of the SDataOut signal and sends data serially bit by bit through the shift register. The SDataOut signal carries the output bit associated with the disk drive on the target backplane and can be used to control the hard disk status indicator.

[0053] Serial data input signal: refers to the SDataIn signal, which is a serial data input signal that carries the input bit associated with the disk drive on the target backplane and is intended to report information such as drive presence detection. Not all initiators and targets support the SDataIn signal.

[0054] Falling edge: In the SGPIO protocol, the falling edge refers to the moment when the signal level changes from a high level (digital "1") to a low level (digital "0"). The falling edge and the rising edge (the moment when the signal level changes from a low level to a high level) together constitute the basic change pattern of the digital signal, which is crucial to the design and logical operation of digital systems and is often used in timing control, signal locking, and data synchronization.

[0055] Falling edge sampling: In the SGPIO protocol, falling edge sampling refers to a data sampling mechanism in which data collection occurs at the falling edge of the clock signal. Specifically, when the clock signal in the SGPIO signal changes from a high level to a low level, that is, at its falling edge, the data is sampled. This mechanism ensures the accuracy and synchronization of data transmission and is an important part of the data transmission mechanism in the SGPIO protocol. In the SGPIO protocol, the sender (initiator) and receiver (target) of the data communicate data in this way, ensuring the correctness and reliability of data transmission.

[0056] Rising edge: In the SGPIO protocol, the rising edge refers to the moment when the digital signal changes from a low level (logic "0") to a high level (logic "1"). In digital circuits and communication systems, the rising edge usually indicates the starting edge of the signal state, that is, the transition point from nothing to something.

[0057] Clock frequency: refers to the basic frequency of the clock in the synchronous circuit, which is measured in "several cycles per second".

[0058] Locking: In digital communication and signal processing, locking usually refers to the synchronization or coordination between signals. In SGPIO communication, locking means that the target party should use the falling edge of SClock to synchronize the SLoad signal and the SData signal, that is, the change or status update of the SLoad signal and the SDataOut signal should be consistent with the falling edge of the SClock signal. Specifically, when the falling edge of the SClock signal occurs, the status of the SLoad signal and the SDataOut signal should be stable, thereby ensuring that the data can be correctly read or processed before the next rising edge of the SClock signal arrives. This synchronization mechanism is very important in digital communication systems, which can avoid errors or conflicts in data transmission. By accurately controlling the synchronization of signals, the integrity of the data and the stability of the system can be ensured.

[0059] Flags: In CPLD, they are usually used to indicate the result status of a certain condition or operation. These flags can be used to control flow, data flow, or perform specific operations. Depending on the specific logic design, flags may have different meanings and uses. Flags are usually associated with the Arithmetic and Logic Unit (ALU), which is responsible for performing arithmetic and logical operations and setting corresponding flags based on the results of the operations. The program can determine the next operation or control flow by checking the status of these flags.

[0060] Hard Disk Drive: Hard Disk Drive, referred to as HDD, is one of the main devices in a computer for storing data and programs.

[0061] Data counter: In a programmable logic device (CPLD), a data counter is a basic digital circuit component used to count input clock pulses to achieve a specific counting function. Specifically, a data counter counts a certain value based on the input clock signal and generates an output signal when the preset value is reached.

[0062] Wave meter: The wave meter in the programmable logic device CPLD is mainly used for frequency measurement. By combining the microcontroller and the programmable logic device, a technology called equal-precision frequency measurement is realized.

[0063] Figure 1 A schematic diagram of a scenario of a hard disk status indicator light control method, device, equipment, and storage medium provided in the present application, such as Figure 1The application environment shown includes a disk array card 101, a programmable logic device 102, and a hard disk status indicator light 103. The disk array card 101 collects hard disk status information, sends data to the programmable logic device 102 through the SGPIO interface, and the programmable logic device 102 parses the data and determines a hard disk status indication signal, and controls the hard disk status indicator light 103 through the hard disk status indication signal.

[0064] In combination with the above scenario, it can be seen that in the prior art, the SGPIO interface data containing the hard disk status information is parsed by the programmable logic device CPLD to control the hard disk indicator light. When the Raid card restarts and causes the SGPIO interface to hang, the Clock signal of the SGPIO interface has no clock output, and the Load signal and the Data signal are forcibly pulled high according to the definition involved in the hardware. There is a technical problem that when the Raid card restarts and causes the SGPIO interface to hang, the CPLD falsely reports that the hard disk has failed, which in turn causes the hard disk status indicator light to be incorrect.

[0065] The control method, device, equipment and storage medium of the hard disk status indicator light provided in the present application, by generating a valid flag bit and a timeout detection flag bit, and controlling the hard disk status indicator light based on the valid flag bit and the timeout detection flag bit, solves the technical problem that when the Raid card restarts, the CPLD falsely reports a hard disk failure, resulting in incorrect indication of the hard disk status indicator light.

[0066] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0067] Figure 2 This is a flow chart of a first embodiment of a method for controlling a hard disk status indicator light provided in the present application. Figure 2 As shown, the method includes:

[0068] S201. After receiving data through the SGPIO interface, determine a hard disk status indication signal according to a valid flag bit and a timeout detection flag bit generated during the receiving process.

[0069] Among them, the valid flag is generated when the number of falling edges of the clock signal obtained during the data reception process meets the number of clocks generated by the SGPIO interface to send a frame of data, and the timeout detection flag is used to indicate whether the SGPIO interface is hung.

[0070] During the operation of the server hard disk, the Raid card collects the status information of the hard disk, and sends the hard disk status information to the CPLD connected to it through the SGPIO interface. The data sent by the SGPIO interface includes the Clock signal, the Load signal and the Data signal. Among them, the Clock signal is the basic clock signal in the SGPIO communication; the Load signal is usually used to indicate the loading status of the data, indicating when a frame of data ends and restarts. The Load signal can be high level valid or low level valid, which depends on the specific hardware implementation. In the embodiment of the present application, the Load signal is high level valid, and its signal is high to indicate that there is no data loaded, and low to indicate that there is data loaded; the Data signal is a serial data output signal, carrying the hard disk status information, and the high and low levels of the Data signal are controlled by the initiator, and the data is sent serially by the shift register. The SGPIO interface will continuously send data containing the hard disk status information to the CPLD, and the CPLD will parse the data after receiving it, and control the hard disk status indicator to indicate the corresponding hard disk status according to the parsed result. In the embodiment of the present application, the processing method of the CPLD for a received frame of data is mainly described.

[0071] In the above process, since the CPLD usually detects the change of the Load signal and determines whether to start reading, latching and forwarding data and prepare to receive new data according to the rising and falling edges of the Load signal transmitted from the SGPIO interface, it does not calculate the number of falling edges of the Clock signal of the SGPIO interface during the data reception process. Therefore, when the Raid card restarts and causes the SGPIO interface to hang, the Clock signal of the SGPIO interface will have no clock output, and the Load signal and Data signal will be forcibly pulled high according to the definition of the hardware design, which will cause the hard disk status indication signal determined by the CPLD to be incorrect, and a certain hard disk will be falsely reported as faulty; at the same time, since it is unclear when the Raid card restart causes the SGPIO interface to hang, the CPLD falsely reports that the faulty hard disk is random.

[0072] In order to solve the above problem, this embodiment determines whether the data received by the CPLD is complete according to the valid flag generated during the receiving process, thereby determining the hard disk status indication signal. Specifically, each time the falling edge of the Load signal of the SGPIO interface is detected, the falling edge of the clock signal of the SGPIO interface is counted, and when the Load signal of the SGPIO interface is detected to be at a high level, the counting is stopped, and when the number of falling edges of the clock signal obtained by this count is consistent with the number of clocks that should be generated for each frame of data, a valid flag is generated. If the valid flag is valid, it means that the data received by the CPLD is complete.

[0073] However, the fact that the data received by the CPLD is complete does not mean that the data is correct. If the Raid card restarts after sending a frame of data, causing the SGPIO interface to hang, the Load signal and the Data signal will both be high, causing the CPLD to falsely report that the last hard disk has failed.

[0074] In order to solve the above problem, this embodiment determines whether the CPLD receives data in timeout according to the timeout detection flag generated during the receiving process, and determines whether the data received by the CPLD has problems. Specifically, it is determined whether the SGPIO interface is hung according to the preset timeout parameter value. If it is determined that the SGPIO interface is hung, the preset timeout detection flag is set to a low level to indicate that the SGPIO interface is hung; otherwise, the preset timeout detection flag is set to a high level to indicate that the SGPIO interface is not hung.

[0075] The specific process of determining whether the SGPIO interface is hung according to the preset timeout parameter value is as follows: when the CPLD detects the falling edge of the Load signal, the timeout parameter value is preset, and the timeout parameter value is obtained by multiplying the time required for the SGPIO interface to send a frame of data by the preset coefficient, and then a timeout detection flag is preset, and the timeout parameter value and the timeout detection flag are combined to obtain a target value. After the CPLD detects the falling edge of the Load signal, every time the system clock of the CPLD changes once a cycle, the target value is reduced by one to obtain a new target value, and this step is repeated until the new target value reaches the timeout parameter value, indicating that the data transmission has timed out, and it is determined that the SGPIO interface is hung; if the new target value has not reached the timeout parameter value at this time, it means that the data transmission has not timed out, and it is determined that the SGPIO interface is not hung.

[0076] In a specific implementation, if the valid flag is valid, and the timeout detection flag indicates that the SGPIO interface has not been hung, the hard disk status indication signal is determined according to the latched data. The validity of the valid flag indicates that the received data content is complete, and the timeout detection flag indicates that the SGPIO interface has not been hung, indicating that the received data content is correct, and will not falsely report that the last hard disk has failed. The received data can be directly used to determine the hard disk status indication signal. If the valid flag is invalid, or the timeout detection flag indicates that the SGPIO interface has been hung, all the latched data are set to 0, and the hard disk status indication signal is determined. The invalid valid flag indicates that the received data content is incomplete, and the timeout detection flag indicates that the SGPIO interface has been hung, indicating that the received data content is wrong and cannot correctly reflect the hard disk status. If the received Data data is used to determine the hard disk status indication signal, it will cause the CPLD to falsely report that the hard disk has failed. Therefore, by setting all the latched data to 0, the received data is avoided from being forwarded, resulting in incorrect indication of the hard disk status indicator. Setting all the latched data to 0 means that the hard disk has no status data. The following is a detailed description of the process of receiving a frame of data: When the CPLD detects the falling edge of the Load signal, it means that the SGPIO interface starts to transmit a frame of data. At this time, the CPLD starts to parse the data and latch it into data A. When the CPLD detects the rising edge of the Load signal, it determines whether to use data A according to the valid flag and the timeout detection flag. In the process of CPLD receiving data, when the number of falling edges of the detected SGPIO interface clock signal meets the conditions, the data valid signal in the CPLD will generate a pulse from low to high, which can be considered to generate a valid flag or the valid flag is valid; on the contrary, if no pulse from low to high is generated, it is considered that no valid flag is generated or the valid flag is invalid; when the data transmission time of the SGPIO interface exceeds the preset timeout parameter value, it indicates that the SGPIO interface is hung, which can be considered to generate a timeout detection flag or the timeout detection flag is valid. On the contrary, if the data transmission time of the SGPIO interface does not exceed the preset timeout parameter value, it is considered that no timeout detection flag is generated or the timeout detection flag is invalid. If the valid flag is valid and the timeout detection flag is invalid, data A is latched into data B; if the timeout detection flag is valid, a string of data all "0" is defined to be latched into data B; if the valid flag is invalid, a string of data all "0" is defined to be latched into data B. When the CPLD detects the falling edge of the Load signal again, data B is latched into data C, and data C is grouped according to the preset strategy, the status information of each disk is redefined, and the hard disk status indication signal is determined. Through this implementation, a correct hard disk status indication signal can be obtained.

[0077] In a specific implementation, because the SGPIO interface will cause the CPLD to falsely report a hard disk failure when it is just powered on, in the embodiment of the present application, the CPLD will also filter the forwarded data, which is mainly reflected in not using the first three frames of data sent from the SGPIO interface and not forwarding them to realize the hard disk lighting control. Specifically, after the CPLD detects the falling edge of the Load signal of the SGPIO interface three times in a row, that is, when the falling edge of the Load signal is detected for the fourth time, it will actually start to receive the data sent by the master device through the SGPIO interface.

[0078] In a specific embodiment, Figure 3 As shown, after receiving the data through the SGPIO interface, the CPLD parses the data, converts the serial data into parallel data, and generates a valid flag and a timeout detection flag. After parsing the SGPIO interface data, according to the rising and falling edges of the Load signal, combined with the valid flag and the timeout detection flag, it is determined whether to latch and send a complete frame of data. If it is determined that the received data is complete and correct, the CPLD will latch the data; if it is determined that the received data is incorrect, the CPLD will define a full "0" data for latching. After the latching is completed, the CPLD will split the hard disk status information contained in the latched data according to the preset strategy, redefine the status information of each hard disk, determine the hard disk status indication signal, and forward it through the interface. The hard disk status indication signal includes the HDD_DATA_ACTIVE signal, indicating whether the hard disk is performing a read and write operation; the HDD_DATA_LOCATE signal, indicating whether the hard disk is located; the HDD_DATA_FAULT signal, indicating whether the hard disk has failed. Through this implementation, a correct hard disk status indication signal can be obtained.

[0079] S202: Control the hard disk status indicator light according to the hard disk status indication signal.

[0080] In this step, the hard disk status indication signal includes the HDD_DATA_ACTIVE signal, the HDD_DATA_LOCATE signal, and the HDD_DATA_FAULT signal. The hard disk status indicator is used to indicate the hard disk read and write status, diagnose hard disk faults, and monitor hard disk activities. It provides an intuitive display of the hard disk working status and plays an important role in fault diagnosis and prevention. The CPLD forwards the determined hard disk status indication signal and controls the hard disk status indicator through a preset strategy.

[0081] Specifically, taking the HDD hard disk as an example, its hard disk status is divided into active (read and write operation), locate (located), and fault (faulty). When the hard disk status indication signals are all "0", that is, the relevant signal interfaces are all low level, it means that there is no data output, and the hard disk status indicator is always on; when the hard disk status indication signal HDD_DATA_FAULT is high level, it means that the hard disk has failed, and the hard disk status indicator is red; when the hard disk status indication signals HDD_DATA_LOCATE and HDD_DATA_FAULT are both high level, it means that the hard disk is in the rebuilding state, and the hard disk status indicator is yellow and flashes regularly.

[0082] The control method of the hard disk status indicator light provided in the embodiment of the present application determines whether the received data has a problem by using the valid flag bit and the timeout detection flag bit generated in the process of receiving SGPIO interface data, and then determines the hard disk status indication signal. According to the hard disk status indication signal, the means of controlling the status indicator light of the hard disk is realized, so that when the SGPIO interface is hung due to the restart of the Raid card, the CPLD is prevented from falsely reporting that a hard disk has failed without relying on the supplier to modify the code or the hardware design changes, thereby solving the problem of incorrect indication of the hard disk status indicator light.

[0083] Figure 4 This is a flow chart of Embodiment 2 of the method for controlling the hard disk status indicator light provided in this application, as shown in FIG. Figure 4 As shown, in this embodiment Figure 2 Based on the embodiment, the generation of the valid flag bit is specifically implemented by the following steps:

[0084] S301 . Each time a falling edge of a Load signal of an SGPIO interface is detected, start counting falling edges of a clock signal of the SGPIO interface.

[0085] In this step, the falling edge refers to the moment when the signal changes from a high level to a low level. During the data transmission process of the SGPIO interface, the Load signal is always at a low level. Detecting the falling edge of the Load signal of the SGPIO interface indicates that the SGPIO interface starts to transmit data. By counting the falling edges of the clock signal of the SGPIO interface, the number of clocks generated during the data transmission process can be obtained.

[0086] S302, when it is detected that the Load signal of the SGPIO interface is at a high level, the counting is stopped, and when the number of falling edges of the clock signal obtained by this counting is consistent with the number of clocks that should be generated for each frame of data, a valid flag is generated.

[0087] In this step, when the Load signal of the SGPIO interface is detected to be high, it means that the SGPIO interface has completed the transmission of a frame of data. The number of clocks that should be generated for each frame of data can be calculated based on the specific hardware design, clock frequency, and data width. If the falling edge count of the clock signal generated during the transmission of a frame of data is consistent with the number of clocks that should be generated for each frame of data, it means that the SGPIO interface has sent a complete frame of data.

[0088] In a specific embodiment, it is assumed that the number of clocks that the SGPIO interface should generate for each frame of data is 12, and a data counter is set. When the CPLD detects that the Load signal is at a high level, the data counter is set to the maximum value "12". When the CPLD detects the falling edge of the Load signal, it starts to receive the first Data data and synchronously latches the Data data. At this time, the data counter is 12. After that, each time a falling edge of the Clock signal of the SGPIO interface is detected, the counter is reduced by one, and the Data data is synchronously latched. When the value of the data counter becomes 1, the data counter is locked and the Load signal is synchronously detected. If the data counter is 1 and the Load signal is at a high level at this time, it means that the number of falling edges of the clock signal obtained by this count is consistent with the number of clocks that should be generated for each frame of data. The data valid signal in the CPLD will generate a pulse from low to high, which can be regarded as generating a valid flag bit, indicating that the received data is complete.

[0089] The method for generating a valid flag bit provided in an embodiment of the present application starts counting the falling edges of the clock signal each time the falling edge of the Load signal of the SGPIO interface is detected, stops counting when the Load signal of the SGPIO interface is detected to be at a high level, and generates a valid flag bit when the number of falling edges of the clock signal obtained by this count is consistent with the number of clocks that should be generated for each frame of data, thereby determining whether the frame of data sent by the SGPIO interface is complete, thereby achieving the effect of making the hard disk status indicator light indicate correctly.

[0090] Figure 5 This is a flow chart of Embodiment 3 of the method for controlling the hard disk status indicator light provided in the present application, as shown in FIG. Figure 5 As shown, in this embodiment Figure 2 Based on the embodiment, the determination of the timeout detection flag is specifically implemented by the following steps:

[0091] S401: Determine whether a SGPIO interface is hung according to a preset timeout parameter value.

[0092] In this step, the timeout parameter value is determined according to the time size of each frame of data. The time size of each frame of data is multiplied by a preset coefficient to obtain the timeout parameter value. Among them, the preset coefficient is at least 1, not more than 2, and preferably 1.5. By multiplying by a preset coefficient, it is possible to adapt to the clock deviation in the signal transmission process and compensate for the impact caused by transmission delay; the time size of each frame of data can be measured by a oscilloscope, or it can be calculated based on the number of clocks that should be generated for each frame of data and the clock frequency. Among them, the clock frequency refers to the basic frequency of the clock in the synchronous circuit, which is measured in "several cycles per second". If the data transmission time exceeds the timeout parameter value, it is determined that the SGPIO interface is hung; if the data transmission time does not exceed the timeout parameter value, it is determined that the SGPIO interface is not hung.

[0093] Specifically, first, when the falling edge of the Load signal of the SGPIO interface is detected, the timeout detection flag is set, and the timeout detection flag is combined with the timeout parameter value to obtain a target value; then, every time the CPLD system clock changes once a cycle, the target value is reduced by one to obtain a new target value, and this step is repeated until the new target value reaches the timeout parameter value, and it is determined that the SGPIO interface is hung. If after the falling edge of the above-mentioned Load signal, when the rising edge of the Load signal of the SGPIO interface is detected, the new target value has not reached the timeout parameter value, it is determined that the SGPIO interface is not hung.

[0094] In a specific implementation, the time size of each frame of data is obtained by calculation, and the timeout parameter value is obtained by multiplying it by a preset coefficient. Assuming that the clock frequency of the SGPIO interface to send data is 8KHz, that is, the time size of a clock cycle is 0.125ms, and each frame of data contains 12 clock numbers, it can be obtained that the time size of the SGPIO interface to send a frame of data is 1.5ms, which is multiplied by the preset coefficient 1.5, and the preset timeout is calculated to be 2.25ms. The preset value of the timeout detection parameter is sampled under the system clock of the CPLD. The system clock frequency of the CPLD is 50MHz, that is, the time size of a clock cycle is 40ns. The timeout parameter value is embodied in the CPLD using the number of system clocks. The timeout time 2.25ms is divided by the time of one clock cycle of the CPLD system clock 40ns, and the timeout detection parameter value is obtained as 56250 system clocks.

[0095] S402: If it is determined that the SGPIO interface is hung, a preset timeout detection flag is set to a low level to indicate that the SGPIO interface is hung.

[0096] It should be noted that if it is determined that the SGPIO interface is not hung, the preset timeout detection flag is set to a high level.

[0097] In a specific implementation, the time size of each frame of data is measured by a wave meter, and then a timeout parameter value is preset. The timeout parameter value is determined by multiplying the time size of each frame of data by a preset coefficient, and the preset coefficient is 1.5. When the CPLD detects the falling edge of the Load signal, a variable timeout detection flag is set to 1 (high level), and the timeout detection flag is merged with the timeout parameter value, and a new variable target value A is set. The timeout detection flag is defined as the highest bit of the target value A, and the target value A is a counter. In the process of sending data through the SGPIO interface, the Load signal is a low level. When the Load signal is at a low level and the highest bit of the target value A is 1, a subtraction operation is performed on the target value A. Whenever the system clock of the CPLD changes once a cycle, the target value A is reduced by one. When the target value A is deducted from the timeout parameter value, the highest bit of the target value A changes from 1 to 0, indicating that the SGPIO interface is hung. The highest bit of the target data A is the timeout detection flag, that is, the timeout detection flag changes from 1 (i.e., high level) to 0 (i.e., low level), which determines that the SGPIO interface is hung. If the timeout detection flag is 1 when the rising edge of the Load signal of the SGPIO interface is detected, it is determined that the SGPIO interface is not hung. The CPLD determines whether the latched Data needs to be sent out based on the situation of the timeout detection flag. If the timeout detection flag is valid, that is, the timeout detection flag is low, the CPLD defines the data to be sent as all "0".

[0098] In a specific implementation, when the CPLD detects the falling edge of the Load signal of the SGPIO interface, the timeout detection flag and the timeout detection valid flag are set to 1 (i.e., a high level), the timeout detection flag and the timeout time parameter value form a target value B, and the timeout detection flag is set to the highest bit of the target value B. When the Load signal is at a low level and the highest bit of the target value B is 1, a subtraction operation is performed on the target value A, and each time the system clock of the CPLD changes once a cycle, the target value B is reduced by one. After the target value B is subtracted from the timeout time parameter value, the highest bit of the target value B changes from 1 to 0, that is, the timeout detection flag changes from 1 to 0. The change of the timeout detection flag from 1 to 0 will trigger the change of the timeout detection valid flag from 1 (high level) to 0 (low level), indicating that the SGPIO interface is hung. It should be noted that, in this implementation, the initial value of the timeout detection valid flag can also be set to 0 (low level). The timeout detection flag changing from 1 to 0 will trigger the timeout detection valid flag to change from 0 (low level) to 1 (high level), thereby determining that the SGPIO interface is hung.

[0099] The method for determining the timeout detection flag provided in the embodiment of the present application determines whether the SGPIO interface is hung according to a preset timeout parameter value, thereby avoiding the SGPIO interface being hung when the Raid card restarts after sending a frame of data, causing the Load signal and the Data signal to be high at this time, causing the CPLD to falsely report that the last hard disk has failed, thereby achieving the effect of making the hard disk status indicator light indicate correctly.

[0100] Figure 6 A structural diagram of the control device for the hard disk status indicator light provided in this application, such as Figure 6 As shown, the control device 50 of the hard disk status indicator light provided in this embodiment includes:

[0101] The processing module 501 is used to determine the hard disk status indication signal according to the valid flag bit and the timeout detection flag bit generated in the receiving process after receiving data through the SGPIO interface. The valid flag bit is generated when the number of falling edges of the clock signal of the SGPIO interface obtained in the data receiving process meets the number of clocks generated by the SGPIO interface to send a frame of data, and the timeout detection flag bit is used to indicate whether the SGPIO interface is hung;

[0102] The control module 502 is used to control the hard disk status indicator light according to the hard disk status indication signal.

[0103] In a possible implementation, after receiving data through the SGPIO interface, the processing module 501 determines the hard disk status indication signal according to the valid flag bit and the timeout detection flag bit generated during the receiving process.

[0104] The specific process of the processing module 501 generating a valid flag is as follows: each time a falling edge of the Load signal of the SGPIO interface is detected, the falling edges of the clock signal of the SGPIO interface are started to be counted; when the Load signal of the SGPIO interface is detected to be at a high level, the counting is stopped; and when the number of falling edges of the clock signal obtained by this count is consistent with the number of clocks that should be generated for each frame of data, a valid flag is generated.

[0105] The processing module 501 determines whether the SGPIO interface is hung according to the preset timeout parameter value. The specific process is as follows: when the processing module 501 detects the falling edge of the Load signal of the SGPIO interface, the time size of each frame of data is multiplied by a preset coefficient to obtain the timeout parameter value. At the same time, the processing module 501 sets the timeout detection flag bit, and merges the timeout detection flag bit with the timeout parameter value to obtain the target value. After the processing module 501 detects the falling edge of the Load signal, whenever the system clock of the CPLD changes once a cycle, the target value is reduced by one to obtain a new target value, and this step is repeated until the new target value reaches the timeout parameter value, and the processing module 501 determines that the SGPIO interface is hung. If it is determined that the SGPIO interface is hung, the preset timeout detection flag bit is set to a low level to indicate that the SGPIO interface is hung. If the valid flag bit is valid, and the timeout detection flag bit indicates that the SGPIO interface is not hung, the processing module 501 determines the hard disk status indication signal according to the latched data. If the valid flag is invalid, or the timeout detection flag indicates that the SGPIO interface is hung, the processing module 501 sets all latched data to 0 and determines the hard disk status indication signal.

[0106] The control module 502 controls the status indicator light of the hard disk according to the hard disk status indication signal. The hard disk status indication signal includes a HDD_DATA_ACTIVE signal, a HDD_DATA_LOCATE signal, and a HDD_DATA_FAULT signal. In a HDD hard disk, when all the hard disk status indication signals are "0", that is, all the related signal interfaces are at a low level, the status indicator light of the hard disk is displayed as always on; when the hard disk status indication signal HDD_DATA_FAULT is at a high level, it means that the hard disk has failed, and the status indicator light of the hard disk is displayed as red; when the hard disk status indication signals HDD_DATA_LOCATE and HDD_DATA_FAULT are both at a high level, it means that the hard disk is in a rebuilding state, and the status indicator light of the hard disk is displayed as yellow and flashes regularly.

[0107] The control device for the hard disk status indicator light provided in the above-mentioned embodiments is used to execute the control method for the hard disk status indicator light in any of the above-mentioned method embodiments. Its implementation principle and technical effect are similar and will not be repeated here.

[0108] Figure 7 This is a schematic diagram of the structure of the controller device provided in this application. Figure 7 As shown, the electronic device 60 provided in this embodiment includes: at least one processor 601 and a memory 602. Optionally, the device 60 also includes a communication component 603. The processor 601, the memory 602 and the communication component 603 are connected via a bus 604.

[0109] In a specific implementation process, at least one processor 601 executes the computer execution instructions stored in the memory 602, so that at least one processor 601 executes the above method.

[0110] The specific implementation process of the processor 601 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0111] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0112] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0113] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0114] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0115] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0116] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0117] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0118] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0122] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0123] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for controlling a hard disk status indicator light, characterized in that: include: After receiving data through the SGPIO interface, the hard disk status indication signal is determined according to the valid flag bit and the timeout detection flag bit generated during the receiving process; wherein the valid flag bit is generated when the number of falling edges of the clock signal obtained during the data receiving process meets the number of clocks generated by the SGPIO interface to send a frame of data, and the timeout detection flag bit is used to indicate whether the SGPIO interface is hung; The hard disk status indicator light is controlled according to the hard disk status indication signal.

2. The method according to claim 1, characterized in that The method further comprises: Each time a falling edge of the Load signal of the SGPIO interface is detected, starting to count the falling edges of the clock signal of the SGPIO interface; The counting is stopped when it is detected that the Load signal of the SGPIO interface is at a high level, and the valid flag is generated when the number of falling edges of the clock signal obtained by this counting is consistent with the number of clocks that should be generated for each frame of data.

3. The method according to claim 2, characterized in that The method further comprises: Determine whether the SGPIO interface is hung according to a preset timeout parameter value; If it is determined that the SGPIO interface is hung, the preset timeout detection flag is set to a low level to indicate that the SGPIO interface is hung.

4. The method according to claim 3, characterized in that The determining, according to a preset timeout parameter value, whether the SGPIO interface is hung includes: When a falling edge of the Load signal of the SGPIO interface is detected, the timeout detection flag is set, and the timeout detection flag is combined with the timeout parameter value to obtain a target value; After the falling edge of the Load signal, each time the system clock undergoes a periodic change, the target value is subtracted by one to obtain a new target value, and this step is repeated until the new target value reaches the timeout parameter value, and it is determined that the SGPIO interface is hung.

5. The method according to claim 4, characterized in that The method further comprises: If the new target value has not reached the timeout parameter value when the rising edge of the Load signal of the SGPIO interface is detected after the falling edge of the Load signal, it is determined that the SGPIO interface is not hung.

6. The method according to any one of claims 1 to 5, characterized in that: The step of determining the hard disk status indication signal according to the valid flag bit and the timeout detection flag bit generated during the receiving process includes: If the valid flag is valid, and the timeout detection flag indicates that the SGPIO interface is not hung, determining the hard disk status indication signal according to the latched data; If the valid flag is invalid, or the timeout detection flag indicates that the SGPIO interface is hung, all latched data are set to 0, and the hard disk status indication signal is determined.

7. The method according to any one of claims 3 to 5, characterized in that: The method further comprises: The timeout parameter value is determined according to the time size of each frame of data.

8. The method according to claim 7, characterized in that Determining the timeout parameter value according to the time size of each frame of data includes: The time size of each frame of data is multiplied by a preset coefficient to obtain the timeout parameter value.

9. A control device for a hard disk status indicator light, characterized in that: include: A processing module, configured to determine a hard disk status indication signal according to a valid flag bit and a timeout detection flag bit generated during the receiving process after receiving data through the SGPIO interface; wherein the valid flag bit is generated when the number of falling edges of the clock signal obtained during the data receiving process meets the number of clocks generated by the SGPIO interface to send a frame of data, and the timeout detection flag bit is used to indicate whether the SGPIO interface is hung; The control module is used to control the hard disk status indicator light according to the hard disk status indication signal.

10. A controller, characterized in that: include: Memory, processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 8 when executed by a processor.

Images