Column gate drive circuit, pixel circuit, display control circuit, and display panel

Abstract

The application relates to a column gate driving circuit, a pixel circuit, a display control circuit and a display panel. The column gate driving circuit comprises a first driving sub-circuit, a second driving sub-circuit, a first target transistor and a second target transistor. The first driving sub-circuit is used for receiving a data signal and outputting the received data signal to a pixel circuit. The second driving sub-circuit is used for receiving the data signal, a first gate control signal and a first enable control signal, generating a column scanning signal according to the data signal, the first gate control signal and the first enable control signal, and outputting the column scanning signal to the first target transistor of the pixel circuit. The first target transistor is located on a data signal writing path between a second electrode and a gate electrode of a driving transistor. The column gate driving circuit can control the writing process of the data signal through a target column scanning signal, and then control the data refreshing process of the pixel circuit, so that the local refreshing of the display panel is realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a column gate driving circuit, a pixel circuit, a display control circuit, and a display panel. Background Technology

[0002] With the continuous development of technology, people have higher and higher requirements for electronic devices, such as higher requirements for the refresh rate of the display screen.

[0003] However, currently, screen refresh rates are fixed, meaning the display panel updates the displayed image at a specific frequency. In applications, some areas of the display panel may show static images while others display dynamic images normally. Since these areas with different display needs can only refresh at a fixed frequency, this results in higher power consumption for the display panel. Summary of the Invention

[0004] Therefore, it is necessary to provide a column gate driving circuit, pixel circuit, display control circuit, and display panel that can perform partial refresh of the display panel to reduce power consumption, in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a column gate driving circuit, comprising:

[0006] The first driving sub-circuit is used to receive data signals and output the received data signals to the pixel circuit;

[0007] The second driving sub-circuit is used to receive the data signal, the first gate control signal, and the first enable control signal, generate a column scan signal according to the data signal, the first gate control signal, and the first enable control signal, and output it to the first target transistor of the pixel circuit; wherein, the first target transistor is located on the data signal writing path between the second electrode and the gate of the driving transistor.

[0008] The aforementioned column gate driving circuit includes a first driving sub-circuit and a second driving sub-circuit. The first driving sub-circuit transmits data signals to the pixel circuit to control the pixel circuit to drive the light-emitting elements. The second driving sub-circuit outputs a target column scan signal to the gate of the second target transistor based on the data signal, the second gate control signal, and the first enable control signal, thereby achieving data signal multiplexing. Simultaneously, the target column scan signal can control the on / off state of the first target transistor. Since the first target transistor is located in the data signal writing path between the second electrode and the gate of the driving transistor, the target column scan signal can control the data signal writing process, thereby controlling the data refresh process of the pixel circuit. Based on this, the column gate driving circuit can control the data refresh process of the pixel circuits in each display area, thus achieving localized refresh of the display panel and reducing the power consumption of the display panel.

[0009] Secondly, this application provides a pixel circuit, the pixel circuit comprising:

[0010] A driving transistor is used to provide driving current to a light-emitting element.

[0011] A data writing module, wherein a first end of the data writing module is used to receive a data signal, a second end of the data writing module is connected to the first terminal of the driving transistor, and a control end of the data writing module is used to receive a first row scan signal, so as to conduct the first and second terminals of the data writing transistor in response to the first row scan signal, and output the data signal to the first terminal of the driving transistor;

[0012] A storage module, wherein a first terminal of the storage module is used to receive a first power supply voltage, and a second terminal of the storage module is connected to the gate of the driving transistor;

[0013] A first target transistor is located on the data signal writing path between the second terminal and the gate of the driving transistor. The gate of the first target transistor is used to receive a target column scan signal to turn on the first and second terminals of the first target transistor in response to the target column scan signal.

[0014] In the aforementioned pixel circuit, since the first target transistor is located on the data signal writing path between the second electrode and the gate of the driving transistor, the on / off state of the first target transistor affects the on / off state of the data signal writing path. Therefore, by controlling the on / off state of the first target transistor through the target column scan signal, the data signal writing process can be controlled, thereby controlling the data refresh process of the pixel circuit. Based on this, by controlling the target column scan signal output to each pixel circuit, the data refresh process of the pixel circuit in each display area can be controlled, thereby achieving localized refresh of the display panel and reducing the power consumption of the display panel.

[0015] Thirdly, this application provides a display control circuit, the display control circuit comprising:

[0016] The column gate drive circuit described above;

[0017] The pixel circuit described above.

[0018] The aforementioned column gate driving circuit outputs a target column scan signal to the first target transistor of the aforementioned pixel circuit, controlling the on / off state of the first target transistor. Since the first target transistor is located in the data signal write path between the second electrode and the gate of the driving transistor, the data refresh process of the pixel circuit can be controlled. Based on this, the column gate driving circuit can control the data refresh process of the pixel circuits in each display area, thereby achieving local refresh of the display panel and reducing the power consumption of the display panel.

[0019] Fourthly, this application provides a display panel, the display panel comprising:

[0020] The display control circuit described above;

[0021] A controller, connected to the column gate drive circuit, is used to provide the data signal, the first gate control signal, and the first enable control signal.

[0022] In the aforementioned display panel, the controller is connected to the column gate driving circuit, providing data signals, a first gate control signal, and a first enable control signal to the column gate driving circuit. The column gate driving circuit outputs a target column scan signal to the gate of the second target transistor based on the data signal, the second gate control signal, and the first enable control signal. The target column scan signal can control the on / off state of the first target transistor. Since the first target transistor is located in the data signal writing path between the second electrode and the gate of the driving transistor, the controller can control the data signal writing process by controlling the provided signals, thereby controlling the data refresh process of the pixel circuit. Based on this, the column gate driving circuit can control the data refresh process of the pixel circuits in each display area, thus achieving localized refresh of the display panel and reducing the power consumption of the display panel. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a circuit diagram of the pixel circuit of the 7T1C architecture in related technologies;

[0025] Figure 2 The circuit diagram for the pixel circuit of the 8T1C architecture;

[0026] Figure 3 This is a circuit diagram of the GOA circuit used to generate the scan signal for the P-type transistor.

[0027] Figure 4 for Figure 3 Signal timing diagram of the GOA circuit in the embodiment;

[0028] Figure 5 This is a circuit diagram of the GOA circuit used to generate the scan signal for an N-type transistor.

[0029] Figure 6 for Figure 5 Signal timing diagram of the GOA circuit in the embodiment;

[0030] Figure 7 This is a schematic diagram of the column gate driving circuit in one embodiment of this application;

[0031] Figure 8 This is a schematic diagram of the refresh area division of the display panel in one embodiment of this application;

[0032] Figure 9 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0033] Figure 10 This is a schematic diagram of the gate drive circuit in another embodiment of this application;

[0034] Figure 11 This is a signal timing diagram of the gate drive circuit in one embodiment of this application;

[0035] Figure 12 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0036] Figure 13 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0037] Figure 14 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0038] Figure 15 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0039] Figure 16 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0040] Figure 17This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0041] Figure 18 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0042] Figure 19 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0043] Figure 20 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0044] Figure 21 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0045] Figure 22 This is a schematic diagram of the column gate driving circuit in another embodiment of this application;

[0046] Figure 23 This is a schematic diagram of the pixel circuit structure in one embodiment of this application;

[0047] Figure 24 This is a schematic diagram of the pixel circuit structure in another embodiment of this application;

[0048] Figure 25 This is a schematic diagram of the refresh area division of the display panel in another embodiment of this application;

[0049] Figure 26 This is a schematic diagram of the pixel circuit structure in another embodiment of this application;

[0050] Figure 27 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0051] Figure 28 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0052] Figure 29 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0053] Figure 30 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0054] Figure 31 This is a schematic diagram of the pixel circuit in another embodiment of this application;

[0055] Figure 32 This is a schematic diagram of the display control circuit in one embodiment of this application;

[0056] Figure 33This is a schematic diagram of the display control circuit in another embodiment of this application;

[0057] Figure 34 This is a schematic diagram of the structure of the display panel in one embodiment of this application;

[0058] Figure 35 This is a schematic diagram of the structure of the display panel in another embodiment of this application.

[0059] Explanation of reference numerals in the attached figures:

[0060] 10-First driving sub-circuit, 20-Second driving sub-circuit, 11-First switching module, 21-Second switching module, 22-Drive module, 221-Voltage regulator circuit, 2211-First latch circuit, 222-Control circuit, 2221-Second latch circuit, 30-Pixel circuit, 31-Storage module, 32-Data writing module, 33-First reset module, 34-Second reset module, 35-Third reset module, 36-First light emission control module, 37-Second light emission control module, 100-Display panel, 110 First refresh area, 120-Second refresh area, 130-Third refresh area, 140-Fourth refresh area, 15-Fifth refresh area, 101-Column gate driving circuit, 40-Row gate driving circuit, 50-Scan control circuit, 60-Controller. Detailed Implementation

[0061] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0063] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0064] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are only used to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions, unless the singular form has a distinctly different meaning in the context.

[0065] Electronic or electrical devices and / or any other related devices or components (e.g., display devices including a display panel and a display panel driver, wherein the display panel driver further includes a drive controller, a gate driver, a gamma reference voltage generator, a data driver, and a transmit driver) according to embodiments of the concepts described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Additionally, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices may be processes or threads running on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. Computer program instructions are stored in memory, which may be implemented in a computing device using standard storage devices such as random access memory (RAM). Computer program instructions may also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices, without departing from the spirit and scope of the exemplary embodiments of the present application.

[0066] While exemplary embodiments of the display module and the display device including the display module have been specifically described herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that the display module and the display device including the display module, constructed according to the principles of this application, may be implemented in ways other than those specifically described herein. This application is also defined in the claims and their equivalents.

[0067] Figure 1 The circuit diagram of the pixel circuit of the 7T1C architecture in the related technology is shown in the reference. Figure 1 The 7T1C architecture pixel circuit includes 7 transistors and 1 storage capacitor. The pixel circuit includes a drive transistor, a gate reset unit, an anode reset unit, a data writing unit, a threshold compensation unit, and a light-emitting control unit.

[0068] Specifically, the first terminal of the driving transistor T3 is used to receive the data signal Data, and the second terminal of the transistor T3 can output the driving current. The value of the driving current is determined by the data signal Data and directly affects the brightness of the light-emitting device. The gate reset unit includes transistor T1, whose first terminal is connected to the reset voltage signal Vinit1, and whose second terminal is connected to the gate of transistor T3. Transistor T1 is used to pull down the gate voltage of transistor T3 to the voltage of the reset voltage signal Vinit1 according to the scan signal received at the gate, thereby resetting the gate of transistor T3. The anode reset unit includes transistor T7, whose first terminal is used to receive the reset voltage signal Vinit2, and whose second terminal is connected to the anode of the light-emitting device. After the gate of transistor T3 is reset, transistor T7 is used to pull down the anode voltage of the light-emitting device to the voltage of the reset voltage signal Vinit2 according to the scan signal received at the gate, thereby resetting the anode of the light-emitting device. The voltage of the reset voltage signal Vinit2 can be understood as the initial charging voltage of the anode of the light-emitting device.

[0069] The data writing unit includes transistor T4. The first terminal of transistor T4 is connected to the data signal line, and the second terminal of transistor T4 is connected to the first terminal of transistor T3. Transistor T4 is used to control the on / off state of the signal transmission path between the data signal and the first terminal of transistor T3 according to the scan signal. The threshold compensation unit includes transistor T2 and storage capacitor C1. Storage capacitor C1 is connected to the first voltage terminal ELVDD and the gate of transistor T3. The first terminal of transistor T2 is connected to the second terminal of transistor T3, and the second terminal of transistor T2 is connected to the gate of transistor T3. Transistor T2 is used to control the on / off state of the signal transmission path between the gate and the second terminal of transistor T3 according to the scan signal, thereby storing the compensation result in storage capacitor C1. By setting the threshold compensation unit, the threshold voltage of transistor T3 can be compensated, thereby avoiding the threshold voltage of transistor T3 from affecting the brightness of the light-emitting device. The light-emitting control unit includes transistor T5 and transistor T6. The first terminal of transistor T5 is connected to the first voltage terminal ELVDD, and the second terminal of transistor T5 is connected to the first terminal of transistor T3. Transistor T5 is used to control the on / off state of the signal transmission path between the first voltage terminal ELVDD and the first electrode of transistor T3 according to the light emission control signal EM. The first electrode of transistor T6 is connected to the second electrode of transistor T3, and the second electrode of transistor T6 is connected to the anode of the light-emitting device. Transistor T6 is used to control the on / off state of the signal transmission path between the second electrode of transistor T3 and the anode of the light-emitting device according to the light emission control signal EM.

[0070] It should be noted that the transistors in the pixel circuit can be either P-type or N-type transistors, and the types of transistors do not have to be exactly the same. Specifically, if the pixel circuit is a Low Temperature Poly-silicon (LTPS) type circuit, then all transistors in the pixel circuit can be P-type transistors. Based on the driving timing of the pixel circuit, transistors T2, T4, and T7 can be connected to the same scan signal, transistor T1 can be connected to another scan signal, and transistors T5 and T6 can be connected to the light emission control signal. If the pixel circuit is a Low Temperature Polycrystalline Oxide (LTPO) type circuit, then some transistors in the pixel circuit can be N-type transistors, for example... Figure 1 Transistors T1 and T2 shown are N-type transistors, while the remaining transistors T3-T7 are P-type transistors. Accordingly, transistors T2 and T4 need to be connected to different scan signals. In some embodiments, all transistors in the pixel circuit may be N-type transistors. It is understood that the pixel circuit may also be... Figure 2 Other architectures, such as the 8T1C shown, will not be described in detail here. The scanning control circuit of this embodiment can be applied to any pixel circuit that includes P-type transistors.

[0071] The row gate driving circuit is used to generate row scan signals to control the on and off states of each transistor in the pixel circuit. The row gate driving circuit can be a gate-driven-on-array (GOA) circuit, which can reduce the size of the display module and lower its manufacturing cost. In all embodiments of this application, the row gate driving circuit is provided as an example of a GOA circuit. When the pixel circuit includes only one type of transistor, the row gate driving circuit can include only two GOA circuits, which are used to generate the light emission control signal and the transistor scan signal, respectively. When the pixel circuit includes both P-type and N-type transistors, since the P-type transistor turns on in response to a low-level signal and the N-type transistor turns on in response to a high-level signal, the row gate driving circuit also needs to include three or five GOA circuits to control the on / off states of each transistor. The three GOA circuits are used to generate the light emission control signal, the P-type transistor scan signal, and the N-type transistor scan signal, respectively. For pixel circuits with more complex architectures, a greater number of GOA circuits are required, such as five groups. Optionally, if the row gate drive circuit includes a large number of GOA circuit groups, multiple GOA circuit groups can be placed on both sides of the display to avoid excessively wide black borders on one side of the display. In related technologies, to reduce the power consumption of the display, only an overall frequency reduction method can be used, but the overall frequency conversion strategy is not flexible enough, thus affecting the user's viewing experience.

[0072] Specifically, the circuit diagram of the GOA circuit can be determined according to the type of scan signal generated for the P-type transistor and the N-type transistor as needed. Figure 3 The circuit diagram is for the GOA circuit used to generate the scan signal of the P-type transistor. The circuit in this embodiment can be referred to as the GOA circuit of the 8T2C architecture. Figure 4 for Figure 3 The signal timing diagram of the GOA circuit in the embodiment is shown in the reference diagram. Figure 4 The low-level state of the scan signal G_out is enabled to control the P-type transistor that receives the scan signal G_out to turn on. Figure 5 The circuit diagram is for a GOA circuit used to generate scan signals for N-type transistors. The circuit in this embodiment can be referred to as a 10T3C architecture GOA circuit. Figure 6 for Figure 5 The signal timing diagram of the GOA circuit in the embodiment is shown in the reference diagram. Figure 6The high-level state of the scan signal G_out enables the N-type transistor that receives the scan signal G_out to turn on. The STV signal received by the GOA circuit can come from an external controller, which can be, but is not limited to, any of a display driver IC (DDIC) and an application processor (AP).

[0073] Therefore, this application provides a column gate driving circuit that can perform partial refresh of the display panel to reduce the power consumption of the display panel. Figure 7 This is a schematic diagram of the column gate driving circuit in one embodiment of this application, as shown below. Figure 7 As shown, the gate drive circuit includes a first drive sub-circuit 10 and a second drive sub-circuit 20.

[0074] The first driving sub-circuit 10 is used to receive the data signal Data and output the received data signal Data to the pixel circuit. The second driving sub-circuit 20 is used to receive the data signal Data, the first gate control signal SW1 and the first enable control signal EN1, generate a column scan signal according to the data signal Data, the first gate control signal SW1 and the first enable control signal EN1, and output it to the first target transistor of the pixel circuit; wherein, the first target transistor is located on the data signal Data writing path between the second terminal and the gate of the driving transistor.

[0075] It should be noted that, Figure 7 Only one column gate drive circuit is shown. In actual products, the display panel may include multiple column gate drive circuits and multiple pixel circuits.

[0076] In this application, the first target transistor can be either a P-type transistor or an N-type transistor. The first enable control signal EN1EN and the first gate control signal SW1 can originate from the display driver chip. The display driver chip is the mainstream controller in current display devices. It is understood that some display driver chips can integrate touch functionality and can be called Touch and Display Driver Integration (TDDI) chips. Alternatively, the enable control signal EN1EN and the first gate control signal SW1 can also originate from the application processor, which can also be called an application chip. Application chips are typically system-on-chips (SoCs). Based on the high integration of SoCs, the size of the display device can be greatly reduced. Therefore, the appropriate controller can be selected to generate the first enable control signal EN1EN and the first gate control signal SW1 according to the specific hardware scheme of the display device; this embodiment does not impose any limitations.

[0077] It can be understood that the first driving sub-circuit 10 receives the data signal Data and outputs the received data signal Data to the pixel circuit to provide the data signal Data to the pixel circuit during the data writing stage. Additionally, the second driving sub-circuit 20 generates a target column scan signal OP1 and outputs it to the first target transistor of the pixel circuit, thereby controlling the on / off state of the first target transistor. Since the first target transistor is located on the data signal Data writing path between the second electrode and the gate of the driving transistor, the second driving sub-circuit 20 can control the data writing process, and thus control the data refresh process of the pixel circuit. Based on this, the column gate driving circuit can control the data refresh process of the pixel circuits in each display area, thereby achieving local refresh of the display panel and reducing the power consumption of the display panel.

[0078] Specifically, it can be as follows Figure 8 As shown, Figure 8 This is a schematic diagram illustrating the refresh area division of the display panel in one embodiment of this application; Figure 8 In the embodiment shown, the display screen can be divided into three refresh areas. The first refresh area 110 on the left and the second refresh area 120 on the right have the same refresh frequency, but the refresh frequency is different from that of the third refresh area 130 in the middle.

[0079] The aforementioned column gate driving circuit includes a first driving sub-circuit 10 and a second driving sub-circuit 20. The first driving sub-circuit 10 transmits a data signal Data to the pixel circuit to control the pixel circuit to drive the light-emitting element. The second driving sub-circuit 20 outputs a target column scan signal OP1 to the gate of the second target transistor based on the data signal Data, the second gate control signal SW2, and the first enable control signal EN1, thereby multiplexing the data signal Data. Simultaneously, the target column scan signal OP1 can control the on / off state of the first target transistor. Since the first target transistor is located in the data signal Data writing path between the second electrode and the gate of the driving transistor, the target column scan signal OP1 can control the data signal Data writing process, thereby controlling the data refresh process of the pixel circuit. Based on this, the column gate driving circuit can control the data refresh process of the pixel circuit in each display area, thus achieving local refresh of the display panel and reducing the power consumption of the display panel.

[0080] In one embodiment, Figure 9 This is a schematic diagram of the column gate driving circuit in another embodiment of this application, as shown below. Figure 9As shown, the first driving sub-circuit 10 is also used to receive the second gate control signal SW2; wherein, the first driving sub-circuit 10 includes: a first switching module 11. The first terminal of the first switching module 11 is used to receive the data signal Data, the second terminal of the first switching module 11 is connected to the pixel circuit, and the control terminal of the first switching module 11 is used to receive the second gate control signal SW2, so as to conduct the first terminal and the second terminal of the first switching module 11 in response to the second gate control signal SW2, so as to output the data signal Data.

[0081] The second gate control signal SW2 can come from either the display driver chip or the application processor. The first switch module 11 may include a switch transistor Tp1, the first terminal of which is used to receive a data signal Data, the second terminal of which is connected to the pixel circuit, and the gate of which is used to receive the second gate control signal SW2.

[0082] In this embodiment, the control terminal of the first switch module 11 responds to the first gate control signal SW1 to turn on the first terminal and the second terminal of the first switch module 11 to output a data signal Data to the pixel circuit. The first switch module 11 can control the output of the data signal Data to the pixel circuit, thereby enabling the pixel circuit to drive the light-emitting element to emit light based on the data signal Data.

[0083] In one embodiment, Figure 10 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 10 As shown, the second driving sub-circuit 20 includes a second switching module 21 and a driving module 22.

[0084] A second switching module 21 has a first terminal for receiving a data signal Data and a control terminal for receiving a first gate control signal SW1, in response to which the first and second terminals of the second switching module 21 are switched on. A driving module 22 has a first terminal connected to the second terminal of the second switching module 21 and a second terminal connected to the gate of the first target transistor. The driving module 22 is used to generate a target column scan signal OP1 based on the data signal Data and the first enable control signal EN1. The level of the target column scan signal OP1 can be the same as or opposite to the first enable control signal EN1. For example, Figure 11 This is a signal timing diagram of the gate drive circuit in one embodiment of this application, as shown below. Figure 11 As shown, the level of the target column scan signal OP1 can be the same as that of the first enable control signal EN1.

[0085] The first gate control signal SW1 can come from the display driver chip or the application processor.

[0086] It can be understood that the second switch module 21 can control the output of the data signal Data to the drive module 22, so that the drive module 22 can generate the target column scan signal OP1 based on the data signal Data and the first enable control signal EN1. Furthermore, by controlling the on / off state of the first switch module 11 and the second switch module 21, simultaneous conduction of the first switch module 11 and the second switch module 21 can be avoided. For example, if the first switch module 11 is on in a high-level state and the second switch module 21 is off in a high-level state, the timing of the first gate control signal SW1 and the second gate control signal SW2 can be as follows: Figure 11 As shown, the first switch module 11 is briefly turned on, and the second switch module 21 is briefly turned off, thereby preventing the first switch module 11 and the second switch module 21 from being turned on simultaneously. This allows the first driving sub-circuit 10 to stably output the data signal Data to the pixel circuit for a long period of time. Through this setting, the simultaneous output of the data signal Data by the first switch module 11 and the second switch module 21 is avoided, thereby reducing signal interference on the first driving sub-circuit 10 and the second driving sub-circuit 20, ensuring the accuracy of the column scan signal and data signal Data output to the pixel circuit, and thus facilitating precise control of the partial refresh of the display panel.

[0087] In one embodiment, Figure 12 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 12 As shown, the second switching module 21 includes an oxide transistor Ti1.

[0088] The first terminal of the oxide transistor Ti1 is used to receive the data signal Data. The second terminal of the oxide transistor Ti1 is connected to the first terminal of the driving module 22. The control terminal of the oxide transistor Ti1 is used to receive the first gate control signal SW1, so as to conduct the first and second terminals of the oxide transistor Ti1 in response to the first gate control signal SW1 and output the data signal Data.

[0089] Among them, the oxide transistor Ti1 can be an N-type transistor.

[0090] It is understandable that oxide transistors Ti1 have the advantages of high carrier mobility, low deposition temperature and high transparency. Compared with low temperature polycrystalline silicon thin film transistors, they have low leakage current. Therefore, they are beneficial to reduce the voltage drop of the data signal Data during transmission, and thus output a relatively stable signal to the drive module 22.

[0091] In one embodiment, Figure 13 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 13 As shown, the driving module 22 includes: a first transistor T1, a second transistor T2, and a voltage regulator circuit 221.

[0092] The first terminal of the first transistor T1 is connected to the first voltage terminal, which is used to output a high-level state signal. The second terminal of the first transistor T1 is connected to the gate of the first target transistor. The gate of the first transistor T1 is used to receive the first enable control signal EN1. In response to the first enable control signal EN1, the first and second terminals of the first transistor T1 are turned on to output a high-level state signal.

[0093] The second terminal of the second transistor T2 is connected to the second voltage terminal, which is used to output a low-level state signal. The gate of the second transistor T2 is used to receive the first enable control signal EN1, so as to turn on the first and second terminals of the second transistor T2 in response to the first enable control signal EN1 and output a low-level state signal.

[0094] In this design, the third gate control signal SW3 is a constant voltage signal, such as a 2V constant voltage signal. The third gate control signal SW3 can originate from either the display driver chip or the application processor. The first transistor T1 is a first-type transistor, and the second transistor T2 is a second-type transistor. In one example, the first-type transistor is a P-type transistor, and the second-type transistor is an N-type transistor. In another example, the first-type transistor is an N-type transistor, and the second-type transistor is a P-type transistor. For ease of explanation, the following description will use an example where the first-type transistor is a P-type transistor and the second-type transistor is an N-type transistor.

[0095] The voltage regulator circuit 221 is connected to the second terminal of the second switching module 21, the first terminal of the first transistor T1, the second terminal of the first transistor T1, the first terminal of the second transistor T2, and the first voltage terminal, respectively. The voltage regulator circuit 221 is used to output a stable target column scan signal OP1 in conjunction with the first transistor T1 according to the data signal Data, the third gate control signal SW3, the high-level state signal, and the low-level state signal.

[0096] It is understandable that, since the first transistor T1 and the second transistor T2 are of different transistor types, when both the gates of the first transistor T1 and the gate of the second transistor T2 receive the first enable control signal EN1, one of the first transistor T1 and the second transistor T2 will be turned on simultaneously, and there will be no simultaneous on / off situation. When the first transistor T1 is turned on in response to the first enable control signal EN1, the first transistor T1 outputs a high-level state signal. The voltage regulator circuit 221 performs stabilization processing on the high-level signal output by the first transistor T1, so that the driving module 22 can output a stable high-level state signal to the gate of the first target transistor. When the second transistor T2 is turned on in response to the first enable control signal EN1, the second transistor T2 outputs a low-level state signal to the voltage regulator circuit 221. The low-level state signal is stabilized by the voltage regulator circuit 221 and then output, so that the driving module 22 can output a stable low-level state signal to the gate of the first target transistor.

[0097] Based on the above, by controlling the high and low levels of the target column scan signal OP1 output by the drive module 22, the on / off state of the first target transistor can be controlled, thereby controlling the on / off state of the data signal Data write path, thus controlling the data refresh process and achieving partial refresh of the display panel. Taking a P-type transistor as an example, when the first target transistor receives a high-level signal, it turns on, and the corresponding pixel circuit refreshes data; when the first target transistor receives a low-level signal, it turns off, and the corresponding pixel circuit cannot refresh data, thus maintaining the data of the previous frame. Therefore, by controlling the on / off state of the first target transistor in the pixel circuits of different display areas, the refresh frequency of each display area can be controlled.

[0098] In one embodiment, Figure 14 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 14 As shown, the voltage regulator circuit 221 includes a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The third transistor T3 is a first-type transistor, while the fourth transistor T4 and the fifth transistor T5 are second-type transistors.

[0099] The first terminal of the third transistor T3 is connected to the first voltage terminal, and the gate of the third transistor T3 is used to receive the first enable control signal EN1. In response to the first enable control signal EN1, the first and second terminals of the third transistor T3 are turned on, and a high-level state signal is output. The first terminals of both the third transistor T3 and the first transistor T1 are connected to the first voltage terminal, and the gates of both the third transistor T3 and the first transistor T1 receive the first enable control signal EN1. It can be understood that the third transistor T3 and the first transistor T1 have a symmetrical structure. By setting the third transistor T3 and the first transistor T1 to a symmetrical structure, external interference can be reduced, and the stability of the high-level state signal output by the first transistor T1 can be guaranteed.

[0100] The first terminal of the fourth transistor T4 is connected to the second terminal of the third transistor T3, and the second terminal of the fourth transistor T4 is connected to the first terminal of the second transistor T2. The gate of the fourth transistor T4 is connected to the second terminal of the second switching module 21. The first terminal of the fifth transistor T5 is connected to the gate of the first target transistor, and the second terminal of the fifth transistor T5 is connected to the first terminal of the second transistor T2. The gate of the fifth transistor T5 is used to receive the third gate control signal SW3, the voltage of which is within the voltage selection range of the data signal Data. It can be seen that the fourth transistor T4 and the fifth transistor T5 are also symmetrical structures. Since the output signal of the first transistor T1 needs to be output through the fifth transistor T5, by setting the fourth transistor T4 and the fifth transistor T5 as symmetrical structures, external interference can be reduced, and the stability of the low-level state signal output by the second transistor T2 can be guaranteed.

[0101] It should be noted that since the second terminal of the fifth transistor T5 is connected to the first terminal of the second transistor T2, the second transistor T2 outputs a low-level signal when it is turned on. Also, since the voltage of the third gate control signal SW3 is within the voltage selection range of the data signal Data, the voltage difference between the second terminal and the gate of the fifth transistor T5 is relatively large when the second transistor T2 is turned on. Therefore, the third gate control signal SW3 is relatively high-level, which allows the second transistor T2 (an N-type transistor) to turn on and output a low-level signal.

[0102] In another embodiment, Figure 15 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 15As shown, the voltage regulator circuit 221 includes: a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. Among them, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are first-type transistors, and the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, and the ninth transistor T9 are second-type transistors.

[0103] The first terminal of the third transistor T3 is connected to the first voltage terminal, the second terminal of the third transistor T3 is connected to the first latch circuit 2211, and the gate of the third transistor T3 is used to receive the first enable control signal EN1. The third transistor T3 and the first transistor T1 have a symmetrical structure. By setting the third transistor T3 and the first transistor T1 to a symmetrical structure, external interference can be reduced, and the stability of the high-level state signal output by the first transistor T1 can be guaranteed.

[0104] The fourth transistor T4 has its second terminal connected to the first terminal of the second transistor T2, and its gate connected to the second terminal of the second switching module 21. The fifth transistor T5 has its second terminal connected to the first terminal of the second transistor T2, and its gate is used to receive the third gate control signal SW3. The voltage of the third gate control signal SW3 is within the voltage selection range of the data signal Data. The fourth transistor T4 and the fifth transistor T5 are also symmetrically structured. Since the output signal of the first transistor T1 needs to be output through the fifth transistor T5, by setting the fourth transistor T4 and the fifth transistor T5 to a symmetrical structure, external interference can be reduced, ensuring the stability of the low-level output signal of the second transistor T2.

[0105] The first latch circuit 2211 is connected to the first voltage terminal, the second terminal of the first transistor T1, the second terminal of the third transistor T3, the first terminal of the fourth transistor T4, and the first terminal of the fifth transistor T5, respectively. The first latch circuit 2211 is used to output a steady-state target column scan signal OP1 according to the high-level state signal and the low-level state signal.

[0106] In this embodiment, the first latch circuit 2211 outputs a stable target column scan signal OP1 based on the high-level state signal and the low-level state signal. This avoids the influence of environmental factors such as temperature changes on the level state of the target column scan signal OP1, thereby preventing the first target transistor from experiencing on / off errors due to fluctuations in the level state of the target column scan signal OP1, thus improving the stability and reliability of the column gate drive circuit.

[0107] In one embodiment, Figure 16 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 16As shown, the first latching circuit 2211 includes: a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9. The sixth transistor T6 and the seventh transistor T7 are first-type transistors, and the eighth transistor T8 and the ninth transistor T9 are second-type transistors.

[0108] The first terminal of the sixth transistor T6 is connected to the first voltage terminal, the second terminal of the sixth transistor T6 is connected to the first node N1, and the gate of the sixth transistor T6 is used to receive the second node signal. The first terminal of the seventh transistor T7 is connected to the first voltage terminal, the second terminal of the seventh transistor T7 is connected to the second node N2, and the gate of the seventh transistor T7 is used to receive the first node signal. The second terminal of the eighth transistor T8 is connected to the first terminal of the fourth transistor T4, the second terminal of the eighth transistor T8 is connected to the first node N1, and the gate of the eighth transistor T8 is used to receive the second node signal. The first terminal of the ninth transistor T9 is connected to the gate of the first target transistor, the second terminal of the ninth transistor T9 is connected to the first terminal of the fifth transistor T5, and the gate of the ninth transistor T9 is used to receive the first node signal.

[0109] It can be understood that the principle of the first latch circuit 2211 is similar to that of the SR latch. The output signals of the sixth transistor T6 and the eighth crystal serve as the gate signals of the seventh transistor T7 and the ninth transistor T9, and vice versa. Specifically, if the level of the first node signal is low, the seventh transistor T7 remains on; if the level of the first node signal is high, the ninth transistor T9 remains on. If the level of the second node signal is low, the sixth transistor T6 remains on; if the level of the second node signal is high, the eighth transistor T8 remains on. Therefore, in this embodiment, one of the sixth transistor T6 and the eighth crystal can remain on. By maintaining the above on state, the influence of environmental factors such as temperature changes on the level of the first node signal (i.e., the target column scan signal OP1) can be avoided, thereby preventing the first target transistor from experiencing on / off errors due to fluctuations in the level of the target column scan signal OP1, thus improving the stability and reliability of the column gate drive circuit.

[0110] In one embodiment, Figure 17 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 17 As shown, the voltage regulator circuit 221 also includes a first voltage regulator capacitor C1.

[0111] The first terminal of the first voltage regulator capacitor C1 is connected to the first voltage terminal, and the second terminal of the first voltage regulator capacitor C1 is connected to the second terminal of the second switching module 21 and the gate of the fourth transistor T4, respectively.

[0112] It can be understood that by connecting the first terminal of the first voltage regulator C1 to the first voltage terminal, the high-level state signal of the first voltage terminal is kept stable, and the data signal Data output from the second terminal of the second switch module 21 is kept stable, so as to provide a stable gate signal to the gate of the fourth transistor T4.

[0113] In another embodiment, Figure 18 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 18 As shown, the driving module 22 includes a first transistor M1, a second transistor M2, and a control circuit 222. The first transistor M1 is a first-type transistor, and the second transistor M2 is a second-type transistor.

[0114] The first terminal of the first transistor M1 is connected to a first voltage terminal, which outputs a low-level state signal. The second terminal of the first transistor M1 is connected to the gate of the first target transistor, which receives a first node signal. The first terminal of the second transistor M2 is connected to a second voltage terminal, which outputs a high-level state signal. The gate of the second transistor M2 receives the first node signal.

[0115] It is understood that the gates of both the first transistor M1 and the second transistor M2 receive the first node signal. Since the first transistor M1 is a first type transistor and the second transistor M2 is a second type transistor, only one of the first transistor M1 and the second transistor M2 is turned on. When the first transistor M1 is turned on, the target column scan signal OP1 output by the driving module 22 is at a low level; when the second transistor M2 is turned on, the target column scan signal OP1 output by the driving module 22 is at a high level.

[0116] The control circuit 222 is connected to the first terminal of the second switching module 21, the gate of the first transistor M1, the gate of the second transistor M2, the first voltage terminal, and the second voltage terminal, respectively. The control circuit 222 is used to output a stable first node signal in conjunction with the first transistor M1 based on the data signal Data, the first enable control signal EN1, the third gate control signal SW3, the high-level state signal, and the low-level state signal. By outputting the first node signal, the control circuit 222 can control the on / off state of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first target transistor to control the data refresh process of the pixel circuit, thus achieving partial refresh of the display panel and reducing the power consumption of the display panel.

[0117] In one embodiment, Figure 19 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 19 As shown, the control circuit 222 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. Among them, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are first-type transistors, and the third transistor M3 and the fourth transistor M4 are second-type transistors.

[0118] The first terminal of the third transistor M3 is connected to the first voltage terminal, and the second terminal of the third transistor M3 is connected to the first node N1. The gate of the third transistor M3 receives the first enable control signal EN1, thereby turning on the first and second terminals of the third transistor M3 in response to the first enable control signal EN1 and outputting a low-level state signal. The first terminal of the fourth transistor M4 is connected to the first voltage terminal, and the second terminal of the fourth transistor M4 is connected to the second node N2. The gate of the fourth transistor M4 receives the first enable control signal EN1. The third transistor M3 and the fourth transistor M4 have a symmetrical structure. By setting the third transistor M3 and the first transistor M1 to a symmetrical structure, external interference can be reduced, ensuring the stability of the low-level state signal output by the first transistor M1, and thus ensuring the stability of the signal at the first node.

[0119] The second terminal of the fifth transistor M5 is connected to the second voltage terminal, and the gate of the fifth transistor M5 is used to receive the first enable control signal EN1. In response to the first enable control signal EN1, the first and second terminals of the fifth transistor M5 are turned on, and a high-level state signal is output.

[0120] The second terminal of the sixth transistor M6 is connected to the first terminal of the fifth transistor M5, and the gate of the sixth transistor M6 is connected to the second terminal of the second switching module 21. The second terminal of the seventh transistor M7 is connected to the first terminal of the fifth transistor M5, and the gate of the seventh transistor M7 is used to receive the third gate control signal SW3. The voltage of the third gate control signal SW3 is within the voltage selection range of the data signal Data. The sixth transistor M6 and the seventh transistor M7 are also symmetrical. Since the output signal of the fifth transistor M5 needs to be output through the seventh transistor M7, by setting the fourth transistor M4 and the fifth transistor M5 to a symmetrical structure, external interference can be reduced, and the stability of the high-level state signal output by the second transistor M2 and the stability of the low-level state signal output by the second transistor M2 can be guaranteed.

[0121] It should be noted that since the second terminal of the seventh transistor M7 is connected to the first terminal of the fifth transistor M5, the fifth transistor M5 outputs a high-level signal when it is turned on. Furthermore, because the voltage of the third gate control signal SW3 is within the voltage selection range of the data signal Data, the voltage difference between the second terminal and the gate of the seventh transistor M7 is relatively large when the second transistor M2 is turned on. Therefore, the third gate control signal SW3 is relatively low-level. Consequently, the second transistor M2, being a P-type transistor, can turn on and output a low-level signal.

[0122] In one embodiment, Figure 20 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 20 As shown, the control circuit 222 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a second latch circuit 2221.

[0123] The first terminal of the third transistor M3 is connected to the first voltage terminal, and the second terminal of the third transistor M3 is connected to the first node N1. The gate of the third transistor M3 receives the first enable control signal EN1, and in response to the first enable control signal EN1, the first and second terminals of the third transistor M3 are turned on, outputting a low-level state signal. The first terminal of the fourth transistor M4 is connected to the first voltage terminal, and the gate of the fourth transistor M4 receives the first enable control signal EN1. The third transistor M3 and the fourth transistor M4 have a symmetrical structure. By setting the third transistor M3 and the first transistor M1 to a symmetrical structure, external interference can be reduced, the stability of the low-level state signal output by the first transistor M1 can be guaranteed, and thus the stability of the first node signal can be guaranteed.

[0124] The second terminal of the fifth transistor M5 is connected to the second voltage terminal, and the gate of the fifth transistor M5 is used to receive the first enable control signal EN1. In response to the first enable control signal EN1, the first and second terminals of the fifth transistor M5 are turned on, and a high-level state signal is output.

[0125] The first terminal of the sixth transistor M6 is connected to the second terminal of the fourth transistor M4, and the second terminal of the sixth transistor M6 is connected to the first terminal of the fifth transistor M5. The gate of the sixth transistor M6 is connected to the second terminal of the second switching module 21. The second terminal of the seventh transistor M7 is connected to the first terminal of the fifth transistor M5, and the gate of the seventh transistor M7 is used to receive the third gate control signal SW3. The voltage of the third gate control signal SW3 is within the voltage selection range of the data signal Data. The sixth transistor M6 and the seventh transistor M7 are also symmetrical. Since the output signal of the fifth transistor M5 needs to be output through the seventh transistor M7, by setting the fourth transistor M4 and the fifth transistor M5 to a symmetrical structure, external interference can be reduced, and the stability of the high-level state signal output by the fifth transistor M5 can be guaranteed.

[0126] The second latch circuit 2221 is connected to the first voltage terminal, the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, the first terminal of the sixth transistor M6, and the first terminal of the seventh transistor M7, respectively. The second latch circuit 2221 is used to output a steady-state target column scan signal OP1 according to the high-level state signal and the low-level state signal.

[0127] In this embodiment, the second latch circuit 2221 outputs a stable target column scan signal OP1 based on the high-level state signal and the low-level state signal. This avoids the influence of environmental factors such as temperature changes on the level state of the target column scan signal OP1, thereby preventing fluctuations in the level state of the target column scan signal OP1 from causing the first target transistor to fail to switch on or off, thus improving the stability and reliability of the column gate drive circuit.

[0128] In one embodiment, Figure 21 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 21 As shown, the second latch circuit 2221 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11. Among them, the eighth transistor M8 and the ninth transistor M9 are second-type transistors, and the tenth transistor M10 and the eleventh transistor M11 are first-type transistors.

[0129] The first terminal of the eighth transistor M8 is connected to the first voltage terminal, the second terminal of the eighth transistor M8 is connected to the first node N1, and the gate of the eighth transistor M8 is used to receive the second node signal. The first terminal of the ninth transistor M9 is connected to the first voltage terminal, the second terminal of the ninth transistor M9 is connected to the second node N2, and the gate of the ninth transistor M9 is used to receive the first node signal. The first terminal of the tenth transistor M10 is connected to the first node N1, the second terminal of the tenth transistor M10 is connected to the first terminal of the seventh transistor M7, and the gate of the tenth transistor M10 is used to receive the second node signal. The first terminal of the eleventh transistor M11 is connected to the second node N2, the second terminal of the eleventh transistor M11 is connected to the first terminal of the sixth transistor M6, and the gate of the eleventh transistor M11 is used to receive the first node signal.

[0130] It can be understood that the principle of the second latch circuit 2221 is similar to that of the SR latch. The output signals of the eighth transistor M8 and the tenth crystal serve as the gate signals of the ninth transistor M9 and the eleventh transistor M11, and the output signals of the ninth transistor M9 and the eleventh transistor M11 serve as the gate signals of the sixth transistor M6 and the eighth crystal. Specifically, if the level of the first node signal is low, the eleventh transistor M11 remains on; if the level of the first node signal is high, the ninth transistor M9 remains on. If the level of the second node signal is low, the tenth transistor M10 remains on; if the level of the second node signal is high, the eighth transistor M8 remains on. Therefore, in this embodiment, one of the eighth transistor M8 and the tenth crystal can remain on. By maintaining the above-mentioned conduction state, the influence of environmental factors such as temperature changes on the level state of the first node signal can be avoided, thereby preventing the fluctuation of the level state of the first node signal from causing the first transistor M1 and the second transistor M2 to conduct incorrectly, which in turn leads to the first target transistor having an on / off error, thereby improving the stability and reliability of the column gate drive circuit.

[0131] In one embodiment, Figure 22 This is a schematic diagram of the gate drive circuit in another embodiment of this application, as shown below. Figure 22 As shown, the control circuit 222 also includes a second voltage-stabilizing capacitor.

[0132] The first end of the second voltage regulator capacitor is connected to the first voltage terminal, and the second end of the second voltage regulator capacitor is connected to the second terminal of the second switching module 21 and the gate of the sixth transistor M6, respectively.

[0133] It can be understood that by connecting the first end of the second voltage regulator capacitor to the first voltage terminal, the low-level state signal of the first voltage terminal is kept stable, and the data signal Data output from the second terminal of the second switching module 21 is kept stable, so as to provide a stable gate signal to the gate of the sixth transistor M6.

[0134] Based on the same inventive concept, this application also provides a pixel circuit. Figure 23 This is a schematic diagram of the pixel circuit structure in one embodiment of this application, as shown below. Figure 23 As shown, the pixel circuit includes: a driving transistor T01, a data writing module 32, a storage module, and a first target transistor T02.

[0135] The driving transistor T01 provides driving current to the light-emitting element. The first terminal of the data writing module 32 receives the data signal Data, and the second terminal of the data writing module 32 is connected to the first terminal of the driving transistor T01. The control terminal of the data writing module 32 receives the first row scan signal S1, and in response to the first row scan signal S1, turns on the first and second terminals of the data writing transistor T04, outputting the data signal Data to the first terminal of the driving transistor T01. The first terminal of the storage module receives the first power supply voltage Vdd, and the second terminal of the storage module is connected to the gate of the driving transistor T01. The first target transistor T02 is located on the data signal Data writing path between the second terminal and the gate of the driving transistor T01. The gate of the first target transistor T02 receives the target column scan signal OP1, and in response to the target column scan signal OP1, turns on the first and second terminals of the first target transistor T02.

[0136] The target column scan signal OP1 can be output by the column gate scan circuit of any of the above embodiments.

[0137] It can be understood that during the writing phase, the data writing module 32 responds to the first row scan signal S1 by turning on the first and second terminals of the data writing transistor T04, and outputs the data signal Data to the first terminal of the driving transistor T01. The data voltage is then written to the gate of the driving transistor T01 via the driving transistor T01 and the first target transistor T02, thereby achieving data refresh of the pixel circuit. Therefore, by controlling the conduction of the first target transistor T02 through the target column scan signal OP1, the data writing process can be controlled, thereby controlling the data refresh process of the pixel circuit.

[0138] In the aforementioned pixel circuit, since the first target transistor T02 is located on the data signal writing path between the second electrode and the gate of the driving transistor T01, the on / off state of the first target transistor T02 affects the on / off state of the data signal writing path. Therefore, by controlling the on / off state of the first target transistor through the target column scan signal OP1, the writing process of the data signal Data can be controlled, thereby controlling the data refresh process of the pixel circuit. Based on this, by controlling the target column scan signal OP1 output to each pixel circuit, the data refresh process of the pixel circuit in each display area can be controlled, thereby achieving local refresh of the display panel and reducing the power consumption of the display panel.

[0139] In one embodiment, Figure 24 This is a schematic diagram of the pixel circuit structure in another embodiment of this application, as shown below. Figure 24 As shown, the pixel circuit also includes a second target transistor T03.

[0140] The second target transistor T03 is located on the data signal Data writing path between the second terminal and the gate of the driving transistor T01. The gate of the second target transistor T03 is used to receive the target row scan signal OP2, so as to turn on the first and second terminals of the second target transistor T03 in response to the target row scan signal OP2.

[0141] It is understandable that, since both the first target transistor T02 and the second target transistor T03 are located on the data signal Data writing path between the second terminal and the gate of the driving transistor T01, the data signal Data can only be written to the gate of the driving transistor T01 via the first target transistor T02 and the second target transistor T03 when both are turned on. Since the first target transistor T02 turns on the first and second terminals of the second target transistor T03 in response to the target column scan signal OP1, and the second target transistor T03 turns on its first and second terminals in response to the target row scan signal OP2, and the pixel circuit at any position can be determined based on the row and column, the data refresh process of the pixel circuit at any position can be controlled by the target column scan signal OP1 and the target row scan signal OP2. Therefore, based on the above pixel circuit, data refresh of any area of ​​the display panel can be achieved. Figure 25 This is a schematic diagram of the refresh area division of the display panel in another embodiment of this application, as shown below. Figure 25 As shown, the display screen can be divided into two refresh areas, with the fourth refresh area 140 in the middle and the fifth refresh area 150 on the periphery having different refresh rates.

[0142] In one embodiment, Figure 26 This is a schematic diagram of the pixel circuit structure in another embodiment of this application, as shown below. Figure 26 As shown, the pixel circuit also includes a first reset module 33.

[0143] The first terminal of the first reset module 33 is connected to the second terminal of the driving transistor T01. The second terminal of the first reset module 33 is used to receive the first reset signal Vint1. The control terminal of the first reset module 33 is used to receive the second row scan signal S2, so as to output the first reset signal Vint1 to the second terminal of the driving transistor T01 in response to the second row scan signal S2.

[0144] It is understandable that, since the first terminal of the first reset module 33 is connected to the second terminal of the driving transistor T01, when the first reset module 33 responds to the second row scan signal S2 and turns on both its first and second terminals, the first reset module 33 outputs a first reset signal Vint1 to the second terminal of the driving transistor T01. The first reset signal Vint1 needs to be written to the gate of the driving transistor T01 via the first target transistor T02. Therefore, controlling the on / off state of the first target transistor T02 through the target column scan signal OP1 can also control the reset of the gate of the driving transistor T01.

[0145] When the pixel circuit includes a first target transistor T02 and a second target transistor T03, the first reset signal Vint1 can only be written to the gate of the driving transistor T01 via the first target transistor T02 and the second target crystal when both the first target transistor T02 and the second transistor are turned on. Therefore, the writing process of the first reset signal Vint1 of the pixel circuit at any position can be controlled based on the target row scan signal OP2 and the target column scan signal OP1.

[0146] In one embodiment, Figure 27 This is a schematic diagram of the pixel circuit structure in another embodiment of this application, as shown below. Figure 27 As shown, the pixel circuit also includes a second reset module 34.

[0147] The first terminal of the second reset module 34 is used to receive the second reset signal Vint2. The second terminal of the second reset module 34 is connected to the anode of the light-emitting element. The control terminal of the second reset module 34 is used to receive the third line scan signal S3, so as to output the second reset signal Vint2 to the anode of the light-emitting device in response to the third line scan signal S3.

[0148] In the application, during the reset phase, the control terminal of the second reset module 34 responds to the third line scan signal S3 to turn on the first and second terminals of the second reset module 34, and the second reset signal Vint2 is written into the anode of the light-emitting device to reset the anode of the light-emitting device, thereby improving the display uniformity of the display panel.

[0149] In one embodiment, Figure 28 This is a schematic diagram of the pixel circuit structure in another embodiment of this application, as shown below. Figure 28 As shown, the pixel circuit also includes a third reset module 35.

[0150] The first terminal of the third reset module 35 is used to receive the third reset signal Vint3. The second terminal of the third reset module 35 is connected to the first terminal of the driving transistor T01. The control terminal of the third reset module 35 is used to receive the third row scan signal S3, and outputs the third reset signal Vint3 to the first terminal of the driving transistor T01 in response to the third row scan signal S3.

[0151] In the application, during the reset phase, the control terminal of the third reset module 35 responds to the third row scan signal S3 to turn on the first and second terminals of the third reset module 35. The third reset signal Vint3 is written to the first terminal of the driving transistor T01 to reset the first terminal of the driving transistor T01, thereby compensating for the threshold offset of the driving transistor T01 and improving the frequency conversion flicker problem.

[0152] In one embodiment, Figure 29 This is a schematic diagram of the pixel circuit structure in another embodiment of this application, as shown below. Figure 29 As shown, the pixel circuit also includes: a first light-emitting control module 36 and a second light-emitting control module 37.

[0153] The first terminal of the first light-emitting control module 36 is used to receive the first power supply voltage Vdd. The second terminal of the first light-emitting control module 36 is connected to the first electrode of the driving transistor T01. The control terminal of the first light-emitting control module 36 is used to receive the light-emitting control signal EM, so as to turn on the first terminal and the second terminal of the first light-emitting control module 36 in response to the light-emitting control signal EM during the light-emitting stage.

[0154] The first terminal of the second light-emitting control module 37 is connected to the second terminal of the driving transistor T01, and the second terminal of the second light-emitting control module 37 is connected to the anode of the light-emitting element. The control terminal of the second light-emitting control module 37 is used to receive the light-emitting control signal EM, so as to turn on the first and second terminals of the second light-emitting control module 37 in response to the light-emitting control signal EM during the light-emitting stage.

[0155] It can be understood that during the light-emitting stage, the first light-emitting control module 36 responds to the light-emitting control signal EM, and the first and second terminals of the first light-emitting control module 36 are turned on, driving the first electrode of the transistor T01 to connect to the first power supply voltage Vdd; the second light-emitting control module 37 responds to the light-emitting control signal EM, and the first and second terminals of the second light-emitting control module 37 are turned on, driving the second electrode of the transistor T01 to connect to the light-emitting device, thereby connecting to the second power supply voltage Vss, so that the driving transistor T01 can provide driving current to the light-emitting device, driving the light-emitting device to emit light.

[0156] Based on the above embodiments, in one embodiment... Figure 30 This is a schematic diagram of the pixel circuit structure in another embodiment of this application. Figure 31 This is a schematic diagram of the pixel circuit structure in another embodiment of this application, as shown below. Figure 30 and 31 As shown, the data writing module 32 may include a writing transistor. The first terminal of the writing transistor is used to receive the data signal Data. The second terminal of the writing transistor is connected to the first terminal of the driving transistor T01. The gate of the writing transistor is used to receive the first row scan signal S1.

[0157] The storage module may include a storage capacitor Cst, the first end of which is used to receive a first power supply voltage Vdd, and the second end of which is connected to the gate of the driving transistor T01.

[0158] The first reset module 33 may include a first reset transistor T05. The first terminal of the first reset transistor T05 is connected to the second terminal of the driving transistor T01. The second terminal of the first reset transistor T05 is used to receive the first reset signal Vint1. The gate of the first reset transistor T05 is used to receive the second row scan signal S2.

[0159] The second reset module 34 may include a second reset transistor T06. The first terminal of the second reset transistor T06 is used to receive the second reset signal Vint2. The second terminal of the second reset transistor T06 is connected to the anode of the light-emitting element. The gate of the second reset module 34 is used to receive the third row scan signal S3.

[0160] The third reset module 35 may include a third reset transistor T07. The first terminal of the third reset transistor T07 is used to receive the third reset signal Vint3. The second terminal of the third reset transistor T07 is connected to the first terminal of the driving transistor T01. The gate of the third reset transistor T07 is used to receive the third row scan signal S3.

[0161] The first light emission control submodule may include a first light emission control transistor T08. The gate of the first light emission control transistor T08 is used to receive the light emission control signal EM. The first terminal of the first light emission control transistor T08 is used to receive the first power supply voltage Vdd. The second terminal of the first light emission control transistor T08 is connected to the first terminal of the driving transistor T01.

[0162] The second light-emitting control submodule may include a second light-emitting control transistor T09. The gate of the second light-emitting control transistor T09 is used to receive the light-emitting control signal EM. The first terminal of the second light-emitting control transistor T09 is connected to the second terminal of the driving transistor T01, and the second terminal of the second light-emitting control transistor T09 is connected to the anode of the light-emitting device.

[0163] In one embodiment, such as Figure 30 As shown, the first target transistor T02 is of type N. When the target column scan signal OP1 is high, the first target transistor T02 is turned on; when the target column scan signal OP1 is low, the first target transistor T02 is turned off. The first target transistor T02 is used to turn on in response to the target column scan signal OP1 during the data writing phase of the pixel circuit.

[0164] The second target transistor T03 is of type N. When the target row scan signal OP2 is high, the second target transistor T03 is turned on; when the target row scan signal OP2 is low, the second target transistor T03 is turned off. The second target transistor T03 is used to turn on in response to the target row scan signal OP2 during the data writing phase of the pixel circuit.

[0165] It is understandable that after determining the types of the first target transistor T02 and the second target transistor T03, the level states of the target row scan signal OP2 and the target column scan signal OP1 can be determined according to the types of the first target transistor T02 and the second target transistor T03, thereby controlling the on / off state of the first target transistor T02 and the second target transistor T03 to achieve data refresh of any area of ​​the display panel.

[0166] In another embodiment, such as Figure 31 As shown, the first target transistor T02 is of type P. When the target column scan signal OP1 is low, the first target transistor T02 is turned on, and when the target column scan signal OP1 is high, the first target transistor T02 is turned off. The first target transistor T02 is used to respond to the target column scan signal OP1 and is turned on during the data writing stage of the pixel circuit.

[0167] The second target transistor T03 is of type N. When the target row scan signal OP2 is at a high level, the second target transistor T03 is turned on, and when the target row scan signal OP2 is at a low level, the second target transistor T03 is turned off. The second target transistor T03 is used to turn on in response to the target row scan signal OP2 during the data writing stage of the pixel circuit.

[0168] After determining the types of the first target transistor T02 and the second target transistor T03, the level states of the target row scan signal OP2 and the target column scan signal OP1 can be determined according to the types of the first target transistor T02 and the second target transistor T03, thereby controlling the on / off state of the first target transistor T02 and the second target transistor T03 to achieve data refresh of any area of ​​the display panel.

[0169] In one embodiment, this application also provides a display control circuit. Figure 32 This is a schematic diagram of the display control circuit in one embodiment of this application, as shown below. Figure 32 As shown, the display control circuit includes: a column gate driving circuit 101 as described in any of the above embodiments; and a pixel circuit 30 as described in any of the above embodiments.

[0170] It can be understood that the column gate driving circuit 101 outputs a target column scan signal OP1 to the first target transistor of the pixel circuit 30, controlling the on / off state of the first target transistor. Since the first target transistor is located on the data signal Data write path between the second electrode and the gate of the driving transistor, the data refresh process of the pixel circuit 30 can be controlled. Based on this, the column gate driving circuit 101 can control the data refresh process of the pixel circuit 30 in each display area, thereby achieving local refresh of the display panel and reducing the power consumption of the display panel.

[0171] In one embodiment, Figure 33 This is a schematic diagram of the display control circuit in another embodiment of this application, as shown below. Figure 33 As shown, the pixel circuit 30 also includes a second target transistor, which is located on the data signal Data write path between the second electrode and the gate of the driving transistor.

[0172] The display control circuit also includes: a row gate driving circuit 40 and a scan control circuit 50.

[0173] The row gate driving circuit 40 is used to output the initial row scan signal. The input terminal of the scan control circuit 50 is connected to the row gate driving circuit 40, and is used to generate the target row scan signal OP2 according to the initial row scan signal and the second enable control signal EN2, and output it to the second target transistor, wherein the second target transistor is located on the data signal Data write path between the second terminal and the gate of the driving transistor.

[0174] It is understandable that, since both the first and second target transistors are located on the data signal writing path between the second terminal and the gate of the driving transistor, the data signal Data can only be written to the gate of the driving transistor via the first and second target transistors when both are turned on. Since the first target transistor turns on the first and second terminals of the second target transistor in response to the target column scan signal OP1, and the second target transistor turns on its first and second terminals in response to the target row scan signal OP2, and the pixel circuit 30 at any position can be determined based on the row and column, the data refresh process of the pixel circuit 30 at any position can be controlled by the target column scan signal OP1 and the target row scan signal OP2. Therefore, based on the above display control circuit, data refresh of any area of ​​the display panel can be achieved.

[0175] In one embodiment, when the second enable control signal EN2 is at a first level, the level of the target scan signal is the same as that of the initial scan signal.

[0176] When the second enable control signal EN2 is in the second level state, the target row scan signal OP2 is in the target level state, where the first level state and the second level state are different, and the target level state is the level state that turns off the second target transistor. Based on the initial scan signal with the second level state, the scan control circuit 50 can generate a target scan signal that is continuously in the target level state to control the corresponding second target transistor to remain off, thereby preventing the corresponding pixel circuit 30 from undergoing data refresh and thus maintaining the data of the previous frame. The first level state and the second level state are different; for example, the first level state can be low and the second level state can be high, or vice versa. The first level state and the second level state can be determined according to the type of the second target transistor, which is not limited in this embodiment.

[0177] In one embodiment, this application also provides a display panel. Figure 34 This is a schematic diagram of the display panel structure in one embodiment of this application, as shown below. Figure 34 As shown, the display panel 100 includes a display control circuit and a controller 60 as described in any of the above embodiments. The controller 60 is connected to the column gate drive circuit 101 and is used to provide a data signal Data, a first gate control signal SW1, and a first enable control signal EN1.

[0178] The aforementioned display panel 100 includes a controller 60 connected to a column gate driving circuit 101. The controller 60 provides a data signal (Data), a first gate control signal (SW1), and a first enable control signal (EN1) to the column gate driving circuit 101. The column gate driving circuit 101 outputs a target column scan signal (OP1) to the gate of the second target transistor based on the data signal (Data), the second gate control signal (SW2), and the first enable control signal (EN1). The target column scan signal (OP1) can control the on / off state of the first target transistor. Since the first target transistor is located in the data signal (Data) writing path between the second electrode and the gate of the driving transistor, the controller 60 can control the writing process of the data signal (Data) by controlling the provided signals, thereby controlling the data refresh process of the pixel circuit 30. Based on this, the column gate driving circuit 101 can control the data refresh process of the pixel circuit 30 in each display area, thus achieving localized refresh of the display panel 100 and reducing the power consumption of the display panel 100.

[0179] In one embodiment, the controller 60 is further configured to acquire the screen to be displayed, determine the refresh area and non-refresh area based on the screen to be displayed, and output the data signal Data, the first gate control signal SW1 and the first enable control signal EN1 to the column gate drive circuit 101.

[0180] In this circuit, the column gate driving circuit 101 connected to the pixel in the refresh area receives a first enable control signal EN1 at a first level, so that the level of the target column scan signal OP1 is at a level that turns on the first target transistor; the column gate driving circuit 101 connected to the pixel in the non-refresh area receives a first enable control signal EN1 at a second level, so that the level of the target column scan signal OP1 is at a level that turns off the first target transistor.

[0181] It can be understood that the column gate driving circuit 101 connected to the pixels in the refresh area provides a first enable control signal EN1 at a first level, turning on the corresponding first target transistors, thereby enabling the pixel circuit 30 in the corresponding refresh area to perform data refresh. Conversely, the column gate driving circuit 101 connected to the pixels in the non-refresh area provides a first enable control signal EN1 at a second level, turning off the corresponding first target transistors, thus preventing the pixel circuit 30 in the corresponding non-refresh area from performing data refresh. Therefore, the controller 60, by controlling the signals provided to each column gate driving circuit 101, can control the data refresh process of the pixel circuit 30 in each display area, thereby achieving partial refresh of the display panel 100 and reducing the power consumption of the display panel 100.

[0182] In one embodiment, Figure 35 This is a schematic diagram of the display panel structure in another embodiment of this application, as shown below. Figure 35As shown, the display control circuit also includes a row gate driving circuit 40 and a scan control circuit 50. The row gate driving circuit 40 is used to output an initial row scan signal. The input terminal of the scan control circuit 50 is connected to the row gate driving circuit 40, and is used to generate a target row scan signal OP2 based on the initial row scan signal and the second enable control signal EN2, and output it to the second target transistor. The second target transistor is located on the data signal Data write path between the second terminal and the gate of the driving transistor.

[0183] The controller 60 is also used to output a second enable control signal EN2 to the scan control circuit 50. When the second enable control signal EN2 is at a first level, the scan control circuit 50 outputs a target line scan signal OP2 to control the second target transistor in the pixel circuit 30 of the refresh area to be turned on. When the second enable control signal EN2 is at a second level, the scan control circuit 50 outputs a target line scan signal OP2 to control the second target transistor in the pixel circuit 30 of the corresponding non-refresh area to be turned off.

[0184] It is understood that since both the first target transistor and the second target transistor are located on the data signal Data writing path between the second terminal and the gate of the driving transistor, the data signal Data can only be written to the gate of the driving transistor via the first target transistor and the second target transistor when both are turned on. Since the first target transistor turns on the first and second terminals of the second target transistor in response to the target column scan signal OP1, and the second target transistor turns on its first and second terminals in response to the target row scan signal OP2, and the pixel circuit 30 at any position can be determined based on the row and column, the controller 60 can control the data refresh process of the pixel circuit 30 at any position by controlling the signals output to each column gate driving circuit 101 and each scan control circuit 50. Therefore, the aforementioned display panel 100 can achieve data refresh in any display area.

[0185] In one embodiment, the controller 60 is a display driver chip.

[0186] In another embodiment, controller 60 may also be an application processor.

[0187] Based on the same inventive concept, this application also provides a display device (not shown), which includes the display panel 100 in the above embodiments.

[0188] It is understood that the display device in the embodiments of this application can be any product or component with display function, such as OLED display device, QLED display device, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, Internet of Things device, etc., and the embodiments disclosed in this application do not limit this.

[0189] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0190] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0191] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A column gate drive circuit, characterized by comprising: The application relates to an array substrate and a driving method thereof. The first driving sub-circuit comprises a first switch module, a first end of the first switch module is used for receiving a data signal, a second end of the first switch module is connected with a pixel circuit, and a control end of the first switch module is used for receiving a second gate control signal so as to turn on the first end and the second end of the first switch module in response to the second gate control signal, thereby outputting the data signal. The second driving sub-circuit comprises a second switch module and a driving module, a first end of the second switch module is used for receiving the data signal, a control end of the second switch module is used for receiving a first gate control signal so as to turn on the first end and the second end of the second switch module in response to the first gate control signal, a first end of the driving module is connected with a second end of the second switch module, and a second end of the driving module is connected with a gate of a first target transistor, the driving module is used for generating a target column scanning signal according to the data signal and a first enable control signal; the first target transistor is located on a data signal writing path between a second electrode and a gate of a driving transistor, a first electrode of the first target transistor is connected with the gate of the driving transistor, a second electrode of the first target transistor is connected with the second electrode of the driving transistor, and the gate of the first target transistor is used for receiving the target column scanning signal; and a first electrode of the driving transistor is used for receiving a first power supply voltage.

2. The column gate drive circuit of claim 1, wherein, The second switch module comprises an oxide transistor, a first electrode of the oxide transistor is used for receiving the data signal, a second electrode of the oxide transistor is connected with the first end of the driving module, and a control end of the oxide transistor is used for receiving the first gate control signal so as to turn on the first electrode and the second electrode of the oxide transistor in response to the first gate control signal. The driving module comprises a first transistor, a first electrode of the first transistor is used for being connected with a first voltage end, the first voltage end is used for outputting a high-level state signal, a second electrode of the first transistor is used for being connected with the gate of the first target transistor, and a gate of the first transistor is used for receiving the first enable control signal; a second transistor, a second electrode of the second transistor is used for being connected with a second voltage end, the second voltage end is used for outputting a low-level state signal, and a gate of the second transistor is used for receiving the first enable control signal; and a voltage stabilizing circuit, the voltage stabilizing circuit is connected with the second end of the second switch module, the first electrode of the first transistor, the second electrode of the first transistor, the first electrode of the second transistor and the first voltage end respectively, and the voltage stabilizing circuit is used for outputting a steady-state target column scanning signal in cooperation with the first transistor according to the data signal, a third gate control signal, the high-level state signal and the low-level state signal.

3. The column gate drive circuit of claim 1, wherein, ​ ​ ​ ​ The third gate control signal is a constant voltage signal, the first transistor is a first type transistor, and the second transistor is a second type transistor; one of the first type transistor and the second type transistor is a P-type transistor, and the other is an N-type transistor.

4. The column gate drive circuit of claim 3, wherein, The voltage stabilizing circuit comprises: a third transistor, a first electrode of the third transistor being connected with the first voltage terminal, and a gate electrode of the third transistor being used for receiving the first enable control signal; a fourth transistor, a first electrode of the fourth transistor being connected with a second electrode of the third transistor, a second electrode of the fourth transistor being connected with a first electrode of the second transistor, and a gate electrode of the fourth transistor being connected with a second terminal of the second switch module; a fifth transistor, a first electrode of the fifth transistor being connected with a gate electrode of the first target transistor, a second electrode of the fifth transistor being connected with the first electrode of the second transistor, and a gate electrode of the fifth transistor being used for receiving a third gate control signal, a voltage of the third gate control signal being in a voltage selection interval of the data signal; The third transistor is the first type transistor, and the fourth transistor and the fifth transistor are the second type transistor.

5. The column gate drive circuit of claim 3, wherein, The voltage stabilizing circuit comprises: a third transistor, a first electrode of the third transistor being connected with the first voltage terminal, and a gate electrode of the third transistor being used for receiving the first enable control signal; a fourth transistor, a second electrode of the fourth transistor being connected with a first electrode of the second transistor, and a gate electrode of the fourth transistor being connected with a second terminal of the second switch module; a fifth transistor, a second electrode of the fifth transistor being connected with the first electrode of the second transistor, and a gate electrode of the fifth transistor being used for receiving a third gate control signal, a voltage of the third gate control signal being in a voltage selection interval of the data signal; a first latch circuit, the first latch circuit being connected with the first voltage terminal, a second electrode of the first transistor, a second electrode of the third transistor, a first electrode of the fourth transistor, and a first electrode of the fifth transistor respectively, and the first latch circuit being used for outputting a steady-state target column scanning signal according to the high-level state signal and the low-level state signal; The third transistor is the first type transistor, and the fourth transistor and the fifth transistor are the second type transistor.

6. The column gate drive circuit of claim 5, wherein, The first latch circuit comprises: a sixth transistor, a first electrode of the sixth transistor being connected with the first voltage terminal, a second electrode of the sixth transistor being connected with a first node, and a gate electrode of the sixth transistor being used for receiving a second node signal; a seventh transistor, a first electrode of the seventh transistor being connected with the first voltage terminal, a second electrode of the seventh transistor being connected with a second node, and a gate electrode of the seventh transistor being used for receiving a first node signal; an eighth transistor, a first electrode of the eighth transistor being connected with a first electrode of the fifth transistor, a second electrode of the eighth transistor being connected with the first node, and a gate electrode of the eighth transistor being used for receiving the second node signal; a ninth transistor, a first electrode of the ninth transistor being connected with the second node, a second electrode of the ninth transistor being connected with the first electrode of the fourth transistor, and a gate electrode of the ninth transistor being used for receiving the first node signal; wherein the sixth transistor and the seventh transistor are the first type transistors, and the eighth transistor and the ninth transistor are the second type transistors.

7. The column gate drive circuit of any one of claims 4 to 6, wherein, The voltage stabilizing circuit further comprises: a first voltage stabilizing capacitor, a first end of the first voltage stabilizing capacitor being connected with the first voltage end, and a second end of the first voltage stabilizing capacitor being connected with the second end of the second switch module and the gate electrode of the fourth transistor respectively.

8. The column gate drive circuit of claim 1, wherein, The driving module comprises: a first transistor, a first electrode of the first transistor being used for being connected with a first voltage end, the first voltage end being used for outputting a low level state signal, a second electrode of the first transistor being used for being connected with the gate electrode of the first target transistor, and a gate electrode of the first transistor being used for receiving a first node signal; a second transistor, a first electrode of the second transistor being used for being connected with a second voltage end, the second voltage end being used for outputting a high level state signal, and a gate electrode of the second transistor being used for receiving the first node signal; a control circuit, the control circuit being connected with the first end of the second switch module, the gate electrode of the first transistor, the gate electrode of the second transistor, the first voltage end and the second voltage end respectively, and the control circuit being used for outputting the first node signal in a steady state in cooperation with the first transistor according to the data signal, the first enable control signal, a third gate control signal, the high level state signal and the low level state signal; wherein the third gate control signal is a constant voltage signal, the first transistor is a first type transistor, and the second transistor is a second type transistor; one of the first type transistor and the second type transistor is a P-type transistor, and the other is an N-type transistor.

9. The column gate drive circuit of claim 8, wherein, The control circuit comprises: a third transistor, a first electrode of the third transistor being used for being connected with the first voltage end, a second electrode of the third transistor being used for being connected with the first node, and a gate electrode of the third transistor being used for receiving the first enable control signal; a fourth transistor, a first electrode of the fourth transistor being used for being connected with the first voltage end, a second electrode of the fourth transistor being connected with the second node, and a gate electrode of the fourth transistor being used for receiving the first enable control signal; a fifth transistor, a second electrode of the fifth transistor being used for being connected with a second voltage end, and a gate electrode of the fifth transistor being used for receiving the first enable control signal; a sixth transistor, a first electrode of the sixth transistor being connected with the second electrode of the fourth transistor, a second electrode of the sixth transistor being connected with the first electrode of the fifth transistor, and a gate electrode of the sixth transistor being connected with the second end of the second switch module; A seventh transistor, a first electrode of the seventh transistor is connected with a second electrode of the third transistor, a second electrode of the seventh transistor is connected with a first electrode of a fifth transistor, a gate electrode of the seventh transistor is used for receiving a third gate control signal, a voltage of the third gate control signal is in a voltage selection interval of the data signal; The fifth transistor, the sixth transistor and the seventh transistor are first type transistors, and the third transistor and the fourth transistor are second type transistors.

10. The column gate drive circuit of claim 8, wherein, The control circuit comprises: A third transistor, a first electrode of the third transistor is used for being connected with the first voltage terminal, a second electrode of the third transistor is used for being connected with the first node, and a gate electrode of the third transistor is used for receiving the first enable control signal; A fourth transistor, a first electrode of the fourth transistor is used for being connected with the first voltage terminal, and a gate electrode of the fourth transistor is used for receiving the first enable control signal; A fifth transistor, a second electrode of the fifth transistor is used for being connected with a second voltage terminal, and a gate electrode of the fifth transistor is used for receiving the first enable control signal; A sixth transistor, a first electrode of the sixth transistor is connected with a second electrode of the fourth transistor, a second electrode of the sixth transistor is connected with a first electrode of the fifth transistor, and a gate electrode of the sixth transistor is connected with a second end of the second switch module; A seventh transistor, a second electrode of the seventh transistor is connected with a first electrode of a fifth transistor, and a gate electrode of the seventh transistor is used for receiving a third gate control signal, a voltage of the third gate control signal is in a voltage selection interval of the data signal; A second latch circuit, the second latch circuit is connected with the first voltage terminal, a second electrode of the third transistor, a second electrode of the fourth transistor, a first electrode of the sixth transistor and a first electrode of the seventh transistor respectively, and the second latch circuit is used for outputting a steady-state target column scanning signal according to the high level state signal and the low level state signal; The fifth transistor, the sixth transistor and the seventh transistor are first type transistors, and the third transistor and the fourth transistor are second type transistors.

11. The column gate drive circuit of claim 10, wherein, The second latch circuit comprises: An eighth transistor, a first electrode of the eighth transistor is used for being connected with the first voltage terminal, a second electrode of the eighth transistor is connected with the first node, and a gate electrode of the eighth transistor is used for receiving a second node signal; A ninth transistor, a first electrode of the ninth transistor is used for being connected with the first voltage terminal, a second electrode of the ninth transistor is connected with a second node, and a gate electrode of the ninth transistor is used for receiving a first node signal; A tenth transistor, a first electrode of the tenth transistor is connected with the first node, a second electrode of the tenth transistor is connected with a first electrode of the seventh transistor, and a gate electrode of the tenth transistor is used for receiving the second node signal; An eleventh transistor, a first electrode of the eleventh transistor is connected with the second node, a second electrode of the eleventh transistor is connected with the first electrode of the sixth transistor, and a gate electrode of the eleventh transistor is used for receiving the first node signal; The eighth transistor and the ninth transistor are second type transistors, and the tenth transistor and the eleventh transistor are first type transistors.

12. The column gate drive circuit of any one of claims 9 to 11, wherein, The control circuit further comprises: A second voltage stabilizing capacitor, a first end of the second voltage stabilizing capacitor is connected with the first voltage end, and a second end of the second voltage stabilizing capacitor is connected with the second end of the second switch module and the gate electrode of the sixth transistor respectively.

13. A pixel circuit, characterized in that, The pixel circuit comprises: A driving transistor, used for providing a driving current to a light emitting element; A data writing module, a first end of the data writing module is used for receiving a data signal, a second end of the data writing module is connected with a first electrode of the driving transistor, and a control end of the data writing module is used for receiving a first row scanning signal, so as to turn on the first electrode and the second electrode of the data writing module in response to the first row scanning signal, and output the data signal to the first electrode of the driving transistor; A storage module, a first end of the storage module is used for receiving a first power voltage, and a second end of the storage module is connected with a gate electrode of the driving transistor; A first target transistor, the first target transistor is located on a data signal writing path between the second electrode and the gate electrode of the driving transistor, and a gate electrode of the first target transistor is used for receiving a target column scanning signal, so as to turn on the first electrode and the second electrode of the first target transistor in response to the target column scanning signal.

14. The pixel circuit of claim 13, wherein, The pixel circuit further comprises: A second target transistor, the second target transistor is located on a data signal writing path between the second electrode and the gate electrode of the driving transistor, and a gate electrode of the second target transistor is used for receiving a target row scanning signal, so as to turn on the first electrode and the second electrode of the second target transistor in response to the target row scanning signal.

15. The pixel circuit according to claim 13 or 14, characterized in that, The pixel circuit further comprises: A first reset module, a first end of the first reset module is connected with the second electrode of the driving transistor, a second end of the first reset module is used for receiving a first reset signal, and a control end of the first reset module is used for receiving a second row scanning signal, so as to output the first reset signal to the second electrode of the driving transistor in response to the second row scanning signal.

16. The pixel circuit of claim 13, wherein, The pixel circuit further comprises: A second reset module, a first end of the second reset module is used for receiving a second reset signal, a second end of the second reset module is connected with an anode of the light emitting element, and a control end of the second reset module is used for receiving a third row scanning signal, so as to output the second reset signal to the anode of the light emitting element in response to the third row scanning signal.

17. The pixel circuit of claim 13, wherein, The pixel circuit further comprises: A third reset module, a first end of the third reset module is configured to receive a third reset signal, a second end of the third reset module is connected with the first electrode of the driving transistor, and a control end of the third reset module is configured to receive a third row scan signal, so as to output the third reset signal to the first electrode of the driving transistor in response to the third row scan signal.

18. The pixel circuit of claim 13, wherein, The pixel circuit further comprises: A first light emitting control module, a first end of the first light emitting control module is configured to receive a first power voltage, a second end of the first light emitting control module is connected with the first electrode of the driving transistor, and a control end of the first light emitting control module is configured to receive a light emitting control signal, so as to turn on the first end and the second end of the first light emitting control module in a light emitting stage in response to the light emitting control signal; A second light emitting control module, a first end of the second light emitting control module is connected with the second electrode of the driving transistor, a second end of the second light emitting control module is connected with the anode of the light emitting element, and a control end of the second light emitting control module is configured to receive the light emitting control signal, so as to turn on the first end and the second end of the second light emitting control module in the light emitting stage in response to the light emitting control signal.

19. The pixel circuit of claim 14, wherein, The first target transistor is of an N type, and is configured to be turned on in a data writing stage of the pixel circuit in response to the target column scan signal; The second target transistor is of an N type, and is configured to be turned on in the data writing stage of the pixel circuit in response to the target row scan signal.

20. The pixel circuit of claim 14, wherein, The first target transistor is of a P type, and is configured to be turned on in the data writing stage of the pixel circuit in response to the target column scan signal; The second target transistor is of an N type, and is configured to be turned on in the data writing stage of the pixel circuit in response to the target row scan signal.

21. A display control circuit, comprising: The display control circuit comprises: The column gate driving circuit according to any one of claims 1 to 12; The pixel circuit according to any one of claims 13 to 20.

22. The display control circuit of claim 21, wherein, The pixel circuit further comprises a second target transistor, which is located on a data signal writing path between the second electrode and the gate electrode of the driving transistor. The display control circuit further comprises: A row gate driving circuit, configured to output an initial row scan signal; A scan control circuit, an input end of the scan control circuit is connected with the row gate driving circuit, configured to generate a target row scan signal according to the initial row scan signal and a second enable control signal, and output the target row scan signal to the second target transistor, wherein the second target transistor is located on the data signal writing path between the second electrode and the gate electrode of the driving transistor, a first electrode of the second target transistor is connected with a second electrode of a first target transistor of the pixel circuit, a second electrode of the second target transistor is connected with the second electrode of the driving transistor, and a gate electrode of the second target transistor is configured to receive the target row scan signal.

23. The display control circuit of claim 22, wherein, In a case where the second enable control signal is in a first level state, a level state of the target row scan signal is the same as that of the initial row scan signal. In a case that the second enable control signal is in a second level state, a level state of the target column scanning signal is a target level state, wherein the first level state and the second level state are different, and the target level state is a level state for turning off the second target transistor.

24. A display panel comprising: The display panel comprises: The display control circuit according to any one of claims 21 to 23; The controller is connected with the column gate driving circuit, and is configured to provide the data signal, the first gate control signal and the first enable control signal.

25. The display panel of claim 24, wherein, The controller is further configured to acquire a to-be-displayed picture, determine a refresh region and a non-refresh region according to the to-be-displayed picture, and output the data signal, the first gate control signal and the first enable control signal to the column gate driving circuit. In a case that the second enable control signal is in a second level state, a level state of the target column scanning signal is a target level state, wherein the first level state and the second level state are different, and the target level state is a level state for turning off the second target transistor.

26. The display panel of claim 25, wherein, The display control circuit further comprises a row gate driving circuit and a scanning control circuit. The row gate driving circuit is configured to output an initial row scanning signal. An input end of the scanning control circuit is connected with the row gate driving circuit, and the scanning control circuit is configured to generate a target row scanning signal according to the initial row scanning signal and a second enable control signal, and output the target row scanning signal to the second target transistor, which is located on a data signal writing path between the second electrode and the gate electrode of the driving transistor. The controller is further configured to output the second enable control signal to the scanning control circuit, and in a case that the second enable control signal is in a first level state, the scanning control circuit outputs the target row scanning signal to control the second target transistor in the pixel circuit of the refresh region to be turned on, and in a case that the second enable control signal is in a second level state, the scanning control circuit outputs the target row scanning signal to control the second target transistor in the pixel circuit corresponding to the non-refresh region to be turned off.

27. The display panel of claim 24, wherein, The controller is a display driving chip.

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