Pixel

Abstract

A pixel is provided. The pixel may include: a first transistor including a first electrode electrically connected to a first power line configured to receive a first driving power, a second electrode, and a gate electrode connected to a first node; a second transistor connected between the data line and the first node, and including a gate electrode electrically connected to the first scan line; a light emitting element including a first electrode connected to a second electrode of the first transistor and a second electrode electrically connected to a second power line configured to receive a second driving power; a first capacitor connected between the first node and a first electrode of the light emitting element; and a second capacitor connected between the first electrode of the light emitting element and the third power line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0083758, filed on Jun. 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Various embodiments of the present disclosure relate to a pixel and a display device including the pixel. Background Art

[0003] As information technology develops, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices and organic light emitting display devices has increased.

[0004] Recently, head-mounted display devices (HMDs) have been developed. A head-mounted display device (HMD) is a display device that a user wears in the form of glasses or a helmet, and is used to create a virtual reality (VR) or augmented reality (AR) experience with a focus formed at a close distance in front of the user's eyes. The head-mounted display device uses a high-resolution panel, and pixels that can be applied to the high-resolution panel are required. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a pixel that can be applied to a high-resolution panel and a display device including the pixel.

[0006] An embodiment of the present disclosure may provide a pixel, comprising: a first transistor, comprising a first electrode electrically connected to a first power line configured to receive a first driving power, a second electrode, and a gate electrode connected to a first node; a second transistor connected between a data line and the first node and comprising a gate electrode electrically connected to a first scan line; a light-emitting element, comprising a first electrode connected to the second electrode of the first transistor and a second electrode electrically connected to a second power line configured to receive a second driving power; a first capacitor connected between the first node and the first electrode of the light-emitting element; and a second capacitor connected between the first electrode of the light-emitting element and a third power line.

[0007] In an embodiment, a ratio of the capacitance of the second capacitor to the capacitance of the first capacitor may be at least 0.1.

[0008] In an embodiment, the second driving power may be a lower voltage than the first driving power.

[0009] In an embodiment, the third power line may receive a first initialization power having a voltage value that turns off the light emitting element in response to receiving the first initialization power at the first electrode of the light emitting element.

[0010] In an embodiment, the first initialization power may be ground power.

[0011] In an embodiment, the pixel may further include: a third transistor connected between the first electrode of the light emitting element and the third power line, and including a gate electrode electrically connected to the second scan line; a third capacitor including a first electrode and a second electrode connected to the first node; and a fourth transistor including a first electrode electrically connected to the fourth power line, a second electrode connected to the first electrode of the third capacitor, and a gate electrode electrically connected to the third scan line.

[0012] In an embodiment, each of the first transistor, the second transistor, the third transistor, and the fourth transistor may include a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode.

[0013] In an embodiment, the first driving power may be supplied to a body electrode of each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0014] In an embodiment, the third scan line may be the same scan line as the second scan line.

[0015] In an embodiment, the horizontal period may include a first period, a second period, and a third period. During the first and second periods, a voltage of the reference power may be supplied to the data line, and during the third period, a voltage of the data signal may be supplied to the data line.

[0016] In an embodiment, the reference power may be set to a voltage value between the first driving power and the second driving power.

[0017] In an embodiment, the second initialization power may be supplied to the fourth power line, and the reference power may be set to a voltage equal to that of the second initialization power.

[0018] In an embodiment, during the first period, the second transistor, the third transistor, and the fourth transistor may be turned on. During the second period and the third period, the second transistor may be turned on, and the third transistor and the fourth transistor may be turned off.

[0019] An embodiment of the present disclosure may provide a display device, the display device comprising pixels connected to a first scan line, a second scan line, a third scan line and a data line. Among the pixels, the pixel located on the i-th pixel row (i is an integer greater than 0) and the j-th pixel column (j is an integer greater than 0) may include: a first transistor, comprising a first electrode electrically connected to a first power line configured to receive a first drive power, a second electrode, and a gate electrode connected to a first node; a second transistor, connected between the j-th data line and the first node, and configured to be turned on when a first scan signal is supplied to the i-th first scan line; a light-emitting element, comprising a first electrode connected to the second electrode of the first transistor and a second electrode electrically connected to a second power line configured to receive a second drive power; a first capacitor, connected between the first node and the first electrode of the light-emitting element; and a second capacitor, connected between the first electrode of the light-emitting element and the third power line configured to receive the first initialization power.

[0020] In an embodiment, a ratio of the capacitance of the second capacitor to the capacitance of the first capacitor may be at least 0.1.

[0021] In an embodiment, a pixel located on the i-th pixel row and the j-th pixel column may further include: a third transistor connected between the first electrode of the light emitting element and the third power line and configured to be turned on when the second scan signal is supplied to the i-th second scan line; a third capacitor including a first electrode and a second electrode connected to the first node; and a fourth transistor including a first electrode electrically connected to a fourth power line configured to receive a second initialization power and a second electrode connected to the first electrode of the third capacitor, the fourth transistor being configured to be turned on when the third scan signal is supplied to the i-th third scan line.

[0022] In an embodiment, each of the first transistor, the second transistor, the third transistor, and the fourth transistor may include a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode. The first driving power may be supplied to the body electrode of each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0023] In an embodiment, a horizontal period in which a pixel located on an i-th pixel row and a j-th pixel column is driven may include a first period, a second period, and a third period. The display device may further include: a data driver configured to supply a voltage of a reference power to a j-th data line during a first period and a second period, and to supply a voltage of a data signal to the j-th data line during a third period; a first scan driver configured to supply a first scan signal to an i-th first scan line during a first period to a third period; a second scan driver configured to supply a second scan signal to an i-th second scan line during a first period; and a third scan driver configured to supply a third scan signal to an i-th third scan line during a first period.

[0024] In an embodiment, the reference power may be equal to the second initialization power having a voltage between the first driving power and the second driving power.

[0025] In an embodiment, the third scan line may be the same scan line as the second scan line, and the third scan driver may be the same scan driver as the second scan driver.

[0026] The objects of the present disclosure are not limited to the above-mentioned objects, and other unmentioned objects will be clearly understood from the appended claims by those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram showing a transistor according to an embodiment of the present disclosure.

[0028] Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 3 It is shown Figure 2 An embodiment of a scan driver is shown in FIG.

[0030] Figure 4 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0031] Figure 5 Is shown driving Figure 4 0047] A waveform diagram of an embodiment of a pixel method is shown in FIG.

[0032] FIG. 6A to FIG. 6D is shown with Figure 5 The driving waveform in FIG. 4 corresponds to the process of operating the pixel.

[0033] Figure 7 is a diagram showing a voltage range of a data signal corresponding to the capacitance of the second capacitor.

[0034] Figure 8is a graph showing a change in voltage of the second node in the embodiment of the present disclosure and in a comparative example.

[0035] Fig. 9 is a graph showing current errors in the embodiment of the present disclosure and in a comparative example.

[0036] Fig.10 is a diagram showing a pixel according to an embodiment of the present disclosure.

[0037] Figures 11 to 14 is a diagram illustrating an electronic device according to various embodiments. DETAILED DESCRIPTION

[0038] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily make and use the present invention. The present disclosure can be implemented in various forms and is not limited to the embodiments to be described below.

[0039] In the accompanying drawings, parts not related to the present disclosure will be omitted to explain the present disclosure more clearly. Reference should be made to the accompanying drawings, in which similar reference numerals used throughout different figures are used to indicate similar components. Therefore, the aforementioned reference numerals may be used in other figures.

[0040] For reference, for convenience of explanation, the size of each component and the thickness of the line showing the component are arbitrarily indicated, and the present disclosure is not limited to the contents shown in the drawings. In the drawings, the thickness of the components may be exaggerated to clearly depict multiple layers and regions.

[0041] In addition, the expression "same" may mean "substantially the same". In other words, the expression "same" may include a range acceptable to those skilled in the art. Other expressions may also be expressions in which the term "substantially" has been omitted.

[0042] Some embodiments are described in conjunction with functional blocks, units and / or modules in the accompanying drawings. It will be appreciated by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. For blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or by a combination of dedicated hardware that performs some functions and processors that perform different functions (e.g., one or more programmed microprocessors and related circuits). In addition, in some embodiments, without departing from the scope of the inventive concept, blocks, units and / or modules can be physically separated into two or more separate blocks, units and / or modules that interact with each other. In some embodiments, without departing from the scope of the inventive concept, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules.

[0043] The term "connection" or "combination" between two components may include both electrical connection and physical connection, but the present disclosure is not limited thereto. For example, the term "connection" used in a description with reference to a circuit diagram may refer to an electrical connection, and the term "connection" used in a description with reference to a cross-sectional view or a plan view may refer to a physical connection.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0045] However, the present disclosure is not limited to the following embodiments and may be modified in various forms. Each embodiment to be described below may be implemented alone or combined with at least another embodiment to make various combinations of the embodiments.

[0046] Figure 1 is a diagram showing a transistor 1 according to an embodiment of the present disclosure.

[0047] Reference Figure 1 , the transistor 1 according to an embodiment of the present disclosure may include a first electrode 2, a second electrode 4, a gate electrode 6, and a body electrode 8. For example, the transistor 1 may be a metal oxide semiconductor field effect transistor (MOSFET). The transistor 1 (e.g., MOSFET) including the body electrode 8 is suitable for realizing high-resolution pixels due to its reduced mounting area.

[0048] The transistor 1 may be formed on a silicon wafer. For example, the panel may be implemented by stacking layers such as a transistor layer, an emission layer, and a capping layer on a silicon wafer. However, the foregoing description is illustrative, and the transistor 1 may be formed on various known substrates (e.g., a glass substrate).

[0049] The first electrode 2 of the transistor 1 can be set as a drain electrode (or a source electrode), and the second electrode 4 of the transistor 1 can be set as a source electrode (or a drain electrode). In the case where the transistor 1 includes a body electrode 8, the threshold voltage of the transistor 1 can be changed by a body effect. The body effect refers to a change in the threshold voltage of the transistor 1 caused by a voltage difference between the body electrode 8 and the source electrode (or the second electrode 4).

[0050] Therefore, in the case where the transistor 1 including the body electrode 8 is formed as a driving transistor of the pixel, the voltage difference between the body electrode 8 and the second electrode 4 is maintained at a relatively low value. Therefore, in an embodiment of the present disclosure, a pixel using the transistor 1 including the body electrode 8 as a driving transistor and capable of compensating for a threshold voltage is proposed.

[0051] Figure 2 is a diagram illustrating a display device 100 according to an embodiment of the present disclosure. Figure 3 It is shown Figure 2 An embodiment of the scan driver 130 is shown in FIG.

[0052] Reference Figure 2 , the display device 100 according to an embodiment of the present disclosure may include a pixel component 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, and a power supply 150. The aforementioned components may be implemented as separate integrated circuits. Two or more of the aforementioned components may be implemented as a single integrated circuit. The scan driver 130 may be formed to be included in the pixel component 110.

[0053] The pixel assembly 110 may include pixels PX connected to first scan lines SL11, SL12, ..., and SL1n, second scan lines SL21, SL22, ..., and SL2n, third scan lines SL31, SL32, ..., and SL3n, data lines DL1, DL2, ..., and DLm, and power lines PL1, PL2, PL3, and PL4 (where n and m are integers of 1 or greater).

[0054] For example, the pixel PXij (refer to Figure 4) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i and the j-th data line DLj (wherein i is a positive integer less than or equal to n, and j is a positive integer less than or equal to m).

[0055] When the first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX may be selected based on horizontal lines (e.g., the pixels PX connected to the same scan line may be grouped into one horizontal line (or pixel row)). Each of the pixels PX selected by the first scan signal may receive a data signal from a corresponding data line (any one of DL1 to DLm) connected thereto. The pixels PX receiving the data signal may generate light of a certain brightness level in response to the voltage of the data signal.

[0056] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required to drive the scan driver 130. The scan driver 130 may generate a first scan signal, a second scan signal, and a third scan signal while shifting the scan start signal in response to the clock signal.

[0057] In order to achieve the above purpose, Figure 3 As shown in FIG. 1 , the scan driver 130 may include a first scan driver 132 , a second scan driver 134 , and a third scan driver 136 .

[0058] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 may sequentially supply the first scan signal to the first scan lines SL11 to SL1n.

[0059] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 in response to the clock signal The second scan driver 134 may sequentially supply the second scan signal to the second scan lines SL21 to SL2n.

[0060] The third scan driver 136 may receive the third scan start signal FLM3 and generate a third scan signal while shifting the third scan start signal FLM3 in response to the clock signal The third scan driver 136 may sequentially supply the third scan signal to the third scan lines SL31 to SL3n.

[0061] Each of the first scan signal, the second scan signal, and the third scan signal may be set to a gate-on voltage to turn on a transistor included in the pixel PX.

[0062] For example, the first scan signal, the second scan signal, and the third scan signal having a low level may be supplied to a P-type transistor. The first scan signal, the second scan signal, and the third scan signal having a high level may be supplied to an N-type transistor. The transistor supplied with the first scan signal, the second scan signal, or the third scan signal may be turned on in response to the first scan signal, the second scan signal, or the third scan signal.

[0063] The supply of the first scan signal, the second scan signal, and the third scan signal may indicate that the gate-on voltage is supplied to the first scan line SL1, the second scan line SL2, and the third scan line SL3. The absence of the first scan signal, the second scan signal, and the third scan signal may indicate that the gate-off voltage is supplied to the first scan line SL1, the second scan line SL2, and the third scan line SL3.

[0064] although Figure 3 The first scan driver 132, the second scan driver 134, and the third scan driver 136 are shown to be connected to the first scan line SL1, the second scan line SL2, and the third scan line SL3, respectively, but the embodiments of the present disclosure are not limited thereto. For example, at least two of the first scan line SL1, the second scan line SL2, and the third scan line SL3 (i.e., at least two of SL1, SL2, and SL3) may be driven by a single scan driver.

[0065] The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required to drive the data driver 140. The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may generate a grayscale signal based on the grayscale of the output data Dout in one horizontal period 1H (refer to Figure 5 ) during which the voltage of the reference power Vref and the voltage Vdata of the data signal are sequentially supplied to the data lines DL1 to DLm. The reference power Vref may be set to a constant voltage.

[0066] like Figure 2 As shown in FIG. 1 , the data driver 140 may be located at an upper side of the pixel assembly 110 . However, the present disclosure is not limited thereto, and the data driver 140 may be located at a lower side of the pixel assembly 110 .

[0067] The timing controller 120 may receive input data Din and a control signal CS from a host system through an interface. For example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The control signal CS may include various signals (including a clock signal).

[0068] The timing controller 120 may generate a scan driving signal SCS and a data driving signal DCS based on the control signal CS. The scan driving signal SCS and the data driving signal DCS may be supplied to the scan driver 130 and the data driver 140, respectively.

[0069] The timing controller 120 may readjust the input data Din to match the specifications of the display device 100. In addition, the timing controller 120 may correct the input data Din to generate output data Dout, and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din in response to an optical measurement result obtained during a manufacturing process.

[0070] The power supply 150 may generate various power voltages required to drive the display device 100. For example, the power supply 150 may generate a first driving power VDD, a second driving power VSS, a first initialization power Vint1, and a second initialization power Vint2.

[0071] The first driving power VDD may be set to supply driving current to the pixel PX. The second driving power VSS may be set to receive driving current from the pixel PX. During a period in which the pixel PX is set to an emission state, the first driving power VDD may be set to a voltage higher than that of the second driving power VSS.

[0072] The first initialization power Vint1 may be provided to enable the light emitting element LD (refer to FIG. 1 ) included in each of the pixels PX to Figure 4 ) is a voltage for initializing the first electrode (or anode electrode) of the light emitting element LD. The first initialization power Vint1 may have a voltage value that turns off the light emitting element LD when supplied to the first electrode of the light emitting element LD. For example, the first initialization power Vint1 may be set to the ground potential GND (refer to Figure 4 ). When the first initialization power Vint1 is set to the ground potential GND, the third power line PL3 may be omitted.

[0073] The second initialization power Vint2 may be a voltage provided to initialize the third capacitor C3. The second initialization power Vint2 and the reference power Vref may be set to the same voltage.

[0074] The first driving power VDD generated from the power supply 150 may be supplied to the first power line PL1, the second driving power VSS generated from the power supply 150 may be supplied to the second power line PL2, the first initialization power Vint1 generated from the power supply 150 may be supplied to the third power line PL3, and the second initialization power Vint2 generated from the power supply 150 may be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 may be commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0075] In an embodiment, the first power line PL1 may include a plurality of power lines. The power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may include a plurality of power lines. The power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may include a plurality of power lines. The power lines may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may include a plurality of power lines. The power lines may be connected to different pixels PX. In other words, in an embodiment of the present disclosure, the pixel PX may be connected to any one of the first power line PL1, any one of the second power line PL2, any one of the third power line PL3, and any one of the fourth power line PL4.

[0076] Figure 4 is a diagram showing a pixel PXij according to an embodiment of the present disclosure. Figure 4 In , the pixel PXij located on the i-th horizontal line and the j-th vertical line is determined.

[0077] Reference Figure 4 , the pixel PXij according to the embodiment of the present disclosure can be connected to the corresponding signal lines SL1i, SL2i, SL3i and DLj. For example, the pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3 and the fourth power line PL4.

[0078] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit configured to control the amount of current to be supplied to the light emitting element LD.

[0079] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. For example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the second node N2 and the first transistor M1. The second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a specific brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0080] An organic light emitting diode may be selected as the light emitting element LD. In addition, an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode may be selected as the light emitting element LD. The light emitting element LD may be an element formed by a combination of an organic material and an inorganic material. Figure 4 It is shown that the pixel PXij includes a single light emitting element LD, but the pixel PXij in the embodiment may include a plurality of light emitting elements LD. The plurality of light emitting elements LD may be connected in series, in parallel, or in combination.

[0081] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0082] Each of the first transistor M1 to the fourth transistor M4 may be a MOSFET including a body electrode. In this case, the first transistor M1 to the fourth transistor M4 may be mounted in a relatively small area, so that the pixel PXij is applied to a high-resolution panel. The body electrodes of the first transistor M1 to the fourth transistor M4 may be supplied with a first driving power VDD. For example, the body electrodes of the first transistor M1 to the fourth transistor M4 may be electrically connected to the first power line PL1.

[0083] In an embodiment, at least one of the first transistor M1 to the fourth transistor M4 may be formed by a transistor other than a MOSFET. For example, at least one of the first transistor M1 to the fourth transistor M4 may be formed by a transistor that does not include a body electrode. For example, at least one of the first transistor M1 to the fourth transistor M4 may be formed by any one of a thin film transistor (TFT), a field effect transistor (FET), and a bipolar junction transistor (BJT).

[0084] In an embodiment, each of the first to fourth transistors M1 to M4 may be formed of an N-type transistor. However, this is illustrative, and at least one of the first to fourth transistors M1 to M4 may be replaced with a P-type transistor.

[0085] The first transistor M1 (or driving transistor) may include a first electrode electrically connected to the first power line PL1 and a second electrode connected to a second node N2. Here, the second node N2 may refer to a node connected to the first electrode of the light emitting element LD. In the foregoing description, the term "connection" implies electrical connection. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current to be supplied from the first driving power VDD to the second driving power VSS via the light emitting element LD in response to the voltage of the first node N1.

[0086] A first electrode of the second transistor M2 may be electrically connected to the data line DLj, and a second electrode of the second transistor M2 may be connected to the first node N1. A gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. When a first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned on to electrically connect the data line DLj to the first node N1.

[0087] The third transistor M3 may include a first electrode connected to the second node N2 and a second electrode electrically connected to the third power line PL3. The gate electrode of the third transistor M3 may be electrically connected to the second scan line SL2i. When the second scan signal GI is supplied to the second scan line SL2i, the third transistor M3 may be turned on to electrically connect the second node N2 with the third power line PL3.

[0088] The fourth transistor M4 may include a first electrode electrically connected to the fourth power line PL4 and a second electrode electrically connected to the first electrode of the third capacitor C3. The gate electrode of the fourth transistor M4 may be electrically connected to the third scan line SL3i. When the third scan signal GR is supplied to the third scan line SL3i, the fourth transistor M4 may be turned on to electrically connect the fourth power line PL4 to the first electrode of the third capacitor C3.

[0089] The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first capacitor C1 may store a voltage between the first node N1 and the second node N2. The first capacitor C1 may function as a coupling capacitor and control a voltage of the second node N2 in response to a voltage change of the first node N1.

[0090] The second capacitor C2 may include a first electrode connected to the second node N2 and a second electrode electrically connected to the third power line PL3. The second capacitor C2 together with the first capacitor C1 may control a voltage variation of the second node N2 in response to a voltage variation on the first node N1.

[0091] The third capacitor C3 may include a first electrode connected to the second electrode of the fourth transistor M4 and a second electrode connected to the first node N1.

[0092] Figure 5 Is shown driving Figure 4 0045] A waveform diagram of an embodiment of the method for a pixel PXij is shown in FIG.

[0093] Reference Figure 5 , a horizontal period 1H (or a specific horizontal period) in which data signals are supplied to pixels PXij located on an i-th horizontal line and a j-th vertical line may be divided into a first period T1, a second period T2, and a third period T3.

[0094] The data driver 140 may supply a voltage of the reference power Vref to the data line DLj during the first period T1 and the second period T2, and may supply a voltage Vdata of the data signal to the data line DLj during the third period T3. The reference power Vref may be set to a voltage between the first driving power VDD and the second driving power VSS. For example, the reference power Vref may be set to the same voltage as the second initialization power Vint2.

[0095] The scan driver 130 (or the first scan driver 132 ) may supply the first scan signal GW to the first scan line SL1 i during the first to third periods T1 to T3 .

[0096] The scan driver 130 (or the second scan driver 134 ) may supply the second scan signal GI to the second scan line SL2 i during the first period T1 .

[0097] The scan driver 130 (or the third scan driver 136 ) may supply the third scan signal GR to the third scan line SL3 i during the first period T1 .

[0098] The first period T1 may be a period in which the first capacitor C1, the second capacitor C2, the third capacitor C3, and the light emitting element LD are initialized. The first period T1 may be referred to as an initialization period.

[0099] The second period T2 may be a period for compensating the threshold voltage of the first transistor M1. During the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1. The second period T2 may be referred to as a threshold voltage compensation period.

[0100] The third period T3 may be a period in which the voltage Vdata of the data signal is supplied from the data line DLj to the pixel PXij. During the third period T3, the voltage Vdata of the data signal may be supplied to the first node N1. The third period T3 may be referred to as a data writing period.

[0101] The fourth period T4 is a period in which the light emitting element LD emits light. During the fourth period T4, the first transistor M1 may control the amount of current flowing from the first driving power VDD to the second driving power VSS via the light emitting element LD in response to the voltage of the first node N1. During the fourth period T4, the light emitting element LD may emit light of a brightness corresponding to the amount of current. The fourth period T4 may be referred to as an emission period.

[0102] FIG. 6A to FIG. 6D is shown with Figure 5 The driving waveform in FIG. 4 corresponds to the process of operating the pixel PXij.

[0103] Reference Fig. 6A In the first period T1, the first scan signal GW is supplied to the first scan line SL1i, the second scan signal GI is supplied to the second scan line SL2i, and the third scan signal GR is supplied to the third scan line SL3i.

[0104] The first scan signal GW supplied to the first scan line SL1i turns on the second transistor M2. If the second transistor M2 is turned on, the data line DLj may be electrically connected to the first node N1. As a result, the voltage of the reference power Vref is supplied from the data line DLj to the first node N1.

[0105] The second scan signal GI supplied to the second scan line SL2i turns on the third transistor M3. If the third transistor M3 is turned on, the voltage of the first initialization power Vint1 is supplied to the second node N2. If the voltage of the first initialization power Vint1 is supplied to the second node N2, the light emitting element LD can be initialized. For example, a parasitic capacitor (not shown) of the light emitting element LD can be discharged by the voltage of the first initialization power Vint1. Here, the first initialization power Vint1 can be set to a voltage that causes the light emitting element LD not to emit light. As a result, the light emitting element LD can be set to a non-emitting state. For example, the first initialization power Vint1 can be set to a ground potential GND.

[0106] If the third scan signal GR is supplied to the third scan line SL3i, the fourth transistor M4 is turned on. If the fourth transistor M4 is turned on, the voltage of the second initialization power Vint2 is supplied to the first electrode of the third capacitor C3. Here, the voltage of the second initialization power Vint2 is supplied to the first electrode of the third capacitor C3, and the voltage of the reference power Vref is supplied to the second electrode of the third capacitor C3. In this case, the third capacitor C3 can be initialized regardless of the voltage in the previous frame period. For example, the reference power Vref and the second initialization power Vint2 can be set to the same voltage. In this case, the voltage charged into the third capacitor C3 during the previous frame period can be discharged.

[0107] During the first period T1, the voltage of the reference power Vref (from the data line DLj) is supplied to the first node N1, and the voltage of the first initialization power Vint1 is supplied to the second node N2. Therefore, regardless of the voltage in the previous frame period, the first capacitor C1 can be initialized. In addition, since the voltage of the first initialization power Vint1 is supplied to the second node N2 during the first period T1, regardless of the voltage in the previous frame period, the second capacitor C2 can be initialized.

[0108] In other words, in the first period T1, the second transistor M2, the third transistor M3, and the fourth transistor M4 may be turned on. Therefore, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the light emitting element LD may be initialized.

[0109] Reference Figure 6B During the second period T2, the supply of the second scan signal GI to the second scan line SL2i is interrupted, and the supply of the third scan signal GR is interrupted. If the supply of the second scan signal GI to the second scan line SL2i is interrupted, the third transistor M3 is turned off. If the supply of the third scan signal GR to the third scan line SL3i is interrupted, the fourth transistor M4 is turned off.

[0110] During the second period T2, the first scan signal GW is kept supplied to the first scan line SL1i so that the second transistor M2 can remain turned on. If the second transistor M2 remains turned on, the voltage of the reference power Vref is supplied to the first node N1. Here, the voltage of the reference power Vref can be set to turn on the first transistor M1.

[0111] If the first transistor M1 is turned on while the voltage of the reference power Vref is supplied to the first node N1, the voltage of the second node N2 increases to a voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the reference power Vref. As a result, the first transistor M1 is turned off.

[0112] During the second period T2, the voltage of the first node N1 is set to the voltage of the reference power Vref, and the voltage of the second node N2 is set to the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the reference power Vref. Therefore, during the second period T2, the threshold voltage of the first transistor M1 can be stored in the first capacitor C1. In addition, when the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the reference power Vref is applied to the second node N2, the voltage of the reference power Vref can be set to a voltage that turns off the light emitting element LD.

[0113] Reference Figure 6C During the third period T3, the second transistor M2 is kept turned on by the first scan signal GW supplied to the first scan line SL1i. In this case, the voltage Vdata of the data signal may be supplied from the data line DLj to the second node N2.

[0114] If the voltage Vdata of the data signal is supplied to the second node N2, the voltage of the first node N1 may be changed from the voltage of the reference power Vref to the voltage Vdata of the data signal. The voltage of the second node N2 may also be changed due to coupling of the first capacitor C1.

[0115] Here, the voltage change of the second node N2 may be determined in response to the ratio of the first capacitor C1 and the second capacitor C2. For example, the voltage of the second node N2 may be changed from the voltage obtained by subtracting the threshold voltage of the first transistor M1 from the voltage of the reference power Vref to a value obtained by multiplying the voltage change of the first node N1 by C1 / (C1+C2). In the case where the voltage change of the second node N2 is controlled by the ratio of the first capacitor C1 and the second capacitor C2, the voltage range of the data signal may be sufficiently widened.

[0116] The amount of current flowing from the first transistor M1 to the light emitting element LD during the fourth period T4 can be determined by the voltages of the first node N1 and the second node N2 (i.e., Vgs). In the case where the voltage variation of the second node N2 is controlled by the ratio of the first capacitor C1 and the second capacitor C2, the voltage variation of the second node N2 can be set to a small value corresponding to the voltage variation of the first node N1. As a result, the voltage range of the data signal can be sufficiently widened.

[0117] For example, in the case where the voltage range of the data signal is relatively small, it is necessary to use a small voltage range to realize various gray levels (e.g., 256 gray levels). Therefore, it becomes difficult to represent accurate gray levels. On the other hand, as described in the embodiments of the present disclosure, in the case where the voltage of the second node N2 is controlled by the ratio of the first capacitor C1 and the second capacitor C2, the voltage range of the data signal can be set to a sufficiently large range. As a result, gray levels can be easily realized.

[0118] Reference Fig.6D During the fourth period T4, the supply of the first scan signal GW to the first scan line SL1i is interrupted, so that the second transistor M2 is set to a turned-off state.

[0119] The first transistor M1 may control the amount of current supplied from the first driving power VDD to the second driving power VSS via the light emitting element LD in response to voltages of the first node N1 and the second node N2. The light emitting element LD may generate light having brightness corresponding to the amount of current supplied from the first transistor M1.

[0120] Regardless of the threshold voltage of the first transistor M1 , the amount of current supplied from the first transistor M1 to the light emitting element LD during the fourth period T4 may be determined as shown in Equation 1.

[0121] [Equation 1]

[0122]

[0123] In Equation 1, ILD represents a current supplied to the light emitting element LD, and k represents a proportionality constant determined by mobility, parasitic capacitance, channel capacitance, and the like of the first transistor M1.

[0124] Referring to Equation 1, it can be understood that the amount of current supplied from the first transistor M1 is determined by the voltage Vdata of the data signal, the voltage of the reference power Vref, and the ratio of the first capacitor C1 and the second capacitor C2 regardless of the threshold voltage of the first transistor M1.

[0125] Figure 7 is a diagram showing a voltage range of a data signal corresponding to the capacitance of the second capacitor C2.

[0126] Reference Figure 7 It can be understood that as the capacitance of the second capacitor C2 increases, the voltage range of the data signal also increases. In other words, as the capacitance of the second capacitor C2 increases, the voltage change of the second node N2 corresponding to the voltage change of the first node N1 decreases. As a result, the voltage range of the data signal can be increased.

[0127] In an embodiment of the present disclosure, the capacitance of the first capacitor C1 and the second capacitor C2 may be set so that C2 / C1 is 0.1 or greater. For example, when the capacitance of the first capacitor C1 and the second capacitor C2 satisfies C2 / C1≥0.1, the voltage range of the data signal may be set to a wide range, and the capacitors C1 and C2 may be easily formed during the manufacturing process.

[0128] Figure 8 is a graph showing the voltage variation of the second node N2 in the embodiment of the present disclosure and the comparative example. Figure 8 In the embodiment of the present disclosure, Figure 4 The pixel PXij shown in FIG. 1 and the comparative example refer to the pixel PXij from Figure 4 The case where the second capacitor C2 is removed from the pixel PXij in FIG. Figure 8 In the diagram, the Y-axis represents voltage and the X-axis represents time.

[0129] Reference Figure 8 In the case of the comparative example, when the voltage Vdata of the data signal is supplied, the voltage of the second node N2 changes significantly. Figure 4 In the case where the second capacitor C2 is removed from the pixel PXij, the voltage change of the first node N1 can be directly transmitted to the second node N2 through the first capacitor C1. In this case, the voltage of the second node N2 can be significantly changed corresponding to the voltage Vdata of the data signal.

[0130] On the other hand, in an embodiment of the present disclosure, a voltage variation of the first node N1 may be transmitted to the second node N2 corresponding to a ratio of the first capacitor C1 and the second capacitor C2, whereby a voltage of the second node N2 may slightly change corresponding to a voltage Vdata of a data signal.

[0131] Here, the slight change in the voltage of the second node N2 means that the voltage difference (i.e., Vbs) between the body electrode and the source electrode of the first transistor M1 is kept low. In other words, in the embodiment of the present disclosure, the use of the first transistor M1 composed of a MOSFET can keep the voltage difference between the body electrode and the source electrode low. Therefore, reliable driving operation can be ensured.

[0132] For example, in the case of the comparative example, the voltage difference (ie, Vbs) between the body electrode and the source electrode of the first transistor M1 is set to a large value. Therefore, when the threshold voltage of the first transistor M1 changes by ±50 mV, the current error of the gray level 32 is set to about 76.06%.

[0133] On the other hand, in the case of the embodiment of the present disclosure, the voltage difference (ie, Vbs) between the body electrode and the source electrode of the first transistor M1 is set to a relatively small value. Therefore, when the threshold voltage of the first transistor M1 changes by ±50mV, the current error of the gray level 32 is set to about 58%.

[0134] Fig. 9 is a graph showing current errors in the embodiment of the present disclosure and in the comparative example. Fig. 9 , the X-axis represents the gray scale, and the Y-axis represents the current error. The current error is expressed as a percentage (%), and represents a change in the driving current in response to a change in the threshold voltage of the first transistor M1. Fig. 9 The current error when the threshold voltage of the first transistor M1 changes by ±50 mV is shown.

[0135] Reference Fig. 9 In the case of the comparative example, when the threshold voltage of the first transistor M1 changes by ±50 mV, the current error can be set to about ±76% or less. In contrast, in the case of the embodiment of the present disclosure, when the threshold voltage of the first transistor M1 changes by ±50 mV, the current error can be set to about ±58% or less.

[0136] Compared with the comparative example, in the case of the present disclosure, a current error corresponding to a variation in the threshold voltage of the first transistor M1 may be minimized.

[0137] Fig.10 is a diagram showing a pixel PXaij according to an embodiment of the present disclosure. Fig.10 In the following description, the Figure 4 The description is repeated with explanation.

[0138] Reference Fig.10 , according to an embodiment of the present disclosure, the pixel PXaij can be connected to the corresponding signal lines SL1i, SL2i and DLj. For example, the pixel PXaij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i and the j-th data line DLj. In an embodiment, the pixel PXaij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3 and the fourth power line PL4.

[0139] A pixel PXaij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit configured to control an amount of current to be supplied to the light emitting element LD.

[0140] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2 and may generate light of a specific brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0141] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4a, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0142] The fourth transistor M4a may include a first electrode electrically connected to the fourth power line PL4 and a second electrode electrically connected to the first electrode of the third capacitor C3. The gate electrode of the fourth transistor M4a may be electrically connected to the second scan line SL2i. When the second scan signal GI is supplied to the second scan line SL2i, the fourth transistor M4a may be turned on to electrically connect the fourth power line PL4 to the first electrode of the third capacitor C3.

[0143] and Figure 4 Compared with the fourth transistor M4 shown in FIG. 1 , the fourth transistor M4a has a gate electrode connected to the second scan line SL2i, but the operation process thereof is the same. Therefore, a detailed description of the operation process will be omitted.

[0144] In the case where the gate electrode of the fourth transistor M4a is connected to the second scan line SL2i, the third scan line SL3i can be omitted. In the case where the third scan line SL3i is omitted, the mounting area of ​​each of the pixels PX can be reduced, thus making it easier to apply the pixel PX to a high-resolution panel. In addition, in the case where the third scan line SL3i is omitted, the degree of freedom of design can be improved.

[0145] In addition, in the case where the third scan line SL3i is omitted, the third scan driver 136 may also be omitted. In the case where the third scan driver 136 is omitted, the mounting area of ​​the scan driver 130 may be reduced, thereby minimizing the dead zone.

[0146] Hereinafter, an electronic device to which the display device 100 according to the aforementioned embodiment can be applied will be described.

[0147] Figures 11 to 14 is a diagram illustrating an electronic device according to various embodiments.

[0148] Reference Fig.11 , the display device 100 according to the aforementioned embodiment may be applied to smart glasses. Smart glasses may include a frame 111 and a lens assembly 112. Smart glasses are wearable electronic devices worn on the user's face (e.g., covering the eyes), and may have a structure that allows a portion of the frame 111 to be folded or unfolded. For example, smart glasses may be a wearable device for augmented reality (AR).

[0149] The frame 111 may include a housing 111b supporting the lens assembly 112 and a leg assembly 111a enabling a user to wear the smart glasses. The leg assembly 111a is coupled to the housing 111b by a hinge, and thus may be folded or unfolded.

[0150] The frame 111 may be equipped with a battery, a touch panel, a microphone and / or a camera. In addition, the frame 111 may be equipped with a projector configured to output light and / or a processor configured to control an optical signal.

[0151] The lens assembly 112 may be an optical assembly configured to transmit or reflect light. The lens assembly 112 may include glass and / or a transparent synthetic resin.

[0152] The display device 100 according to the aforementioned embodiment may be applied to the lens assembly 112. For example, the user may perceive an image displayed by an optical signal transmitted from the projector in the frame 111 through the lens assembly 112. For example, the user may perceive information such as time and data displayed on the lens assembly 112.

[0153] Reference Fig.12 The display device 100 according to the aforementioned embodiment may be applied to a head mounted display device (HMD). The HMD may include a head mounting band 121 and a display housing 122. For example, the HMD may be a wearable electronic device that can be worn on the user's head.

[0154] The head mounting band 121 is coupled to the display housing 122 and is used to mount the display housing 122 on the user's head. The head mounting band 121 may include a horizontal band and a vertical band for mounting the HMD to the user's head, and may be configured so that the horizontal band surrounds the side of the user's head and the vertical band surrounds the upper part of the user's head. However, the present disclosure is not limited to the aforementioned embodiments. For example, the head mounting band 121 may be implemented in the form of a glasses frame or a helmet.

[0155] The display housing 122 can house the display device 100 and include at least one lens. At least one lens can provide an image to the user. For example, the display device 100 according to the aforementioned embodiment can be applied to a left eye lens and a right eye lens implemented in the display housing 122.

[0156] Reference Fig.13 , the display device 100 according to the aforementioned embodiment may be applied to a smart watch. The smart watch may include a display component 131 and a band component 133. The smart watch is a wearable electronic device. The band component 133 may be mounted on a user's wrist. The display device 100 according to the aforementioned embodiment may be applied to the display component 131. For example, the display component 131 may provide image data including information such as time, date, etc.

[0157] Reference Fig.14 The display device 100 according to the aforementioned embodiment may be applied to a car display. For example, the car display may be an electronic device provided inside or outside a vehicle to provide image data.

[0158] For example, the display device 100 according to the aforementioned embodiment can be applied to at least one of an infotainment panel 141, an instrument panel 142, an auxiliary driving display 143, a head-up display 144, a side-view mirror display 145 and a rear seat display 146 that can be set in a vehicle.

[0159] In a pixel and a display device including the pixel according to an embodiment of the present disclosure, the pixel may be implemented using a transistor suitable for high resolution, for example, a metal oxide semiconductor field effect transistor (MOSFET).

[0160] In addition, the pixel according to the embodiment of the present disclosure may include a driving transistor having a body electrode, and the threshold voltage of the driving transistor may be reliably compensated.

[0161] In addition, the pixel according to the embodiment of the present disclosure may transmit the data signal using capacitor coupling, whereby the voltage range of the data signal may be set to a relatively large range.

[0162] However, the effects of the present disclosure are not limited to the above-described effects, and various modifications may be made without departing from the spirit and scope of the present disclosure.

[0163] While embodiments of the present disclosure have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure as embodied in the accompanying claims.

Claims

1. A pixel, comprising: a first transistor including a first electrode electrically connected to a first power line configured to receive a first driving power, a second electrode, and a gate electrode connected to a first node; a second transistor connected between the data line and the first node and including a gate electrode electrically connected to the first scan line; a light emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode electrically connected to a second power line configured to receive a second driving power; a first capacitor connected between the first node and the first electrode of the light emitting element; as well as The second capacitor is connected between the first electrode of the light emitting element and a third electric force line.

2. The pixel according to claim 1, wherein: A ratio of a capacitance of the second capacitor to a capacitance of the first capacitor is at least 0.

1.

3. The pixel according to claim 1, wherein: The third power line receives a first initialization power having a voltage value that turns off the light emitting element in response to receiving the first initialization power at the first electrode of the light emitting element.

4. The pixel according to claim 3, wherein: The first initialization power is ground power.

5. The pixel according to claim 1, further comprising: a third transistor connected between the first electrode of the light emitting element and the third power line and including a gate electrode electrically connected to a second scan line; a third capacitor including a first electrode and a second electrode connected to the first node; as well as A fourth transistor includes a first electrode electrically connected to a fourth power line, a second electrode connected to the first electrode of the third capacitor, and a gate electrode electrically connected to a third scan line.

6. The pixel according to claim 5, wherein: Each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a metal oxide semiconductor field effect transistor including a body electrode, and The first driving power is supplied to the body electrode of each of the first transistor, the second transistor, the third transistor, and the fourth transistor.

7. The pixel according to claim 5, wherein: The third scan line and the second scan line include the same scan line.

8. The pixel according to claim 5, in, The horizontal period includes the first period, the second period and the third period. wherein during the first period and the second period, a voltage of a reference power is supplied to the data line, and during the third period, a voltage of a data signal is supplied to the data line, and The reference power is a voltage value between the first driving power and the second driving power.

9. The pixel according to claim 8, wherein: Second initialization power is supplied to the fourth power line, and the reference power has a voltage equal to that of the second initialization power.

10. The pixel according to claim 8, in, During the first period, the second transistor, the third transistor and the fourth transistor are turned on, and During the second period and the third period, the second transistor is turned on, and the third transistor and the fourth transistor are turned off.

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