Pixel

Abstract

A pixel includes: a first transistor including a first electrode, a second electrode, and a gate electrode connected to a first node, a second node, and a third node, respectively; a second transistor connected between the data line and the third node, the second transistor including a gate electrode connected to the first scan line; a third transistor connected between a first power line to which a voltage of the first driving power source is supplied and the first node, the third transistor including a gate electrode connected to an emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and a second power line to which the voltage of the second driving power source is supplied; and a light emitting element connected between the second node and the second power line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0084442 filed in the Korean Intellectual Property Office on June 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to pixels and display devices including pixels. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information increases. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used.

[0005] Recently, a head mounted display device (HMD) has been developed. The HMD is a display device that a user wears in the form of glasses or a helmet, thereby realizing virtual reality (VR) or augmented reality (AR) that forms a focus at a distance close to the eyes. A high-resolution panel is applied to the HMD, and therefore, pixels that can be applied to the high-resolution panel are required.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore the above information may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0007] The embodiment provides a pixel that can be applied to a high-resolution panel and a display device including the same.

[0008] According to aspects of the present disclosure, a pixel is provided, the pixel comprising a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a third capacitor and a light-emitting element. The first transistor comprises a first electrode connected to a first node, a second electrode connected to a second node and a gate electrode connected to a third node. The second transistor is connected between a data line and the third node, and the second transistor comprises a gate electrode connected to a first scan line. The third transistor is connected between a first power line to which a voltage of a first driving power source is supplied and the first node, and the third transistor comprises a gate electrode connected to an emission control line. The first capacitor is connected between the first node and the third node. The second capacitor is connected between the second node and the third node. The third capacitor is connected between the third node and the second power line to which a voltage of a second driving power source is supplied. The light-emitting element is connected between the second node and the second power line.

[0009] The pixel may further include a fourth transistor including a first electrode connected to the second node, a second electrode connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode connected to the second scan line.

[0010] When the voltage of the initialization power source is supplied to the second node, the light emitting element may be turned off.

[0011] Each of the first to fourth transistors may be a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode.

[0012] The voltage of the first driving power source may be supplied to the body electrode of each of the first to fourth transistors.

[0013] One horizontal period may include a first period, a second period, and a third period. During the first period, the second transistor, the third transistor, and the fourth transistor may be set to be in an on state. During the second period, the second transistor and the fourth transistor may be set to be in the on state, and the third transistor may be set to be in an off state. During the third period, the third transistor and the fourth transistor may be set to be in the on state, and the second transistor may be set to be in the off state.

[0014] A voltage of a data signal may be supplied to the data line during the first period to the third period.

[0015] According to another aspect of the present disclosure, a pixel is provided, the pixel comprising a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a third capacitor and a light-emitting element. The first transistor comprises a first electrode connected to a first node, a second electrode connected to a second node and a gate electrode connected to a third node. The second transistor is connected between a data line and the third node, and the second transistor comprises a gate electrode connected to a first scan line. The third transistor is connected between a first power line to which a voltage of a first driving power source is supplied and the first node, and the third transistor comprises a gate electrode connected to an emission control line. The first capacitor is connected between the first node and the third node. The second capacitor is connected between the second node and the third node. The third capacitor is connected between the third node and the first power line. The light-emitting element is connected between the second node and the second power line to which a voltage of a second driving power source is supplied.

[0016] The third capacitor may be supplied with the voltage of the first driving power source through the first power line.

[0017] The pixel may further include a fourth transistor including a first electrode connected to the second node, a second electrode connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode connected to the second scan line.

[0018] When the voltage of the initialization power source is supplied to the second node, the light emitting element may be turned off.

[0019] Each of the first to fourth transistors may be a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode, and the voltage of the first driving power source may be supplied to the body electrode of each of the first to fourth transistors.

[0020] One horizontal period may include a first period, a second period, and a third period. During the first period, the second transistor, the third transistor, and the fourth transistor may be set to be in an on state. During the second period, the second transistor and the fourth transistor may be set to be in the on state, and the third transistor may be set to be in an off state. During the third period, the third transistor and the fourth transistor may be set to be in the on state, and the second transistor may be set to be in the off state. The voltage of the data signal may be supplied to the data line during the first period to the third period.

[0021] According to another aspect of the present disclosure, a display device is provided, the display device includes pixels connected to a write scan line, an initialization scan line, a data line and an emission control line. The pixel located in the i-th pixel row (where i is an integer of 1 or greater) and the j-th pixel column (where j is an integer of 1 or greater) includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, a third capacitor and a light-emitting element. The first transistor includes a first electrode connected to a first node, a second electrode connected to a second node and a gate electrode connected to a third node. The second transistor is connected between the j-th data line and the third node among the data lines, and when the first scan signal is supplied to the first scan line among the write scan lines, the second transistor is turned on. The third transistor is connected between the first power line to which the voltage of the first driving power source is supplied and the first node, and when the emission control signal is supplied to the k-th emission control line (where k is an integer of 1 or greater), the third transistor is turned off. The first capacitor is connected between the first node and the third node. The second capacitor is connected between the second node and the third node. The third capacitor is connected to the third node. The light emitting element is connected between the second node and a second power line to which a voltage of a second driving power source is supplied.

[0022] The third capacitor may be connected between the third node and the second power line.

[0023] The third capacitor may be connected between the third node and the first power line.

[0024] The pixels located in the i-th pixel row and the j-th pixel column may further include a fourth transistor, the fourth transistor including a first electrode connected to the second node and a second electrode connected to a third power line to which a voltage from an initialization power source is supplied, and the fourth transistor is turned on when a second scan signal is supplied to a second scan line among the initialization scan lines.

[0025] Each of the first to fourth transistors may be a metal oxide semiconductor field effect transistor (MOSFET) including a body electrode, and the voltage of the first driving power source may be supplied to the body electrode of each of the first to fourth transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0027] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. The same reference numerals refer to the same elements throughout.

[0028] Figure 1 is a diagram showing a transistor according to an embodiment of the present disclosure.

[0029] Figure 2 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 3 It is shown Figure 2 FIG. 4 is a diagram of an embodiment of a pixel unit, a scan driver, and an emission driver shown in FIG.

[0031] Figure 4 It is shown Figure 2 An embodiment of a pixel is shown in FIG.

[0032] Figure 5 It is shown Figure 4 0 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0033] Figure 6 , Figure 7 , Figure 8 and Fig. 9 is an example of an operation process of a pixel. Figure 5 The driving waveform shown in the figure corresponds to the figure.

[0034] Fig.10 It is shown Figure 2 An embodiment of a pixel is shown in FIG. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the following description, only the necessary parts for understanding the operation according to the present disclosure are described, and the description of other parts is omitted so as not to unnecessarily obscure the subject matter of the present disclosure. In addition, the present disclosure is not limited to the exemplary embodiments described herein, but can be implemented in various different forms. On the contrary, the exemplary embodiments described herein are provided to describe the disclosed content in detail and completely, and the idea of ​​the present disclosure is fully conveyed to those of ordinary skill in the art.

[0036] Throughout the specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or indirectly connected or coupled to another element, with one or more intermediate elements between the element and another element. The technical terms used in this article are only for the purpose of illustrating a specific embodiment, and are not intended to limit the embodiment. It will be understood that when a component "includes" an element, unless there is another description contrary thereto, it should be understood that the component does not exclude another element, but may further include another element. It will be understood that, for the purpose of this disclosure, "at least one of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items in X, Y, and Z (e.g., XYZ, XY, YZ, XZ). Similarly, for the purpose of this disclosure, "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more items in X, Y, and Z (e.g., XYZ, XY, YZ, XZ).

[0037] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0038] In addition, embodiments of the present disclosure are described herein with reference to schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the drawings are schematic in nature, and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the present disclosure.

[0039] Figure 1 is a diagram showing a transistor 10 according to an embodiment of the present disclosure.

[0040] Reference Figure 1 , the transistor 10 according to an embodiment of the present disclosure may include a first electrode 12, a second electrode 14, a gate electrode 16, and a body electrode 18. In an example, the transistor 10 may be a metal oxide semiconductor field effect transistor (MOSFET). Since the transistor 10 (e.g., MOSFET) including the body electrode 18 has a small mounting area, the transistor 10 may be suitable for realizing a high-resolution pixel.

[0041] The transistor 10 may be formed on a silicon wafer. In an example, a transistor layer, a light emitting layer, a cover layer, etc. may be stacked on a silicon wafer to implement a panel. However, this is merely illustrative, and the transistor 10 may be formed on various substrates currently known in the art (e.g., a glass substrate).

[0042] The first electrode 12 of the transistor 10 may be set as a source electrode (or a drain electrode), and the second electrode 14 of the transistor 10 may be set as a drain electrode (or a source electrode). When the transistor 10 includes a body electrode 18, the threshold voltage of the transistor 10 may be changed by a body effect. The body effect refers to that the threshold voltage of the transistor 10 changes due to a voltage difference between the body electrode 18 and the first electrode 12 of the transistor 10.

[0043] According to an embodiment of the present disclosure, when the transistor 10 including the body electrode 18 is used as a driving transistor, threshold voltage compensation may be possible.

[0044] Figure 2 is a diagram illustrating a display device 100 according to an embodiment of the present disclosure. Figure 3 It is shown Figure 2 1 , a diagram of an embodiment of a pixel unit 110, a scan driver 130, and an emission driver 160 shown in FIG.

[0045] Reference Figure 2 , the display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, a power supply 150, and an emission driver 160. The above components may be implemented as separate integrated circuits, and at least two of the above components may be integrated into one integrated circuit. In addition, the scan driver 130 and / or the emission driver 160 may be formed in the pixel unit 110.

[0046] The pixel unit 110 may include pixels PX connected to write scan lines SL11, SL12, ... and SL1n, initialization scan lines SL21, SL22, ... and SL2n, data lines DL1, DL2, ... and DLm, emission control lines EL1, EL2, ... and ELo, and power lines PL1, PL2 and PL3, where n, m and o are integers of 1 or greater.

[0047] For example, the pixel PXij located in the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) (see, for example, Figure 4) can be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk and the j-th data line DLj, where i is a positive integer of n or less, j is a positive integer of m or less, and k is a positive integer of o or less. Here, k is a number equal to or less than i. In the example, when each of the emission control lines EL1 to ELo is connected to the pixels PX located in one horizontal line, k may be a number equal to i. In the example, when each of the emission control lines EL1 to ELo is connected to the pixels PX located in at least two horizontal lines, k may be a number less than i.

[0048] The pixels PX may be selected in units of horizontal lines, for example, when the first scan signal is supplied to the write scan lines SL11 to SL1n, the pixels PX connected to the same scan line may be classified as one horizontal line (or pixel row). The pixels PX selected by the first scan signal may be supplied with a data signal from a data line (a corresponding one of the data lines DL1 to DLm) connected thereto. The pixels PX supplied with the data signal may generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0049] The timing controller 120 may receive input data Din and a control signal CS from a host system through an interface. In an example, the timing controller 120 may receive input data Din and a control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. Various signals including a clock signal may be included in the control signal CS.

[0050] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 160, respectively.

[0051] The timing controller 120 may rearrange the input data Din to be suitable for the specification of the display device 100. In addition, the timing controller 120 may generate output data Dout by correcting the input data Din, and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din corresponding to the optical measurement result measured during the process.

[0052] The scan driver 130 may receive a scan driving signal SCS from the timing controller 120. A scan start signal and a clock signal required for driving the scan driver 130 may be included in the scan driving signal SCS. In response to the clock signal, the scan driver 130 may generate a first scan signal and a second scan signal while shifting the scan start signal.

[0053] To this end, the scan driver 130 may include Figure 3 The first scan driver 132 and the second scan driver 134 are shown in FIG.

[0054] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 in response to the clock signal. The first scan driver 132 may sequentially supply the first scan signal to the write scan lines SL11 to SL1n.

[0055] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially supply the second scan signal to the initialization scan lines SL21 to SL2n. The first scan signal and the second scan signal may be set to a gate-on voltage so that the transistor included in the pixel PX may be turned on.

[0056] In the example, the first scan signal and the second scan signal having a low level may be supplied to the P-type transistor, and the first scan signal and the second scan signal having a high level may be supplied to the N-type transistor. The transistor supplied with the first scan signal or the second scan signal may be turned on in response to the first scan signal or the second scan signal. Thereafter, supplying the first scan signal and the second scan signal may mean that the gate-on voltage is supplied to the write scan line SL1 and the initialization scan line SL2. In addition, not supplying the first scan signal and the second scan signal may mean that the gate-off voltage is supplied to the write scan line SL1 and the initialization scan line SL2.

[0057] exist Figure 3 , it is shown that the first scan driver 132 and the second scan driver 134 are connected to the write scan line SL1 and the initialization scan line SL2, respectively. However, the embodiments of the present disclosure are not limited thereto. In an example, the write scan line SL1 and the initialization scan line SL2 may be driven by one scan driver.

[0058] The data driver 140 may receive the output data Dout and the data driving signal DCS from the timing controller 120. The data driving signal DCS may include a sampling signal and / or a timing signal required to drive the data driver 140.

[0059] The data driver 140 may generate a data signal based on the data driving signal DCS and the output data Dout. For example, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout.

[0060] The data driver 140 may apply a specific voltage to the data lines DL1 to DLm based on the generated analog data signal. Figure 5 , the data driver 140 may be configured to generate a plurality of pulses of data in a horizontal period 1H (eg, see Figure 5 ) during which the voltage Vdata of the data signal (for example, see Figure 5 ) are supplied to the data lines DL1 to DLm.

[0061] The power supply 150 may generate various power sources required for driving of the display device 100. For example, the power supply 150 may generate a first driving power source VDD, a second driving power source VSS, and an initialization power source Vint.

[0062] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that is supplied with a driving current from the pixel PX. During a period in which the pixel PX is set to be in an emission state, the first driving power source VDD may be set to a voltage higher than a voltage of the second driving power source VSS.

[0063] The initialization power source Vint may be a power source for each of the light emitting elements LD (see, for example, Figure 4 ) is a power source for initializing the first electrode (or anode electrode) of the light emitting element LD. When the voltage of the initialization power source Vint is supplied to the first electrode of the light emitting element LD, the initialization power source Vint may have a voltage value that turns off the light emitting element LD.

[0064] A voltage of a first driving power source VDD generated in the power supply 150 may be supplied to the first power line PL1, a voltage of a second driving power source VSS generated in the power supply 150 may be supplied to the second power line PL2, and a voltage of an initialization power source Vint generated in the power supply 150 may be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0065] In an embodiment, the first power line PL1 may be configured with a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be configured with a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be configured with a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in an embodiment of the present disclosure, a pixel PX may be connected to any one of the plurality of power lines of the first power line PL1, any one of the plurality of power lines of the second power line PL2, and any one of the plurality of power lines of the third power line PL3.

[0066] The emission driver 160 may receive the emission driving signal ECS from the timing controller 120. The emission start signal EFLM (eg, see Figure 3 ) and a clock signal may be included in the emission driving signal ECS. The emission driver 160 may generate an emission control signal while shifting the emission start signal EFLM in response to the clock signal. The emission driver 160 may sequentially supply the emission control signal to the emission control lines EL1 to ELo. The emission control signal may be set to a gate-off voltage so that the transistor included in the pixel PX may be turned off.

[0067] In the example, the emission control signal with a high level may be supplied to the P-type transistor, and the emission control signal with a low level may be supplied to the N-type transistor. The transistor receiving the emission control signal may be turned off in response to the emission control signal. Afterwards, supplying the emission control signal may mean that the gate-off voltage is supplied to the emission control line EL. In addition, not supplying the emission control signal may mean that the gate-on voltage is supplied to the emission control line EL.

[0068] Figure 4 It is shown Figure 2 FIG. 1 is a diagram of an embodiment of a pixel PX shown in FIG. Figure 4 , pixels PXij located in the i-th horizontal line and the j-th vertical line will be shown.

[0069] Reference Figure 4 , according to an embodiment of the present disclosure, the pixel PXij can be connected to the corresponding i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk and the j-th data line DLj. For example, the pixel PXij can be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1, the second power line PL2 and the third power line PL3.

[0070] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0071] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. In an example, the first electrode (or anode electrode) of the light emitting element LD may be connected to the first power line PL1 via the second node N2, the first transistor M1, the first node N1, and the third transistor M3, and the second electrode (or cathode electrode) of the light emitting element LD may be connected to the second power line PL2. The light emitting element LD may generate light of a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0072] The light emitting element LD may be selected as an organic light emitting diode. In addition, the light emitting element LD may be selected as an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In addition, the light emitting element LD may be an element composed of a combination of an organic material and an inorganic material. Figure 4 , it is shown that the pixel PXij includes a single light emitting element LD. However, in embodiments, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series / parallel.

[0073] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0074] The first transistor M1 to the fourth transistor M4 may be transistors each including a body electrode. For example, each of the first transistor M1 to the fourth transistor M4 may be a metal oxide semiconductor field effect transistor (MOSFET). The first transistor M1 to the fourth transistor M4 may be installed in a narrow area, and therefore, the pixel PXij may be applied to a high-resolution panel. The body electrode of each of the first transistor M1 to the fourth transistor M4 may be supplied with a voltage of a first driving power source VDD. In an example, the body electrode of each of the first transistor M1 to the fourth transistor M4 may be connected to a first power line PL1.

[0075] In an embodiment, each of the first to fourth transistors M1 to M4 may be formed as a P-type transistor. However, this is merely illustrative, and at least one of the first to fourth transistors M1 to M4 may be replaced with an N-type transistor.

[0076] The first electrode of the first transistor M1 may be connected to the first node N1, and the second electrode of the first transistor M1 may be connected to the second node N2. The term "connection" includes the meaning of "connection". The gate electrode of the first transistor M1 may be connected to the third node N3. The first node N1 may represent a node connected to the second electrode of the third transistor M3, and the second node N2 may represent a node connected to the first electrode of the light emitting element LD. The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD.

[0077] The second transistor M2 may be connected between the jth data line DLj and the third node N3. In addition, the gate electrode of the second transistor M2 may be connected to the i-th write scan line SL1i. When the first scan signal GW is supplied to the i-th write scan line SL1i, the second transistor M2 may be turned on to connect the j-th data line DLj and the third node N3 to each other.

[0078] A first electrode of the third transistor M3 may be connected to the first power line PL1, and a second electrode of the third transistor M3 may be connected to the first node N1. In addition, a gate electrode of the third transistor M3 may be connected to the kth emission control line ELk. When the emission control signal EM is supplied to the kth emission control line ELk, the third transistor M3 may be turned off, and when the emission control signal EM is not supplied, the third transistor M3 may be turned on. When the third transistor M3 is turned off, the first power line PL1 and the first node N1 may be disconnected from each other.

[0079] A first electrode of the fourth transistor M4 may be connected to the second node N2, and a second electrode of the fourth transistor M4 may be connected to the third power line PL3. In addition, a gate electrode of the fourth transistor M4 may be connected to the i-th initialization scan line SL2i. When the second scan signal GB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 may be turned on to connect the second node N2 and the third power line PL3 to each other.

[0080] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first capacitor C1 may transmit a voltage change of the first node N1 to the third node N3 while being driven as a coupling capacitor. In addition, the first capacitor C1 may store a voltage of the third node N3.

[0081] The second capacitor C2 may be connected between the second node N2 and the third node N3. The second capacitor C2 may transmit a voltage change of the second node N2 while being driven as a coupling capacitor.

[0082] The third capacitor C3 may be connected between the third node N3 and the second power line PL2 to which the voltage of the second drive power source VSS is supplied. However, embodiments of the present disclosure are not limited thereto. In an example, the third capacitor C3 may be connected to the first power line PL1 to which the voltage of the first drive power source VDD is supplied. In another example, the third capacitor C3 may be connected to an additional power line to which a voltage different from the voltage of any one of the first drive power source VDD and the second drive power source VSS is supplied. When the pixel PXij is driven, the voltage or voltage variation of the third node N3 may vary according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3. This will be referred to later. Figures 6 to 9 Detailed description.

[0083] Figure 5 It is shown Figure 4 0 is a waveform diagram of an embodiment of a driving method of a pixel PXij shown in FIG.

[0084] Reference Figure 2 , Figure 4 and Figure 5 , a horizontal period 1H (or a specific horizontal period) in which data signals are supplied to pixels PXij located in an i-th horizontal line and a j-th vertical line may be divided into a first period T1, a second period T2, and a third period T3.

[0085] The data driver 140 may supply a voltage Vdata of a data signal to the j-th data line DLj during the first period T1 , the second period T2 , and the third period T3 .

[0086] The scan driver 130 (or the first scan driver 132 ) may supply the first scan signal GW to the i-th write scan line SL1 i during the first period T1 and the second period T2 .

[0087] The scan driver 130 (or the second scan driver 134 ) may supply the second scan signal GB to the i-th initialization scan line SL2 i during the first to third periods T1 to T3 .

[0088] The emission driver 160 may supply the emission control signal EM to the kth emission control line ELk during the second period T2.

[0089] The first period T1 is a period in which the voltage of the first driving power source VDD is supplied to the first node N1, the voltage of the initialization power source Vint is supplied to the second node N2, and the voltage Vdata of the data signal is supplied to the third node N3. During the first period T1, the light emitting element LD may be initialized. During the first period T1, the first capacitor C1, the second capacitor C2, and the third capacitor C3 may store the voltage Vdata of the data signal supplied to the third node N3 while being initialized. The first period T1 may be referred to as an initialization period or a data signal writing period.

[0090] The second period T2 is a period in which the voltage of the initialization power source Vint is supplied to the second node N2 and the voltage Vdata of the data signal is supplied to the third node N3. During the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the first capacitor C1. The second period T2 may be referred to as a first threshold voltage compensation period.

[0091] During the third period T3, the first transistor M1 controls the amount of current supplied from the first driving power source VDD to the initialization power source Vint. It is possible to prevent unnecessary current from being supplied to the light emitting element LD after the second period T2. The third period T3 may be referred to as a brightness control period.

[0092] During the fourth period T4, in response to the voltage of the third node N3, the first transistor M1 controls the amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light emitting element LD. During the fourth period T4, the light emitting element LD may emit light of a brightness corresponding to the amount of current supplied from the first transistor M1. The fourth period T4 may be referred to as an emission period or a second threshold voltage compensation period.

[0093] Figures 6 to 9 is a graph showing a pixel PXij (see Figure 4 ) of the embodiment of the operation process Figure 5 The driving waveform shown in the figure corresponds to the figure.

[0094] Reference Figure 6 During the first period T1, the first scan signal GW is supplied to the i-th write scan line SL1i, and the second scan signal GB is supplied to the i-th initialization scan line SL2i. In addition, during the first period T1, the emission control signal EM is not supplied to the k-th emission control line ELk, and therefore, the third transistor M3 is set to be in a turned-on state. When the third transistor M3 is turned on, the voltage of the first driving power source VDD is supplied to the first node N1.

[0095] When the first scan signal GW is supplied to the i-th write scan line SL1i, the second transistor M2 is turned on. When the second transistor M2 is turned on, the voltage Vdata of the data signal from the j-th data line DLj is supplied to the third node N3. The first capacitor C1 can be initialized by the voltage Vdata of the data signal and the voltage of the first drive power source VDD. In the example, during the first period T1, the first capacitor C1 can be charged with a voltage corresponding to the voltage Vdata of the data signal and the voltage of the first drive power source VDD, regardless of the voltage charged in the previous period (or the previous frame period).

[0096] When the second scan signal GB is supplied to the i-th initialization scan line SL2i, the fourth transistor M4 is turned on. When the fourth transistor M4 is turned on, the voltage of the initialization power source Vint is supplied to the second node N2. When the voltage of the initialization power source Vint is supplied to the second node N2, the light emitting element LD can be initialized. In the example, when the voltage of the initialization power source Vint is supplied, the parasitic capacitor (not shown) of the light emitting element LD can be discharged. The voltage of the initialization power source Vint can be set to a voltage at which the light emitting element LD is turned off (or does not emit light), and therefore, the light emitting element LD can be set to be in a non-emitting state.

[0097] The second capacitor C2 may be initialized by the voltage Vdata of the data signal supplied to the third node N3 and the voltage of the initialization power source Vint supplied to the second node N2. In an example, during the first period T1, the second capacitor C2 may be charged with a voltage corresponding to the voltage Vdata of the data signal and the voltage of the initialization power source Vint, regardless of the voltage charged in the previous period (or previous frame period).

[0098] The third capacitor C3 may be initialized by the voltage Vdata of the data signal supplied through the jth data line DLj. For example, the third capacitor C3 may be charged with a voltage corresponding to the voltage Vdata of the data signal and the voltage of the second driving power source VSS regardless of the voltage charged in the previous period (or previous frame period).

[0099] During the first period T1, the current supplied from the first transistor M1 may be supplied to the initialization power source Vint via the fourth transistor M4 in response to the voltage of the third node N3. Therefore, during the first period T1, the light emitting element LD may maintain a non-emission state.

[0100] Reference Figure 7During the second period T2, the turn-on state of the second transistor M2 may be maintained by the first scan signal GW supplied to the i-th write scan line SL1i, and the turn-on state of the fourth transistor M4 may be maintained by the second scan signal GB supplied to the i-th initialization scan line SL2i.

[0101] In addition, during the second period T2, the third transistor M3 may be turned off by the emission control signal EM supplied to the kth emission control line ELk. When the third transistor M3 is turned off, the electrical connection between the first power line PL1 and the first node N1 is blocked.

[0102] Since the second transistor M2 is set to be in a conductive state during the second period T2, the voltage Vdata of the data signal from the j-th data line DLj is supplied to the third node N3. The voltage of the first node N1 can be reduced from the voltage of the first driving power source VDD to a voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage (or the absolute value of the threshold voltage) of the first transistor M1 and the voltage Vdata of the data signal.

[0103] That is, during the second period T2, the third node N3 may be set to the voltage Vdata of the data signal, and the first node N1 may be set to a voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 and the voltage Vdata of the data signal. Therefore, during the second period T2, the threshold voltage of the first transistor M1 may be stored in the first capacitor C1.

[0104] Since the fourth transistor M4 is set to be in the on state during the second period T2, the current from the first node N1 to the second node N2 via the first transistor M1 can be supplied to the initialization power source Vint via the fourth transistor M4. Therefore, during the second period T2, the light emitting element LD can maintain a non-emission state.

[0105] Reference Figure 8 During the third period T3, the supply of the emission control signal EM to the kth emission control line ELk is suspended, and thus the third transistor M3 may be set to be in a turned-on state. In addition, during the third period T3, the supply of the first scan signal GW to the i-th write scan line SL1i is suspended, and thus the second transistor M2 may be set to be in a turned-off state. During the third period T3, the supply of the second scan signal GB to the i-th initialization scan line SL2i is maintained, and thus the turned-on state of the fourth transistor M4 is maintained.

[0106] Since the third transistor M3 is set to be in a conducting state during the third period T3, the first transistor M1 controls the amount of current supplied from the first driving power source VDD to the second node N2 in response to the voltage applied to the third node N3. Since the fourth transistor M4 is set to be in a conducting state, the current supplied to the second node N2 can be supplied to the initialization power source Vint. Therefore, during the third period T3, the light emitting element LD is set to a non-emission state, and thus the accurate grayscale display of the display device 100 can be achieved. For example, the voltage of the second node N2 can be increased to a voltage higher than the desired voltage by the second period T2. Therefore, an unexpected current may be provided to the light emitting element LD. For example, even when a black grayscale is achieved in the pixel PXij, the light emitting element LD may temporarily emit light. In an embodiment of the present disclosure, during the third period T3, the current supplied from the first transistor M1 is supplied to the initialization power source Vint, and therefore, the accidental emission of the light emitting element LD can be prevented. However, when the grayscale can be stably achieved in the display device 100, the third period T3 can be omitted.

[0107] Reference Fig. 9 During the fourth period T4, the supply of the second scan signal GB to the i-th initialization scan line SL2i is suspended, and thus the fourth transistor M4 may be turned off. During the fourth period T4, the first scan signal GW is not supplied to the i-th write scan line SL1i, and thus the second transistor M2 maintains a turned-off state. During the fourth period T4, the emission control signal EM is not supplied to the k-th emission control line ELk, and thus the third transistor M3 maintains a turned-on state.

[0108] The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD. During the fourth period T4, the light emitting element LD may generate light of brightness corresponding to the amount of driving current supplied from the first transistor M1.

[0109] Will refer to Figures 6 to 9 A threshold voltage compensation process according to an embodiment of the present invention is described in detail.

[0110] First, refer to Figure 7, the threshold voltage of the first transistor M1 may be determined by the voltage difference between the body electrode and the source electrode (e.g., the first node N1). For example, when it is assumed that the voltage of the first driving power source VDD is set to 8V, during the second period T2, the body electrode of the first transistor M1 may be set to 8V, and the source electrode of the first transistor M1 may be set to a voltage lower than the voltage of the body electrode. In an example, when it is assumed that the first node N1 is set to 4V, the voltage difference between the body electrode and the source electrode of the first transistor M1 may be set to 4V, for example, VBS=4V. The first transistor M1 may have a first threshold voltage corresponding to 4V as the voltage difference between the body electrode and the source electrode.

[0111] In the second period T2, the first threshold voltage can be compensated. For example, during the second period T2, the third node N3 is set to the voltage Vdata of the data signal, and the first node N1 is set to the voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 and the voltage Vdata of the data signal. The threshold voltage of the first transistor M1 can be stored in the first capacitor C1. In this way, according to an embodiment of the present disclosure, the threshold voltage of the first transistor M1 can be mainly compensated during the second period T2. For example, after the second period T2, when the third transistor M3 is turned on, the threshold voltage reflected on the first node N1 can be reflected on the voltage of the third node N3, and the conduction and / or cutoff of the first transistor M1 can be controlled according to the voltage reflected by the third node N3. Therefore, the first threshold voltage of the first transistor M1 can be compensated.

[0112] At the same time, refer to Fig. 9 , the threshold voltage of the first transistor M1 may be changed in the fourth period T4. For example, during the fourth period T4, the first node N1 may be set to the voltage of the first driving power source VDD. Therefore, the source electrode of the first transistor M1 may have the same voltage as the body electrode of the first transistor M1. For example, the voltage difference between the source electrode and the body electrode of the first transistor M1 may be about 0V. According to the changed voltage difference between the body electrode and the source electrode of the first transistor M1, the first transistor M1 may have a second threshold voltage different from the first threshold voltage.

[0113] During the fourth period T4, when the voltage of the first driving power source VDD is supplied to the first node N1, the voltage of the third node N3 may vary according to the voltage change of the first node N1. The third period T3 may be provided as described above, and the emission control signal EM may be enabled to a low level in the third period T3 before the fourth period T4. In the third period T3, the voltage of the third node N3 may vary according to the voltage change of the first node N1. In an embodiment, the voltage of the third node N3 may be set as shown in Expression 1.

[0114] Expression 1

[0115] VN3a∝Vdata+(VDD-(Vdata+|Vth(M1)|))×C1 / (C1+C2+C3)

[0116] Referring to Expression 1, VN3a may represent the voltage of the third node N3. During the fourth period T4, the voltage of the first node N1 may be changed from the voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal to the voltage of the first driving power source VDD. Therefore, VDD-(Vdata+|Vth(M1)|) may represent the voltage change of the first node N1.

[0117] According to the voltage variation of the first node N1, the voltage of the third node N3 may also be varied by coupling of the first capacitor C1. The varied voltage of the third node N3 may be defined as the sum of the voltage Vdata of the data signal and the voltage variation of the third node N3.

[0118] The voltage change of the third node N3 can be determined by the ratio of the first capacitor C1, the second capacitor C2 and the third capacitor C3. For example, as shown in Expression 1, the voltage change of the third node N3 caused by the voltage change of the first node N1 can be a value obtained by multiplying the voltage change of the first node N1 by C1 / (C1+C2+C3). In this way, when the voltage change of the third node N3 is controlled by the ratio of the first capacitor C1, the second capacitor C2 and the third capacitor C3, the voltage Vdata range of the data signal can be set to be wide enough. For example, the voltage Vdata range of the data signal can be determined according to the components included in the pixel PXij. In an embodiment of the present disclosure, since the voltage of the third node N3 changes according to the ratio of the first capacitor C1, the second capacitor C2 and the third capacitor C3, the voltage Vdata range of the data signal can be set to be wide. For example, the voltage change of the third node N3 can become relatively low according to the ratio of the first capacitor C1, the second capacitor C2 and the third capacitor C3, and therefore, the voltage of the third node N3 can also become relatively low. Therefore, although the voltage Vdata range of the data signal is set relatively wide, the voltage applied to the third node N3 can belong to the required voltage range. For example, the data driver 140 can use a relatively wide voltage range of about 3.29V to implement 255 gray levels. Therefore, a fine gray scale representation of the pixel PXij according to an embodiment of the present disclosure can be achieved.

[0119] The third capacitor C3 is adjusted to reflect the ratio of the voltage change of the first node N1 to the voltage change of the third node N3. For example, when the voltage stored in the third capacitor C3 increases, the voltage change of the third node N3 can be reduced relative to the voltage change of the first node N1. The voltage Vdata range of the data signal can be selected to be more suitable for the display device 100.

[0120] Meanwhile, after the voltage of the third node N3 is set as shown in Expression 1, the amount of current supplied to the second node N2 through the first transistor M1 may vary in response to the voltage of the third node N3. Therefore, the voltage of the drain electrode (eg, the second node N2) of the first transistor M1 may be changed.

[0121] The second node N2 and the third node N3 are connected to each other through the second capacitor C2. The voltage of the third node N3 may be further changed according to the voltage change of the second node N2. For example, the voltage of the third node N3 may be changed by coupling the second capacitor C2.

[0122] Expression 2

[0123] VN3b∝VN3a+ΔVN2×C2 / (C1+C2+C3)

[0124] Referring to Expression 2, ΔVN2 may represent a voltage change of the second node N2, and VN3b may represent a voltage of the third node N3 corresponding to the voltage change (ΔVN2) of the second node N2. As shown in Expression 2, the voltage of the third node N3 may be determined by a value obtained by multiplying the voltage change (ΔVN2) of the second node N2 by C2 / (C1+C2+C3) and VN3a of Expression 1.

[0125] According to an embodiment of the present disclosure, the voltage variation (ΔVN2) of the second node N2 is reflected on the voltage of the third node N3 through the second capacitor C2, so that the threshold voltage of the first transistor M1 can be secondarily compensated.

[0126] The voltage change (ΔVN2) of the second node N2 may be set corresponding to the threshold voltage change of the first transistor M1. For example, the voltage change (ΔVN2) of the second node N2 may be determined differently corresponding to the change from the first threshold voltage of the first transistor M1 to the second threshold voltage of the first transistor M1. For example, the voltage change (ΔVN2) of the second node N2 may reflect the second threshold voltage of the first transistor M1. When the voltage of the third node N3 further changes according to the voltage change (ΔVN2) of the second node N2, the first transistor M1 may be turned on and / or off, and therefore, the second threshold voltage of the first transistor M1 may be compensated.

[0127] When the threshold voltage compensation of the first transistor M1 is not performed, the current error rate (%) may become larger. The current error rate uses a percentage (%) to represent the change in the driving current corresponding to the threshold voltage change of the first transistor M1. According to an embodiment of the present disclosure, when the threshold voltage of the first transistor M1 included in the pixel PXij changes to 20mV, the current error rate can be set to about 3.4% or less. When the threshold voltage of the first transistor M1 changes to -20mV, the current error rate can be set to about -3.5% or less. For example, in this embodiment, corresponding to the threshold voltage change of the first transistor M1, the current error rate can be set between about 3.4% and about -3.5%, and therefore, it can be seen that the threshold voltage of the first transistor M1 is stably compensated.

[0128] According to an embodiment of the present disclosure, Figure 2 The first transistor M1 in each of the pixels PX shown in FIG. 1 independently performs threshold voltage compensation. For example, Figure 2Each of the pixels PX included in the pixel unit 110 shown in FIG. 1 may include a first transistor M1. The first transistor M1 of each of the pixels PX may provide different threshold voltages during the driving process of the display device 100. The voltage change of the first node N1 of the pixel PX and the voltage change of the second node N2 may also be set differently corresponding to the threshold voltage of the respective first transistor M1. The voltage change of the first node N1 and the voltage change of the second node N2 are reflected on the third node N3 of the pixel PX, so that the threshold voltage of the first transistor M1 included in each of the pixels PX can be compensated. Therefore, the display device 100 can have an improved grayscale performance.

[0129] Fig.10 It is shown Figure 2 An embodiment of a pixel PX is shown in FIG.

[0130] Reference Fig.10 , according to an embodiment of the present disclosure, the pixel PXija can be connected to the corresponding i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk and the j-th data line DLj. For example, the pixel PXija can be connected to the i-th write scan line SL1i, the i-th initialization scan line SL2i, the k-th emission control line ELk and the j-th data line DLj. In an embodiment, the pixel PXija can also be connected to the first power line PL1, the second power line PL2 and the third power line PL3.

[0131] The pixel PXija according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0132] In addition, the pixel circuit according to the embodiment of the present disclosure may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, and a third capacitor C3a.

[0133] In the following, in addition to the third capacitor C3a, Figure 4 The pixel PXij shown in FIG. Fig.10 The pixel PXija shown in FIG. 1 is a pixel PXija, and repeated description will be simplified or omitted.

[0134] In addition, corresponding to Figure 5 The driving waveform of the pixel PXij shown in Fig.10 The pixels shown in PXija can be used with Figures 6 to 9 The operation process of the pixel PXij shown in FIG. 1 is driven identically, and repeated description will be simplified or omitted.

[0135] The third capacitor C3a may be connected between the third node N3 and the first power line PL1 to which the voltage of the first driving power source VDD is supplied. However, the embodiments of the present disclosure are not limited thereto. In an example, the third capacitor C3a may be connected to the second power line PL2 to which the voltage of the second driving power source VSS is supplied. In another example, the third capacitor C3a may be connected to an additional power line to which a voltage different from the voltage according to any one of the first driving power source VDD and the second driving power source VSS is supplied. When the pixel PXija is driven, as shown in FIG. Figure 4 As described above, the voltage variation of the third node N3 may reflect the first threshold voltage and the second threshold voltage of the first transistor M1. The voltage variation of the third node N3 may vary according to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3a.

[0136] Reference Figure 6 , in the first period T1, the voltage of the first driving power source VDD may be supplied to the first node N1, the voltage of the initialization power source Vint may be supplied to the second node N2, and the voltage Vdata of the data signal may be supplied to the third node N3. During the first period T1, when the first capacitor C1, the second capacitor C2, and the third capacitor C3a are initialized, the first capacitor C1, the second capacitor C2, and the third capacitor C3a may store the voltage Vdata of the data signal supplied to the third node N3. For example, the third capacitor C3a may be initialized by the voltage Vdata of the data signal supplied through the j-th data line DLj. Therefore, during the first period T1, the third capacitor C3a may be charged with a voltage corresponding to the voltage Vdata of the data signal, regardless of the voltage charged in the previous period (or the previous frame period).

[0137] In addition, refer to Figure 7 , in the second period T2, the first threshold voltage of the first transistor M1 of the pixel PXija can be compensated. For example, during the second period T2, the third node N3 is set to the voltage Vdata of the data signal, and the first node N1 is set to the voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal. The threshold voltage of the first transistor M1 can be stored in the first capacitor C1. Therefore, the voltage between the gate electrode and the source electrode of the first transistor M1 can be equally maintained. In this way, according to an embodiment of the present disclosure, the threshold voltage of the first transistor M1 can be mainly compensated during the second period T2.

[0138] Reference Fig. 9During the fourth period T4, the voltage of the first node N1 of the pixel PXija can be changed from the voltage (Vdata+|Vth(M1)|) obtained by adding the absolute threshold voltage of the first transistor M1 to the voltage Vdata of the data signal to the voltage of the first driving power source VDD. Therefore, the voltage of the third node N3 can also be changed by the coupling of the first capacitor C1.

[0139] The voltage change of the third node N3 of the pixel PXija may be determined corresponding to the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3a. For example, the voltage of the third node N3 may change by a value obtained by multiplying the voltage change of the first node N1 by C1 / (C1+C2+C3a) of the voltage Vdata from the data signal.

[0140] In this way, when the voltage change of the third node N3 is controlled by the ratio of the first capacitor C1, the second capacitor C2 and the third capacitor C3a, the voltage Vdata range of the data signal can be set to be wide enough. For example, the voltage Vdata range of the data signal can be determined according to the layout of the pixel PXija. According to an embodiment of the present disclosure, when the voltage of the third node N3 changes corresponding to the ratio of the first capacitor C1, the second capacitor C2 and the third capacitor C3a, the voltage Vdata range of the data signal can be set to be wide. In addition, according to an embodiment of the present disclosure, Figure 2 The data driver 140 shown in FIG. 1 can implement 32 to 255 gray levels using a voltage range of about 3.5 V. Therefore, a fine gray level representation of the pixel PXija according to an embodiment of the present disclosure can be achieved.

[0141] Then, the voltage of the third node N3 may be changed according to the voltage change of the second node N2. For example, the voltage of the third node N3 may be changed by coupling the second capacitor C2. During the fourth period T4, the voltage of the third node N3 may be changed by multiplying the voltage change (ΔVN2) of the second node N2 by C2 / (C1+C2+C3a).

[0142] According to an embodiment of the present disclosure, the voltage change (ΔVN2) of the second node N2 is reflected on the voltage of the third node N3, so that the threshold voltage of the first transistor M1 included in the pixel circuit of the pixel PXija can be compensated. For example, in the fourth period T4, the voltage change (ΔVN2) of the second node N2 can be determined differently corresponding to the change from the first threshold voltage to the second threshold voltage of the first transistor M1. Therefore, the threshold voltage of the first transistor M1 included in the pixel circuit of the pixel PXija can be stably compensated.

[0143] In a pixel according to the present disclosure and a display device including the pixel, a transistor suitable for high resolution (e.g., MOSFET) can be used to implement the pixel. According to the present disclosure, the pixel includes a driving transistor having a body electrode, and therefore, the threshold voltage of the driving transistor can be stably compensated. In addition, according to the present disclosure, the pixel can widely set the voltage range of the data signal.

[0144] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art at the time of filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A pixel, wherein The pixels include: a first transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, the second transistor comprising a gate electrode connected to the first scan line; a third transistor connected between the first power line to which the voltage of the first driving power source is supplied and the first node, the third transistor including a gate electrode connected to an emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and a second power line to which a voltage of a second driving power source is supplied; and The light emitting element is connected between the second node and the second power line.

2. The pixel according to claim 1, wherein: The pixel also includes a fourth transistor including a first electrode connected to the second node, a second electrode connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode connected to a second scan line.

3. The pixel according to claim 2, wherein: When the voltage of the initialization power source is supplied to the second node, the light emitting element is turned off.

4. The pixel according to claim 2, wherein: Each of the first to fourth transistors is a metal oxide semiconductor field effect transistor including a body electrode.

5. The pixel according to claim 4, wherein: The voltage of the first driving power source is supplied to the body electrode of each of the first to fourth transistors.

6. The pixel according to claim 2, wherein: A horizontal period includes the first period, the second period and the third period. wherein, during the first period, the second transistor, the third transistor and the fourth transistor are set to be in a conducting state, wherein during the second period, the second transistor and the fourth transistor are set to be in the on state, and the third transistor is set to be in the off state, and During the third period, the third transistor and the fourth transistor are set to be in the on state, and the second transistor is set to be in the off state.

7. The pixel according to claim 6, wherein: During the first period to the third period, a voltage of a data signal is supplied to the data line.

8. A pixel, wherein The pixels include: a first transistor including a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode connected to a third node; a second transistor connected between the data line and the third node, the second transistor comprising a gate electrode connected to the first scan line; a third transistor connected between the first power line to which the voltage of the first driving power source is supplied and the first node, the third transistor including a gate electrode connected to an emission control line; a first capacitor connected between the first node and the third node; a second capacitor connected between the second node and the third node; a third capacitor connected between the third node and the first power line; and The light emitting element is connected between the second node and a second power line to which a voltage of a second driving power source is supplied.

9. The pixel according to claim 8, wherein: The third capacitor is supplied with the voltage of the first driving power source through the first power line.

10. The pixel according to claim 8, wherein: The pixel also includes a fourth transistor including a first electrode connected to the second node, a second electrode connected to a third power line to which a voltage of an initialization power source is supplied, and a gate electrode connected to a second scan line.

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