Display panel and electronic equipment

Abstract

The invention relates to a display panel and electronic equipment. The display panel comprises a display substrate, a driving chip and a circuit board. A wiring area of the display substrate is provided with a plurality of pins, and the plurality of pins comprise a first pin. The driving chip is installed in the wiring area of the display substrate and is provided with a plurality of interfaces, and the plurality of interfaces comprise enabling interfaces. The enabling interface is configured to control the use of a communication protocol and is electrically connected with the first pin. The circuit board is provided with a plurality of golden fingers, the plurality of golden fingers comprise first golden fingers, the plurality of golden fingers of the circuit board are connected with the plurality of pins, and the first golden fingers are connected with the first pins. A first potential signal can be applied to the enabling interface through the circuit board, and a second potential signal can also be applied to the enabling interface; when a first potential signal is applied to the enabling interface, the communication protocol is not used; and when a second potential signal is applied to the enabling interface, the communication protocol is used.

Description

Technical Field

[0001] The present application relates to a display panel and an electronic device. Background Art

[0002] Wearable devices usually include a display panel. The display panel includes a display substrate and a driver chip and a flexible circuit board bound to the display substrate. The driver chip, the flexible circuit board, and the display substrate usually use the MIPI protocol to transmit signals. The MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.

[0003] However, when in AOD (always-on display) mode, there is no need to transmit high-speed signals and the amount of data is very small. At this time, still using the MIPI protocol will not be conducive to reducing the burden on the system and reducing power consumption. Summary of the invention

[0004] According to a first aspect of an embodiment of the present application, a display panel is provided, the display panel comprising:

[0005] A display substrate having a display area and a wiring area, wherein the display area includes a plurality of pixel units, and the wiring area is provided with a plurality of pins, wherein the plurality of pins includes a first pin;

[0006] a driving chip mounted on the wiring area of ​​the display substrate, having a plurality of interfaces, wherein the plurality of interfaces include an enabling interface, the enabling interface being configured to control the use of a communication protocol, the enabling interface being electrically connected to the first pin;

[0007] A circuit board having a plurality of gold fingers, wherein the plurality of gold fingers include a first gold finger, the plurality of gold fingers of the circuit board are connected to the plurality of pins, and the first gold finger is connected to the first pin;

[0008] Among them, the enabling interface can be applied with a first potential signal or a second potential signal through the circuit board; when the enabling interface is applied with the first potential signal, the communication protocol is not used; when the enabling interface is applied with the second potential signal, the communication protocol is used.

[0009] In some embodiments, the communication protocol comprises a QSPI protocol.

[0010] In some embodiments, when the QSPI protocol is not used, the MIPI communication protocol is used.

[0011] In some embodiments, the plurality of gold fingers of the circuit board are connected to the plurality of pins by binding, and the first gold finger is connected to the first pin by binding.

[0012] In some embodiments, the first potential signal is a high potential, and the second potential signal is a low potential.

[0013] In some embodiments, the plurality of interfaces further include a second interface and a third interface, wherein one of the second interface and the third interface is used to provide a first potential signal, and the other is used to provide a second potential signal;

[0014] The plurality of pins further include a second pin and a third pin, the second interface is electrically connected to the second pin, and the third interface is electrically connected to the third pin;

[0015] The plurality of golden fingers further include a second golden finger and a third golden finger, wherein the second golden finger is connected to the second pin, and the third golden finger is connected to the third pin;

[0016] The circuit board also has a plurality of pads, the plurality of pads include a first pad, a second pad and a third pad, the first pad is electrically connected to the first gold finger, the second pad is electrically connected to the second gold finger, and the third pad is electrically connected to the third gold finger;

[0017] The first pad is alternatively connected to the second pad or the third pad.

[0018] In some embodiments, the second golden finger is connected to the second pin by binding, and the third golden finger is connected to the third pin by binding.

[0019] In some embodiments, the first pad is electrically connected to the first gold finger through a trace in the circuit board, the second pad is electrically connected to the second gold finger through a trace in the circuit board, and the third pad is electrically connected to the third gold finger through a trace in the circuit board.

[0020] In some embodiments, the second pad and the third pad are both adjacent to the first pad, and the second pad and the third pad are disposed on different sides of the first pad.

[0021] In some embodiments, the first pad and the second pad are connected via a conductive body disposed on the surface of the circuit board;

[0022] Alternatively, the first pad is connected to the third pad via a conductive body disposed on the surface of the circuit board.

[0023] In some embodiments, the circuit board further has a fifth pad and a board-to-board interface, the fifth pad has a first potential, and is used to provide a first potential signal to the first gold finger, and a resistor element is connected between the fifth pad and the first gold finger;

[0024] The board-to-board interface is electrically connected to the first gold finger, and the board-to-board interface can switch between a first state and a second state. In the first state, the board-to-board interface is in a high-impedance state or a floating state; in the second state, the board-to-board interface has a second potential and provides a second potential signal to the enable interface.

[0025] In some embodiments, the fifth pad is connected to ground.

[0026] In some embodiments, the plurality of interfaces further comprises a second interface, the second interface being used to selectively provide a first potential signal or a second potential signal;

[0027] The plurality of pins further include a second pin, and the second interface is electrically connected to the second pin; the plurality of gold fingers further include a second gold finger, and the second gold finger is connected to the second pin, and the second gold finger is electrically connected to the first gold finger.

[0028] In some embodiments, the second interface is a GPIO interface; the second interface switches to output the first potential signal or the second potential signal in a programmed manner.

[0029] According to a second aspect of an embodiment of the present application, an electronic device is provided, and the electronic device includes the display panel as described above.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] Figure 1 is a schematic diagram of a structure of a display panel applied to a wearable device;

[0033] Figure 2 yes Figure 1 A schematic diagram of circuit connections of some structures in the display panel is shown;

[0034] Figure 3 is a schematic structural diagram of a display panel according to an embodiment of the present application;

[0035] Figure 4 yes Figure 3 A schematic diagram showing a usage state of the display panel is shown;

[0036] Figure 5 yes Figure 3A schematic diagram showing another usage state of the display panel is shown;

[0037] Figure 6 is a structural schematic diagram of a display panel according to another embodiment of the present application;

[0038] Figure 7 yes Figure 6 A schematic diagram showing a usage state of the display panel is shown;

[0039] Figure 8 yes Figure 6 A schematic diagram showing another usage state of the display panel is shown;

[0040] Fig. 9 is a structural schematic diagram of a display panel according to another embodiment of the present application;

[0041] Fig.10 is a schematic structural diagram of a display panel according to another embodiment of the present application;

[0042] Figures 11 to 18 It is a schematic diagram of a method for manufacturing a circuit board according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0044] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0045] Figure 1 It is a structural schematic diagram of a display panel applied to a wearable device. The display panel may be a flexible OLED display panel. In order to reduce the size and boundary of the entire display panel, COP (Chip On Panel) technology is usually used to directly bond the driver chip 40 (Driver IC) to the display substrate 20, and multiple interfaces J on the driver chip 40 are connected to multiple pins P on the display substrate 20. When assembling the circuit board 60, multiple gold fingers G on the circuit board 60 are directly bonded to multiple pins P on the display substrate 20.

[0046] Please also refer to Figure 1 and Figure 2, some power interfaces J1 on the driver chip 40 need to lead out signals to connect capacitors C externally on the circuit board 60, one end (or one plate) B1 of capacitor C is connected to the power interface J1 of the driver chip 40, and the other end (or another plate) B2 is grounded. The external capacitor C plays a filtering role. When the power signal output by the driver chip 40 is mixed with a clutter signal, capacitor C will lead out the clutter signal and import it into the earth, thereby filtering out the clutter. Of course, in some cases, components such as TVS (Transient Voltage Suppressors), diodes, Flash memories, ALS (Ambient Light Sensor), ZIF connectors, and magnetic beads will also be included. Corresponding pads can be reserved on the circuit board 60, and these components can be mounted on the surface of the circuit board 60 through SMT technology (Surface Mount Technology).

[0047] Wearable devices often use the MIPI (Mobile Industry Processor Interface) protocol to transmit signals, which can transmit high-speed signals, with large data volume, low power consumption and good anti-interference performance. However, when in AOD (Always on display) mode, there is no need to transmit high-speed signals and the data volume is also very small. At this time, a better choice is to introduce the QSPI (Queue Serial peripheral interface) communication protocol and use the QSPI protocol to transmit data in AOD mode. However, the technology of using the QSPI protocol in AOD mode is not yet mature, so the present application provides two solutions that are compatible with the use of the QSPI protocol and do not use the QSPI protocol.

[0048] Figure 3 1 is a schematic structural diagram of a display panel 100 according to an embodiment of the present application. Figure 4 yes Figure 3 The schematic diagram of the display panel 100 in a usage state is shown. Figure 5 yes Figure 3 FIG. 1 is a schematic diagram showing another usage state of the display panel 100 .

[0049] Please refer to Figure 3 The display panel 100 may include a display substrate 20, a driving chip 40 and a circuit board 60. The display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area), and the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.

[0050] The driver chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN). The enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.

[0051] The circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.

[0052] The enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60. When the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.

[0053] In the above embodiment, the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.

[0054] There are various positional relationships between the display area 23 and the wiring area 25. In some embodiments, the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.

[0055] There are many ways to arrange the plurality of pins P. In some embodiments, the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).

[0056] There are many ways to install the driver chip 40. In some embodiments, the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.

[0057] The enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25. In some embodiments, the wire 28 is disposed inside the wiring area 25 of the display substrate 20. In some embodiments, the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.

[0058] The communication protocol can be any communication protocol. In some embodiments, the communication protocol is the QSPI protocol. The QSPI protocol is a (Queue Serial peripheral interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is applicable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used. The other protocols include the MIPI (Mobile Industry Processor Interface) protocol. The MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.

[0059] In some embodiments, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.

[0060] There are many ways to arrange the plurality of gold fingers G. In some embodiments, the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.

[0061] In some embodiments, the circuit board 60 is a flexible printed circuit (FPC).

[0062] In some embodiments, the first potential signal is a high potential, and the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.

[0063] Further, the plurality of interfaces J further include a second interface J3 and a third interface J6, the second interface J3 is used to provide a first potential signal, and the third interface J6 is used to provide a second potential signal; the plurality of pins P further include a second pin P5 and a third pin P8. The second interface J3 is electrically connected to the second pin P5, and the third interface J6 is electrically connected to the third pin P8.

[0064] The plurality of gold fingers G further include a second gold finger G5 and a third gold finger G8, the second gold finger G5 is connected to the second pin P5, and the third gold finger G8 is connected to the third pin P8.

[0065] The circuit board 60 also has a plurality of pads, including a first pad S1, a second pad S2 and a third pad S3, the first pad S1 is electrically connected to the first gold finger G3, the second pad S2 is electrically connected to the second gold finger G5, and the third pad S3 is electrically connected to the third gold finger G8.

[0066] The above connection makes: the first pad S1 electrically connected to the enabling interface J1; the second pad S2 electrically connected to the second interface J3 and having a first potential; the third pad S3 electrically connected to the third interface J6 and having a second potential.

[0067] When the specific communication protocol is not needed, the first pad S1 and the second pad S2 may be connected. Figure 4 As shown, the enabling interface J1 is connected to the first potential signal; at this time, the third interface J6 with the second potential and the third pad S3 are in a floating state.

[0068] When the specific communication protocol needs to be used, the first pad S1 and the third pad S3 may be connected, such as Figure 5 As shown, the enabling interface J1 is connected to the second potential signal; at this time, the second interface J3 with the first potential and the second pad S2 are in a floating state.

[0069] Please refer to Figures 3 to 5, the second interface J3 can be electrically connected to the second pin P5 through a wiring 28 in the wiring area 25; the third interface J6 can be electrically connected to the third pin P8 through a wiring 28 in the wiring area 25. In some embodiments, the wiring 28 for connecting the second interface J3 and the second pin P5 and / or the wiring 28 for connecting the third interface J6 and the third pin P8 are arranged inside the wiring area 25 of the display substrate 20. In some embodiments, the wiring 28 for connecting the second interface J3 and the second pin P5 and / or the wiring 28 for connecting the third interface J6 and the third pin P8 are arranged on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, two scattered wires are provided, so that: one end of the first wire is welded to the second interface J3, and the other end of the first wire is welded to the second pin P5; one end of the second wire is welded to the third interface J6, and the other end of the second wire is welded to the third pin P8.

[0070] In some embodiments, the second gold finger G5 is connected to the second pin P5 by binding, and the third gold finger G8 is connected to the third pin P8 by binding.

[0071] The first pad S1 can be electrically connected to the first gold finger G3 through a trace 68 in the circuit board 60. In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the first pad S1, and the other end of the wire is welded to the first gold finger G3. The wire serves as the trace 68.

[0072] Similarly, the second pad S2 can be electrically connected to the second gold finger G5 through a trace 68 in the circuit board 60. In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the second pad S2, and the other end of the wire is welded to the second gold finger G5. The wire serves as the trace 68.

[0073] The third pad S3 can be electrically connected to the third gold finger G8 through a trace 68 in the circuit board 60. In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the third pad S3, and the other end of the wire is welded to the third gold finger G8. The wire serves as the trace 68.

[0074] For convenient connection, the second pad S2 and the third pad S3 may be arranged adjacent to the first pad S1. For example, the second pad S2 and the third pad S3 may be arranged on different sides of the first pad S1. In some embodiments, the second pad S2 is arranged on the right side of the first pad S1, and the third pad S3 is arranged on the lower side of the first pad S1.

[0075] The plurality of pads provided on the circuit board 60 may further include a fourth pad S4. In some embodiments, the fourth pad S4 may be a pad for grounding, used to provide a grounding path for the circuit board 60 or a component mounted on the circuit board 60. For example, when a capacitor component is mounted on the circuit board 60, one plate of the capacitor may be directly soldered to the fourth pad S4.

[0076] The first pad S1 and the second pad S2 can be connected by a conductive body 72 disposed on the surface of the circuit board 60. The first pad S1 and the third pad S3 can be connected by a conductive body 74 disposed on the surface of the circuit board 60. The conductive body 72 and the conductive body 74 are both good conductors, and their resistance values ​​are small, which can be regarded as almost zero resistance. The material of the conductive body 72 and the conductive body 74 can be copper, aluminum or silver. The structure and manufacturing method of the conductive body 72 and the conductive body 74 can be referred to in the following Fig.18 The conductive body 51 in the embodiment.

[0077] Figure 6 2 is a schematic structural diagram of a display panel 200 according to an embodiment of the present application. Figure 7 yes Figure 6 The schematic diagram of the display panel 200 in a usage state is shown. Figure 8 yes Figure 6 FIG. 2 is a schematic diagram showing another usage state of the display panel 200 .

[0078] Please refer to Figure 6The display panel 200 may include a display substrate 20, a driving chip 40 and a circuit board 60. The display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area), and the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.

[0079] The driver chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN). The enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.

[0080] The circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.

[0081] The enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60. When the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.

[0082] In the above embodiment, the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.

[0083] There are various positional relationships between the display area 23 and the wiring area 25. In some embodiments, the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.

[0084] There are many ways to arrange the plurality of pins P. In some embodiments, the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).

[0085] There are many ways to install the driver chip 40. In some embodiments, the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.

[0086] The enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25. In some embodiments, the wire 28 is disposed inside the wiring area 25 of the display substrate 20. In some embodiments, the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.

[0087] The communication protocol can be any communication protocol. In some embodiments, the communication protocol is the QSPI protocol. The QSPI protocol is a (Queue Serial peripheral interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is applicable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used. The other protocols include the MIPI (Mobile Industry Processor Interface) protocol. The MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.

[0088] In some embodiments, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.

[0089] There are many ways to arrange the plurality of gold fingers G. In some embodiments, the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.

[0090] In some embodiments, the circuit board 60 is a flexible printed circuit (FPC).

[0091] In some embodiments, the first potential signal is a high potential, and the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.

[0092] Further, the plurality of interfaces J further include a second interface J3 and a third interface J6, the second interface J3 is used to provide a second potential signal, and the third interface J6 is used to provide a first potential signal; the plurality of pins P further include a second pin P5 and a third pin P8. The second interface J3 is electrically connected to the second pin P5, and the third interface J6 is electrically connected to the third pin P8.

[0093] The plurality of gold fingers G further include a second gold finger G5 and a third gold finger G8, the second gold finger G5 is connected to the second pin P5, and the third gold finger G8 is connected to the third pin P8.

[0094] The circuit board 60 also has a plurality of pads, including a first pad S1, a second pad S2 and a third pad S3, the first pad S1 is electrically connected to the first gold finger G3, the second pad S2 is electrically connected to the second gold finger G5, and the third pad S3 is electrically connected to the third gold finger G8.

[0095] The above connection makes: the first pad S1 electrically connected to the enabling interface J1; the second pad S2 electrically connected to the second interface J3 and having the second potential; the third pad S3 electrically connected to the third interface J6 and having the first potential.

[0096] When the specific communication protocol is not needed, the first pad S1 and the third pad S3 may be connected. Figure 7 As shown, the enabling interface J1 is connected to the first potential signal; at this time, the second interface J3 with the second potential and the second pad S2 are in a floating state.

[0097] When the specific communication protocol needs to be used, the first pad S1 and the second pad S2 may be connected, such as Figure 8 As shown, the enabling interface J1 is connected to the second potential signal; at this time, the third interface J6 with the first potential and the third pad S3 are in a floating state.

[0098] Please refer to Figures 6 to 8 , the second interface J3 can be electrically connected to the second pin P5 through a wiring 28 in the wiring area 25; the third interface J6 can be electrically connected to the third pin P8 through a wiring 28 in the wiring area 25. In some embodiments, the wiring 28 for connecting the second interface J3 and the second pin P5 and / or the wiring 28 for connecting the third interface J6 and the third pin P8 are arranged inside the wiring area 25 of the display substrate 20. In some embodiments, the wiring 28 for connecting the second interface J3 and the second pin P5 and / or the wiring 28 for connecting the third interface J6 and the third pin P8 are arranged on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, two scattered wires are provided, so that: one end of the first wire is welded to the second interface J3, and the other end of the first wire is welded to the second pin P5; one end of the second wire is welded to the third interface J6, and the other end of the second wire is welded to the third pin P8.

[0099] In some embodiments, the second gold finger G5 is connected to the second pin P5 by binding, and the third gold finger G8 is connected to the third pin P8 by binding.

[0100] The first pad S1 can be electrically connected to the first gold finger G3 through a trace 68 in the circuit board 60. In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the first pad S1, and the other end of the wire is welded to the first gold finger G3. The wire serves as the trace 68.

[0101] Similarly, the second pad S2 can be electrically connected to the second gold finger G5 through a trace 68 in the circuit board 60. In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the second pad S2, and the other end of the wire is welded to the second gold finger G5. The wire serves as the trace 68.

[0102] The third pad S3 can be electrically connected to the third gold finger G8 through a trace 68 in the circuit board 60. In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the third pad S3, and the other end of the wire is welded to the third gold finger G8. The wire serves as the trace 68.

[0103] For convenient connection, the second pad S2 and the third pad S3 may be arranged adjacent to the first pad S1. For example, the second pad S2 and the third pad S3 may be arranged on different sides of the first pad S1. In some embodiments, the second pad S2 is arranged on the right side of the first pad S1, and the third pad S3 is arranged on the lower side of the first pad S1.

[0104] With the front Figures 3 to 5 What is different from the illustrated embodiment is that the plurality of pads disposed on the circuit board 60 does not include a fourth pad for grounding.

[0105] The first pad S1 and the second pad S2 can be connected by a conductive body 85 disposed on the surface of the circuit board 60. The first pad S1 and the third pad S3 can be connected by a conductive body 83 disposed on the surface of the circuit board 60. The conductive body 85 and the conductive body 83 are both good conductors, and their resistance values ​​are small, which can be regarded as almost zero resistance. The material of the conductive body 85 and the conductive body 83 can be copper, aluminum or silver. The structure and manufacturing method of the conductive body 85 and the conductive body 83 can be referred to in the following Fig.18 The conductive body 51 in the embodiment.

[0106] Fig. 9 3 is a schematic structural diagram of a display panel 300 according to an embodiment of the present application.

[0107] Please refer to Fig. 9 The display panel 300 may include a display substrate 20, a driving chip 40 and a circuit board 60. The display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area), and the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.

[0108] The driver chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN). The enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.

[0109] The circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.

[0110] The enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60. When the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.

[0111] In the above embodiment, the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.

[0112] There are various positional relationships between the display area 23 and the wiring area 25. In some embodiments, the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.

[0113] There are many ways to arrange the plurality of pins P. In some embodiments, the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).

[0114] There are many ways to install the driver chip 40. In some embodiments, the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.

[0115] The enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25. In some embodiments, the wire 28 is disposed inside the wiring area 25 of the display substrate 20. In some embodiments, the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.

[0116] The communication protocol can be any communication protocol. In some embodiments, the communication protocol is the QSPI protocol. The QSPI protocol is a (Queue Serial peripheral interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is applicable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used. The other protocols include the MIPI (Mobile Industry Processor Interface) protocol. The MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.

[0117] In some embodiments, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.

[0118] There are many ways to arrange the plurality of gold fingers G. In some embodiments, the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.

[0119] In some embodiments, the circuit board 60 is a flexible printed circuit (FPC).

[0120] In some embodiments, the first potential signal is a high potential, and the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.

[0121] Further, the circuit board 60 also has a fifth pad SG and a board-to-board interface BP (i.e., B2B PIN). The fifth pad SG has a first potential (i.e., a high potential) for providing a first potential signal to the first gold finger G3. In some embodiments, the fifth pad SG is a ground pad connected to the ground. A resistor element R is also connected between the fifth pad SG and the first gold finger G3.

[0122] When the circuit board 60 is connected to other circuit boards, the board-to-board interface BP will be electrically connected to or in direct contact with the corresponding interface on the other circuit boards. The other circuit boards can be connected to the controller of the electronic device to which the display panel 300 belongs, and provide signals to the board-to-board interface BP. The board-to-board interface BP has two states, wherein the first state is to maintain a high impedance state (Hi-Z) or a floating state, and the second state is to be provided with a second potential signal and have a second potential (i.e., a low potential). The board-to-board interface BP is electrically connected to the first gold finger G3. In some embodiments, in addition to a board-to-board interface BP, another board-to-board interface is also included, and the other board-to-board interface is also used to be electrically connected to or in direct contact with the corresponding interface on the other circuit boards.

[0123] No resistor element may be inserted between the board-to-board interface BP and the first gold finger G3. The board-to-board interface BP and the fifth pad SG may share a trace. In one embodiment, the first end of the resistor element R is connected to the fifth pad SG, and the second end of the resistor element R is connected to the first gold finger G3 via a trace 68; the board-to-board interface BP is connected to the second end of the resistor element R or the trace 68 via a trace 69. The trace 68 or a portion thereof is shared by the board-to-board interface BP and the fifth pad SG.

[0124] The resistance element R has a relatively large resistance value. The resistance value of the resistance element R may be significantly greater than the resistance values ​​of the trace 68 and the trace 69. In some embodiments, the resistance value of the resistance element R is 0.1 megaohms (MΩ) to 1 megaohm, for example, 0.1 megaohms, 0.2 megaohms, 0.3 megaohms, 0.5 megaohms, 0.7 megaohms, 0.9 megaohms or 1 megaohm.

[0125] When the specific communication protocol is not needed, the board-to-board interface BP can be kept in a high impedance state (Hi-Z) or a floating state, and at this time, the enable interface J1 is provided with a first potential signal by the fifth pad SG.

[0126] When the specific communication protocol needs to be used, the board-to-board interface BP can be kept at the second potential (low potential), at which time the fifth pad SG is equivalent to being short-circuited, and the enabling interface J1 is provided with a second potential signal by the board-to-board interface BP.

[0127] In some embodiments, the trace 68 is disposed inside the circuit board 60. In some embodiments, the trace 68 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the second end of the resistor R, and the other end of the wire is welded to the first gold finger G3. The wire is used as the trace 68.

[0128] In some embodiments, the trace 69 is disposed inside the circuit board 60. In some embodiments, the trace 69 is disposed on the surface of the circuit board 60. For example, a scattered wire is provided, one end of the wire is welded to the second end of the resistor element R, and the other end of the wire is welded to the board-to-board interface BP. The wire is used as the trace 69.

[0129] Fig.10 4 is a schematic diagram of the structure of a display panel 400 according to an embodiment of the present application.

[0130] Please refer to Fig.10 The display panel 400 may include a display substrate 20, a driving chip 40 and a circuit board 60. The display substrate 20 has a display area 23 (AA area) and a wiring area 25 (Pad area), and the wiring area 25 is provided with a plurality of pins P, and the plurality of pins P include a first pin P3.

[0131] The driver chip 40 is installed in the wiring area 25 of the display substrate 20, and has multiple interfaces J, which include an enable interface J1 (i.e., EN interface or EN PIN). The enable interface J1 is configured to control the use of a specific communication protocol, and the enable interface J1 is electrically connected to the first pin P3.

[0132] The circuit board 60 has a plurality of gold fingers G, the plurality of gold fingers G include a first gold finger G3, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P, and the first gold finger G3 is connected to the first pin P3.

[0133] The enabling interface J1 can be applied with a first potential signal or a second potential signal through the circuit board 60. When the enabling interface J1 is applied with the first potential signal, the specific communication protocol is not used; when the enabling interface is applied with the second potential signal, the specific communication protocol is used.

[0134] In the above embodiment, the specific communication protocol can be selected for use or not. This is conducive to giving full play to the advantages of the communication protocol and avoiding its disadvantages. For example, when it is detected that it is at a time suitable for using the communication protocol, a second potential signal can be applied to the enabling interface to enable the specific communication protocol to be used. When it is detected that it is at a time not suitable for using the communication protocol, a first potential signal can be applied to the enabling interface to disable the specific communication protocol from being used.

[0135] There are various positional relationships between the display area 23 and the wiring area 25. In some embodiments, the display area 23 is the main body of the display substrate 20, having a plurality of pixel units for displaying images; the wiring area 25 is located at an edge of the display substrate 20 to achieve electrical connection with external components. In some embodiments, the display area 23 is adjacent to the wiring area 25.

[0136] There are many ways to arrange the plurality of pins P. In some embodiments, the plurality of pins P are located on a side of the wiring area 25 away from the display area 23 and are arranged along a straight line. In other embodiments, the plurality of pins P may also be arranged along multiple sides of the wiring area 25. For example, the plurality of pins P may be arranged along three outer sides of the wiring area 25 (excluding the side of the wiring area 25 adjacent to the display area 23).

[0137] There are many ways to install the driver chip 40. In some embodiments, the driver chip 40 is installed in the wiring area 25 by bonding. In some embodiments, the driver chip 40 is installed in the wiring area 25 by plugging. For example, the driver chip 40 is provided with a connector, and the wiring area 25 is provided with a matching connector. By plugging the connector into the matching connector, the driver chip 40 can be installed on the wiring area 25.

[0138] The enabling interface J1 can be electrically connected to the first pin P3 through a wire 28 in the wiring area 25. In some embodiments, the wire 28 is disposed inside the wiring area 25 of the display substrate 20. In some embodiments, the wire 28 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the enabling interface J1, and the other end of the wire is welded to the first pin P3. The wire serves as the wire 28.

[0139] The communication protocol can be any communication protocol. In some embodiments, the communication protocol is the QSPI protocol. The QSPI protocol is a (Queue Serial peripheral interface) communication protocol. It can be set that when the display panel is in AOD (Always on display) mode, the QSPI protocol is used. Because in AOD mode, the display panel does not need to transmit high-speed signals and the amount of data is also small, the use of the QSPI communication protocol is applicable and helps to reduce the workload of the driver chip. It can be further set that when the display panel is in other modes (for example, normal display), the QSPI protocol is not used, and other protocols are used. The other protocols include the MIPI (Mobile Industry Processor Interface) protocol. The MIPI protocol can transmit high-speed signals, has a large amount of data, low power consumption, and good anti-interference performance.

[0140] In some embodiments, the plurality of gold fingers G of the circuit board 60 are connected to the plurality of pins P by bonding, and the first gold finger G3 is connected to the first pin P3 by bonding.

[0141] There are many ways to arrange the plurality of gold fingers G. In some embodiments, the plurality of gold fingers G are located on a side of the circuit board 60 adjacent to the wiring area 25 and are arranged along a straight line.

[0142] In some embodiments, the circuit board 60 is a flexible printed circuit (FPC).

[0143] In some embodiments, the first potential signal is a high potential, and the second potential signal is a low potential, that is, when a high potential signal is applied to the enable interface J1, the specific communication protocol is not used; when a low potential signal is applied to the enable interface J1, the specific communication protocol is used.

[0144] Furthermore, the plurality of interfaces J further include a second interface J4, and the second interface J4 is used to selectively provide a first potential signal (high potential signal) or a second potential signal (low potential signal). In some embodiments, the second interface J4 is a GPIO interface (General-purpose input / output). The second interface J4 can switch to output the first potential signal or the second potential signal by programming (Code).

[0145] The plurality of pins P further include a second pin P6. The second interface J4 is electrically connected to the second pin P6.

[0146] The plurality of gold fingers G further include a second gold finger G6, which is connected to the second pin P6. In the circuit board 60, the second gold finger G6 is electrically connected to the first gold finger G3. In some embodiments, the second gold finger G6 is connected to the first gold finger G3 via a trace 68, a trace 67, and a trace 65.

[0147] The above connection ensures that the enabling interface J1 and the second interface J4 are electrically connected and have the same potential.

[0148] When the specific communication protocol does not need to be used, the second interface J4 can be controlled to be at the first potential, and provide a first potential signal to the enabling interface J1.

[0149] When the specific communication protocol needs to be used, the second interface J4 can be controlled to be at a second potential, and a second potential signal can be provided to the enabling interface J1.

[0150] The second interface J4 can be electrically connected to the second pin P6 through a wire 28 in the wiring area 25. In some embodiments, the wire 28 for connecting the second interface J4 and the second pin P6 is disposed inside the wiring area 25 of the display substrate 20. In some embodiments, the wire 28 for connecting the second interface J4 and the second pin P6 is disposed on the surface of the wiring area 25 of the display substrate 20. For example, after the driver chip 40 is installed in the wiring area 25, a scattered wire is provided, one end of the wire is welded to the second interface J4, and the other end of the wire is welded to the second pin P6.

[0151] In some embodiments, the second gold finger G6 is connected to the second pin P6 by binding.

[0152] In some embodiments, the traces 68, 67, 65 are disposed inside the circuit board 60. In some embodiments, the traces 68, 67, 65 are disposed on the surface of the circuit board 60.

[0153] The display panel in the above embodiments may be a flexible display panel using OLED display technology.

[0154] The present application also provides an electronic device, which may include various display panels as described above. In some embodiments, the electronic device may be a wearable device. The wearable device may be a watch.

[0155] The present application also provides a method for manufacturing a display panel, which can be used to manufacture the various display panels mentioned above. The method for manufacturing a display panel may include:

[0156] Provide a display substrate, a driving chip and a circuit board;

[0157] The display substrate has a display area and a wiring area, the display area includes a plurality of pixel units, the wiring area is provided with a plurality of pins, and the plurality of pins include a first pin;

[0158] The driver chip is mounted on the wiring area of ​​the display substrate, wherein the driver chip has a plurality of interfaces, wherein the plurality of interfaces include an enable interface, wherein the enable interface is configured to control the use of a communication protocol, and the enable interface is electrically connected to the first pin;

[0159] Connecting the circuit board to the display substrate, the circuit board having a plurality of gold fingers, the plurality of gold fingers including a first gold finger, the plurality of gold fingers of the circuit board being connected to the plurality of pins, the first gold finger being connected to the first pin;

[0160] Among them, the enabling interface can be applied with a first potential signal or a second potential signal through the circuit board; when the enabling interface is applied with the first potential signal, the communication protocol is not used; when the enabling interface is applied with the second potential signal, the communication protocol is used.

[0161] Further, the step of providing or making a circuit board may include the following steps.

[0162] like Fig.11 First, a double-layer board 53 is provided. The double-layer board 53 may include a first metal layer 536, a first insulating layer 534 and a second metal layer 532. The first metal layer 536 and the second metal layer 532 may be made of copper. The first insulating layer 534 may be made of a PI (polyimide) flexible material to make the double-layer board 53 flexible as a whole. The second metal layer 532 may be etched with a chemical solution to form a desired circuit. A hole 5320 is formed in a portion of the second metal layer 532 that is etched away.

[0163] like Fig.12 , the double-layer board 53 and the single-layer board 55 are bonded together by a glue layer 57. The material of the glue layer 57 can be AD glue. The single-layer board 55 can include a second insulating layer 554 and a third metal layer 552. The material of the second insulating layer 554 can be PI (polyimide) flexible material, so that the single-layer board 55 has flexibility as a whole. The material of the third metal layer 552 can be copper.

[0164] like Fig.13 , a contact hole 530 may be formed in the double-layer board 53 and a contact hole 550 may be formed in the single-layer board 55 by using a laser drilling process.

[0165] like Fig.14 , metal material is filled in the contact hole 530 to form a metal hole column 539, and metal material is filled in the contact hole 550 to form a metal hole column 559. The metal hole column 539 and the metal hole column 559 can be formed by electroplating process. The material of the metal hole column 539 and the metal hole column 559 can be copper.

[0166] like Fig.15 The first metal layer 536 and the third metal layer 552 can be etched with chemical solution to form the required circuit. The etched away portion of the first metal layer 536 will form a hole 5363. The etched away portion of the third metal layer 552 will form a hole 5523.

[0167] like Fig.16 , a first protective layer 59 (Coverlay) is covered on the surface of the first metal layer 536, and a second protective layer 58 (Coverlay) is covered on the surface of the third metal layer 552; and then a hole 592 is opened in the first protective layer 59. The metal structure exposed by the hole 592 is used as a pad. The pad can be the first pad, the second pad, and the third pad mentioned above.

[0168] Conventional three-layer circuit boards (flexible circuit boards) are relatively thick, which will squeeze the space of the display panel and the electronic device. The embodiment of the present application adopts a double-layer board + single-layer board structure, which can greatly reduce the overall thickness of the circuit board. The double-layer board is used to route the signal line; most of the single-layer board is paved with metal to shield signal interference.

[0169] like Fig.17 , forming solder paste 513 in the hole 592. The material of the solder paste 513 can be tin. The solder paste 513 is electrically connected to the pad below the hole 592.

[0170] like Fig.18 , a conductive body 51 is formed above the first protective layer 59 and the solder paste 513. The conductive body 51 may be made of a metal material, such as copper. After the conductive body 51 is placed on the solder paste 513, an annealing process may be used to solidify and fix the connection between the conductive body 51 and the solder paste 513. The conductive body 51 is used to connect two different pads.

[0171] In the present application, different embodiments may complement each other if there is no conflict.

[0172] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more than two, unless otherwise clearly defined.

[0173] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0174] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display panel, characterized in that: The display panel comprises: A display substrate having a display area and a wiring area, wherein the display area includes a plurality of pixel units, and the wiring area is provided with a plurality of pins, wherein the plurality of pins includes a first pin; a driving chip mounted on the wiring area of ​​the display substrate, having a plurality of interfaces, wherein the plurality of interfaces include an enabling interface, the enabling interface being configured to control the use of a communication protocol, the enabling interface being electrically connected to the first pin; A circuit board having a plurality of gold fingers, wherein the plurality of gold fingers include a first gold finger, the plurality of gold fingers of the circuit board are connected to the plurality of pins, and the first gold finger is connected to the first pin; Among them, the enabling interface can be applied with a first potential signal or a second potential signal through the circuit board; when the enabling interface is applied with the first potential signal, the communication protocol is not used; when the enabling interface is applied with the second potential signal, the communication protocol is used.

2. The display panel according to claim 1, wherein: The communication protocol includes the QSPI protocol.

3. The display panel according to claim 2, wherein: When the QSPI protocol is not used, the MIPI communication protocol is used.

4. The display panel according to claim 1, wherein: The plurality of gold fingers of the circuit board are connected to the plurality of pins by binding, and the first gold finger is connected to the first pin by binding.

5. The display panel according to claim 1, wherein: The first potential signal is a high potential, and the second potential signal is a low potential.

6. The display panel according to claim 1, wherein: The plurality of interfaces further include a second interface and a third interface, wherein one of the second interface and the third interface is used to provide a first potential signal, and the other is used to provide a second potential signal; The plurality of pins further include a second pin and a third pin, the second interface is electrically connected to the second pin, and the third interface is electrically connected to the third pin; The plurality of golden fingers further include a second golden finger and a third golden finger, wherein the second golden finger is connected to the second pin, and the third golden finger is connected to the third pin; The circuit board also has a plurality of pads, the plurality of pads include a first pad, a second pad and a third pad, the first pad is electrically connected to the first gold finger, the second pad is electrically connected to the second gold finger, and the third pad is electrically connected to the third gold finger; The first pad is alternatively connected to the second pad or the third pad.

7. The display panel according to claim 6, wherein: The second golden finger is connected to the second pin by binding, and the third golden finger is connected to the third pin by binding.

8. The display panel according to claim 6, wherein: The first pad is electrically connected to the first gold finger through a trace in the circuit board, the second pad is electrically connected to the second gold finger through a trace in the circuit board, and the third pad is electrically connected to the third gold finger through a trace in the circuit board.

9. The display panel according to claim 6, wherein: The second pad and the third pad are both adjacent to the first pad, and the second pad and the third pad are disposed on different sides of the first pad.

10. The display panel according to claim 6, wherein: The first pad and the second pad are connected via a conductive body arranged on the surface of the circuit board; Alternatively, the first pad is connected to the third pad via a conductive body disposed on the surface of the circuit board.

11. The display panel according to claim 1, wherein: The circuit board further comprises a fifth pad and a board-to-board interface, the fifth pad has a first potential and is used to provide a first potential signal to the first gold finger, and a resistor element is connected between the fifth pad and the first gold finger; The board-to-board interface is electrically connected to the first gold finger, and the board-to-board interface can be switched between a first state and a second state, and in the first state, the board-to-board interface is in a high-impedance state or a floating state; In the second state, the board-to-board interface has a second potential, and provides a second potential signal to the enable interface.

12. The display panel according to claim 11, wherein: The fifth pad is connected to the ground.

13. The display panel according to claim 1, wherein: The plurality of interfaces further comprises a second interface, the second interface being used to selectively provide a first potential signal or a second potential signal; The plurality of pins further include a second pin, and the second interface is electrically connected to the second pin; the plurality of gold fingers further include a second gold finger, and the second gold finger is connected to the second pin, and the second gold finger is electrically connected to the first gold finger.

14. The display panel according to claim 13, wherein: The second interface is a GPIO interface; the second interface switches to output a first potential signal or a second potential signal in a programming manner.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 14.

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