Pixel circuit, driving method thereof, display panel and display device

Abstract

This disclosure provides a pixel circuit and its driving method, a display panel, and a display device, relating to the field of display technology, to reduce flicker values. The pixel circuit includes a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a storage sub-circuit. The driving sub-circuit is configured to control the conduction and cutoff of the circuit between the second and third nodes under the control of the voltage of the first node. The compensation sub-circuit is configured to control the conduction and cutoff of the circuit between the first and third nodes in response to a first scan signal received at a first scan signal terminal. The reset sub-circuit is configured to transmit a first initialization signal received at a first initialization signal terminal to the first node in response to a reset signal received at a reset signal terminal. The storage sub-circuit is configured to store the voltages of the first and second nodes. This application is used for image display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit and its driving method, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, high contrast, and flexible display.

[0003] Currently, display devices use variable refresh rate display panels to meet users' needs for low power consumption and high refresh rates. However, when displaying at low frequencies, the frame rate of the display panel decreases, and the human eye becomes more sensitive to the flicker of the display panel, resulting in the human eye being able to perceive flickering in the displayed image. Summary of the Invention

[0004] This disclosure provides a pixel circuit and its driving method, a display panel, and a display device to reduce the flicker value of the display panel and improve the problem of flickering in the display screen that is perceptible to the human eye.

[0005] On one hand, a pixel circuit is provided. The pixel circuit includes a driving sub-circuit, a compensation sub-circuit, a reset sub-circuit, and a storage sub-circuit.

[0006] The driving sub-circuit is coupled to the first node, the second node, and the third node. The driving sub-circuit is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node.

[0007] The compensation sub-circuit is coupled to the first scan signal terminal, the first node, and the third node. The compensation sub-circuit is configured to control the conduction and cutoff of the circuit between the first node and the third node in response to a first scan signal received at the first scan signal terminal.

[0008] The reset sub-circuit is coupled to a first initialization signal terminal, a reset signal terminal, and the first node. The reset sub-circuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of a reset signal received at the reset signal terminal.

[0009] The storage subcircuit is coupled to a first voltage signal terminal, the first node, and the second node. The storage subcircuit is configured to store the voltages of the first node and the second node.

[0010] In some embodiments, the storage sub-circuit includes a first storage capacitor and a second storage capacitor. The first plate of the first storage capacitor is connected to the first voltage signal terminal, and the second plate of the first storage capacitor is connected to the first node. The first plate of the second storage capacitor is connected to the first voltage signal terminal, and the second plate of the second storage capacitor is connected to the second node.

[0011] In some embodiments, the compensation sub-circuit includes a first sub-transistor and a second sub-transistor connected in series. A first terminal of the first sub-transistor is connected to the first node, a second terminal of the first sub-transistor and / or a first terminal of the second sub-transistor is connected to a fourth node, a second terminal of the second sub-transistor is connected to the third node, and the control electrodes of the first and second sub-transistors are connected to the first scan signal terminal. The pixel circuit further includes a leakage prevention sub-circuit coupled to a control signal terminal, a constant voltage terminal, and the fourth node. The leakage prevention sub-circuit is configured to transmit a constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of a control signal received at the control signal terminal.

[0012] In some embodiments, the pixel circuit further includes a light-emitting control sub-circuit, which is coupled to a first voltage signal terminal, an enable signal terminal, a second node, a third node, and a fifth node. The fifth node is connected to the anode of the light-emitting device. The light-emitting control sub-circuit is configured to control the circuit between the first voltage signal terminal and the second node to be turned on and off in response to an enable signal received at the enable signal terminal; and to control the circuit between the third node and the fifth node to be turned on and off; wherein the signals received at the enable signal terminal and the control signal terminal are the same.

[0013] In some embodiments, the pixel circuit further includes a data writing sub-circuit coupled to a data signal terminal, a second scan signal terminal, and the second node. The data writing sub-circuit is configured to transmit a data signal received at the data signal terminal to the second node in response to a first operating voltage of a second scan signal received at the second scan signal terminal; and to transmit a data refresh signal received at the data signal terminal to the second node in response to a second operating voltage of the second scan signal received at the second scan signal terminal; the data refresh signal is a data signal received by other row pixel circuits.

[0014] In some embodiments, the cutoff time of the first operating voltage of the second scan signal is prior to the cutoff time of the operating voltage of the first scan signal. Furthermore, the time interval between the cutoff time of the first operating voltage of the second scan signal and the cutoff time of the operating voltage of the first scan signal is greater than or equal to one row scan period. The row scan period is the duration of one operating voltage of the second scan signal.

[0015] In some embodiments, the start time of the first operating voltage of the second scan signal is after the end time of the operating voltage of the reset signal. Furthermore, the time interval between the start time of the first operating voltage of the second scan signal and the end time of the operating voltage of the reset signal is greater than or equal to one row scan period. The row scan period is the duration of one operating voltage of the second scan signal.

[0016] In some embodiments, the compensation sub-circuit includes a P-type transistor. The duration of the operating voltage of the first scan signal is greater than or equal to four row scan periods. The voltage of the first row scan period after the first scan signal starts operating is greater than the voltage of the second row scan period after the first scan signal starts operating. The row scan period is the duration of one operating voltage of the second scan signal. The duration of the first operating voltage of the second scan signal coincides with the 2Nth row scan period of the operating voltage of the first scan signal, where N ≥ 2 and N is an integer.

[0017] In some embodiments, the start and end times of the second operating voltage of the second scan signal are located between the end time of the operating voltage of the first scan signal and the start time of the operating voltage of the enable signal. Furthermore, the time interval between the start time of the second operating voltage of the second scan signal and the end time of the operating voltage of the first scan signal is greater than or equal to one row scan period. The time interval between the end time of the second operating voltage of the second scan signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scan period. The row scan period is the duration of one operating voltage of the second scan signal.

[0018] In some embodiments, the data writing sub-circuit is further configured to transmit the data holding signal received at the data signal terminal to the second node in response to a third operating voltage of the second scan signal received at the second scan signal terminal.

[0019] In some embodiments, the reset sub-circuit is further coupled to a second initialization signal terminal, a third scan signal terminal, and a fifth node. The reset sub-circuit is also configured to, under the control of the operating voltage of the third scan signal received at the third scan signal terminal, transmit the second initialization signal received at the second initialization signal terminal to the fifth node.

[0020] In some embodiments, the start time of the working voltage of the reset signal is before the start time of the working voltage of the first scan signal. Furthermore, the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scan signal is greater than or equal to three line scan periods. And / or; the end time of the working voltage of the reset signal is after the start time of the working voltage of the first scan signal; and the time interval between the end time of the working voltage of the reset signal and the start time of the working voltage of the first scan signal is greater than or equal to two line scan periods.

[0021] In the pixel circuit of this embodiment, after a frame display begins, the storage sub-circuit can store the voltage at the second node after the previous frame display ends, so that the second node maintains a relatively stable potential corresponding to the first voltage signal. This allows the first and third nodes of the driving sub-circuit to generate a stable and large bias voltage, improving the hysteresis characteristics of the driving sub-circuit, thereby improving the afterimage performance of the sub-pixel, reducing the flicker value of the display panel, and improving the problem of flickering in the display screen that can be perceived by the human eye.

[0022] On the other hand, a method for driving a pixel circuit is provided. This method is used to drive a pixel circuit as described in any of the above embodiments. A display frame includes a refresh frame, which includes a first reset phase and a second reset phase.

[0023] In the first reset phase, the reset sub-circuit, responding to the operating voltage of the reset signal at the reset signal terminal, transmits the first initialization signal received at the first initialization signal terminal to the first node. Furthermore, the storage sub-circuit stores the voltage of the second node after the end of the previous frame. In the second reset phase, the reset sub-circuit, responding to the operating voltage of the reset signal at the reset signal terminal, transmits the first initialization signal received at the first initialization signal terminal to the first node. The compensation sub-circuit, responding to the operating voltage of the first scan signal received at the first scan signal terminal, transmits the voltage of the first node to the third node. And, under the control of the voltage of the first node, the driving sub-circuit transmits the voltage of the third node to the second node.

[0024] In some embodiments, the pixel circuit further includes a data writing sub-circuit, and the refresh frame further includes a first data writing phase and a second data writing phase.

[0025] During the first data writing phase, the data writing sub-circuit, in response to the first operating voltage of the second scan signal received at the second scan signal terminal, transmits the data signal received at the data signal terminal to the second node and writes it into the storage sub-circuit. The driving sub-circuit, under the control of the voltage of the first node, transmits the voltage of the second node to the third node. The compensation sub-circuit, in response to the operating voltage of the first scan signal received at the first scan signal terminal, transmits the voltage of the third node to the first node.

[0026] During the second data writing phase, the storage sub-circuit discharges, transmitting the stored data signal to the second node. Under the control of the voltage at the first node, the driving sub-circuit transmits the voltage of the second node to the third node. The compensation sub-circuit, responding to the operating voltage of the first scan signal received at the first scan signal terminal, transmits the voltage of the third node to the first node.

[0027] In some embodiments, the compensation sub-circuit includes a P-type transistor; the second reset phase includes at least three row scan periods. During the second reset phase, the voltage of the first row scan period after the first scan signal is activated is greater than the voltage of the second row scan period after the first scan signal is activated. The first data write phase occurs after the second reset phase and coincides with the 2Nth row scan period after the start time of the second reset phase, where N ≥ 2 and N is an integer.

[0028] In some embodiments, the pixel circuit includes a data writing sub-circuit, and the refresh frame further includes a third reset phase and a first light emission phase, the third reset phase being located between the second data writing phase and the first light emission phase. In the third reset phase, the data writing sub-circuit, in response to a second operating voltage of the second scan signal received at the second scan signal terminal, transmits the data refresh signal received at the data signal terminal to the second node.

[0029] In some embodiments, the difference between the start time of the third reset phase and the end time of the second data writing phase is greater than or equal to one row scan period. And / or, the difference between the end time of the third reset phase and the start time of the first light emission phase is greater than or equal to one row scan period.

[0030] In some embodiments, the difference between the start time of the first reset phase and the start time of the frame in which the first reset phase is located is greater than or equal to two line scan periods.

[0031] In some embodiments, the pixel circuit includes a data writing sub-circuit, a leakage prevention sub-circuit, and a light emission control sub-circuit. The pixel circuit has a first refresh frequency and a second refresh frequency, the second refresh frequency being lower than the first refresh frequency. At the first refresh frequency, a display frame includes a refresh frame; at the second refresh frequency, a display frame includes a refresh frame and at least one holding frame. The holding frame includes a black insertion phase, a fourth reset phase, and a second light emission phase.

[0032] During the black insertion phase, the light emission control sub-circuit is configured to control the circuit transmitting the drive current signal to cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal.

[0033] In the fourth reset phase, the data writing sub-circuit responds to the third operating voltage of the second scan signal received at the second scan signal terminal and transmits the data holding signal received at the data signal terminal to the second node.

[0034] In the second light-emitting stage, the light-emitting control sub-circuit, in response to the operating voltage of the enable signal received at the enable signal terminal, transmits the first voltage signal received at the first voltage signal terminal to the second node; the driving sub-circuit generates a driving current signal based on the voltage of the first node and the voltage of the second node; and the light-emitting control sub-circuit, in response to the operating voltage of the enable signal received at the enable signal terminal, transmits the driving current signal to the light-emitting device; the leakage prevention sub-circuit, in response to the operating voltage of the control signal received at the control signal terminal, transmits the constant voltage signal received at the constant voltage terminal to the fourth node.

[0035] In some embodiments, the difference between the end time of the fourth reset phase and the start time of the second light emission phase is greater than or equal to one line scan period.

[0036] In another aspect, a display panel is provided. The display device includes a plurality of pixel circuits as described in any of the above embodiments. The plurality of pixel circuits are arranged in M ​​rows and N columns, each row including N pixel circuits arranged along a first direction, and each column including M pixel circuits arranged along a second direction, where M > 1, N > 1, and M and N are both integers.

[0037] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the first to the Mth rows of pixel circuits.

[0038] The display panel further includes a first gate driving circuit, which comprises M+Q cascaded first shift registers. From the first stage first shift register to the last stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers. Each first shift register includes a first signal output terminal. The first scan signal terminal of the Pth row pixel circuit is connected to the first signal output terminal of the P+Qth first shift register; the reset signal terminal of the Pth row pixel circuit is connected to the first output terminal of the Pth first shift register; P≤M, Q>0, and P and Q are both integers.

[0039] In some embodiments, along the second direction, from the first row of pixel circuits to the last row of pixel circuits, the M rows of pixel circuits are respectively the first to the Mth rows of pixel circuits.

[0040] The display panel further includes a second gate driving circuit and a third gate driving circuit. The second gate driving circuit includes M cascaded second shift registers, from the first stage to the last stage, where the M second shift registers are respectively the 1st to the Mth second shift registers. Each second shift register includes a second signal output terminal. The first scan signal terminal of the Pth row pixel circuit is connected to the second signal output terminal of the Pth second shift register, where P ≤ M, and P is an integer.

[0041] The third gate drive circuit includes M cascaded third shift registers, from the first-stage third shift register to the last-stage third shift register, with the M third shift registers being the 1st to the Mth third shift registers respectively. Each third shift register includes a third signal output terminal. The reset signal terminal of the Pth row pixel circuit is connected to the third signal output terminal of the Pth third shift register, where P ≤ M, and P is an integer.

[0042] In another aspect, a display device is provided. The display device includes a display panel as described in any of the above embodiments.

[0043] The beneficial effects of the pixel circuit driving method, display panel, and display device provided in this disclosure embodiment are the same as those of the pixel circuit provided in the above technical solution, and will not be repeated here. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0045] Figure 1 This is a structural diagram of a display device according to some embodiments;

[0046] Figure 2 This is a structural diagram of another display device according to some embodiments;

[0047] Figure 3 for Figure 1 A sectional view along section line AA';

[0048] Figure 4 This is a structural diagram of a display panel according to some embodiments;

[0049] Figure 5 for Figure 4 A sectional view along the section line CC'.

[0050] Figure 6 This is a structural block diagram of a pixel circuit according to some embodiments;

[0051] Figure 7 for Figure 6 The circuit diagram of the pixel circuit shown;

[0052] Figure 8A This is a block diagram of another pixel circuit according to some embodiments;

[0053] Figure 8B This is a structural block diagram of another pixel circuit according to some embodiments;

[0054] Figure 9A for Figure 8A The circuit diagram of the pixel circuit shown;

[0055] Figure 9B for Figure 8B The circuit diagram of the pixel circuit shown;

[0056] Figure 10 This is a structural diagram of a gate driving circuit for a display panel according to some embodiments;

[0057] Figure 11 This is a structural diagram of a gate driving circuit for another display panel according to some embodiments;

[0058] Figure 12 This is a structural diagram of a gate driving circuit for another display panel according to some embodiments;

[0059] Figure 13 This is a timing diagram of a pixel circuit according to some embodiments;

[0060] Figure 14 This is another timing diagram of a pixel circuit according to some embodiments;

[0061] Figure 15 This is yet another timing diagram of a pixel circuit according to some embodiments. Detailed Implementation

[0062] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0063] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0064] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0065] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0066] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0067] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0068] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0069] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0070] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0071] Given the measurements discussed and the errors associated with a particular number of measurements (i.e., limitations of the measurement system), as used herein, “about,” “approximately,” or “roughly” includes stated values ​​and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0072] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0073] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] In this specification, unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that, unless expressly defined herein, terms (e.g., those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted as having an ideal or overly formal meaning.

[0076] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0077] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0078] In the embodiments of this disclosure, the transistor used may be a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin film transistors as an example.

[0079] In the embodiments of this disclosure, the control electrode of each thin-film transistor is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first electrode and the second electrode of the thin-film transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, when the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0080] In embodiments of this disclosure, the capacitor can be a capacitor device fabricated separately through a process, such as by fabricating dedicated capacitor electrodes. Each capacitor electrode can be implemented using a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be the parasitic capacitance between transistors, or it can be implemented through the transistor itself and other devices or circuits, or it can utilize the parasitic capacitance between the circuit's own lines.

[0081] In the embodiments of this disclosure, nodes such as the first node, the second node, the first control node, and the second control node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0082] In embodiments of this disclosure, "operating voltage" refers to a voltage that enables the operated transistors included therein to conduct; correspondingly, "non-operating voltage" refers to a voltage that does not enable the operated transistors included therein to conduct.

[0083] In embodiments of this disclosure, "low level" refers to a voltage that enables the included P-type transistor to conduct but does not enable the included N-type transistor to conduct (i.e., the N-type transistor is turned off); correspondingly, "high level" refers to a voltage that enables the included N-type transistor to conduct but does not enable the included P-type transistor to conduct (i.e., the P-type transistor is turned off).

[0084] like Figure 1 and Figure 2 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0085] For example, the display device 1000 can be any product or component with display function, such as a television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, wearable device, virtual reality (VR) device, etc.

[0086] For example, such as Figure 1 As shown, the display device 1000 can be a portable display product; for example, the display device 1000 can be... Figure 1 The mobile phone shown. For example, see [link to relevant documentation]. Figure 2 The display device 1000 can be a wearable device; for example, the display device 1000 can be... Figure 2 The watch shown.

[0087] The following uses the aforementioned display device 1000 as an example. Figure 1 The present invention uses a mobile phone as an example to illustrate some embodiments of the present invention, but the implementation of the present invention is not limited thereto.

[0088] In some embodiments, see Figure 3 The display device 1000 includes a display panel 100.

[0089] The display panel 100 includes a light-emitting side and a non-light-emitting side arranged opposite to each other. The light-emitting side is the side of the display panel 100 used for display, i.e. Figure 3 The upper side of the middle.

[0090] For example, such as Figure 3 As shown, the above-mentioned display device 1000 may also include a housing 200, a cover plate 300, a circuit board 400, and other electronic components.

[0091] See Figure 3The cover plate 300 can be a single-layer glass cover plate or can include multiple layers of sub-cover plates stacked together. This embodiment of the present disclosure does not make specific limitations.

[0092] like Figure 3 As shown, the longitudinal section of the housing 200 can be, for example, U-shaped. The display panel 100 and the circuit board 400 are disposed inside the housing 200, and the cover plate 300 is disposed at the opening of the housing 200. The circuit board 400 is disposed on the side of the display panel 100 away from the cover plate 300, and the circuit board 400 is connected to the display panel 100 to provide the required display signals to the display panel 100.

[0093] The aforementioned display panel 100 comes in various types, and can be selected and configured according to actual needs.

[0094] For example, the display panel 100 may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc., and the embodiments disclosed herein are not specifically limited thereto.

[0095] The following description uses the above-mentioned display panel 100 as an OLED display panel as an example to illustrate some embodiments of this disclosure.

[0096] In some embodiments, see Figure 5 The display panel 100 includes a display substrate 110 and an encapsulation layer 120 for encapsulating the display substrate 110.

[0097] The encapsulation layer 120 can be an encapsulation film or an encapsulation substrate; the embodiments disclosed herein do not impose specific limitations.

[0098] In some embodiments, see Figure 4 The display panel 100 has a display area A, which is an area for displaying images and is configured to set multiple sub-pixels P.

[0099] For example, see Figure 4 The display panel 100 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in the display area A.

[0100] The substrate 11 mentioned above includes various types, and can be selected and set according to actual needs.

[0101] For example, substrate 11 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a polymethyl methacrylate (PMMA) substrate, etc.

[0102] For example, substrate 11 can be a flexible substrate. For example, the flexible substrate can be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate, etc.

[0103] Among them, see Figure 4 and Figure 5 Each sub-pixel P includes a light-emitting device 10 and a pixel circuit 20. The pixel circuit 20 includes a plurality of thin-film transistors 30.

[0104] like Figure 5 As shown, the thin-film transistor 30 includes a semiconductor channel 31, a source 32, a drain 33, and a gate 34, with both the source 32 and the drain 33 in contact with the semiconductor channel 31.

[0105] like Figure 5 As shown, the light-emitting device 10 includes a first electrode 11, a light-emitting functional layer 12, and a second electrode 13. The first electrode 11 is electrically connected to the source 32 or drain 33 of a thin-film transistor 30. Figure 5 The diagram illustrates the electrical connection between the first electrode 11 and the drain 33 of the thin-film transistor 30.

[0106] It should be noted that the above-mentioned light-emitting functional layer 12 may include only the light-emitting layer, or it may include, in addition to the light-emitting layer, at least one of the following: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0107] Currently, display devices use variable refresh rate display panels to meet users' needs for low power consumption and high refresh rates. However, when displaying at low frequencies, the frame rate of the display panel decreases, making the human eye more sensitive to the flicker of the display panel, resulting in the human eye being able to perceive flickering in the displayed image.

[0108] Research has revealed that the channel of the driving transistor in the pixel circuit exhibits a significant hysteresis effect due to the presence of numerous defect states. This causes the image from the previous moment (previous frame period) to often remain in the image display of the next moment, resulting in a flickering display problem.

[0109] It should be noted that the hysteresis effect refers to an uncertainty in the electrical characteristics of a driving transistor under a certain bias voltage. That is, the magnitude of the current driving the transistor is not only related to the current bias voltage, but also to the bias voltage state in the previous period.

[0110] Based on this, see Figure 6 The pixel circuit 20 provided in some embodiments of this disclosure includes a driving sub-circuit 21, a compensation sub-circuit 22, a reset sub-circuit 23, and a storage sub-circuit 24.

[0111] In some examples, such as Figure 6 As shown, the driving sub-circuit 21 is coupled to the first node N1, the second node N2, and the third node N3. The driving sub-circuit 21 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the voltage of the first node N1; and to generate a driving current signal based on the voltage of the first node N1 and the voltage of the second node N2.

[0112] For example, such as Figure 7 As shown, the driving sub-circuit 21 includes an eighth transistor T8 (i.e., the driving transistor mentioned above). The first terminal of the eighth transistor T8 is connected to the second node N2, the second terminal of the eighth transistor T8 is connected to the third node N3, and the control terminal of the eighth transistor T8 is connected to the first node N1.

[0113] In some examples, such as Figure 6 As shown, the compensation sub-circuit 22 is coupled to the first scan signal terminal GATE1, the first node N1, and the third node N3. The compensation sub-circuit 22 is configured to control the conduction and cutoff of the circuit between the first node N1 and the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1.

[0114] For example, see Figure 7 The compensation sub-circuit 22 includes a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series. The first terminal of the first sub-transistor T1-1 is connected to the first node N1. The second terminal of the first sub-transistor T1-1 and / or the first terminal of the second sub-transistor T1-2 are connected to the fourth node N4. The second terminal of the second sub-transistor is connected to the third node N3. The control terminals of the first sub-transistor T1-1 and the second sub-transistor T1-2 are connected to the first scan signal terminal GATE1.

[0115] It should be noted that there may be other transistors connected in series between the first sub-transistor T1-1 and the second sub-transistor T1-2. That is, the compensation sub-circuit 22 may also include three, four or more transistors connected in series. This disclosure does not specifically limit the embodiments.

[0116] The following uses the example of the compensation sub-circuit 22 including a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series to illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and it is also possible to consider that the compensation sub-circuit 22 includes three, four or more transistors connected in series, as long as the same technical concept is applied.

[0117] In some examples, such as Figure 6 As shown, the reset sub-circuit 23 is coupled to the first initialization signal terminal VINIT1, the reset signal terminal RESET, and the first node N1. The reset sub-circuit 23 is configured to, in response to the operating voltage of the reset signal received at the reset signal terminal RESET, transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the voltage of the first node N1.

[0118] For example, see Figure 7 The reset circuit 23 includes multiple fifth transistors T5 connected in series. One end of each fifth transistor T5 is connected to the first initialization signal terminal VINIT1, and the other end is connected to the first node N1. The control electrode of each fifth transistor T5 is connected to the reset signal terminal RESET.

[0119] For example, such as Figure 7 As shown, the reset circuit 23 includes two fifth transistors T5 connected in series, which form a dual-gate transistor to reduce leakage current.

[0120] Among them, see Figure 13 , Figure 14 and Figure 15 The start time of the working voltage of the reset signal is before the start time of the working voltage of the first scan signal; and the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scan signal is greater than or equal to 3 line scan periods. Figure 13 The example given is that the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scan signal is 8 line scan periods.

[0121] In addition, see Figure 13 , Figure 14 and Figure 15 The cutoff time of the reset signal's operating voltage is located after the start time of the first scan signal's operating voltage. Furthermore, the time interval between the cutoff time of the reset signal's operating voltage and the start time of the first scan signal's operating voltage is greater than or equal to two line scan periods. Figure 13 The example given is that the time interval between the cutoff time of the working voltage of the reset signal and the start time of the working voltage of the first scan signal is three line scan periods.

[0122] In some examples, such as Figure 6 As shown, the storage sub-circuit 24 is coupled to the first voltage signal terminal VDD, the first node N1, and the second node N2. The storage sub-circuit 24 is configured to store the voltages of the first node N1 and the second node N2.

[0123] For example, such as Figure 7 As shown, the storage sub-circuit 24 includes a first storage capacitor C1 and a second storage capacitor C2. The first plate of the first storage capacitor C1 is connected to the first voltage signal terminal VDD, and the second plate of the first storage capacitor C1 is connected to the first node N1. The first plate of the second storage capacitor C2 is connected to the first voltage signal terminal VDD, and the second plate of the second storage capacitor C2 is connected to the second node N2.

[0124] In this case, after a frame is displayed, the storage sub-circuit 24 can store the voltage at the second node N2 after the previous frame is displayed, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal. This causes the first node N1 and the third node N3 of the driving sub-circuit 21 to generate a stable and large bias voltage, improving the hysteresis characteristics of the driving sub-circuit 21, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering of the display screen that can be perceived by the human eye.

[0125] In other words, after a frame is displayed, the second storage capacitor C2 can store the voltage at the second node N2 (i.e., the first terminal of the eighth transistor T8) after the previous frame was displayed, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal. This causes the first terminal (second node N2) and the control terminal (third node N3) of the eighth transistor T8 to generate a stable and large bias voltage, improving the hysteresis characteristics of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering in the display screen that can be perceived by the human eye.

[0126] In some embodiments, such as Figure 8A As shown, the pixel circuit 20 also includes a leak prevention sub-circuit 25.

[0127] In some examples, such as Figure 8A and Figure 9B As shown, the leak prevention sub-circuit 25 is coupled to the control signal terminal K, the constant voltage terminal VC, and the fourth node N4. The leak prevention sub-circuit 25 is configured to transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.

[0128] The constant voltage signal has a voltage range of -7V to 7V. For example, the constant voltage signal can be any one of -7V, -6V, -5V, -4V, -3V, -2V, -1V, 0V, 1V, 2V, 3V, 4V, 5V, 6V, and 7V. Specifically, the voltage value with better leakage protection effect can be obtained through experimental testing as the actual voltage value of the constant voltage signal. This embodiment does not make specific limitations here.

[0129] For example, such as Figure 9B As shown, the leak prevention sub-circuit 25 includes a second transistor T2. The first terminal of the second transistor T2 is connected to the constant voltage terminal VC, the second terminal of the second transistor T2 is connected to the fourth node N4, and the control terminal of the second transistor T2 is connected to the control signal terminal K.

[0130] In this case, during the light-emitting stage, the anti-leakage sub-circuit 25 can respond to the working voltage of the control signal received at the control signal terminal K and transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 to reduce the voltage difference between the fourth node N4 and the first node N1, reduce the risk of leakage at the first node N1, thereby reducing the flicker value of the display panel 100 and improving the problem that the human eye can perceive the flickering of the display screen.

[0131] In some embodiments, such as Figure 8A As shown, the pixel circuit 20 also includes a light emission control sub-circuit 26.

[0132] In some examples, such as Figure 8A As shown, the light-emitting control sub-circuit 26 is coupled to the first voltage signal terminal VDD, the enable signal terminal EM, the second node N2, the third node N3, and the fifth node N5. The light-emitting control sub-circuit 26 is configured to control the circuit between the first voltage signal terminal VDD and the second node N2 to be turned on and off in response to the enable signal received at the enable signal terminal EM; and to control the circuit between the third node N3 and the fifth node N5 to be turned on and off.

[0133] Here, the first voltage signal can be the signal from the positive terminal of a DC power supply, for example, the first voltage signal can be 5V.

[0134] It should be noted that the fifth node N5 is connected to the anode of the light-emitting device 10 so that the driving current signal can be transmitted to the light-emitting device 10.

[0135] For example, such as Figure 9BAs shown, the light-emitting control sub-circuit 26 includes a third transistor T3 and a fourth transistor T4. The first terminal of the third transistor T3 is connected to the first voltage signal terminal VDD, the second terminal of the third transistor T3 is connected to the second node N2, and the control terminal of the third transistor T3 is connected to the enable signal terminal EM. The first terminal of the fourth transistor T4 is connected to the third node N3, the second terminal of the fourth transistor T4 is connected to the fifth node N5, and the control terminal of the fourth transistor T4 is connected to the enable signal terminal EM.

[0136] Based on this, such as Figure 9B As shown, the signals received at the enable signal terminal EM and the control signal terminal K are the same. This allows the enable signal terminal EM and the control signal terminal K to be connected to the same signal line, such as the gate line mentioned below, to simplify the circuit structure. That is, during the light-emitting phase, the anti-leakage sub-circuit 25, in response to the operating voltage of the control signal received at the enable signal terminal EM, transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4. This reduces the voltage difference between the fourth node N4 and the first node N1, lowers the risk of leakage at the first node N1, and thus reduces the flicker value of the display panel 100, improving the problem of flickering in the display screen that is perceptible to the human eye.

[0137] In some embodiments, such as Figure 8A As shown, the pixel circuit 20 also includes a data writing sub-circuit 27.

[0138] In some examples, such as Figure 8A As shown, the data writing sub-circuit 27 is coupled to the data signal terminal DATA, the second scan signal terminal GATE2, and the second node N2. The data writing sub-circuit 27 is configured to transmit the data signal received at the data signal terminal DATA to the second node N2 in response to a first operating voltage of the second scan signal received at the second scan signal terminal GATE2; and to transmit the data refresh signal received at the data signal terminal DATA to the second node N2 in response to a second operating voltage of the second scan signal received at the second scan signal terminal GATE2. This data refresh signal is a data signal received by other row pixel circuits 20, such as the data signal received by the pixel circuit 20 of the adjacent next row.

[0139] It should be noted that the magnitudes of the first working voltage and the second working voltage of the second scanning signal can be the same, but the timing of the first working voltage and the second working voltage are not the same.

[0140] For example, see Figure 13 , Figure 14 and Figure 15The cutoff time of the first operating voltage of the second scan signal is located before the cutoff time of the operating voltage of the first scan signal. Furthermore, the time interval between the cutoff time of the first operating voltage of the second scan signal and the cutoff time of the operating voltage of the first scan signal is greater than or equal to one line scan period H.

[0141] It should be noted that the row scan period H is the duration of one working voltage of the second scan signal.

[0142] For example, such as Figure 13 As shown, the time interval between the cutoff time of the first working voltage of the second scan signal and the cutoff time of the working voltage of the first scan signal is 5 line scan periods H.

[0143] For example, see Figure 13 , Figure 14 and Figure 15 The start time of the first operating voltage of the second scan signal is after the cutoff time of the operating voltage of the reset signal. Furthermore, the time interval between the start time of the first operating voltage of the second scan signal and the cutoff time of the operating voltage of the reset signal is greater than or equal to one row scan period H.

[0144] For example, such as Figure 13 As shown, the time interval between the start time of the first working voltage of the second scan signal and the end time of the working voltage of the reset signal is 2 line scan periods H.

[0145] In some embodiments, see Figure 9B The aforementioned compensation sub-circuit 22 includes P-type transistors. Furthermore, in conjunction with... Figure 13 , Figure 14 and Figure 15 The duration of the operating voltage of the first scan signal is greater than or equal to four line scan periods H. The voltage of the first line scan period H after the first scan signal starts working is greater than the voltage of the second line scan period H after the first scan signal starts working. This line scan period H is the duration of one operating voltage of the second scan signal. In other words, the stability of the first scan signal output in the even-numbered line scan period H is greater than the stability in the odd-numbered line scan period H.

[0146] In this disclosure, the voltage of the first row scan period H after the first scan signal is activated can be understood as the first period after the effective level of the first scan signal begins to be input, i.e. Figure 13 The first line scan period H after the first falling edge of the first scan signal terminal GATE1, which is also the first line scan period H counting from left to right in the second reset phase P12; or, it can be understood as being used to... Figure 9A The first time period after the first sub-transistor T1-1 in the middle is turned on by the input level.

[0147] In this disclosure, the voltage of the second row scanning period H after the first scan signal is activated can be understood as the second period after the effective level of the first scan signal begins to be input, i.e. Figure 13 The second row scan period H after the first falling edge of the first scan signal terminal GATE1, which is also the second row scan period H counting from left to right in the second reset phase P12; or, it can be understood as being used to... Figure 9A The second time period after the first sub-transistor T1-1 in the middle is turned on by the input level.

[0148] Based on this, the time of the first working voltage of the second scanning signal coincides with the 2Nth row scanning period H of the working voltage of the first scanning signal, where N≥2 and N is an integer.

[0149] For example, such as Figure 13 As shown, the duration of the working voltage of the first scan signal is 11 line scan periods H. The duration of the first working voltage of the second scan signal coincides with the 6th line scan period H of the working voltage of the first scan signal, i.e., N=3.

[0150] In addition, see Figure 13 , Figure 14 and Figure 15 The start and end times of the second working voltage of the second scan signal are located between the end time of the working voltage of the first scan signal and the start time of the working voltage of the enable signal.

[0151] Furthermore, the time interval between the start time of the second operating voltage of the second scan signal and the cutoff time of the operating voltage of the first scan signal is greater than or equal to one line scan period H. The time interval between the cutoff time of the second operating voltage of the second scan signal and the start time of the operating voltage of the enable signal is greater than or equal to one line scan period H.

[0152] For example, such as Figure 13 As shown, the time interval between the start time of the second operating voltage of the second scan signal and the cutoff time of the operating voltage of the first scan signal is two line scan periods H. The time interval between the cutoff time of the second operating voltage of the second scan signal and the start time of the operating voltage of the enable signal is one line scan period H.

[0153] In some embodiments, as shown in the figure, the data writing sub-circuit 27 is further configured to transmit the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2.

[0154] Here, the voltage range of the data hold signal is 0V to V. GMP Among them, V GMPThis refers to the black state voltage of sub-pixel P. The black state voltage is the voltage at which the target gray level of a sub-pixel P is 0. The black state voltage is used as the driving voltage for the sub-pixel P, so that the corresponding sub-pixel does not emit light.

[0155] For example, the voltage range of the data hold signal is 0V to 7V, such as any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V, and 7V. Here, the specific voltage value of the data hold signal can be determined based on experimental testing, and the voltage value with the lower flicker value can be taken as the actual voltage value of the data hold signal. This embodiment of the disclosure does not impose a specific limitation here.

[0156] It should be noted that the magnitudes of the first working voltage, the second working voltage, and the third working voltage of the second scanning signal can be the same, but the timing sequence of the first working voltage, the second working voltage, and the third working voltage is not the same.

[0157] In some embodiments, such as Figure 9B As shown, the data writing sub-circuit 27 includes a seventh transistor T7. The first terminal of the seventh transistor T7 is connected to the data signal terminal DATA, the second terminal of the seventh transistor T7 is connected to the second node N2, and the control terminal of the seventh transistor T7 is connected to the second scan signal terminal GATE2.

[0158] In some embodiments, such as Figure 8A As shown, the reset sub-circuit 23 is also coupled to the second initialization signal terminal VININT2, the third scan signal terminal GATE3, and the fifth node N5. The reset sub-circuit 23 is also configured to transmit the second initialization signal received at the second initialization signal terminal VININT2 to the fifth node N5 under the control of the operating voltage of the third scan signal received at the third scan signal terminal GATE3, so as to reset the anode (fifth node N5) of the light-emitting device 10.

[0159] For example, such as Figure 9A As shown, the reset circuit 23 also includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2, the second terminal of the sixth transistor VINIT2 is connected to the fifth node N5, and the control terminal of the sixth transistor T6 is connected to the third scan signal terminal GATE3.

[0160] In this case, the control electrode of the sixth transistor T6, which resets the anode (fifth node N5) of the light-emitting device 10, can be controlled by the third scan signal terminal GATE3, thereby resetting the anode (fifth node N5) of the light-emitting device 10 and improving the luminous efficiency.

[0161] Furthermore, the aforementioned third scan signal terminal GATE3 can be connected to the same signal line as the second scan signal terminal GATE2, meaning that the signals received at the third scan signal terminal GATE3 and the second scan signal terminal GATE2 can be the same, and the third scan signal terminal GATE3 can also be referred to as the second scan signal terminal GATE2.

[0162] At this time, as Figure 8B As shown, the reset sub-circuit 23 is coupled to the second initialization signal terminal VININT2, the second scan signal terminal GATE2, and the fifth node N5. The reset sub-circuit 23 is configured to transmit the second initialization signal received at the second initialization signal terminal VININT2 to the fifth node N5 under the control of the operating voltage of the third scan signal received at the second scan signal terminal GATE2, so as to reset the anode (fifth node N5) of the light-emitting device 10.

[0163] For example, such as Figure 9B As shown, the reset circuit 23 also includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2, the second terminal of the sixth transistor VINIT2 is connected to the fifth node N5, and the control terminal of the sixth transistor T6 is connected to the second scan signal terminal GATE2.

[0164] In this case, the control electrode of the sixth transistor T6, which resets the anode (fifth node N5) of the light-emitting device 10, and the control electrode of the seventh transistor T7 can both be controlled by the second scan signal terminal GATE2, so that the anode (fifth node N5) of the light-emitting device 10 is reset at the same time during the data writing process, simplifying the circuit structure.

[0165] The following example illustrates some embodiments of this disclosure by connecting the third scan signal terminal GATE3 and the second scan signal terminal GATE2 to the same signal line. However, the implementation of this disclosure is not limited thereto.

[0166] In some embodiments, such as Figure 4 As shown, all the pixel circuits 20 are arranged in multiple rows and columns. Each row includes multiple pixel circuits 20 arranged along a first direction X, and each column includes multiple pixel circuits 20 arranged along a second direction Y. The first direction X and the second direction Y are approximately perpendicular.

[0167] It should be noted that the first direction X can be, for example, the row direction of multiple pixel circuits 20 arranged together, and the second direction Y can be, for example, the column direction of multiple pixel circuits 20 arranged together.

[0168] The following describes some embodiments of this disclosure by taking an example of all pixel circuits 20 arranged in multiple rows and columns; however, the implementation of this disclosure is not limited thereto. Furthermore, a plurality of pixel circuits 20 arranged along the first direction X are referred to as a row of pixel circuits 20, and a plurality of pixel circuits 20 arranged along the second direction Y are referred to as a column of pixel circuits 20.

[0169] Based on this, the display panel 100 also includes multiple gate lines GL, multiple data lines DL, multiple first power lines VDL, multiple first initialization signal lines VL1, multiple second initialization signal lines VL2, and multiple constant voltage signal lines VCL.

[0170] like Figure 4 As shown, each gate line GL extends approximately along a first direction X and is configured to transmit any one of a first scan signal, a second scan signal, a reset signal, and an enable signal (control signal). For example, a gate line GL can be connected to any one of the first scan signal terminal GATE1, the second scan signal terminal GATE2, the reset signal terminal RESET, and the enable signal terminal EN (control signal terminal K) of a row pixel circuit 20.

[0171] like Figure 4 As shown, the data line DL extends generally along the second direction Y and is configured to transmit data signals. For example, a data line DL can be connected to the data signal terminal DATA of a column of pixel circuits 20.

[0172] like Figure 4 As shown, the first power line VDL extends generally along the second direction Y and is configured to transmit a first power supply voltage signal. For example, a first power line VDL can be connected to a first voltage signal terminal VDD of a column of pixel circuits 20.

[0173] like Figure 4 As shown, the first initialization signal line VL1 extends generally along the first direction X and is configured to transmit a first initialization signal. For example, a first initialization signal line VL1 can be connected to the first initialization signal terminal VINIT1 of a row pixel circuit 20.

[0174] like Figure 4 As shown, the second initialization signal line VL2 extends approximately along the first direction X and is configured to transmit a second initialization signal. One second initialization signal line VL2 may, for example, be connected to the second initialization signal terminal VINIT2 of a row pixel circuit 20.

[0175] like Figure 4 As shown, the constant voltage signal line VCL extends approximately along the second direction Y and is configured to transmit a constant voltage signal. For example, a constant voltage signal line VCL can be connected to the constant voltage signal terminal VC of a row of pixel circuitry 20.

[0176] like Figure 5 As shown, along a direction perpendicular to and away from the substrate 11, the display panel 100 includes a substrate 11, a semiconductor layer ACT, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, an interlayer insulating layer ILD, a first source / drain conductive layer SD1, a first planarization layer PLN1, a second source / drain conductive layer SD2, and a second planarization layer PLN2.

[0177] Based on this, refer to Figure 4 and Figure 5 The semiconductor channel 31 of the transistor may be located, for example, in the semiconductor layer ACT. The gate line GL, the gate 34 of the transistor, and the first plate of the capacitors (first capacitor C1 and second capacitor C2) may be located, for example, in the first gate conductive layer GT1. The second plate of the capacitors (first capacitor C1 and second capacitor C2), the first initialization signal line VL1, and the second initialization signal line may be located, for example, in the second gate conductive layer GT2. The source 32, drain 33, first power supply line VDL, and constant voltage signal line VCL of the transistor may be located, for example, in the first source-drain conductive layer SD1. The data line DL may be located, for example, in the second source-drain conductive layer SD2.

[0178] In some embodiments, such as Figure 5 As shown, the display panel 100 also includes a pixel defining layer (PDL), which has multiple openings, and a light-emitting device 10 is located in one of the openings.

[0179] In some embodiments, such as Figure 5 As shown, the display panel 100 also includes a spacer PS, which can be disposed between the pixel defining layer PDL and the first electrode 11 of the light-emitting device 10 to support the mask in the process, so that the gap between the mask and the pixel defining layer PDL is uniform.

[0180] In some embodiments, see Figure 4 The display panel 100 also has a peripheral area B, which is disposed on at least one side of the display area A. Figure 4 The diagram illustrates the arrangement of the surrounding area B around the display area A.

[0181] like Figure 4 As shown, the peripheral area B includes a first border area B1, a second border area B2, a third border area B3, and a fourth border area B4. Along the first direction X, the first border area B1 and the second border area B2 are located on opposite sides of the display area A. Along the second direction Y, the third border area B3 and the fourth border area B4 are located on the other opposite sides of the display area A.

[0182] The peripheral area B is a region where no image is displayed, and it is configured to set the gate drive circuit 130 and the source drive circuit 140, etc.

[0183] In some embodiments, see Figure 9B and 10 The gate driving circuit 130 includes a first gate driving circuit 131, which includes a plurality of cascaded first shift registers RS1. Each first shift register RS1 includes a first signal output terminal, and the first signal output terminal of each first shift register RS1 is connected to the first scan signal terminal GATE1 and / or the reset signal terminal RESET of at least one row of pixel circuit 20.

[0184] For example, such as Figure 9B and 10 As shown, multiple pixel circuits 20 are arranged in M ​​rows and N columns. Each row includes N pixel circuits 20 arranged along the first direction X, and each column includes M pixel circuits 20 arranged along the second direction Y, where M > 1, N > 1, and M and N are both integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20. Figure 10 The following diagram uses a 2480-row pixel circuit 20 as an example.

[0185] The first gate drive circuit 131 includes M+Q cascaded first shift registers RS1, from the first stage first shift register RS1 to the last stage first shift register RS1, and the M+Q first shift registers RS1 are respectively the 1st to the M+Qth first shift registers RS1. Figure 10 The example shown is Q equal to 8.

[0186] Based on this, the first scan signal terminal GATE1 of the P-th row pixel circuit 20 is connected to the first signal output terminal of the P+Q-th first shift register RS1. The reset signal terminal RESET of the P-th row pixel circuit 20 is connected to the first signal output terminal of the P-th first shift register RS1. Furthermore, P≤M, Q>0, and both P and Q are integers.

[0187] In this configuration, the first gate driving circuit 131 can provide the first scan signal and the reset signal to the first scan signal terminal GATE1 and the reset signal terminal RESET of all pixel circuits 20, respectively. That is, the first scan signal terminal GATE1 and the reset signal terminal RESET of one pixel circuit 20 can share a single gate driving circuit 130, which is beneficial to the display device 1000 (see [link]). Figure 1 The narrow bezel design.

[0188] In some examples, such as Figure 10As shown, along the first direction X, the first gate driving circuit 131 is disposed in the display area A (see Figure 131). Figure 4 On one side of the display area A (see) Figure 4 The pixel circuits 20 in each row are driven sequentially on one side, i.e., driven on one side.

[0189] In other examples, such as Figure 11 As shown, along the first direction X, two first gate driving circuits 131 are disposed in the display area A (see Figure 1). Figure 4 On opposite sides of the display area A (see [reference]), and through two first gate drive circuits 131, simultaneously from the display area A (see [reference]). Figure 4 The pixel circuits 20 in each row are driven sequentially from both sides of the opposite side, i.e., dual-side driving.

[0190] In other embodiments, see Figure 12 The gate driving circuit 130 includes a second gate driving circuit 132 and a third gate driving circuit 133.

[0191] Among them, such as Figure 9B and Figure 12 As shown, the second gate drive circuit 132 includes a plurality of cascaded second shift registers RS2, each second shift register RS2 includes a second signal output terminal, and the second signal output terminal of each second shift register RS2 is connected to the first scan signal terminal GATE1 of at least one row of pixel circuits 20.

[0192] For example, such as Figure 12 As shown, multiple pixel circuits 20 are arranged in M ​​rows and N columns. Each row includes N pixel circuits 20 arranged along the first direction X, and each column includes M pixel circuits 20 arranged along the second direction Y, where M > 1, N > 1, and M and N are both integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20. Figure 12 The following diagram uses a 2480-row pixel circuit 20 as an example.

[0193] The second gate drive circuit 132 includes M cascaded second shift registers RS2, from the first-stage second shift register RS2 to the last-stage second shift register RS2, with the M second shift registers RS2 being the first to the Mth second shift registers RS2 respectively. Each second shift register RS2 includes a second signal output terminal.

[0194] Based on this, the first scanning signal terminal GATE1 of the P-th row pixel circuit 20 is connected to the second signal output terminal of the P-th second shift register RS2, where P≤M and P is an integer.

[0195] In addition, such as Figure 9B and Figure 12 As shown, the third gate drive circuit 133 includes multiple cascaded third shift registers RS3, each third shift register RS3 includes a third signal output terminal, and the third signal output terminal of each third shift register RS3 is connected to the reset signal terminal RESET of at least one row of pixel circuits 20.

[0196] For example, such as Figure 12 As shown, multiple pixel circuits 20 are arranged in M ​​rows and N columns. Each row includes N pixel circuits 20 arranged along the first direction X, and each column includes M pixel circuits 20 arranged along the second direction Y, where M > 1, N > 1, and M and N are both integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20. Figure 12 The following diagram uses a 2480-row pixel circuit 20 as an example.

[0197] The third gate drive circuit 133 includes M cascaded third shift registers RS3, from the first-stage third shift register RS3 to the last-stage third shift register RS3, with the M third shift registers RS3 being the 1st to the Mth third shift registers RS3 respectively. Each third shift register RS3 includes a third signal output terminal.

[0198] Based on this, the RESET signal terminal of the P-th row pixel circuit is connected to the third signal output terminal of the P-th third shift register RS3, where P≤M and P is an integer.

[0199] In this configuration, the second gate driving circuit 132 can provide a first scan signal to the first scan signal terminal GATE1 of all pixel circuits 20, and the third gate driving circuit 133 can provide a reset signal to the reset signal terminal RESET of all pixel circuits 20. In this configuration, the ratio of the duration of the first scan signal received by the first scan signal terminal GATE1 of the pixel circuit 20 to the duration of the reset signal received by the reset signal terminal RESET can be arbitrarily adjusted, which is beneficial for improving image retention, reducing flicker, and thus improving display quality.

[0200] In some examples, such as Figure 12 As shown, along the first direction X, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively disposed in the display area A (see...). Figure 4 On opposite sides of the first frame region B1, namely, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively disposed in the first frame region B1 (see Figure 4 ) and the second border area B2 (see Figure 4 ), and from display area A (see Figure 4The single-sided, row-by-row sequential driving of the pixel circuits 20 is beneficial for reducing the size of the display device 1000 (see [link]). Figure 1 Reduce the bezels to increase the screen-to-body ratio.

[0201] In some embodiments, see Figures 10-12 The gate drive circuit 130 also includes a fourth gate drive circuit 134.

[0202] Among them, such as Figure 9B and Figure 10 As shown, the fourth gate drive circuit 134 includes multiple cascaded fourth shift registers RS4, each fourth shift register RS4 including a fourth signal output terminal, and the fourth signal output terminal of each fourth shift register RS4 is connected to the enable signal terminal EM of at least one row of pixel circuits 20.

[0203] For example, such as Figure 10 As shown, multiple pixel circuits 20 are arranged in M ​​rows and N columns. Each row includes N pixel circuits 20 arranged along the first direction X, and each column includes M pixel circuits 20 arranged along the second direction Y, where M > 1, N > 1, and M and N are both integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20. Figure 10 The following diagram uses a 2480-row pixel circuit 20 as an example.

[0204] The fourth gate drive circuit 134 includes M cascaded fourth shift registers RS4, from the first-stage fourth shift register RS4 to the last-stage fourth shift register RS4, with the M fourth shift registers RS4 being the 1st to the Mth fourth shift registers RS4 respectively. Each of the fourth shift registers RS4 includes a fourth signal output terminal.

[0205] Based on this, the enable signal terminal EM of the P-th row pixel circuit 20 is connected to the fourth signal output terminal of the P-th fourth shift register RS4 of the fourth gate drive circuit 134, where P≤M and P is an integer.

[0206] like Figure 10 As shown, when the display panel 100 includes a first gate driving circuit 131, the first gate driving circuit 131 and the fourth gate driving circuit 134 are respectively disposed in the first frame area B1 (see...). Figure 4 ) and the second border area B2 (see Figure 4 This is beneficial to the display device 1000 (see...). Figure 1 The narrow bezel design.

[0207] like Figure 11As shown, when the display panel 100 includes two first gate driving circuits 131, and the two first gate driving circuits 131 are respectively disposed in the first border area B1 and the second border area B2, the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 can be respectively disposed in the first border area B1 and the second border area B2 to form cross-drive, so as to make full use of the area of ​​the first border area B1 and the second border area B2 and improve the uniformity of the screen display.

[0208] like Figure 12 As shown, when the display panel 100 includes a second gate driving circuit 132 and a third gate driving circuit 133, the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 are respectively set in the first border area B1 and the second border area B2 to form a cross drive, so as to make full use of the area of ​​the first border area B1 and the second border area B2 and improve the uniformity of the screen display.

[0209] In some embodiments, see Figures 10-12 The gate drive circuit 130 also includes a fifth gate drive circuit 135.

[0210] Among them, such as Figure 9B and Figure 12 As shown, the fifth gate drive circuit 135 includes multiple cascaded fifth shift registers RS5, each fifth shift register RS5 includes a fifth signal output terminal, and the fifth signal output terminal of each fifth shift register RS5 is connected to the second scan signal terminal GATE2 of at least one row of pixel circuits 20.

[0211] For example, such as Figure 12 As shown, multiple pixel circuits 20 are arranged in M ​​rows and N columns. Each row includes N pixel circuits 20 arranged along the first direction X, and each column includes M pixel circuits 20 arranged along the second direction Y, where M > 1, N > 1, and M and N are both integers. Furthermore, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20. Figure 12 The following diagram uses a 2480-row pixel circuit 20 as an example.

[0212] The fifth gate drive circuit 135 includes M cascaded fifth shift registers RS5, from the first-stage fifth shift register RS5 to the last-stage fifth shift register RS5, with the M fifth shift registers RS5 being the 1st to the Mth fifth shift registers RS5 respectively. Each fifth shift register RS5 includes a fifth signal output terminal.

[0213] Based on this, the enable signal terminal EM of the P-th row pixel circuit 20 is connected to the fourth signal output terminal of the P-th fifth shift register RS5 of the fourth gate drive circuit 134, where P≤M and P is an integer.

[0214] In some examples, such as Figures 10-12 As shown, the display panel 100 includes two fifth gate driving circuits 135, which are respectively disposed in the first frame area B1 (see...). Figure 4 ) and the second border area B2 (see Figure 4 That is, the second scan signal terminal GATE2 of the P-th row pixel circuit 20 is connected to the fifth signal output terminal of the P-th fifth shift register RS5 of the two fifth gate drive circuits 135, forming a dual-sided drive, where P≤M and P is an integer. This configuration reduces the impact of voltage drop on the second scan signal, thereby improving the brightness uniformity of the displayed image.

[0215] Some embodiments of this disclosure also provide a driving method for a pixel circuit 20, used to drive the pixel circuit 20 as described in any of the above embodiments.

[0216] Among them, such as Figure 13 As shown, a display frame F includes a refresh frame F1, and the refresh frame F1 includes a first reset phase P11 and a second reset phase P12.

[0217] In the first reset phase P11, the reset sub-circuit 23, in response to the working voltage of the reset signal at the reset signal terminal RESET, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 to reset the first node N1. Furthermore, the storage sub-circuit 24 stores the voltage of the second node N2 after the end of the previous frame, so that the second node N2 can form a relatively stable potential (the voltage of the second voltage signal).

[0218] In other words, such as Figure 9B As shown, the fifth transistor T5 is turned on under the control of the reset signal received at the RESET terminal, transmitting the first initialization signal received at the VINIT1 terminal to the first node N1. Furthermore, the second storage capacitor C2 stores the voltage of the second node N2 after the end of the previous frame.

[0219] At this time, during the first reset phase P11, a large bias voltage can be formed between the second node N2 and the first node N1, so that a stable and large bias voltage is generated between the source terminal and the control terminal of the eighth transistor T8, improving the hysteresis characteristics of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering in the display screen.

[0220] It should be noted that the difference between the start time of the first reset phase P11 and the start time of the frame F in which the first reset phase P11 is located is greater than or equal to two line scan periods H, so as to avoid the rising and falling edges of the signals of the first reset phase P11 interleaving at the end of the previous frame F, which would affect the first reset phase P11.

[0221] In the second reset phase P12, the reset sub-circuit 23, in response to the operating voltage of the reset signal at the reset signal terminal RESET, transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1. The compensation sub-circuit 22, in response to the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmits the voltage of the first node N1 to the third node N3. Furthermore, under the control of the voltage of the first node N1, the drive sub-circuit 21 transmits the voltage of the third node N3 to the second node N2, thereby resetting the third node N3 and the second node N2 sequentially.

[0222] In other words, such as Figure 9B As shown, the first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the first scan signal received at the first scan signal terminal GATE1, transmitting the voltage of the first node N1 to the third node N3. Furthermore, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, transmitting the voltage of the third node N3 to the second node N2.

[0223] At this time, in the second reset phase P12, the second node N2 and the third node N3 can be reset to reduce the impact of the residual voltage of the previous frame on the data writing of this frame, thereby improving the brightness uniformity of the display screen.

[0224] In some embodiments, such as Figure 13 As shown, refresh frame F1 also includes a first data writing phase P21 and a second data writing phase P22.

[0225] In the first data writing phase P21, the data writing sub-circuit 27, responding to the first operating voltage of the second scan signal received at the second scan signal terminal GATE2, transmits the data signal received at the data signal terminal DATA to the second node N2 and writes it to the storage sub-circuit 24. Under the control of the voltage of the first node N1, the driving sub-circuit 21 transmits the voltage of the second node N2 to the third node N3. The compensation sub-circuit 22, responding to the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmits the voltage of the third node N3 to the first node N1.

[0226] In other words, such as Figure 9BAs shown, the seventh transistor T7 is turned on under the control of the first operating voltage of the second scan signal received at the second scan signal terminal GATE2, and transmits the data signal received at the data signal terminal DATA to the second node N2. The second storage capacitor C2 stores the voltage of the data signal written by the second node N2.

[0227] Furthermore, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, transmitting the voltage of the third node N3 to the second node N2. The first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmitting the voltage of the third node N3 to the first node N1.

[0228] At this time, during the first data writing stage P21, data signals can be written to the first node N1 and the second storage capacitor C2.

[0229] During the second data writing phase P22, the storage sub-circuit 24 discharges to transmit the stored data signal to the second node N2. Under the control of the voltage at the first node N1, the drive sub-circuit 21 transmits the voltage of the second node N2 to the third node N3. The compensation sub-circuit 22, responding to the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmits the voltage of the third node N3 to the first node N1.

[0230] In other words, such as Figure 9B As shown, the second storage capacitor C2 discharges, transmitting the data signal written in the first data writing stage P21 to the second node N2. The eighth transistor T8 is turned on under the control of the voltage of the first node N1, transmitting the voltage of the third node N3 to the second node N2. The first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, transmitting the voltage of the third node N3 to the first node N1.

[0231] At this time, during the second data writing stage P22, the second storage capacitor C2 can continuously discharge to continuously write the data signal to the first node N1, increasing the data writing time, which is beneficial to improving the brightness uniformity of the display screen and enhancing the display effect.

[0232] In some embodiments, such as Figure 9B and Figure 13 As shown, the compensation sub-circuit 22 includes P-type transistors. Furthermore, the second reset phase P12 includes at least three row scan periods H.

[0233] During the second reset phase P12, the voltage of the first row scan period H after the first scan signal is activated is greater than the voltage of the second row scan period H after the first scan signal is activated. That is, the stability of the first scan signal H output during the even-numbered row scan period H is greater than the stability of the first scan signal H during the odd-numbered row scan period H.

[0234] For example, the first scan signal of the first signal output terminal of the first shift register RS1 is output by the clock signal line. During the first row scan period H of the second reset phase P12, the first signal output terminal outputs a high-level signal of the clock signal line. During the second row scan period H of the second reset phase P12, the first signal output terminal outputs a low-level signal of the clock signal line.

[0235] Furthermore, during the other odd-numbered row scan periods H in the second reset phase P12, the first signal output is in a floating state. During the other even-numbered row scan periods H in the second reset phase P12, the first signal output is a low-level signal on the output clock signal line. At this time, the stability of the first scan signal output during the even-numbered row scan periods H is greater than the stability during the odd-numbered row scan periods H.

[0236] Based on this, the first data writing stage P21 is located after the second reset stage P12, and coincides with the 2Nth row scan period H after the start time of the second reset stage P12, where N≥2 and N is an integer.

[0237] In this case, the first data writing phase P21 is performed during the even-numbered row scanning period H when the stability of the first scan signal is relatively high. This can improve the accuracy of data signal writing, thereby improving the brightness uniformity of the displayed image. In particular, when the display panel 100 includes the first gate driving circuit 131, the risk of the last few rows of sub-pixels P being brighter than other sub-pixels P can be reduced, thus improving the brightness uniformity of the displayed image.

[0238] For example, such as Figure 13 As shown, the second reset phase P12 includes three row scan periods H. At this time, the sixth row scan period H after the start time of the first data writing phase P21 and the second reset phase P12 coincides, that is, it is performed during the sixth row scan period H when the stability of the first scan signal is relatively high.

[0239] Furthermore, the falling edge of the second scan signal and the rising edge of the reset signal can be staggered by two line scan periods H, avoiding the impact of the second reset phase P12 on data writing, and the brightness uniformity of the displayed screen is relatively high.

[0240] In some embodiments, such as Figure 13 As shown, the refresh frame F also includes the first emission stage P3.

[0241] In the first light-emitting stage P3, the light-emitting control sub-circuit 26, in response to the operating voltage of the enable signal received at the enable signal terminal EM, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The driving sub-circuit 21 generates a driving current signal based on the voltage of the first node N1 and the voltage of the second node N2.

[0242] Furthermore, the light-emitting control sub-circuit 26, in response to the operating voltage of the enable signal received at the enable signal terminal EM, transmits the drive current signal to the light-emitting device 10. The leakage prevention sub-circuit 25, in response to the operating voltage of the control signal received at the control signal terminal K, transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4.

[0243] In other words, such as Figure 9B As shown, the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The eighth transistor T8 generates a drive current signal based on the voltage of the first node N1 and the voltage of the second node N2.

[0244] Furthermore, both the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal received at the enable signal terminal EM, transmitting the drive current signal to the light-emitting device 10 to drive the light-emitting device 10 to emit light. The second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, transmitting the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, thereby reducing the leakage current of the first node N1 and improving the brightness uniformity of the display screen.

[0245] Based on this, such as Figure 13 As shown, the refresh frame F may also include a third reset phase P13, which is located between the second data writing phase P22 and the first light emission phase P3.

[0246] In the third reset phase P13, the data writing sub-circuit 27 responds to the second working voltage of the second scan signal received at the second scan signal terminal GATE2 and transmits the data refresh signal received at the data signal terminal DATA to the second node N2.

[0247] In other words, such as Figure 9B As shown, the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2, and transmits the data refresh signal received at the data signal terminal DATA to the second node N2. In this way, the data signals received by the pixel circuits 20 of other rows can be reused to reset the second node N2 and the fourth node N4 again, so as to improve the brightness uniformity of the display screen. There is no need to change the circuit structure, and the structure is simple.

[0248] In some examples, see Figure 13 , Figure 14 and Figure 15 The difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is greater than or equal to one row scan period H, in order to reduce the risk of the rising and falling edges of each signal in the third reset phase P13 and the second data writing phase P2 interleaving, thereby affecting data writing or reset.

[0249] For example, such as Figure 13 As shown, the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is 2 row scan periods H, in order to avoid the rising and falling edges of the signals in the third reset phase P13 and the second data writing phase P2 from interleaving, which would affect the data writing or reset.

[0250] In some examples, see Figure 13 , Figure 14 and Figure 15 The difference between the cutoff time of the third reset phase P13 and the start time of the first light emission phase P3 is greater than or equal to one line scan period H, so as to avoid the rising and falling edges of each signal in the third reset phase P13 and the first light emission phase P3 interleaving, which would affect data writing or light emission.

[0251] For example, such as Figure 13 As shown, the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is one row scan period H, in order to avoid the rising and falling edges of the signals in the third reset phase P13 and the second data writing phase P2 from interleaving, which would affect the data writing or reset.

[0252] In some embodiments, see Figure 9B and Figure 13 The pixel circuit 20 has a first refresh frequency and a second refresh frequency, the second refresh frequency being less than the first refresh frequency. At the first refresh frequency, a display frame F includes a refresh frame F1. At the second refresh frequency, a display frame F includes a refresh frame F1 and at least one hold frame F2.

[0253] At this time, the display panel 100 can, for example, display at high and low frequencies of 30Hz, 40Hz, 60Hz and 120Hz, or at high and low frequencies of 40Hz, 55Hz, 82Hz and 165Hz, and the embodiments disclosed herein are not limited thereto.

[0254] Among them, such as Figure 13 As shown, the holding frame F2 includes a black insertion phase P4, a fourth reset phase P5, and a second light emission phase P6.

[0255] During the black insertion phase P4, the light emission control sub-circuit 26 is configured to control the circuit transmitting the drive current signal to cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal EM.

[0256] In other words, such as Figure 9B As shown, the third transistor T3 and the fourth transistor T4 are turned off under the control of the enable signal received at the enable signal terminal EM, thereby controlling the circuit that transmits the drive current signal to turn off.

[0257] At this time, after the first light-emitting stage P3 of refresh frame F1, a black screen can be inserted to provide a rest time for the light-emitting device 10, avoid abnormal light emission of the light-emitting device 10 due to prolonged bias voltage, improve the image display effect and extend the service life of the light-emitting device 10.

[0258] In the fourth reset phase P5, the data writing sub-circuit 27 responds to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2 and transmits the data holding signal received at the data signal terminal DATA to the second node N2.

[0259] It should be noted that the voltage range of the data hold signal is 0V to V. GMP Among them, V GMP This refers to the black-state voltage of sub-pixel P. The black-state voltage is the voltage at which the target grayscale of a sub-pixel P is 0. When the target grayscale of a sub-pixel P is 0, the black-state voltage is directly used as the driving voltage for that sub-pixel P, causing the corresponding sub-pixel to not emit light. For example, the voltage range of the data hold signal is 0V to 7V, such as any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V, and 7V. Here, the specific voltage value of the data hold signal can be determined experimentally, using the voltage value with the lower flicker value as the actual voltage value of the data hold signal. This embodiment of the present disclosure does not impose a specific limitation on this.

[0260] In other words, such as Figure 9B As shown, the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2, and transmits the data holding signal received at the data signal terminal DATA to the second node N2 to reset the second node N2.

[0261] In the second light-emitting stage P6, the light-emitting control sub-circuit 26, in response to the operating voltage of the enable signal received at the enable signal terminal EM, transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The driving sub-circuit 21 generates a driving current signal based on the voltage of the first node N1 and the voltage of the second node N2.

[0262] Furthermore, the light-emitting control sub-circuit 26, in response to the operating voltage of the enable signal received at the enable signal terminal EM, transmits the drive current signal to the light-emitting device 10. The leakage prevention sub-circuit 22, in response to the operating voltage of the control signal received at the control signal terminal K, transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4.

[0263] In other words, such as Figure 9B As shown, the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2. The eighth transistor T8 generates a drive current signal based on the voltage of the first node N1 and the voltage of the second node N2.

[0264] Furthermore, both the third transistor T3 and the fourth transistor T4 are turned on under the control of the enable signal received at the enable signal terminal EM, transmitting the drive current signal to the light-emitting device 10 to drive the light-emitting device 10 to emit light. The second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, transmitting the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, thereby reducing the leakage current of the first node N1 and improving the brightness uniformity of the display screen.

[0265] In some examples, see Figure 13 , Figure 14 and Figure 15 The difference between the cutoff time of the fourth reset phase P5 and the start time of the second light emission phase P6 is greater than or equal to one line scan period H, so as to avoid the rising and falling edges of each signal in the fourth reset phase P5 and the second light emission phase P6 interleaving, which would affect the reset or light emission.

[0266] For example, such as Figure 13 As shown, the difference between the cutoff time of the fourth reset stage P5 and the start time of the second light emission stage P6 is one line scan period H, so as to avoid the rising and falling edges of the signals in the fourth reset stage P5 and the second light emission stage P6 from interleaving, which would affect the reset or light emission.

[0267] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises: a driving sub-circuit coupled with a first node, a second node and a third node; the driving sub-circuit is configured to control conduction and cutoff of a circuit between the second node and the third node under control of a voltage of the first node; a compensation sub-circuit coupled with a first scan signal terminal, the first node and the third node; the compensation sub-circuit is configured to control conduction and cutoff of a circuit between the first node and the third node in response to a first scan signal received at the first scan signal terminal; a reset sub-circuit coupled with a first initialization signal terminal, a reset signal terminal and the first node; the reset sub-circuit is configured to transmit a first initialization signal received at the first initialization signal terminal to the first node in response to a working voltage of a reset signal received at the reset signal terminal; a storage sub-circuit coupled with a first voltage signal terminal, the first node and the second node; the storage sub-circuit is configured to store voltages of the first node and the second node; a starting time of the working voltage of the reset signal is before a starting time of a working voltage of the first scan signal; and a time interval between the starting time of the working voltage of the reset signal and the starting time of the working voltage of the first scan signal is greater than or equal to 3 row scanning periods; and / or; a cutoff time of the working voltage of the reset signal is after the starting time of the working voltage of the first scan signal; and a time interval between the cutoff time of the working voltage of the reset signal and the starting time of the working voltage of the first scan signal is greater than or equal to 2 row scanning periods.

2. The pixel circuit of claim 1, wherein, The storage sub-circuit comprises: a first storage capacitor, a first plate of the first storage capacitor being connected with the first voltage signal terminal, and a second plate of the first storage capacitor being connected with the first node; a second storage capacitor, a first plate of the second storage capacitor being connected with the first voltage signal terminal, and a second plate of the second storage capacitor being connected with the second node.

3. The pixel circuit of claim 1, wherein, The compensation sub-circuit comprises: a first sub-transistor and a second sub-transistor connected in series, a first end of the first sub-transistor being connected with the first node, a second end of the first sub-transistor and / or a first end of the second sub-transistor being connected with a fourth node, a second end of the second sub-transistor being connected with the third node, and control electrodes of the first sub-transistor and the second sub-transistor being connected with the first scan signal terminal; The pixel circuit further comprises: a leakage prevention sub-circuit coupled with a control signal terminal, a constant voltage terminal and the fourth node; the leakage prevention sub-circuit is configured to transmit a constant voltage signal received at the constant voltage terminal to the fourth node in response to a working voltage of a control signal received at the control signal terminal.

4. The pixel circuit of claim 3, wherein, Further comprising: a light emission control sub-circuit coupled with the first voltage signal terminal, an enable signal terminal, the second node, the third node and a fifth node; the fifth node being connected with an anode of a light emitting device; The light-emitting control sub-circuit is configured to control the conduction and cutoff of the circuit between the first voltage signal terminal and the second node, and control the conduction and cutoff of the circuit between the third node and the fifth node in response to the enable signal received at the enable signal terminal; and the signals received at the enable signal terminal and the control signal terminal are the same.

5. The pixel circuit according to any one of claims 1 to 4, characterized by, Further comprising: a data writing sub-circuit coupled with the data signal terminal, the second scan signal terminal and the second node; the data writing sub-circuit is configured to transmit the data signal received at the data signal terminal to the second node in response to the first working voltage of the second scan signal received at the second scan signal terminal; and transmit the data refresh signal received at the data signal terminal to the second node in response to the second working voltage of the second scan signal received at the second scan signal terminal; the data refresh signal is the data signal received by other row pixel circuits. The cutoff time of the first working voltage of the second scan signal is before the cutoff time of the working voltage of the first scan signal; 6. The pixel circuit of claim 5, wherein, and the time interval between the cutoff time of the first working voltage of the second scan signal and the cutoff time of the working voltage of the first scan signal is greater than or equal to one row scanning period; the row scanning period is the duration of one working voltage of the second scan signal. The start time of the first working voltage of the second scan signal is after the cutoff time of the working voltage of the reset signal; 7. The pixel circuit of claim 5, wherein, and the time interval between the start time of the first working voltage of the second scan signal and the cutoff time of the working voltage of the reset signal is greater than or equal to one row scanning period; the row scanning period is the duration of one working voltage of the second scan signal. The compensation sub-circuit comprises a P-type transistor; 8. The pixel circuit of claim 5, wherein, The duration of the working voltage of the first scan signal is greater than or equal to 4 row scanning periods; the voltage of the first row scanning period after the working of the first scan signal is greater than the voltage of the second row scanning period after the working of the first scan signal; the row scanning period is the duration of one working voltage of the second scan signal; The time of the first working voltage of the second scan signal coincides with the 2Nth row scanning period of the working voltage of the first scan signal, N≥2, and N is an integer. The start and end time of the second working voltage of the second scan signal is between the cutoff time of the working voltage of the first scan signal and the start time of the working voltage of the enable signal; 9. The pixel circuit of claim 5, wherein, and the time interval between the start time of the second working voltage of the second scan signal and the cutoff time of the working voltage of the first scan signal is greater than or equal to one row scanning period; the time interval between the cutoff time of the second working voltage of the second scan signal and the start time of the working voltage of the enable signal is greater than or equal to one row scanning period; the row scanning period is the duration of one working voltage of the second scan signal. ​ 10. The pixel circuit of claim 5, wherein, The data writing sub-circuit is further configured to transmit the data holding signal received at the data signal end to the second node in response to a third operating voltage of a second scan signal received at the second scan signal end.

11. The pixel circuit of claim 5, wherein, The reset sub-circuit is further coupled with a second initialization signal end, a third scan signal end and a fifth node; and the reset sub-circuit is further configured to transmit a second initialization signal received at the second initialization signal end to the fifth node under the control of an operating voltage of a third scan signal received at the third scan signal end.

12. A driving method of a pixel circuit, characterized by, The pixel circuit is used for driving, and one display frame includes one refresh frame, and the refresh frame includes a first reset phase and a second reset phase. In the first reset phase, the reset sub-circuit transmits a first initialization signal received at the first initialization signal end to the first node in response to an operating voltage of a reset signal of the reset signal end; and the storage sub-circuit stores a voltage of the second node after the end of a previous frame. In the second reset phase, the reset sub-circuit transmits the first initialization signal received at the first initialization signal end to the first node in response to the operating voltage of the reset signal of the reset signal end. The compensation sub-circuit transmits the voltage of the first node to the third node in response to an operating voltage of a first scan signal received at the first scan signal end. The driving sub-circuit transmits the voltage of the second node to the third node under the control of the voltage of the first node.

13. The driving method according to claim 12, wherein The pixel circuit further includes a data writing sub-circuit, and the refresh frame further includes a first data writing phase and a second data writing phase. In the first data writing phase, the data writing sub-circuit transmits a data signal received at the data signal end to the second node and writes the data signal into the storage sub-circuit in response to a first operating voltage of a second scan signal received at the second scan signal end. The driving sub-circuit transmits the voltage of the second node to the third node under the control of the voltage of the first node. The compensation sub-circuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal end. In the second data writing phase, the storage sub-circuit discharges and transmits the stored data signal to the second node. The driving sub-circuit transmits the voltage of the second node to the third node under the control of the voltage of the first node; and the compensation sub-circuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal end.

14. The driving method according to claim 13, wherein The compensation sub-circuit includes a transistor which is a P-type transistor; and the second reset phase includes at least three row scanning periods. In the second reset phase, a voltage of a first row scanning period after the first scan signal works is greater than a voltage of a second row scanning period after the first scan signal works. The first data writing phase is located after the second reset phase and coincides with a 2Nth row scanning period after the start time of the second reset phase, N≥2, and N is an integer.

15. The driving method according to claim 13, wherein The pixel circuit comprises a data writing sub-circuit, and the refresh frame further comprises a third reset stage and a first light emitting stage, the third reset stage being located between the second data writing stage and the first light emitting stage. In the third reset stage, the data writing sub-circuit transmits a data refresh signal received at the data signal end to the second node in response to a second working voltage of a second scan signal received at the second scan signal end.

16. The driving method according to claim 15, wherein A difference between a start time of the third reset stage and an end time of the second data writing stage is greater than or equal to a row scanning period; and / or, a difference between an end time of the third reset stage and a start time of the first light emitting stage is greater than or equal to a row scanning period.

17. The driving method according to any one of claims 12 to 16, wherein The pixel circuit comprises a data writing sub-circuit, a leakage prevention sub-circuit and a light emitting control sub-circuit; the pixel circuit has a first refresh frequency and a second refresh frequency, the second refresh frequency being less than the first refresh frequency; at the first refresh frequency, one display frame comprises one refresh frame; at the second refresh frequency, one display frame comprises one refresh frame and at least one holding frame; the holding frame comprises a black insertion stage, a fourth reset stage and a second light emitting stage; In the black insertion stage, the light emitting control sub-circuit is configured to control a circuit for transmitting a driving current signal to be turned off in response to a non-working voltage of an enabling signal received at the enabling signal end; In the fourth reset stage, the data writing sub-circuit transmits a data holding signal received at the data signal end to the second node in response to a third working voltage of a second scan signal received at the second scan signal end; In the second light emitting stage, the light emitting control sub-circuit transmits a first voltage signal received at the first voltage signal end to the second node in response to a working voltage of an enabling signal received at the enabling signal end; The driving sub-circuit generates a driving current signal according to a voltage of the first node and a voltage of the second node; The light emitting control sub-circuit transmits the driving current signal to a light emitting device in response to a working voltage of an enabling signal received at the enabling signal end; and the leakage prevention sub-circuit transmits a constant voltage signal received at a constant voltage end to a fourth node in response to a working voltage of a control signal received at a control signal end.

18. The driving method according to claim 17, wherein An end time of the fourth reset stage is greater than or equal to a row scanning period from a start time of the second light emitting stage.

19. A display panel, characterized by Comprise: A plurality of pixel circuits as claimed in any one of claims 1-11, the plurality of pixel circuits being arranged as M rows and N columns, each row comprising N pixel circuits arranged along a first direction, and each column comprising M pixel circuits arranged along a second direction, M>1, N>1, and M and N are integers.

20. The display panel of claim 19, wherein, From the first row of pixel circuits to the last row of pixel circuits along the second direction, the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits. The display panel further comprises: The first gate drive circuit comprises M+Q first shift registers connected in cascade, and the first shift registers from the first stage to the last stage are the 1st to the M+Qth first shift registers respectively. The first scan signal end of the Pth row of pixel circuits is connected with the first signal output end of the P+Qth first shift register, and the reset signal end of the Pth row of pixel circuits is connected with the first signal output end of the Pth first shift register, wherein P≤M, Q>0, and P and Q are integers.

21. The display panel of claim 19, wherein, From the first row of pixel circuits to the last row of pixel circuits along the second direction, the M rows of pixel circuits are the 1st to the Mth rows of pixel circuits respectively. The display panel further comprises: The second gate drive circuit comprises M second shift registers connected in cascade, and the second shift registers from the first stage to the last stage are the 1st to the Mth second shift registers respectively. The third gate drive circuit comprises M third shift registers connected in cascade, and the third shift registers from the first stage to the last stage are the 1st to the Mth third shift registers respectively.

22. A display device comprising: The display panel comprises: The display panel as claimed in any one of claims 19-21.

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