Memory device and memory system including plurality of switching transistors in string

Abstract

The invention relates to a memory device and a memory system including a plurality of switching transistors in a string. The memory device includes a cell array and a control circuit. The cell array includes a plurality of memory cells and a plurality of switching transistors. The control circuit is configured to perform a check and recovery operation with respect to an operation state of the plurality of switching transistors during an operation margin set for the plurality of data input / output operations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the benefit of priority to Korean Patent Application No. 10-2023-0085219, filed on June 30, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of the present disclosure described herein relate to a memory device, and more particularly, to a plurality of switching transistors coupled to a plurality of memory cells included in the memory device. Background Art

[0004] A data processing system including a memory system or a data storage device can store more data in the data storage device and store data in the data storage device faster. Memory systems have been developed for outputting data stored in the data storage device faster. The data storage device can include non-volatile memory cells and / or volatile memory cells for storing data. Summary of the invention

[0005] Embodiments of the present disclosure may provide a memory device and a memory system including the memory device, which may improve data input / output performance by performing inspection and recovery operations regarding degradation of operation states of a plurality of switching transistors without affecting data input / output operations.

[0006] In addition, embodiments of the present disclosure can reduce errors in data input / output operations performed in a memory device through inspection and recovery operations regarding degradation of operating states of multiple switching transistors, thereby improving operational reliability of the memory device and a memory system including the memory device.

[0007] An embodiment of the present disclosure may provide a memory device including a cell array and a control circuit, the cell array including a plurality of memory cells and a plurality of switching transistors, the control circuit being configured to perform a check and recovery operation on an operating state of the plurality of switching transistors during an operating margin set for a plurality of data input / output operations.

[0008] The multiple switching transistors may include: at least one drain selection transistor configured to control the connection between the multiple memory cells and the bit line; at least one source selection transistor configured to control the connection between the multiple memory cells and the common source line; and at least one intermediate switching transistor arranged between the multiple memory cells.

[0009] At least one intermediate switching transistor may be disposed between two vertically stacked portions, each vertically stacked portion including at least some of the plurality of memory cells.

[0010] The plurality of data input / output operations may include one or more erase operations for erasing data remaining in the plurality of memory cells and one or more program operations for programming data in the plurality of memory cells.

[0011] The control circuit may be configured to perform the check operation during an operation margin of the one or more erase operations, and may perform the recovery operation during an operation margin of the one or more program operations.

[0012] The control circuit may be configured to perform the check and recovery operations during an operation margin of the plurality of programming operations.

[0013] The control circuit may be configured to divide the checking and restoring operation into a plurality of unit operations based on positions of the plurality of switching transistors.

[0014] The control circuit may be configured to perform a unit operation for each of the plurality of switch transistors during an operation margin set for each of the plurality of data input / output operations.

[0015] The control circuit may be configured to perform a unit operation on a single switching transistor during an operation margin set for a plurality of data input / output operations.

[0016] The memory device may further include a buffer configured to store position information of a degraded switching transistor among the plurality of switching transistors.

[0017] The control circuit may be configured to generate a switching transistor recovery command including position information based on which one of a plurality of data input / output operations is performed in the cell array.

[0018] The control circuit may be configured to generate a control signal for a check operation when an erase command is input.

[0019] The control circuit may be configured to generate a control signal for a recovery operation when a program command is input.

[0020] In another embodiment, a memory system may include: a memory device including multiple memory cells and multiple switching transistors; and a controller configured to generate a program command for performing a programming operation on the multiple memory cells based on whether a check and recovery operation is performed regarding an operating state of the multiple switching transistors.

[0021] The program command may be one of: a first program command for performing a program operation and a check and recovery operation; and a second program command for performing only a program operation without performing the check and recovery operation.

[0022] The controller may be configured to generate a first program command based on program data to be programmed in a plurality of memory cells of the cell array as part of multi-bit data during a program operation.

[0023] The controller can be configured to: generate an erase command for erasing remaining data in multiple memory cells and for checking the operating states of multiple switching transistors; and generate a programming command for a programming operation and a recovery operation for restoring the operating state of a degraded switching transistor among the multiple switching transistors.

[0024] The multiple switching transistors may include: at least one drain selection transistor configured to control the connection between the multiple memory cells and the bit line; at least one source selection transistor configured to control the connection between the multiple memory cells and the common source line; and at least one intermediate switching transistor arranged between the multiple memory cells.

[0025] In another embodiment, a memory system may include: a memory device including a plurality of memory cells and a plurality of switching transistors; and a controller configured to transmit a plurality of data input / output commands to the memory device, the plurality of data input / output commands being designed for the memory device to perform check and restore operations for checking and restoring operating states of the plurality of switching transistors during a plurality of data input / output operations performed based on the plurality of data input / output commands.

[0026] The plurality of data input / output commands may include a program command for the memory device to perform a program operation for programming data therein and a check and restore operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The description herein refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0028] Figure 1 A memory device according to an embodiment of the present disclosure is shown.

[0029] Figure 2 A memory device according to another embodiment of the present disclosure is shown.

[0030] Figure 3 A memory cell array according to another embodiment of the present disclosure is shown.

[0031] Figure 4A check and recovery operation regarding an operating state of a switching transistor according to another embodiment of the present disclosure is shown.

[0032] Figure 5 A check and restore operation regarding an operation state of a switching transistor during an erase operation according to an embodiment of the present disclosure is shown.

[0033] Figure 6 A check and restore operation regarding an operation state of a switching transistor during a data input / output operation according to an embodiment of the present disclosure is illustrated.

[0034] Figure 7 A finite state machine included in a memory device according to another embodiment of the present disclosure is shown.

[0035] Figure 8 A check and restore operation regarding an operation state of a switching transistor during a program operation according to an embodiment of the present disclosure is illustrated.

[0036] Fig. 9 A memory system according to another embodiment of the present disclosure is shown.

[0037] Fig.10 A memory system according to another embodiment of the present disclosure is shown.

[0038] Fig.11 A first example of a check and restore operation regarding an operation state of a switching transistor during a data input / output operation according to an embodiment of the present disclosure is shown.

[0039] Fig.12 A second example of the checking and restoring operation regarding the operating state of the switching transistor during the data input / output operation according to the embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any one of the disclosed embodiments.

[0041] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc.) are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0042] In this disclosure, the terms "comprising", "including", "includes" and "comprising" are open ended. As used in the appended claims, these terms specify the presence of the recited elements and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including additional components, for example, interface units, circuits, etc.

[0043] In the present disclosure, various units, circuits, or other components may be described or stated as being "configured to" perform one or more tasks. In such contexts, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. In this way, even when a specified block / unit / circuit / component is not currently operating, such as not being turned on or activated, it can be said that the block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuit / components used with "configured to" include hardware, circuits, memories storing program instructions that can be run to implement operations, and the like. In addition, "configured to" may include general structures, such as general circuits, that are manipulated by software and / or firmware (e.g., an FPGA or general processor that runs software to operate in a manner capable of performing the task to be solved). "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to a manufacturing device (e.g., an integrated circuit suitable for implementing or performing one or more tasks).

[0044] As used in this disclosure, the terms "machine", "circuit" or "logic" refer to all of the following: (a) pure hardware circuit implementations, such as implementations in analog and / or digital circuits only, and (b) combinations of circuits and software and / or firmware, such as (if applicable): (i) a combination of processors, or (ii) a portion of a processor / software including a digital signal processor, software and memory that work together to enable a device such as a mobile phone or server to perform various functions, and (c) a circuit that requires software or firmware for operation, such as a microprocessor or a portion of a microprocessor, even if the software or firmware is not actually present. This definition of "machine", "circuit" or "logic" applies to all uses of the term in this application, including in any claims. As a further example, as used in this application, the terms "machine", "circuit" or "logic" also cover implementations of only a processor or multiple processors or portions of a processor and its (or their) accompanying software and / or firmware. The terms "machine", "circuit" or "logic" also cover integrated circuits such as memory devices if applicable to the specific claimed element.

[0045] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding them, and do not imply any type of ordering, such as spatial, temporal, logical, etc. The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. Further, although the terms can be used to identify various elements in this article, these elements are not limited by these terms. These terms are used to distinguish an element from another element with the same or similar name in addition. For example, the first circuit can be distinguished from the second circuit.

[0046] Further, the term "based on" is used to describe one or more factors that influence a determination. The term does not exclude additional factors that may influence the outcome of a determination. That is, a determination may be based solely on those factors or at least in part on those factors. Consider the phrase "determining A based on B." Although in this case, B is a factor that influences the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based solely on B.

[0047] Embodiments will now be described with reference to the drawings, wherein like reference numerals refer to like elements throughout.

[0048] Figure 1 A memory device according to an embodiment of the present disclosure is shown.

[0049] Reference Figure 1 , the memory device 150 may include a cell array 330. The cell array 330 may have a two-dimensional or three-dimensional structure. The cell array 330 may include a plurality of memory cells capable of storing data and a plurality of switch transistors configured to control the connection between the plurality of memory cells and bit lines, source lines, etc., as will be described later. Figure 2 and Figure 3 The structure of the cell array 330 is described.

[0050] The memory device 150 may include a control circuit 180. The control circuit 180 may receive a command CMD input from outside the memory device. The command CMD may be received from the controller 130 (see Fig. 9 and Fig.10 ) or host 102 (see Fig. 9 ) transmission. For example, the command CMD may be used to output data stored in the cell array 330, store data in the cell array 330, or erase data stored or retained in the cell array 330. According to an embodiment, the command CMD may be used to check the operating state of the memory device 150 or perform an operation to improve the input / output performance, life, loss, etc. of the memory device 150.

[0051] The control circuit 180 receiving the command CMD may transmit the control signal CTRS to the voltage supply circuit 170. The voltage supply circuit 170 may generate at least one voltage in response to the control signal CTRS and transmit the at least one voltage to the cell array 330. For example, in response to the control signal CTRS, the voltage supply circuit 170 may supply a read voltage to a memory cell storing read data and supply a pass voltage to another memory cell coupled to the corresponding memory cell. The voltage supply circuit 170 may transmit various voltages capable of determining the on or off of a plurality of switch transistors to the cell array 330 in response to the control signal CTRS.

[0052] During a read operation, the cell array 330 may output data stored in a memory cell to the page buffer 322 in response to at least one voltage applied by the voltage supply circuit 170. In addition, during a program operation, the data stored in the page buffer 322 may be stored in a memory cell within the cell array 330. When the control circuit 180 attempts to erase data stored in a plurality of memory cells, data stored in a plurality of memory cells included in a preset unit or group (e.g., a memory block) in the cell array 330 may be erased together. In addition to data input / output operations for the memory cells in the cell array 330, the control circuit 180 may also check operating states of a plurality of switching transistors in the cell array 330 and perform a recovery operation on at least one degraded switching transistor. In this case, the cell array 330 may output operating states (e.g., data) of the switching transistor to the page buffer 322 in response to a plurality of voltages applied by the voltage supply circuit 170. Here, the operating state of the switching transistor may indicate a threshold voltage of the switching transistor. This will be referred to later. Figure 4 Describe the operating state of a switching transistor.

[0053] The control circuit 180 may check the operation state of the switch transistor in the cell array 330 through a process CHECK / VERIFY of checking the value stored in the page buffer 322. According to an embodiment, if it is determined that the operation state of the switch transistor in the cell array 330 is different from the preset state, the position information SWTR_LO of the corresponding switch transistor may be stored in the restore buffer 186.

[0054] If the operation of checking and restoring the operating state of the switching transistor in the cell array 330 is continuously performed, the control circuit 180 may not need to store the position information of the switching transistor to be restored. However, if the operation of checking and restoring the operating state of the switching transistor in the cell array 330 cannot be continuously performed, the control circuit 180 may store the position information about the degraded switching transistor, which may cause an error during the data input / output operation, which error is identified by checking the operating state of the switching transistor. After saving the position of the switching transistor, the operation of restoring the operating state of the switching transistor corresponding to the saved position may be performed via a subsequent operation. This will be referred to later. Figure 6 , Figure 8 , Fig.11 and Fig.12 An operation of checking and restoring the operation state of the switching transistors in the cell array 330 is described.

[0055] Figure 2 A memory device according to another embodiment of the present disclosure is shown. Specifically, Figure 2 A memory plane included in the memory device 150 or a memory cell group (eg, a cell array) included in a memory die according to an embodiment of the present disclosure is shown.

[0056] Reference Figure 2 , the memory device 150 may include at least one memory group 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of nonvolatile memory cells MC0 to MCn-1 connected to corresponding bit lines in a plurality of bit lines BL0 to BLm-1. The cell strings 340 are arranged in corresponding columns of the memory group 330, and each cell string 340 may include at least one drain select transistor DST and at least one source select transistor SST. The nonvolatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the nonvolatile memory cells MC0 to MCn-1 may be configured as a multi-layer cell (MLC) storing a data item having a plurality of bits per cell. The cell string 340 may be electrically connected to a corresponding bit line in the bit lines BL0 to BLm-1.

[0057] In an embodiment, the memory group 330 may include NAND-type flash memory cells MC0 to MCn-1. In another embodiment, the memory group 330 may be implemented as a NOR-type flash memory, a hybrid flash memory in which at least two different types of memory cells are mixed or combined, or a monolithic NAND flash memory in which a controller is embedded in a single memory chip. In an embodiment, the memory group 330 may include a flash memory cell including a charge trap flash (CTF) layer including a conductive floating gate or an insulating layer.

[0058] According to an embodiment, Figure 2 The memory device 150 shown may include at least one memory block. The memory group 330 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks in the memory device 150 may be implemented as a 3D structure, for example, a vertical structure. Each of the memory blocks may have a three-dimensional structure extending from a first direction to a third direction (e.g., an x-axis direction, a y-axis direction, and a z-axis direction).

[0059] The memory group 330 including at least one memory block may be connected to a plurality of bit lines BL, a plurality of source select lines SSL, a plurality of drain select lines DSL, a plurality of word lines WL, a plurality of virtual word lines DWL, and a plurality of common source lines CSL. In one embodiment, the memory group 330 may include a plurality of NAND strings NS, which may correspond to the cell strings 340, for example, respectively. Each NAND string NS may include a plurality of memory cells MC and may be connected to corresponding bit lines in the bit lines BL. In addition, the source select transistor SST of each NAND string NS may be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS may be connected to the corresponding bit line BL. In each NAND string NS, the memory cell MC may be arranged between the source select transistor SST and the drain select transistor DST.

[0060] The memory device 150 may include a voltage supply circuit 170, which may supply a word line voltage, for example, one or more predetermined voltages such as a program voltage, a read voltage, and a pass voltage to a corresponding word line among the word lines according to an operation mode, or may provide a voltage to a group block (for example, a well region) forming each memory block including the memory cells MC. In this case, the voltage generation operation of the voltage supply circuit 170 may be performed under the control of the control circuit 180. Moreover, the voltage supply circuit 170 may generate a plurality of variable read voltages to distinguish a plurality of data items from each other.

[0061] In response to the control of the control circuit 180, one of the memory blocks (or sectors) of the memory cell array may be selected, and one of the word lines of the selected memory block may be selected. The word line voltage may be supplied individually to the selected word line and the unselected word lines of the memory group 330. The voltage supply circuit 170 may include a voltage generating circuit for generating a target voltage having various levels, which target voltage may be applied to the word lines of the memory group 330.

[0062] The memory device 150 may also include a read / write circuit 320 controlled by the control circuit 180. Depending on the operation mode, the read / write circuit 320 may operate as a sense amplifier or a write driver. For example, in a verification operation and a read operation, the read / write circuit 320 may operate as a sense amplifier for reading data items from a memory cell array. In a programming operation, the read / write circuit 320 may operate as a write driver that controls the potential of the bit line according to the data items to be stored in the memory cell array. The read / write circuit 320 may receive data items to be programmed to the cell array from a page buffer during a programming operation. The read / write circuit 320 may drive the bit line based on the input data items. To this end, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, each corresponding to each column or each bit line, or each column pair or each bit line pair. According to an embodiment, each of the page buffers 322, 324, 326 may include a plurality of latches. According to an embodiment, the number of latches or page buffers coupled to each bit line may be equal to or greater than the number of bits of data stored in the memory cell MC.

[0063] The page buffers 322, 324, 326 may be connected to a data input / output device, such as a serialization circuit or a serializer, through a plurality of buses BUS. When each of the page buffers 322, 324, 326 is connected to the data input / output device through a different bus, a delay that may occur when data is transmitted from the page buffers 322, 324, 326 may be reduced. For example, each page buffer 322, 324, 326 may perform data transmission without waiting time.

[0064] According to an embodiment, the memory device 150 may receive a write command, write data, and information about a location where the write data is to be stored (e.g., a physical address). The control circuit 180 causes the voltage supply circuit 170 to generate a program pulse, a pass voltage, etc. for a program operation performed in response to the write command, and to generate one or more voltages for a verification operation performed after the program operation.

[0065] When programming multi-bit data items in nonvolatile memory cells included in the memory group 330, an error rate may be higher than an error rate when a single-bit data item is stored in the nonvolatile memory cell. For example, errors in nonvolatile memory cells may be caused by inter-cell interference (CCI). In order to reduce errors in nonvolatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the data items stored between nonvolatile memory cells should be reduced.

[0066] To this end, the memory device 150 may perform an incremental step pulse programming (ISPP) operation to effectively narrow the threshold voltage distribution of the non-volatile memory cells. In an embodiment, the memory device 150 may use the ISPP operation for a multi-step programming operation. For example, the memory device 150 may divide the programming operation into a least significant bit (LSB) programming operation and a most significant bit (MSB) operation according to a predetermined order between non-volatile memory cells or pages.

[0067] The multi-bit values ​​programmed in the memory cells (e.g., NAND-type flash memory cells MC0 to MCn-1 in the memory group 330) in the NAND flash memory can be determined based on the threshold voltage window or threshold voltage distribution to which the threshold voltage of the cell belongs. As the size of each memory cell is reduced and more bits (e.g., 3 bits, 4 bits, or 5 bits) of data are programmed per memory cell, the width of the threshold voltage window used to represent each multi-bit value becomes narrower, thereby increasing the error rate when determining the multi-bit value stored in the memory cell. This is because when the amount of charge stored in each memory cell decreases with the feature size, process variations become more prevalent, resulting in large differences in the threshold voltages of different memory cells storing the same value. Therefore, it becomes increasingly difficult to determine which value the threshold voltage of a memory cell corresponds to.

[0068] According to an embodiment, the control circuit 180 may include a read retry table (RRT). The RRT may be stored in the memory device 150. A read error may occur in the process of applying a read voltage to a non-volatile memory cell in the memory device 150 through a word line and reading data stored in the non-volatile memory cell. The control circuit 180 in the memory device 150 may manage information about a read retry mechanism for resolving a read error. One of the information about the read retry mechanism is to read the RRT. The read retry mechanism uses the RRT for the recorded position where the error occurred, so that the memory device 150 can ensure data integrity by applying an appropriate correction value (e.g., changing the read voltage level) when rereading.

[0069] Figure 3 A memory cell array according to another embodiment of the present disclosure is shown.

[0070] Reference Figure 3 , the memory cell array may have a structure including parts or layers stacked along a vertical direction D1. The memory cell array may include at least one memory block. Hereinafter, a direction substantially perpendicular to the upper surface of the substrate may be defined as a first direction D1, and two directions parallel to the upper surface of the substrate and intersecting each other may be defined as a second direction D2 and a third direction D3, respectively. For example, the second direction D2 and the third direction D3 may intersect each other substantially perpendicularly. The first direction D1 may be referred to as a vertical direction, the second direction D2 may be referred to as a row direction, and the third direction D3 may be referred to as a column direction. The direction indicated by the arrow in the figure and the direction opposite thereto are described as the same direction.

[0071] For ease of description, Figure 3 NAND strings or cell strings SG1 to SGk connected to one bit line BL and one common source line CSL among cell strings included in a memory block are shown.

[0072] The memory block may include a plurality of cell strings SG1 to SG5 connected between the same bit line (BL) and a common source line CSL. Each of the cell strings SG1 to SGk may include at least one source selection transistor SST controlled by a source selection line SSL, a plurality of memory cells controlled by a word line WL, an intermediate switching transistor CST disposed in an intermediate boundary layer IBL and controlled by an intermediate switching word line CSWL, and a drain selection transistor DST controlled by each drain selection line DSL1, DSL2, DSL3, ..., DSLk.

[0073] According to an embodiment, a plurality of memory cells connected to at least one word line located at both ends of the first stack ST1 and the second stack ST2 in the first direction D1 may be virtual cells. No data may be stored in the virtual cells. Further, according to an embodiment, the virtual cells may be used to store data having a smaller number of bits than other memory cells. According to an embodiment, the intermediate boundary layer IBL may include at least one gate line. One gate line corresponds to an intermediate switch word line CSWL, which may simultaneously control the switching operation of the intermediate switch transistors CST connected thereto. Further, although Figure 3 A structure in which a first stack ST1 and a second stack ST2 are stacked is shown, but three or more stacks may be vertically stacked in the cell array 330. When a plurality of stacks are stacked, an intermediate boundary layer IBL may be formed and disposed between each two stacked stacks. The intermediate boundary layer IBL may include at least one switching transistor configured to couple a memory cell in one of the two stacks to other memory cells in the other stack.

[0074] Figure 3An embodiment is shown in which source selection transistors SST included in the plurality of cell strings SG1 to SGk are connected to a common source line CSL However, according to an embodiment, a certain number of source selection transistors may be coupled to each of a plurality of source ground selection lines.

[0075] Reference Figures 1 to 3 , the cell array 330 may include a plurality of memory blocks arranged along a plurality of directions D1, D2, and D3. In an embodiment, the memory blocks may be composed of Figure 1 and Figure 2 For example, a read voltage, a program voltage, or an erase voltage may be applied to the memory block and the word line selected by the control circuit 180.

[0076] Each of the cell strings SG1 to SGk may include a plurality of switching transistors and a plurality of memory cells capable of storing data. Here, the plurality of switching transistors may include a drain select transistor DST, a source select transistor SST, and a middle switch transistor CST. Figure 3 An embodiment is shown in which each of the cell strings SG1 to SGk includes one drain selection transistor DST, one source selection transistor SST, and one intermediate switch transistor CST, respectively. However, according to embodiments, each of the cell strings SG1 to SGk may include a plurality of drain selection transistors DST, a plurality of source selection transistors SST, or a plurality of intermediate switch transistors CST.

[0077] Figure 4 A check and recovery operation regarding an operating state of a switching transistor according to another embodiment of the present disclosure is shown. Figure 3 The drain selection transistor DST described in is a type of switching transistor. Figure 4 A change in the threshold voltage of the drain selection transistor DST is shown as an example, and an operation of checking and restoring the operating state of the switching transistor is shown.

[0078] Reference Figures 1 to 4 , the NAND string 340 or cell strings SG1 to SGk included in the cell array 330 of the memory device 150 may include a drain selection transistor DST operating as a switching transistor. Here, the switching transistor may include an element for operating the NAND string 340 or cell strings SG1 to SGk instead of for storing data.

[0079] In an initial state, the threshold voltage distribution of the drain selection transistors DST included in the NAND string 340 or the cell strings SG1 to SGk may be between two voltage levels applied to the drain selection lines DSL1, DSL2, DSL3, . . . , DSLk. Figure 4Among the four drain selection lines DSL1, DSL2, DSL3, DSL4 shown, a first voltage level may be applied to deactivate the first to third drain selection lines DSL1, DSL2, DSL3. However, a second voltage level may be applied to activate the fourth drain selection line DSL4. The threshold voltage distribution of the plurality of drain selection transistors DST included in the NAND string 340 or the cell strings SG1 to SGk may be preset to be between the first voltage level and the second voltage level.

[0080] As time passes and data is input / output to / from the memory device 150, degradation may occur in the plurality of memory cells and the plurality of switch transistors included in the NAND string 340 or the cell strings SG1 to SGk. When the program-erase cycle (P / E cycle) of the memory block in the memory device 150 increases, the temperature in the memory device 150 increases, or a high voltage is applied or used in the memory device 150, the threshold voltage distribution of the switch transistors and the memory cells included in the NAND string 340 or the cell strings SG1 to SGk may not remain constant. For example, if the switch transistor is not manipulated (maintained) for a long time, the threshold voltage distribution of the switch transistor may decrease. Further, when a high level voltage is repeatedly applied to the switch transistor, interference may occur, and thus the threshold voltage distribution of the switch transistor may increase.

[0081] As time passes and a degraded state occurs, the threshold voltage distribution of the plurality of drain selection transistors DST included in the NAND string 340 or the cell strings SG1 to SGk may not be between the first voltage level and the second voltage level. For example, the threshold voltage distribution of the plurality of drain selection transistors DST may be transformed to be lower than the first voltage level or higher than the second voltage level. When the threshold voltage distribution of the plurality of drain selection transistors DST included in the NAND string 340 or the cell strings SG1 to SGk deviates from the range between the first voltage level and the second voltage level, at least some of the drain selection transistors DST may not operate as switches based on the first voltage level and the second voltage level applied to the drain selection transistors DST through the drain selection lines DSL1, DSL2, DSL3, ..., DSLk. Therefore, the memory device 150 can check the threshold voltage distribution of the switch transistor and restore the threshold voltage distribution of the switch transistor to its initial state.

[0082] When a degraded switch transistor is found in the operation of checking the threshold voltage distribution of the switch transistor, the memory device 150 may perform a recovery operation to convert the threshold voltage of the degraded switch transistor to a range between the first voltage level and the second voltage level. For example, if the threshold voltage of the degraded switch transistor has a level lower than the first voltage level, a programming operation for the degraded switch transistor may be performed to increase the threshold voltage of the degraded switch transistor to a range between the first voltage level and the first voltage level. Conversely, when the threshold voltage of the degraded switch transistor has a level higher than the second voltage level, a selective erase operation may be performed to reduce the threshold voltage of the corresponding switch transistor. Through this recovery operation, the threshold voltage distribution of the plurality of drain select transistors DST included in the NAND string 340 or the cell strings SG1 to SGk may be located between the first voltage and the second voltage, so that the plurality of drain select transistors DST may not have a problem operating as switches in response to the first and second voltage levels.

[0083] Figure 5 A check and restore operation regarding an operation state of a switching transistor during an erase operation according to an embodiment of the present disclosure is shown.

[0084] Reference Figure 5 , a check and recovery operation on the operating state of the switching transistor can be performed during an erase operation for a specific storage block. The erase operation can be performed in response to an erase command (ERS command). Among the read operation, the program operation, and the erase operation, the longest operating margin can be set for the erase operation. According to an embodiment, among the data input / output operations, the erase operation can have the longest operating margin. Further, the programming operation can have a longer operating margin than the read operation. The operating margin of each of the read operation, the program operation, and the erase operation can be determined based on an international standard or specification related to the memory device 150 or the I / O performance or throughput of the memory device 150.

[0085] Assuming that the check and restore operation regarding the operation state of the switching transistor affects data input / output operations such as storing data in a memory cell, reading data stored in a memory cell, or erasing data stored in a memory cell, the operation performance of the memory device 150 may be degraded. In order to avoid or prevent the operation performance of the memory device 150 from being degraded, the check and restore operation regarding the operation state of the switching transistor may be additionally performed during the operation margin of the erase operation because the erase operation can obtain the longest operation margin.

[0086] Reference Figure 5, a first operation margin tERA_Margin1 of an erase operation corresponding to an erase command (ERS command) may be preset. During the first operation margin tERA_Margin1 of the erase operation, an operation of erasing data stored or remaining in a specific memory block may be performed, and it may be verified whether all data in the corresponding memory block has been completely erased by the erase operation. Therefore, the first operation margin tERA_Margin1 of the erase operation may include a first portion (ERS Exe.) of an erase voltage being applied to a corresponding memory block and a second portion (Verify) of a verification voltage being applied to the corresponding memory block.

[0087] After the erase operation is completed (i.e., after applying an erase voltage and then applying a verification voltage to check whether all data in a specific memory block has been erased), the first operation margin tERA_Margin1 of the erase operation may remain because the first operation margin tERA_Margin1 may be sufficiently set. For example, because the erase operation may be performed multiple times based on the operation state of the memory block, the first operation margin tERA_Margin1 of the erase operation may be generously set.

[0088] The memory device 150 may check whether the switch transistor included in the corresponding memory block is degraded during the remaining time of the first operation margin tERA_Margin1 (see Figure 5 tERA_Margin1 shown in FIG. 1 ). At this time, it may be checked whether the threshold voltage of a specific switching transistor is lower than a preset first voltage (L) or higher than a preset second voltage (R). After checking whether the switching transistor included in the corresponding memory block is degraded, the memory device 150 may perform a recovery operation on the degraded switching transistor (see FIG. 1 ). Figure 5 For example, the memory device 150 may use a programming pulse to increase a threshold voltage of a specific switching transistor (“ST recovery procedure (L)”), or may use an erase pulse to decrease a threshold voltage of a specific switching transistor (“ST recovery procedure (R)”).

[0089] Reference Figure 3 and Figure 5, in order to store more data in the memory device 150, the cell array may have a structure stacked along the vertical direction D1. Therefore, the number of memory cells and the number of stacks included in the memory block of the memory device 150 may increase. As the number of memory cells and the number of stacks included in the memory block of the memory device 150 increase, the time required or used to check whether the data in a specific memory block has been erased by applying a verification voltage after applying an erase voltage may become longer. If the second part (verification) of applying the verification voltage becomes longer, the second operation margin tERA_Margin2 of the erase operation including the time required to check whether the switching transistor is degraded ("ST degradation check (L / R)") and the time to perform a recovery operation ("ST recovery procedure (L / R)") on the degraded switching transistor will increase.

[0090] Since the second operation margin tERA_Margin2 requiring the erase operation corresponding to the erase command (ERS command) is increased from the first operation margin tERA_Margin1 , the operation performance of the memory device 150 may be reduced.

[0091] Figure 6 The checking and restoring operation of the operating state of the switching transistor during the data input / output operation according to the embodiment of the present disclosure is shown. The checking and restoring operation of the switching transistor can be distributed over multiple input / output operations.

[0092] Reference Figure 6 , a check and recovery operation on the operating state of the switching transistor can be performed respectively throughout the erase operation and the programming operation. As described above, among the data input / output operations performed in the memory device 150, the operating margins of the erase operation and the programming operation can be set to be longer than other operations. As the number of memory cells and the number of stacks included in the memory block of the memory device 150 increase, it may be difficult to check the operating state of the switching transistor and perform a recovery operation on a degraded switching transistor during the first operating margin tERA_Margin1 of the erase operation. The memory device 150 can check the operating state of the switching transistor during the first operating margin tERA_Margin1 of the erase operation, and then perform a recovery operation on the degraded switching transistor during the operating margin tProg_Margin of the programming operation. In this way, as Figure 5 As shown, there is no need to increase the first operation margin tERA_Margin1 of the erase operation corresponding to the erase command (ERS command) to the second operation margin tERA_Margin2, thereby preventing degradation of the operation performance of the memory device 150.

[0093] During the first operation margin tERA_Margin1 of the erase operation corresponding to the erase command (ERS command), the memory device 150 may operate a specific memory block by applying a first portion of the erase voltage (ERS Exe.) and applying a second portion of the verification voltage (Verify). Data stored or remaining in the corresponding memory block may be erased. Thereafter, the memory device 150 may check whether the switching transistor included in the corresponding memory block is degraded during the remaining time (see Figure 6 "ST Deterioration Inspection (L / R)" in the manual.

[0094] like Figure 1 As described in , the control circuit 180 in the memory device 150 may store the result of checking whether at least one switching transistor is degraded (ie, the position information of the degraded switching transistor) in the restoration buffer 186 .

[0095] Thereafter, according to an embodiment, the memory device 150 may perform a recovery operation on the degraded switching transistor (see Figure 6 ”ST recovery procedure (L / R)” in the description). The operation margin tProg_Margin of the programming operation may include a first process (programming) of applying a programming pulse to a memory cell for storing data and a second process (verification) of verifying the stored data. The operation margin tProg_Margin of the programming operation may be smaller than the first operation margin tERA_Margin1 of the erasing operation, and thus it may be difficult to immediately perform a recovery operation on a degraded switching transistor. As described above, the memory device 150 may use a programming pulse to increase the threshold voltage of a specific switching transistor (“ST recovery procedure (L)”) or use an erase pulse to lower the threshold voltage of a specific switching transistor (“ST recovery procedure (R)”). Since there may not be enough time for the recovery operation, the process of increasing the threshold voltage of a specific switching transistor using a programming pulse (“ST recovery procedure (L)”) and the process of lowering the threshold voltage of a specific switching transistor using an erase pulse (“ST recovery procedure (R)”) may be divided into several unit operations (e.g., half of the process using a programming pulse and an erase pulse: see Figure 6 "ST recovery procedure (L) = 1 / 2", "ST recovery procedure (L) = 1 / 2", "ST recovery procedure (R) = 1 / 2", "ST recovery procedure (R) = 1 / 2").

[0096] According to an embodiment, the controller (130, see Fig. 9 and Fig.10 ) or host (102, see Fig. 9) inputs four programming commands PGM①, PGM②, PGM③, PGM④. In addition, in another embodiment, four programming commands PGM①, PGM②, PGM③, PGM④ are generated after the memory device 150 receives the erase command (ERS command) and the programming command (PGM command). The control circuit 180 may generate four programming commands PGM①, PGM②, PGM③, PGM④ based on the operating state of the memory device 150. The programming commands PGM①, PGM②, PGM③, PGM④ may generate corresponding unit operations: ST recovery program (L)=1 / 2, ST recovery program (L)=1 / 2, ST recovery program (R)=1 / 2, and ST recovery program (R)=1 / 2.

[0097] For ease of description, Figure 6 , an example of performing a single recovery operation divided into two unit operations (i.e., two "ST recovery program (L) = 1 / 2" and "ST recovery program (L) = 1 / 2" and two "ST recovery program (R) = 1 / 2" and "ST recovery program (R) = 1 / 2") is described. However, the inspection and recovery operations regarding the operating state of the switching transistor can be divided into multiple unit operations. Then, the multiple unit operations can be performed together with multiple erase operations that are performed separately during each of the first operating margin tERA_Margin1 and multiple programming operations that are performed separately during each of the operating margin tProg_Margin. In this way, even if the number of memory cells and the number of stacks increase, the memory device 150 does not need to increase the first operating margin tERA_Margin1 of the erase operation and the operating margin tProg_Margin of the programming operation, and thus the operating performance of the memory device 150 can be improved.

[0098] Figure 7 A finite state machine included in a memory device according to another embodiment of the present disclosure is shown.

[0099] Reference Figures 1 to 3 and Figure 7 , the control circuit 180 may include a finite state machine 182 for controlling data input / output operations within the memory device 150 .

[0100] The control circuit 180 may generate a control signal CTRL_STBY for a standby state in an idle state IDLE. In addition, the control circuit 180 may generate a control signal CTRL_SWTR_LO for controlling position information of a switching transistor in an idle state IDLE. At this time, the switching transistor may include a degraded switching transistor. The control signal CTRL_SWTR_LO for controlling the position information of the switching transistor is used for a preparation operation for restoring the threshold voltage of the degraded switching transistor by storing the position information in a buffer or at a preset storage location or adding the position to a data input / output command generated or executed later.

[0101] When a read command is input, the control circuit 180 may generate a read control signal CTRL_RD to perform a read operation READ OP., and after performing the read operation READ OP., the obtained read data RD_DATA may be output. With the output of the read data RD_DATA, the control circuit 180 may transition from the state of the read operation READ OP to the idle state IDLE. According to an embodiment, the operation margin of the read operation READ OP may not be long compared to other input / output operations. Therefore, a control signal for checking and restoring the operation state of the switch transistor may not be generated or used during the state of the read operation READ OP.

[0102] When the erase command is input, the control circuit 180 may generate an erase control signal CTRL_ER for performing an erase operation ERASE OP and a verification signal CTRL_VERI for verifying the erase operation. In addition, since the operation margin of the erase operation ERASE OP is greater than the operation margin of other data input / output operations, the control circuit 180 may generate or use a control signal CTRL_SWTR_CH to check the operation state of the switch transistor. After performing the erase operation ERASE OP and the verification operation, the control circuit 180 may check the erase verification result ER_VER. In addition, based on the control signal CTRL_SWTR_CH for checking the operation state of the switch transistor, the control circuit 180 may collect the location information SWTR_LO of the degraded switch transistor.

[0103] When a program command is input, the control circuit 180 may generate a program control signal CTRL_PROG for performing a program operation PROGRAM OP and a verification signal CTRL_VERI for verifying the program operation. The operation margin of the program operation PROGRAM OP may be less than the operation margin of the erase operation ERASE OP. However, the operation margin of the program operation PROGRAM OP may be longer than the operation margin of the read operation READ OP. Therefore, the control circuit 180 may generate a control signal CTRL_SWTR_RE for performing a recovery operation on a degraded switch transistor during the program operation PROGRAM OP. After performing the program operation PROGRAM OP and the verification operation, the control circuit 180 may check the program verification result PROG_VER. In addition, based on the control signal CTRL_SWTR_RE for performing a recovery operation of the degraded switch transistor, the control circuit 180 may check the recovery result SWTR_RE_R of the switch transistor.

[0104] Figure 7 The finite state machine 182 described in the foregoing is described as an example and may be modified according to the internal components and operation performance of the memory device 150. The memory device 150 may generate a control signal for checking and restoring the operation state of the switching transistor during at least one erase operation ERASE OP or at least one program operation PROGRAM OP. Figure 6 As described in , when the inspection and restoration operations regarding the operation state of the switching transistor are divided into a plurality of unit operations, the control signal for the switching transistor may be generated a plurality of times for the plurality of unit operations.

[0105] Figure 8 A check and restore operation regarding an operation state of a switching transistor during a program operation according to an embodiment of the present disclosure is illustrated.

[0106] Reference Figures 1 to 3 and Figure 8 , multi-bit data can be programmed into a plurality of memory cells in the cell array 330 . Figure 8 Various methods of programming 3 bits of data in each memory cell are described. Figure 8 Two types of multi-bit data programming are shown, but a method of performing the multi-bit data programming operation may vary according to embodiments.

[0107] For example, a programming operation for storing 3-bit data in each memory cell can be divided into a unit operation for programming each bit of data. A programming operation for storing multi-bit data may include an LSB operation for storing LSB (least significant bit) data in each memory cell in an erased state, a CSB operation for storing CSB (mid-significant bit) data, and an MSB operation for storing MSB (most significant bit) data. When LSB, CSB, and MSB data are stored in each memory cell, the time tLSB, tCSB, and tMSB required or used to program each data may be different. For example, the time tLSB required to program LSB data may be shorter than the time tCSB required to program CSB data, and the time tCSB required to program CSB data may be shorter than the time tMSB required to program MSB data (i.e., tMSB>tCSB>tLSB).

[0108] According to an embodiment, an operation of storing 3-bit multi-bit data in each memory cell may be divided into three sub-operations, including a first programming operation for distinguishing two types of memory cells (e.g., a first cell maintained in an erased state and a second cell programmed with one of the programming states (erased or programmed), a second programming operation for programming LSB data, and a third programming operation for programming the remaining two bits of CSB and MSB data. In this case, the time tMSB, tCSB used to program the two bits of CSB and MSB data may be longer than the time tLSB used to program the LSB data. The time tLSB used to program the LSB data may be longer than the time tP used in the first programming operation for distinguishing the first cell maintained in an erased state from the second cell programmed with one of the programming states (i.e., tMSB / tCSB>tLSB>tP).

[0109] As described above, the time required may vary depending on which bit of the multi-bit data is programmed into the memory cell during the programming operation. However, the operating margin tProg_Margin set for the programming operation in the memory device 150 may not vary based on the bit of the multi-bit data to be programmed. For all bits of the multi-bit data, the operating margin tProg_Margin may be set to be the same. Therefore, when a programming command (programming CMD) is input, a programming and verification operation (programming verification) is performed on the programming bit of the multi-bit data during the operating margin tProg_Margin corresponding to the programming command (programming CMD). Further, optionally, the memory device 150 may perform a check and recovery operation on the operating state of the switching transistors DSL, SSL, and CST during the remaining time within the operating margin tProg_Margin.

[0110] According to the data corresponding to the program command (program CMD), the remaining time or the optional margin that can be used to check the operating state of the switching transistors DSL, SSL, CST and perform a recovery operation on the degraded switching transistor may be different. In addition, according to an embodiment, when programming and verification of specific data (for example, MSB data) are performed, there is not enough time for checking the operating state of the switching transistors DSL, SSL, CST and performing a recovery operation on the degraded switching transistor. Figure 6 and Figure 8 , depending on which bit of the multi-bit data corresponds to the program command (program CMD), the memory device 150 can check the operating state of the switching transistors DSL, SSL, CST, and can perform a recovery operation on the degraded switching transistor. The memory device 150 can determine whether to perform some or all of the check and recovery operations on the operating state of the switching transistors DSL, SSL, CST.

[0111] Fig. 9 A data processing system according to an embodiment of the present disclosure is shown.

[0112] Reference Fig. 9 , the data processing system 100 may include a host 102 that interfaces or couples with a memory system, such as a memory system 110. For example, the host 102 and the memory system 110 may be coupled to each other via a data bus, a host cable, etc. to perform data communication.

[0113] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be considered as physically separate components or elements from each other. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a path.

[0114] The memory device 150 may include a plurality of memory chips 252 connected to the controller 130 via a plurality of channels CH0, CH1, ..., CHn and paths W0, ..., W_k. The memory chip 252 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, a memory plane may be considered to be a logical or physical partition including at least one storage block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that may temporarily store data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode for performing multiple data input / output operations in parallel or simultaneously. According to an embodiment, the storage blocks included in each memory plane or each memory die included in the memory device 150 may be grouped to input / output multiple data entries as a super storage block. Based on the operating performance of the memory system 110, the memory plane may be changed. Fig. 9 The internal configuration of the memory device 150 is shown. The embodiments of the present disclosure may not be limited to Fig. 9 Internal configuration shown.

[0115] According to an embodiment, the memory device 150 and the controller 130 may be components or elements divided by function. Further, according to an embodiment, the memory device 150 and the controller 130 may be implemented with a single chip or multiple chips.

[0116] The controller 130 may perform data input / output operations such as a read operation, a program operation, an erase operation, etc. in response to a request or a command input from an external device such as the host 102. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of nonvolatile memory cells included in the memory device 150 is transferred to the controller 130. Further, the controller 130 may independently perform operations regardless of a request or a command input from the host 102. With respect to the operating state of the memory device 150, the controller 130 may perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) for checking whether a storage block is a bad block and disposing of the bad block.

[0117] Each memory die 252 may include multiple storage blocks. A storage block may be understood as a group of nonvolatile memory cells that remove data together through a single erase operation. Although not shown, a storage block may include a page, which is a group of nonvolatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a storage block may include multiple pages. The memory device 150 may include a voltage supply circuit capable of supplying at least one voltage to a storage block. The voltage supply circuit may supply a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to a nonvolatile memory cell included in a storage block.

[0118] The host 102 interoperating with the memory system 110 or the data processing system 110 including the memory system 110 and the host 102 is a mobile electronic device (e.g., a vehicle), a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.), and a non-portable electronic device (e.g., a desktop computer, a game console, a TV, a projector, etc.). The host 102 may provide interoperation between the host 102 and a user using the data processing system 100 or the memory system 110 through at least one operating system (OS). The host 102 transmits a plurality of commands corresponding to the user's request to the memory system 110, and the memory system 110 performs data input / output operations corresponding to the plurality of commands (e.g., operations corresponding to the user's request).

[0119] Reference Fig. 9 , the controller 130 in the memory system operates with the host 102 and the memory device 150. As shown, the controller 130 may have a layered structure including a host interface (HIL) 220, a flash translation layer (FTL) 240, and a memory interface layer or flash interface layer (FIL) 260.

[0120] As an example, Fig. 9 1 and 130. The host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260 described in the embodiment of the present invention may be implemented in various forms according to the operation performance of the memory system 110. According to an embodiment, the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the flash interface layer (FIL) 260 may perform operations through a multi-core or a processor having a pipeline structure included in the controller 130.

[0121] The host 102 and the memory system 110 may communicate data using a predetermined set of rules or processes, or use a preset interface to send and receive data between them. Examples of multiple sets of rules or processes for data communication standards or interfaces for sending and receiving data supported by the host 102 and the memory system 110 include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industrial Processor Interface (MIPI), etc. According to an embodiment, the host 102 and the memory system 110 may be connected to each other via a Universal Serial Bus (USB). Universal Serial Bus (USB) is a highly scalable, hot-swappable, plug-and-play serial interface that ensures cost-effective standard connections with peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, video conferencing cameras, etc.

[0122] The memory system 110 may support high-speed non-volatile memory (NVMe). High-speed non-volatile memory (NVMe) is an interface based at least on a high-speed peripheral component interconnect (PCIe), which is designed to improve the performance and design flexibility of a host 102, a server, a computing device, etc. equipped with a non-volatile memory system 110. PCIe can use a slot or a specific cable to connect a computing device (e.g., a host 102) and a peripheral device (e.g., a memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, 82 pins, etc.) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication exceeding hundreds of MB per second. According to an embodiment, the PCIe scheme can achieve a bandwidth of tens to hundreds of gigabits per second.

[0123] The buffer manager 280 in the controller 130 may control the input / output of data or operation information in conjunction with the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (HIL) 260. To this end, the buffer manager 280 may set or establish various buffers, caches, or queues in the memory, and control the data input / output of the buffers, caches, or queues, or the data transmission between the buffers, caches, or queues in response to requests or commands generated by the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260. For example, the controller 130 may temporarily store the read data provided by the memory device 150 in response to a request from the host 102 before providing the read data to the host 102. Moreover, the controller 130 may temporarily store the write data provided by the host 102 in the memory before storing the write data in the memory device 150. When controlling operations such as read operations, program operations, and erase operations performed within the memory device 150, read data or write data transmitted or generated between the controller 130 in the memory system 110 and the memory device 150 may be stored and managed in a buffer, a queue, etc. established in the memory by the buffer manager 280. In addition to the read data or the write data, the buffer manager 280 may also store signals or information (e.g., mapping data, read commands, program commands, etc. for performing operations such as programming and reading data between the host 102 and the memory device 150) in a buffer, a cache, a queue, etc. established in the memory. The buffer manager 280 may set or manage a command queue, a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc.

[0124] The host interface layer (HIL) 220 may handle commands, data, etc. transmitted from the host 102. By way of example and not limitation, the host interface layer (HIL) 220 may include a command queue manager 222 and an event queue manager 224. The command queue manager 222 may sequentially store commands, data, etc. received from the host 102 in a command queue, and output them to the event queue manager 224, for example, in the order in which they are stored in the command queue manager 222. The event queue manager 224 may sequentially transmit events to process commands, data, etc. received from the command queue. According to an embodiment, the event queue manager 224 may classify, manage, or adjust commands, data, etc. received from the command queue. Further, according to an embodiment, the host interface layer 220 may include an encryption manager 226 configured to encrypt a response or output data to be transmitted to the host 102, or to decrypt an encrypted portion of a command or data transmitted from the host 102.

[0125] A plurality of commands or data of the same characteristics may be sent from the host 102, or a plurality of commands and data of different characteristics may be transmitted to the memory system 110 after being mixed or jumbled by the host 102. For example, a plurality of commands for reading data, i.e., read commands, may be delivered, or commands for reading data, i.e., read commands, and commands for programming / writing data, i.e., write commands may be transmitted alternately to the memory system 110. The command queue manager 222 of the host interface layer 220 may sequentially store the commands, data, etc. transmitted from the host 102 in the command queue. Thereafter, the host interface layer 220 may estimate or predict what type of internal operation the controller 130 will perform based on the characteristics of the commands, data, etc. that have been sent from the host 102. The host interface layer 220 may determine the processing order and priority of the commands, data, etc. based on their characteristics. According to the characteristics of the commands, data, etc. transmitted from the host 102, the event queue manager 224 in the host interface layer 220 is configured to receive from the buffer manager 280 an event that should be processed or handled internally in the memory system 110 or the controller 130 according to the commands, data, etc. input from the host 102. Then, the event queue manager 224 can transmit the events including the commands, data, etc. to the flash translation layer (FTL) 240.

[0126] According to an embodiment, the flash translation layer (FTL) 240 may include a host request manager (HRM) 242, a mapping manager (MM) 244, a state manager 246, and a block manager 248. Further, according to an embodiment, the flash translation layer (FTL) 240 may implement a multithreading scheme to perform data input / output (I / O) operations. The multithreaded FTL may be implemented by a multi-core processor using the multithreading included in the controller 130. For example, the host request manager (HRM) 242 may manage events transmitted from an event queue. The mapping manager (MM) 244 may handle or control mapping data. After checking the operating state of the memory device 150, the state manager 246 may perform operations such as garbage collection (GC) or wear leveling (WL). The block manager 248 may run commands or instructions on blocks in the memory device 150.

[0127] The host request manager (HRM) 242 may use the mapping manager (MM) 244 and the block manager 248 to handle or process requests according to read commands and program commands and events transferred from the host interface layer 220. The host request manager (HRM) 242 may send a query request to the mapping manager (MM) 244 to determine a physical address corresponding to a logical address input with the event. The host request manager (HRM) 242 may send a read request and a physical address to the memory interface layer 260 to process the read request, i.e., handle the event. In one embodiment, the host request manager (HRM) 242 may send a program request (or a write request) to the block manager 248 to program data to a specific empty page in the memory device 150 where no data is stored, and then a mapping update request corresponding to the program request may be transmitted to the mapping manager (MM) 244 to update items related to the programmed data in the information that maps the logical address and the physical address to each other.

[0128] The block manager 248 may convert the program request transferred from the host request manager (HRM) 242, the mapping manager (MM) 244, and / or the state manager 246 into a flash program request for the memory device 150 to manage the flash blocks in the memory device 150. In order to maximize or enhance the programming performance or writing performance of the memory system 110, the block manager 248 may collect the program requests and send the flash program requests for multi-plane and single programming operations to the memory interface layer 260. In an embodiment, the block manager 248 sends several flash program requests to the memory interface layer 260 to enhance or maximize the parallel processing of a multi-channel and multi-directional flash controller.

[0129] In an embodiment, the block manager 248 may manage the blocks in the memory device 150 according to the number of valid pages, select and erase a block without valid pages when a free block is needed, and select a block including the least number of valid pages when it is determined that garbage collection is to be performed. The state manager 246 may perform garbage collection to move valid data stored in the selected block to an empty block and erase data stored in the selected block, so that the memory device 150 may have sufficient free blocks (i.e., empty blocks without data).

[0130] When the block manager 248 provides information about the block to be erased to the state manager 246, the state manager 246 can check all flash memory pages of the block to be erased to determine whether each page of the block is valid. For example, to determine the validity of each page, the state manager 246 can identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine whether each page is valid, the state manager 246 can compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. The state manager 246 sends a program request to the block manager 248 for each valid page. When the programming operation is completed, the mapping table can be updated by the mapping manager 244.

[0131] The mapping manager 244 may manage mapping data, such as a logical-physical mapping table. The mapping manager 244 may process various requests, such as queries, updates, etc. generated by the host request manager (HRM) 242 or the state manager 246. The mapping manager 244 may store the entire mapping table in the memory device 150, such as a flash memory / non-volatile memory, and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs while processing a query or update request, the mapping manager 244 may send a read request to the memory interface layer 260 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 244 exceeds a certain threshold, a program request may be sent to the block manager 246, so that a clean cache block is formed and the dirty mapping table may be stored in the memory device 150.

[0132] When garbage collection is performed, the state manager 246 copies the valid page to the free block, and the host request manager (HRM) 242 can program the latest version of the data of the same logical address of the page and issue an update request at the same time. When the state manager 246 requests a mapping update in a state where the copy of the valid page is not completed normally, the mapping manager 244 may not perform a mapping table update. This is because when the state manager 246 requests a mapping update and the valid page copy is completed later, the mapping request is issued together with the old physical information. When or only when the latest mapping table still points to the old physical address, the mapping manager 244 can perform a mapping update operation to ensure accuracy.

[0133] The memory interface layer or flash interface layer (FIL) 260 may exchange data, commands, status information, etc. with the plurality of memory chips 252 in the memory device 150 through a data communication method. According to an embodiment, the memory interface layer 260 may include a status check scheduler 262 and a data path manager 264. The status check scheduler 262 may check and determine the operation status of the plurality of memory chips 252 connected to the controller 130, the operation status of the plurality of channels CH0, CH1, ..., CHn, and the plurality of paths W0, ..., W_k, etc. The transmission and reception of data or commands may be scheduled in response to the operation status of the plurality of memory chips 252 and the plurality of channels CH0, CH1, ..., CHn. The data path manager 264 may control the transmission and reception of data, commands, etc. through the plurality of channels CH0, CH1, ..., CHn and the paths W0, ..., W_k based on the information transmitted from the status check scheduler 262. According to an embodiment, the data path manager 264 may include a plurality of transceivers, each corresponding to each of the plurality of channels CH0, CH1, ..., CHn. Further, according to an embodiment, the status check schedule manager 262 and the data path manager 264 included in the memory interface layer 260 may be implemented as a memory control sequence generator or coupled with the memory control sequence generator.

[0134] According to an embodiment, the memory interface layer 260 may further include an ECC (Error Correction Code) circuit 266 configured to perform error checking and correction on data transmitted between the controller 130 and the memory device 150. The ECC unit 266 may be implemented as a separate module, circuit, or firmware in the controller 130, but may also be implemented in each memory chip 252 included in the memory device 150 according to an embodiment. The ECC circuit 266 may include a program, circuit, module, system, or device for detecting and correcting error bits of data processed by the memory device 150.

[0135] In order to find and correct any errors of the data transmitted from the memory device 150, the ECC circuit 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding on the data to be programmed in the memory device 150 to generate encoded data with parity bits added, and store the encoded data in the memory device 150. When the controller 130 reads the data stored in the memory device 150, the ECC decoder may detect and correct the error bits included in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the ECC circuit 266 may determine whether the error correction decoding is successful or not, and output an instruction signal based on the result of the error correction decoding, such as a correction success signal or a correction failure signal. The ECC circuit 266 may use the parity bits that have been generated for the data stored in the memory device 150 during the ECC encoding process to correct the error bits of the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, the ECC circuit 138 may not correct the error bits, but may output a correction failure signal indicating that the correction of the error bits has failed.

[0136] According to an embodiment, the error correction circuit 138 may perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems and / or devices for performing error correction operations based on at least one of the above codes.

[0137] For example, the encoder in the ECC circuit 266 can generate a codeword, which is a unit of ECC application data. A codeword with a length of n bits can include k bits of user data and (nk) bits of parity. The code rate can be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. When the length of the codeword is long and the code rate is small, the error correction capability of the ECC circuit 266 can be improved. In addition, the ECC circuit 266 uses information read from channels CH0, CH1, ..., CHn to perform decoding. The decoder in the ECC circuit 266 can be divided into a hard decision decoder and a soft decision decoder according to how many bits represent the information to be decoded. The hard decision decoder uses the memory unit output information represented by 1 bit to decode, and the 1 bit of information used at this time is called hard decision information. The soft decision decoder uses a more accurate memory unit output information composed of 2 bits or more bits, which is called soft decision information. The ECC circuit 266 can use hard decision information or soft decision information to correct errors included in the data.

[0138] According to an embodiment, to increase error correction capability, ECC circuit 266 may use a concatenated code that uses two or more codes. In addition, ECC circuit 266 may use a product code that divides a codeword into several rows and columns and applies a different relatively short ECC to each row and column.

[0139] According to an embodiment, the manager included in the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260 may be implemented with a general-purpose processor, an accelerator, a dedicated processor, a co-processor, a multi-core processor, etc. According to an embodiment, the manager may be implemented with firmware that works with the processor.

[0140] According to an embodiment, the memory device 150 is implemented as a nonvolatile memory such as a flash memory, for example, a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a magnetic RAM (MRAM), a NAND flash memory, a NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of a phase change random access memory (PCRAM), a resistance random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0141] Fig.10 A data storage system according to an embodiment of the present disclosure is shown. Fig.10A memory system including multiple cores or multiple processors is shown, which is an example of a data storage system. The memory system can support a high-speed non-volatile memory (NVMe) protocol.

[0142] NVMe is a transmission protocol designed for solid-state storage that runs much faster than traditional hard drives. NVMe can support higher input / output operations per second (IOPS) and lower latency, resulting in faster data transfer speeds and improved overall performance of data storage systems. Unlike SATA, which is designed for hard drives, NVMe can exploit the parallelism of solid-state storage to use multiple queues and processors (e.g., CPUs) more efficiently. NVMe is designed to allow the host to use multiple threads to achieve higher bandwidth. NVMe can take full advantage of the full parallelism provided by SSDs. However, due to limited firmware scalability, limited computing power, and high hardware contention within SSDs, memory systems may not be able to process a large number of I / O requests in parallel.

[0143] Reference Fig.10 , a host as an external device can be connected to the memory system through multiple PCIe Gen 3.0 channels, PCIe physical layer 412 and PCIe core 414. The controller 400 may include three embedded processors 432A, 432B, 432C, each embedded processor using two cores 302A, 302B. Herein, the multiple cores 302A, 302B or the multiple embedded processors 432A, 432B, 432C may have a pipeline structure.

[0144] The plurality of embedded processors 432A, 432B, 432C may be connected to an internal DRAM controller 434 via a processor interconnect. The controller 400 further includes a low density parity check (LDPC) sequencer 460, a direct memory access (DMA) engine 420, a high-speed scratchpad memory 450 for metadata management, and an NVMe controller 410. The components within the controller 400 may be connected to a plurality of channels connected to the plurality of memory packages 152 via a flash physical layer 440. The plurality of memory packages 152 may correspond to Fig. 9 Multiple memory chips 252 described in.

[0145] According to an embodiment, the NVMe controller 410 included in the controller 400 is a storage controller designed to be used with a solid-state drive (SSD) using an NVMe interface. The NVMe controller 410 can manage data transfer between the SSD and the computer CPU and other functions such as error correction, wear leveling, and power management. The NVMe controller 410 can use a simplified, low-overhead protocol to support fast data transfer rates.

[0146] According to an embodiment, the high-speed scratch pad memory 450 may be a storage area set by the NVMe controller 410 for temporarily storing data. The high-speed scratch pad memory 450 may be used to store data waiting to be written to multiple memory packages 152. The high-speed scratch pad memory 450 may also be used as a buffer to speed up the write process, typically using a small amount of dynamic random access memory (DRAM) or static random access memory (SRAM). When a write command is run, the data may be first written to the high-speed scratch pad memory 450 and then transferred to multiple memory packages 152 in larger blocks. The high-speed scratch pad memory 450 may be used as a temporary memory buffer to help optimize the write performance of multiple memory packages 152. The high-speed scratch pad memory 450 may be used as an intermediate memory for data before the data is written to the non-volatile memory unit.

[0147] The direct memory access (DMA) engine 420 included in the controller 400 is a component that transfers data between the NVMe controller 410 and the host memory in the host system without involving the processor of the host. The DMA engine 420 can support the NVMe controller 410 to read data directly from the host memory or write data to the host memory without the intervention of the host processor. According to an embodiment, the DMA engine 420 can use DMA descriptors to implement or support high-speed data transfer between the host and the NVMe device, and the DMA descriptor includes information about data transfer, such as buffer address, transfer length, and other control information.

[0148] A low-density parity check (LDPC) sequencer 460 in the controller 400 is a component that performs error correction on data stored in a plurality of memory packages 152. Herein, an LDPC code is an error correction code that is commonly used in NAND flash memories to reduce a bit error rate. The LDPC sequencer 460 may be designed to immediately process encoding and decoding of LDPC codes when reading data from and writing data to the NAND flash memory. According to an embodiment, the LDPC sequencer 460 may divide the data into a plurality of blocks, encode each block using an LDPC code, and store the encoded data in a plurality of memory packages 152. Thereafter, when the encoded data is read from the plurality of memory packages 152, the LDPC sequencer 460 may decode the encoded data based on the LDPC code and correct errors that may have occurred during a write operation or a read operation. The LDPC sequencer 460 may correspond to Fig. 9 ECC module 266 described in.

[0149] In addition, although Fig. 9 and Fig.10An example of a memory system including a memory device 150 or a plurality of memory packages 152 capable of storing data is shown, but a data storage system according to an embodiment of the present disclosure may not be limited to Fig. 9 and Fig.10 For example, the memory device 150, the plurality of memory packages 152, or the data storage device controlled by the controller 130, 400 may include a volatile or non-volatile memory device. Fig.10 , it is described that the controller 400 can communicate with the memory system (see Fig. 9 ) performs data communication with the host 102 outside. In an embodiment, the controller 400 may perform data communication with at least one host through a protocol such as a high-speed computing link (CXL).

[0150] In addition, according to an embodiment, the apparatus and method for executing distributed processing or allocation / redistribution of multiple instructions in a controller of a multiprocessor including a pipeline structure according to an embodiment of the present disclosure can be applied to a data processing system including multiple memory systems or multiple data storage devices. For example, a memory pool system (MPS) is a very general, adaptable, flexible, reliable and efficient memory management system, in which a memory pool, such as a logical partition of a main memory or a storage device reserved for processing a task or a group of tasks, can be used to control or manage a storage device connected to a controller. The controller of a multiprocessor including a pipeline structure can control the transfer of data and programs to a memory pool controlled or managed by the memory pool system (MPS).

[0151] Fig.11 A first example of a check and restore operation regarding an operation state of a switching transistor during a data input / output operation according to an embodiment of the present disclosure is shown.

[0152] Reference Figures 1 to 11 , the memory device 150 or the memory system 110 may receive a special program command (special PGM CMD) from the controller 130 or the host 102. In addition, the controller 130 or the host 102 may generate an erase command (erase CMD) and a general program command (normal PGM CMD).

[0153] like Figure 5 and Figure 6As described above, the memory device 150 may perform an erase operation corresponding to an erase command (erase CMD) during a first operating margin tERA_Margin1, and then check the operating state of the switch transistor and perform a recovery operation on the degraded switch transistor during the remaining time tERA_Margin1 of the first operating margin. In addition, the memory device 150 does not perform a check and recovery operation on the operating state of the switch transistor during an operating margin of a programming operation corresponding to a general programming command (normal PGM CMD). However, the memory device 150 may perform a check and recovery operation on the operating state of the switch transistor during an operating margin of a programming operation corresponding to a special programming command (special PGM CMD).

[0154] Reference Fig.11 , a specific memory block included in the memory device 150 may include four cell strings String0, String1, String2, and String3. Each cell string String0, String1, String2, and String3 may include a drain selection transistor DST, a source selection transistor SST, and an intermediate switch transistor CST. Figure 5 As described in, it may be difficult to perform inspection and recovery operations on the operating states of the drain selection transistor DST, the source selection transistor SST and the intermediate switching transistor CST included in each cell string String0, String1, String2, String3 during the first operating margin tERA_Margin1 corresponding to the erase command (erase CMD).

[0155] Reference Fig.11 , an inspection (e.g., reading) and recovery operation on the operation state of the drain selection transistor DST and the source selection transistor SST included in each cell string String0, String1, String2, String3 can be performed during the first operation margin tERA_Margin1 corresponding to the erase command (erase CMD). On the other hand, an inspection (i.e., reading) and recovery operation on the operation state of the intermediate switch transistor CST included in each cell string String0, String1, String2, String3 can be performed during the programming operation corresponding to the special programming command (special PGM CMD).

[0156] According to some embodiments Case1, Case2, and Case3, the target may be changed for the check and recovery operation on the operating state of the switch transistor performed during the first operating margin tERA_Margin1 corresponding to the erase command (erase CMD) and the operating margin of the program operation corresponding to the special program command (special PGM CMD). For example, in the first case Case1, the check and recovery operation on the operating state of the drain select transistor DST and the source select transistor SST may be performed during the first operating margin tERA_Margin1 corresponding to the erase command (erase CMD), and the check and recovery operation on the operating state of the middle switch transistor CST may be performed during the operating margin of the program operation corresponding to the special program command (special PGM CMD). In the second case Case2, the check and recovery operation on the operation state of the drain selection transistor DST and the middle switch transistor CST can be performed during the first operation margin tERA_Margin1 corresponding to the erase command (erase CMD), and the recovery operation on the operation state of the source selection transistor SST can be performed during the operation margin of the programming operation corresponding to the special programming command (special PGM CMD). In the third case Case3, the check and recovery operation on the operation state of the middle switch transistor CST and the source selection transistor SST can be performed during the first operation margin tERA_Margin1 corresponding to the erase command (erase CMD), and the check and recovery operation on the operation state of the drain selection transistor DST can be performed during the operation margin of the programming operation corresponding to the special programming command (special PGM CMD).

[0157] Reference Fig.11 , the memory device 150 may perform a check and recovery operation on the operation state of the switch transistor based on the position or type of the switch transistor included in each cell string String0, String1, String2, String3 during an operation margin set for a specific data input / output operation. The check and recovery operation on the operation state of the switch transistor may be performed individually based on a target (e.g., one of the switch transistors included in each cell string String0, String1, String2, String3).

[0158] Fig.12 A second example of the checking and restoring operation regarding the operating state of the switching transistor during the data input / output operation according to the embodiment of the present disclosure is shown.

[0159] Reference Figures 1 to 12, the memory device 150 or the memory system 110 may receive a special program command (special PGM CMD) from the controller 130 or the host 102. Further, the controller 130 or the host 102 may generate an erase command (erase CMD) and a general program command (normal PGM CMD).

[0160] like Fig.11 As described in, the memory device 150 may perform an erase operation during a first operation margin tERA_Margin1 corresponding to an erase command (erase CMD), and perform a check operation on the operating state of the switch transistor during the remaining time of the first operation margin tERA_Margin1. In addition, the memory device 150 does not perform a check and recovery operation on the operating state of the switch transistor during an operation margin of a program operation corresponding to a general program command (normal PGM CMD). However, the memory device 150 may perform a recovery operation on the operating state of the switch transistor during an operation margin of a program operation corresponding to a special program command (special PGM CMD).

[0161] Reference Fig.12 , a specific memory block included in the memory device 150 may include four cell strings String0, String1, String2, and String3. Each cell string String0, String1, String2, and String3 may include a drain selection transistor DST, a source selection transistor SST, and an intermediate switch transistor CST. Figure 5 As described in, it may be difficult to perform inspection and recovery operations on the operating states of the drain selection transistor DST, the source selection transistor SST and the intermediate switching transistor CST included in each cell string String0, String1, String2, String3 during the first operating margin tERA_Margin1 corresponding to the erase command (erase CMD).

[0162] Reference Fig.12 , the operation state of the drain selection transistor DST, the source selection transistor SST and the intermediate switch transistor CST included in each cell string String0, String1, String2, String3 can be checked during the first operation margin tERA_Margin1 corresponding to the erase command (erase CMD). On the other hand, the recovery operation of the drain selection transistor DST, the source selection transistor SST and the intermediate switch transistor CST included in each cell string String0, String1, String2, String3 can be performed during the operation margin of the programming operation in response to a special programming command (programming PGM CMD).

[0163] According to the embodiments Case1 and Case2, the target can be changed for the inspection and recovery operation of the operating state of the switching transistor performed during the first operating margin tERA_Margin1 corresponding to the erase command (erase CMD) and the operating margin set for the programming operation corresponding to the special programming command (special PGM CMD). For example, in the first case Case1, the inspection operation of the operating state of the drain select transistor DST, the source select transistor SST, and the middle switch transistor CST can be performed during the first operating margin tERA_Margin1 corresponding to the erase command (erase CMD). Then, the recovery operation of the drain select transistor DST, the source select transistor SST, and the middle switch transistor CST can be performed during the operating margin of the programming operation corresponding to the special programming command (special PGM CMD). In the second case Case2, the inspection (i.e., reading) and recovery operation of the operating state of the drain select transistor DST, the source select transistor SST, and the middle switch transistor CST can be performed during the operating margin of the programming operation corresponding to the special programming command (special PGM CMD).

[0164] Reference Fig.12 , the memory device 150 may divide the check and recovery operation on the operation state of the switch transistor included in each cell string String0, String1, String2, String3 into a plurality of unit operations. During the operation margin set for a plurality of specific data input / output operations, the plurality of unit operations may be performed separately. That is, the operation of checking (i.e., reading) the operation state of the switch transistor and recovering the operation state of the degraded switch transistor may be performed within the operation margin predetermined for performing a plurality of data input / output operations.

[0165] As described above, a memory device or a memory system according to an embodiment of the present disclosure may maintain and manage an operation state of a switching transistor coupled to a memory cell while reducing an influence on data input / output performance of the memory device or the memory system.

[0166] Further, the memory device or the memory system according to the embodiments of the present disclosure can reduce errors that may occur in data input / output operations.

[0167] Method, process and / or operation described herein can be performed by code or instruction, and these codes or instructions are to be operated by computer, processor, controller or other signal processing device.This computer, processor, controller or other signal processing device can be the device described herein or the element except the element described herein.Because the algorithm of the basis of the operation of formation method or computer, processor, controller or other signal processing device is described in detail, the code or instruction of the operation of implementation method embodiment can convert computer, processor, controller or other signal processing device into the special processor of execution method herein.

[0168] Moreover, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the above code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device, which may be detachably or fixedly coupled to a computer, processor, controller or other signal processing device for running the code or instructions for executing the method embodiments or operating the device embodiments herein.

[0169] For example, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented in, for example, non-transitory logic including hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits including, but not limited to, an application specific integrated circuit, a field programmable gate array, a combination of logic gates, a system on a chip, a microprocessor, or another type of processing or control circuit.

[0170] When implemented at least in part with software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic circuits, interfaces, decoders, drivers, and other signal generation and signal processing feature components may include, for example, memory or other storage devices, which are used to store, for example, codes or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be a device described herein or an element other than the elements described herein. Because the algorithm that forms the basis of the operation of the method or computer, processor, microprocessor, controller, or other signal processing device is described in detail, the code or instructions for implementing the operation of the method embodiment can convert the computer, processor, controller, or other signal processing device into a dedicated processor that performs the method described herein.

[0171] Although the present teaching has been shown and described with respect to a particular embodiment, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the concept and scope of the present disclosure as defined in the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: a cell array including a plurality of memory cells and a plurality of switch transistors; as well as A control circuit performs a check and restore operation on the operation states of the plurality of switch transistors during an operation margin set for a plurality of data input / output operations performed in the cell array.

2. The memory device of claim 1 , wherein the plurality of switch transistors comprises: at least one drain select transistor controlling connection between the plurality of memory cells and a bit line; at least one source select transistor controlling connection between the plurality of memory cells and a common source line; as well as At least one intermediate switch transistor is disposed between the plurality of memory cells.

3. The memory device of claim 2, wherein the at least one intermediate switch transistor is disposed between two vertically stacked portions, each vertically stacked portion including at least some of the plurality of memory cells.

4. The memory device of claim 1 , wherein the plurality of data input / output operations comprises: one or more erase operations for erasing remaining data in the plurality of memory cells; as well as One or more programming operations are used to program data in the plurality of memory cells. 5 . The memory device of claim 4 , wherein the control circuit performs the check operation during an operation margin set for the one or more erase operations, and performs the recovery operation during an operation margin set for the one or more program operations.

6. The memory device of claim 4, wherein the control circuit performs the checking and recovery operations during an operation margin of a plurality of programming operations. 7 . The memory device of claim 1 , wherein the control circuit divides the check and restore operation into a plurality of unit operations based on positions of the plurality of switch transistors. 8 . The memory device according to claim 7 , wherein the control circuit performs the unit operation on each of the plurality of switch transistors during the operation margin set for each of the plurality of data input / output operations.

9. The memory device of claim 7, wherein the control circuit performs the unit operation on a single switch transistor during the operation margin set for the plurality of data input / output operations. 10 . The memory device according to claim 1 , further comprising a buffer storing position information of a degraded switch transistor among the plurality of switch transistors. 11 . The memory device according to claim 10 , wherein the control circuit generates a switching transistor recovery command including the position information, and one of the plurality of data input / output operations is performed in the cell array based on the position information.

12. The memory device according to claim 1, wherein the control circuit generates a control signal for the checking operation when an erase command is input.

13. The memory device according to claim 1, wherein the control circuit generates a control signal for the recovery operation when a program command is input.

14. A memory system comprising: A memory device comprising a plurality of memory cells and a plurality of switch transistors; as well as A controller generates a program command for performing a program operation on the plurality of memory cells based on whether a check and restore operation with respect to an operation state of the plurality of switch transistors is performed.

15. The memory system of claim 14, wherein the program command is one of the following: a first program command for executing the program operation and the check and restore operation; and The second program command is used to execute only the program operation without executing the check and restore operation. 16 . The memory system of claim 15 , wherein the controller generates the first program command based on program data to be programmed in the plurality of memory cells of the cell array as part of multi-bit data during the program operation.

17. The memory system of claim 14, wherein the controller: generating an erase command for an erase operation for erasing data remaining in the plurality of memory cells and a check operation for checking operation states of the plurality of switch transistors; and Program commands for the program operation and a recovery operation for recovering an operation state of a degraded switching transistor among the plurality of switching transistors are generated.

18. The memory system of claim 14, wherein the plurality of switch transistors comprises: at least one drain select transistor controlling connection between the plurality of memory cells and a bit line; at least one source select transistor controlling connection between the plurality of memory cells and a common source line; as well as At least one intermediate switch transistor is disposed between the plurality of memory cells.

19. A memory system comprising: A memory device comprising a plurality of memory cells and a plurality of switch transistors; as well as A controller transmits a plurality of data input / output commands to the memory device, the plurality of data input / output commands being designed for the memory device to perform a check and restore operation for checking and restoring the operating states of the plurality of switch transistors during a plurality of data input / output operations performed based on the plurality of data input / output commands. 20 . The memory system of claim 19 , wherein the plurality of data input / output commands include a program command for the memory device to perform a program operation for programming data in the memory device and the check and restore operation.

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