Method of operating memory, memory and memory system

Abstract

The present disclosure provides a memory operation method, a memory and a memory system, relating to the technical field of memory, aiming to solve the problem of how to shorten the programming time. The method comprises: performing a plurality of first programming verification operations on a plurality of storage units of the memory to obtain a plurality of storage units in a first programming state to an i-th programming state, i being a positive integer, and in the first programming verification operation, whether to perform the first programming verification operation of the next programming state is determined based on whether a first verification result reaches a first preset value, and the first verification result comprises the number of storage units in the current programming state. The second programming verification operation is performed on the storage units in the n-th programming state to obtain a second verification result of the storage units in the n-th programming state, n being a positive integer. If the second verification result of the storage units in the n-th programming state is greater than or equal to a second preset value, the second programming verification operation is performed on the storage units in the n+1-th programming state, and the second preset value and the first preset value are different.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to a method for operating a memory, a memory, and a memory system. Background Technology

[0002] NAND flash memory is a non-volatile storage technology, meaning it retains data even after power is off, offering advantages such as low storage cost and high storage capacity. Existing NAND flash memory chips typically use incremental steppulse programming (ISPP) to program the memory cells, employing progressively increasing programming voltages. Each programming pulse is followed by a corresponding verification pulse to check whether the memory cell's threshold voltage has reached the target value.

[0003] As the number of bits stored in a memory cell increases, the programming time also increases. The number of programming pulses applied and the number of programming verification operations performed are crucial factors determining programming time. Therefore, how to reduce programming time while ensuring programming quality has become an urgent problem to be solved. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for operating a memory, a memory, and a memory system, aimed at solving the problem of how to shorten programming time.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions.

[0006] Firstly, a method for operating a memory is provided. This method includes: performing multiple first programming verification operations on multiple memory cells of the memory to obtain multiple memory cells in programming states 1 to ith, where i is a positive integer; in each of the first programming verification operations, determining whether to perform a first programming verification operation in the next programming state based on whether the first verification result reaches a first preset value; the first verification result includes the number of memory cells in the current programming state; performing a second programming verification operation on the memory cells in the nth programming state to obtain a second verification result for the memory cells in the nth programming state, where n is a positive integer; and performing a second programming verification operation on the memory cells in the (n+1)th programming state if the second verification result of the memory cells in the nth programming state is greater than or equal to a second preset value, where the second preset value is different from the first preset value.

[0007] The memory operation method provided in the above embodiments of this disclosure employs a two-step programming approach, including coarse programming and fine programming. In coarse programming, a first programming verification operation for the next programming state is determined based on a first preset value. In fine programming, a second programming verification operation for the next programming state is determined based on a second preset value. Compared to using the same preset value for both coarse and fine programming, the memory operation method provided in this application uses different preset values ​​for coarse and fine programming. This reduces the impact of coarse programming on fine programming, thereby reducing the number of verification operations in fine programming and reducing programming time.

[0008] In some embodiments, before performing a second programming verification operation on the memory cell in the nth programming state to obtain a second verification result of the memory cell in the nth programming state, the method further includes: obtaining a pre-verification result of the memory cell in the nth programming state based on the verification voltage of the second programming verification operation.

[0009] In these embodiments, the pre-verification result is the number of memory units that have reached the nth programming state after coarse programming is completed. The pre-verification result can be understood as the impact of coarse programming on fine programming. Based on the pre-verification result, the value of the second preset value in fine programming can be adjusted, thereby reducing the verification operation of fine programming and reducing programming time.

[0010] In some embodiments, the second verification result includes the number of storage units in the nth programming state, and the second preset value is greater than the first preset value.

[0011] In these embodiments, if the second verification result includes the number of storage units in the nth programming state, it is equivalent to the second verification result including the impact of coarse programming on fine programming. In this case, the second preset value is greater than the first preset value, which can reduce the impact of coarse programming on fine programming, thereby reducing the verification operation of fine programming and reducing programming time.

[0012] In some embodiments, the second verification result includes the number of memory cells in the nth programming state, excluding the number of memory cells corresponding to the pre-verification result, and the second preset value is less than the first preset value.

[0013] In these embodiments, if the second verification result does not include the number of storage units in the nth programming state, it is equivalent to the second verification result having already proposed the impact of coarse programming on fine programming. In this case, the second preset value is less than the first preset value, which can reduce the impact of coarse programming on fine programming, thereby reducing the verification operation of fine programming and reducing programming time.

[0014] In some embodiments, performing multiple first programming verification operations on multiple memory cells of the memory to obtain multiple memory cells in the first programming state to the i-th programming state includes: performing a first programming verification operation on the memory cell in the m-th programming state to obtain a first verification result of the memory cell in the m-th programming state, where m is a positive integer. If the first verification result of the memory cell in the m-th programming state is greater than or equal to a first preset value, performing a first programming verification operation on the memory cell in the (m+1)-th programming state. If the first verification result of the memory cell in the m-th programming state is less than the first preset value, performing a first programming verification operation on the memory cell in the m-th programming state. If the first verification result obtained by performing a first programming verification operation on the memory cell in the highest programming state is greater than or equal to the first preset value, multiple memory cells in the first programming state to the i-th programming state are obtained.

[0015] In these embodiments, based on the comparison result of the first verification result of the storage unit of the m-th programming state with the first preset value, it is determined whether to continue the first programming verification operation of the current programming state or to perform the first programming verification operation of the next programming state. The start time of each programming state to be verified can be dynamically determined, which can improve the accuracy of the determined start time of each programming state to be verified and reduce the number of verifications to shorten the programming time.

[0016] In some embodiments, the step size of the plurality of programming pulses in the first programming verification operation is greater than the step size of the plurality of programming pulses in the second programming verification operation.

[0017] In these embodiments, multiple first programming verification operations can be understood as coarse programming, and multiple second programming verification operations can be understood as fine programming. The memory operation method provided in this application first performs coarse programming to quickly reach different programming states and improve programming speed, and then performs fine programming to obtain better programming quality and shorten programming time.

[0018] In some embodiments, if the second verification result of the storage cell in the nth programming state is less than the second preset value, a second programming verification operation is performed on the storage cell in the nth programming state.

[0019] In these embodiments, if the second verification result is less than the second preset value, it indicates that only a small number of memory cells have reached the nth programming state. Therefore, it can be predicted that after applying the next programming pulse, almost no memory cells with a target programming state of n+1 will be able to reach the n+1 programming state. In this case, there is no need to perform the second programming verification operation on the memory cells in the n+1 programming state. This reduces the number of second programming verification operations, which helps to shorten programming time and reduce the number of pending second verification results, thus improving programming efficiency.

[0020] In some embodiments, the method further includes: obtaining a first number of times the first programming verification operation is performed, and determining a first preset value based on the first number; obtaining a second number of times the second programming verification operation is performed, and determining a second preset value based on the second number.

[0021] In these embodiments, by obtaining the number of programming verification operations and determining the preset value based on the number of operations, the programming characteristics that change with the number of iterations can be tracked in the programming verification operations. The range of the preset value can be flexibly adjusted, reducing the slow programming speed caused by improper determination of the preset value, which is conducive to improving programming speed and ensuring programming quality.

[0022] Secondly, a memory is provided, comprising: a memory cell array including multiple memory cells; peripheral circuitry coupled to the memory cell array, the peripheral circuitry being configured to: perform multiple first programming verification operations on the multiple memory cells of the memory to obtain multiple memory cells in programming states 1 to ith, where i is a positive integer; in the first programming verification operations, based on whether the first verification result reaches a first preset value, determine whether to perform a first programming verification operation in the next programming state; the first verification result includes the number of memory cells in the current programming state; perform a second programming verification operation on the memory cells in the nth programming state to obtain a second verification result for the memory cells in the nth programming state, where n is a positive integer; if the second verification result of the memory cells in the nth programming state is greater than or equal to a second preset value, perform a second programming verification operation on the memory cells in the (n+1)th programming state, where the second preset value is different from the first preset value.

[0023] For the benefits of the second aspect, please refer to the explanation of the first aspect.

[0024] In some embodiments, the peripheral circuitry is further configured to: acquire the pre-verification result of the memory cell in the nth programming state based on the verification voltage of the second programming verification operation.

[0025] In some embodiments, the second verification result includes the number of storage units in the nth programming state, and the second preset value is greater than the first preset value.

[0026] In some embodiments, the second verification result includes the number of memory cells in the nth programming state, excluding the number of memory cells corresponding to the pre-verification result, and the second preset value is less than the first preset value.

[0027] In some embodiments, the peripheral circuit is further configured to: perform a first programming verification operation on the memory cell of the m-th programming state to obtain a first verification result of the memory cell of the m-th programming state, where m is a positive integer. If the first verification result of the memory cell of the m-th programming state is greater than or equal to a first preset value, perform a first programming verification operation on the memory cell of the (m+1)-th programming state. If the first verification result of the memory cell of the m-th programming state is less than the first preset value, perform a first programming verification operation on the memory cell of the m-th programming state. If the first verification result obtained by performing the first programming verification operation on the memory cell of the highest programming state is greater than or equal to the first preset value, a plurality of memory cells from the 1st programming state to the 1st programming state are obtained.

[0028] In some embodiments, the step size of the plurality of programming pulses in the first programming verification operation is greater than the step size of the plurality of programming pulses in the second programming verification operation.

[0029] In some embodiments, the peripheral circuit is further configured to perform a second programming verification operation on the memory cell of the nth programming state if the second verification result of the memory cell in the nth programming state is less than a second preset value.

[0030] In some embodiments, the peripheral circuitry is further configured to: acquire a first number of times the first programming verification operation is performed, and determine a first preset value based on the first number; acquire a second number of times the second programming verification operation is performed, and determine a second preset value based on the second number.

[0031] Thirdly, a memory system is provided, the memory system comprising: one or more memories of the second aspect, and a memory controller coupled to the memories and configured to control the memories.

[0032] It is understood that the beneficial effects of the memory operation method, memory and memory system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0034] Figure 1 A threshold voltage distribution diagram of the current programming state is provided for an embodiment of this application;

[0035] Figure 2 A schematic diagram of the structure of an exemplary system S1 having a storage system 10 provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram of a memory card provided in an embodiment of this application;

[0037] Figure 4 A schematic diagram of another memory card provided in an embodiment of this application;

[0038] Figure 5 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0039] Figure 6 A flowchart illustrating a memory operation method provided in an embodiment of this application;

[0040] Figure 7 A threshold voltage distribution diagram for the nth programming state is provided in an embodiment of this application;

[0041] Figure 8 Another threshold voltage distribution diagram for the nth programming state provided in this application embodiment;

[0042] Figure 9 This is a flowchart illustrating a rough programming of a memory according to an embodiment of this application. Detailed Implementation

[0043] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0044] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "multiple" means two or more. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0047] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0048] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0049] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0050] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0051] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0052] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0053] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0054] In the development of NAND memory, early NAND memory chips mostly used single-level cells (SLC), meaning that one memory cell stores 1 bit of data. At this time, each memory cell has two states, specifically 0 and 1.

[0055] With the development of NAND flash memory, the storage cells of NAND flash memory chips have gradually evolved from single-level cells to multi-level cells (MLC), where one storage cell stores 2 bits of data. Then came triple-level cells (TLC), where one storage cell stores 3 bits of data. Even quad-level cells (QLC) were introduced, where one storage cell stores 4 bits of data. Correspondingly, the number of states of NAND flash memory chips has increased from 2 to 4, 8, and even 16.

[0056] NAND storage cells can have 2 n There are 2 states, where n is the number of bits that a storage unit can store. For example, an SLC storage unit can have 2 states, an MLC storage unit can have 4 states, a TLC storage unit can have 8 states, and a QLC storage unit can have 16 states. n The state can include one erase state and 2. n -1 programming state. NAND memory can be programmed and / or read from page by page. During the programming operation, the NAND memory cell is programmed to have 2 n Each state is represented, and n bits of data are written into the NAND memory cell as one of these states. The programming operation of NAND memory is divided into three steps, such as pressure programming (i.e., applying programming pulses), program verify (PV), and scanning verification results.

[0057] For NAND memory, programming time (t) PROG Programming quality (e.g., maintaining the read budget window) is a crucial metric for NAND flash memory performance. Therefore, improving programming speed and reducing programming time while ensuring programming quality is paramount. Since the duration of the applied programming pulses cannot be changed, the number of programming pulses applied, the number of programming verifications, the time spent on each verification, and the time spent scanning the verification results are all significant factors determining programming time. For example, in a QLC (Quick Low Voltage) memory cell, the time spent on programming verification for 15 states accounts for more than half of the total programming time; therefore, reducing the time spent on programming verification for each state is critical to improving programming time.

[0058] Therefore, a programming verification method is proposed, where each programming verification state includes a corresponding start time. Taking a TLC memory cell as an example, a TLC memory cell has one erase state and seven programming states, which are denoted as L1, L2, L3, L4, L5, L6, and L7 respectively, from state 1 to state 7. As shown in Table 1, Table 1 is a table of programming verification operations and start times for different programming states. Here, PV1 represents the programming verification operation performed on state 1 (L1), PV2 represents the programming verification operation performed on state 2 (L2), and so on.

[0059] Table 1

[0060] Programmatic verification (PV) Start time (start loop) PV1 1 PV2 3 PV3 4 PV4 5 PV5 7 PV6 9 PV7 11

[0061] The start time of the programming verification operation can be defined by which programming pulse the operation begins after. For example, a start time of 1 for the programming verification operation of state 1 means that programming verification of state 1 begins after the application of the first programming pulse and before the application of the second programming pulse.

[0062] Compared to performing programming verification on each state after each programming pulse, the above programming verification method reduces the number of verifications to some extent. However, differences in programming characteristics can occur when different units are being programmed simultaneously. Setting the same start time for all dies, blocks, or word lines (WL) for each state still introduces errors. Furthermore, this method, which determines the start time of verification for each state by the number of programming pulse loops, cannot adapt to the different programming speeds of memory cells in different program / erase cycles. Since the end of life (EOL) is faster than the beginning of life (BOL), the programming verification time is set earlier to ensure proper programming of the EOL and avoid over-programming.

[0063] To reduce programming time, a dynamic program verifystart (DPVS) algorithm is proposed. This algorithm determines whether to start verification in the next programming state based on the number of successful pass cells in the current state. By adapting the programming speed of pass cells, the verification time overhead can be reduced.

[0064] Taking QLC NAND flash memory as an example, a 16-16 two-pass programming scheme is commonly used. This scheme reduces the coupling effect between adjacent word lines (WLs). The two-pass programming scheme includes coarse programming and fine programming. Furthermore, the programming operation first performs coarse programming, followed by fine programming, and the DPVS algorithm is applied in both. The number of verifications for coarse programming is shown in Table 2, and the number of verifications for fine programming is shown in Table 3.

[0065] Table 2

[0066] frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p1 √ √ √ √ √ √ √ p2 √ √ √ √ √ √ √ √ p3 √ √ √ √ √ p4 √ √ √ √ √ p5 √ √ √ √ p6 √ √ √ √ p7 √ √ √ √ p8 √ √ √ √ p9 √ √ √ √ p10 √ √ √ √ p11 √ √ √ √ p12 √ √ √ √ √ p13 √ √ √ √ √ p14 √ √ √ √ √ p15 √ √ √ √ √

[0067] Table 3

[0068] frequency 1 2 3 4 5 6 7 8 9 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p1 √ √ √ √ √ √ √ √ p2 √ √ √ √ √ √ √ √ √ √ √ p3 √ √ √ √ √ √ √ √ √ √ √ p4 √ √ √ √ √ √ √ √ √ p5 √ √ √ √ √ √ √ √ √ √ p6 √ √ √ √ √ √ √ √ √ √ √ p7 √ √ √ √ √ √ √ √ √ √ p8 √ √ √ √ √ √ √ √ √ √ √ p9 √ √ √ √ √ √ √ √ √ √ p10 √ √ √ √ √ √ √ √ √ p11 √ √ √ √ √ √ √ √ p12 √ √ √ p13 √ p14 p15

[0069] Table 3 (continued)

[0070]

[0071]

[0072] As can be seen from Tables 2 and 3, when both DPVS algorithms are applied, the number of verifications for fine programming is greater than that for coarse programming. Furthermore, after coarse programming and before fine programming begins, the memory cells are roughly distributed within their respective threshold voltage ranges. If the determination of whether to start the next programming state verification is based on the number of successful memory cells in the current state, fine programming will be affected by coarse programming, increasing the number of verifications required for fine programming.

[0073] like Figure 1 As shown, Figure 1 This application provides a threshold voltage distribution diagram for a current programming state, as illustrated in an embodiment. Figure 1 The diagram shows the threshold voltage distribution plots for the final coarse programming of the current state, and the threshold voltage distribution plots for the final fine programming of the current state. From... Figure 1 As can be seen, after completing the coarse programming of the current state and before starting the fine programming of the current state, the number of memory cells obtained based on the verification voltage of the fine programming includes the number of memory cells that reached the current state during coarse programming. If the number of memory cells is used to determine whether to perform the verification operation of the next programming state during fine programming, the number of verifications in fine programming will increase.

[0074] Therefore, this application provides a memory operation method that employs a two-step programming approach, including coarse programming and fine programming. In coarse programming, a first programming verification operation for the next programming state is determined based on a first preset value. In fine programming, a second programming verification operation for the next programming state is determined based on a second preset value. Compared to using the same preset value for both coarse and fine programming, the memory operation method provided in this application uses different preset values ​​for coarse and fine programming, which can reduce the impact of coarse programming on fine programming, thereby reducing the number of verification operations in fine programming and reducing programming time.

[0075] For ease of understanding, the storage system to which the memory operation method provided in the embodiments of this application is applied will be introduced below.

[0076] like Figure 2 As shown, Figure 2 This is a schematic diagram of an exemplary system S1 with a storage system 10 provided for embodiments of this disclosure. System S1 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Storage system 10 (also referred to as a NAND memory system) includes a memory 101 and a controller 102. Storage system 10 can communicate with host computer 20 via controller 102, wherein controller 102 can be coupled to memory 101 via memory channel 30. In some embodiments, memory 101 in this disclosure can be a three-dimensional non-volatile memory, such as NAND flash memory, which can also be simply referred to as flash memory or NAND memory. Of course, memory 101 in this disclosure can also be other types of memory. Storage system 10 can have more than one memory 101, and each memory 101 can be managed by controller 102.

[0077] In some embodiments, the host computer 20 may be a processor of an electronic device, such as a central processing unit (CPU), a system-on-chip (SoC), or an application processor (AP). The host computer 20 may send data to be stored in the storage system 10 or read data stored in the storage system 10.

[0078] The controller 102 can process input / output (I / O) requests received from the host computer 20, ensure data integrity and effective storage, and also manage the memory 101. The memory channel 30 can provide data via the data bus and control communication between the controller 102 and the memory 101.

[0079] Continue to refer to Figure 2 The memory 101 can be a memory chip (package), a memory die, or any part of a memory die, and can include one or more memory planes 1011, each memory plane 1011 including multiple memory blocks 10111. The same and concurrent operations can occur at each memory plane 10111. The size of a memory block 10111 can be a megabyte (MB), and a memory block 10111 is the smallest unit for performing an erase operation. Figure 1 The memory 101 in the example includes four memory surfaces 1011, and each memory surface 1011 includes six memory blocks 10111. Each memory block 10111 may include multiple memory cells, wherein each memory cell can be addressed by means of bit lines (BLs) and word lines (WLs). The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The orientation of the bit lines and word lines is... Figure 1 The blocks 10111 are designated as “BL” and “WL”, respectively. In this disclosure, one or more memory blocks 10111 may also be referred to as a “memory array” or “array”. A memory array is a core area within a memory device that performs storage functions.

[0080] The memory 101 also includes a peripheral circuitry region 1012, which is the peripheral area of ​​the memory surface 1011. The peripheral circuitry region 1012 (also referred to as peripheral circuitry) contains numerous digital, analog, and / or mixed-signal circuits (e.g., page buffer / sensor amplifier 10121, row decoder / word line driver 10122, column decoder / bit line driver 10123, and peripheral control circuitry 10124) to support the functionality of the memory 101. The peripheral control circuitry 10124 may include registers, active and / or passive semiconductor devices, such as transistors, diodes, capacitors, or resistors. The peripheral control circuitry 10124 of the peripheral circuitry region 1012 can be configured to initiate programming operations on selected memory cells in the NAND flash memory string within the memory block 10111. In some embodiments, the peripheral control circuit 10124 receives programming commands from the controller 102 via an interface, and in response, sends control signals to the row decoder / word line driver 10122, column decoder / bit line driver 10123, and voltage generator located in the peripheral circuit area 1012. Figure 2(not shown in the image) to initiate programming operations on the selected memory cell.

[0081] Notice, Figure 2 The layout of the electronic devices in the storage system 10 and memory 101 is shown as an example. The storage system 10 and memory 101 may have other layouts and may include additional devices. For example, memory 101 may also include a high-voltage charge pump, input / output circuitry, etc. Storage system 10 may also include firmware and a data scrambler, etc. In some embodiments, the peripheral circuitry region 1012 and the memory array may be formed independently on separate wafers and interconnected by wafer bonding.

[0082] The controller 102 and one or more memories 101 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package. That is, the storage system 10 can be implemented and packaged into different types of terminal electronic products. Figure 3 In one example shown, controller 102 and a single memory 101 can be integrated into memory card 40. Memory card 40 may include Personal Computer Memory Card International Association (PCMCIA), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD card), or UFS, etc. Memory card 40 may also include memory card connector 41 that couples memory card 40 to host computer 20. Figure 4 In another example shown, the controller 102 and multiple memories 101 may be integrated into a solid-state drive (SSD) 50. The SSD 50 may also include an SSD connector 51 that couples the SSD 50 to the host computer 20.

[0083] like Figure 5 As shown, Figure 5This is a schematic diagram of the structure of a memory 101 provided in an embodiment of the present disclosure. The memory 101 includes one or more memory blocks 10111. Each memory block 10111 includes a memory string 60. Each memory string 60 includes memory cells 601. Memory cells 601 sharing the same bit line form a memory string 60. The memory string 60 may also include at least one field-effect transistor (e.g., a metal-oxide-semiconductor field-effect transistor, MOSFET) at each end, which is controlled by a top select gate (TSG) 71 and a bottom select gate (BSG) 72, respectively. The drain terminal of the top select gate 71 may be connected to a bit line 80, and the source terminal of the bottom select gate 72 may be connected to an array common source (ACS) 82. The ACS 82 may be shared by the memory strings 60 throughout the memory block 10111 and is also referred to as the source line (SL).

[0084] In some embodiments, the peripheral circuitry region 1012 of memory 101 may support GIDL-assisted erase operations. Memory block 10111 may be coupled to row decoder / word line driver 10122 via word line 81, bottom select gate 72, and top select gate 71. Memory block 10111 may be coupled to page buffer / sensor amplifier 10121 via bit line 80. Row decoder / word line driver 10122 may select one of the memory blocks 10111 on memory 101 in response to an X-path control signal provided by peripheral control circuitry 10124. Row decoder / word line driver 10122 may pass a voltage provided from voltage generator 90 to word line 81 according to the X-path control signal. During read and program operations, row decoder / word line driver 10122 may pass a read voltage Vread and a programmable voltage Vpgm to the selected word line 81 according to the X-path control signal received from peripheral control circuitry 10124, and pass a voltage Vpass to the unselected word line 81.

[0085] The column decoder / bit line driver 10123 can transmit a suppressor voltage Vinhibit to the non-selectable line and connect the selectable line 80 to ground based on the Y-path control signal received from the peripheral control circuit 10124. That is, the column decoder / bit line driver 10123 can be configured to select or deselect one or more memory strings 60 based on the Y-path control signal from the peripheral control circuit 10124. The page buffer / sensor amplifier 10121 can be configured to read data from and program (write) data to the memory block 10111 based on the Y-path control signal from the peripheral control circuit 10124. For example, the page buffer / sensor amplifier 10121 can store a page of data to be programmed into a memory page. In another example, the page buffer / sensor amplifier 10121 can perform a verification operation to ensure that data has been correctly programmed into each memory cell 601. In yet another example, during a read operation, the page buffer / sensor amplifier 10121 can sense the current flowing through bit line 80 that reflects the logic state (i.e., data) of memory cell 601, as well as the amplification factor that amplifies small signals to measurable signals.

[0086] The input / output buffer 91 can transmit I / O data from / to the page buffer / sensor amplifier 10121, and transmit address ADDR signals or command CMD signals to the peripheral control circuitry 10124. In some embodiments, the input / output buffer 91 can serve as an interface between the controller 102 and the memory 101.

[0087] Peripheral control circuitry 10124 can control page buffer / sensor amplifier 10121 and row decoder / word line driver 10122 in response to command CMD transmitted from input / output buffer 91. During programming operations, peripheral control circuitry 10124 can control row decoder / word line driver 10122 and page buffer / sensor amplifier 10121 to program selected memory cell 601. During read operations, peripheral control circuitry 10124 can control row decoder / word line driver 10122 and page buffer / sensor amplifier 10121 to read selected memory cell 601. X-path control signals include row address X-ADDR, and Y-path control signals include column address Y-ADDR, which can be used to locate selected memory cell 601 in memory block 10111. Row address X-ADDR can include page index, block index, and face index to identify memory page, memory block 10111, and memory face 1011, respectively. Column address Y-ADDR can identify a byte or word in the data of a memory page.

[0088] In some implementations, the peripheral control circuitry 10124 may include one or more control logic units. Each control logic unit described herein may include a software module and / or firmware module running on a processor, such as a microcontroller unit (MCU) as part of the peripheral control circuitry 10124, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC), such as an application-specific IC (ASIC), a field-programmable gate array (FPGA), or a combination of software modules, firmware modules, and hardware modules.

[0089] The voltage generator 90 can generate voltages for the word line 81 and the bit line 80 under the control of the external control circuit 10124. The voltages generated by the voltage generator 90 include the read voltage Vread, the programming voltage Vpgm, the pass voltage Vpass, and the inhibit voltage Vinhibit.

[0090] In some embodiments, the memory 101 may be formed based on floating gate technology. In some embodiments, the memory 101 may be formed based on charge trapping technology. The charge trapping-based memory 101 can provide high storage density and high intrinsic reliability. The stored data or logic state (e.g., the threshold voltage Vth of the memory cell 601) depends on the amount of charge trapped in the storage layer. In some embodiments, the memory 101 may be a three-dimensional (3D) memory device, wherein the memory cells 601 may be vertically stacked on top of each other.

[0091] In some embodiments, during an erase operation, a negative voltage difference is applied between the gate and source terminals (e.g., ACS82) of 601, allowing all trapped electron charges in the storage layer of memory cell 601 to be removed, and all memory cells 601 in the same storage block 10111 can be reset to the erase state ER as logic "1". For example, this voltage difference can be induced by setting the control gate in memory cell 601 to ground and applying a positive voltage to the source line 82. In this example, a voltage pulse can be applied to memory cell 601 during the erase operation.

[0092] Applied to the memory described above, embodiments of this application provide a method for operating the memory, such as... Figure 6 As shown, Figure 6 This is a flowchart illustrating a method for operating a memory according to an embodiment of this application. The method for operating the memory includes the following steps.

[0093] S601. The memory performs multiple first programming verification operations on multiple memory cells to obtain multiple memory cells from the first programming state to the i-th programming state, where i is a positive integer. In the first programming verification operation, it is determined whether to execute the first programming verification operation of the next programming state based on whether the first verification result reaches the first preset value. The first verification result includes the number of memory cells in the current programming state.

[0094] For example, the memory may include a memory array consisting of multiple memory cells, and the memory cells may include single-level cells, multi-level cells, three-level cells, four-level cells, or cells with a higher number of levels.

[0095] The storage operation method provided in this application adopts a two-step programming approach. Taking QLC NAND as an example, the number of programming states of the memory can be 15, i.e., i = 15. That is, in the coarse programming, multiple first programming verification operations are performed on multiple memory cells to obtain multiple memory cells in programming states 1 to 15. Among them, the memory cells in programming states 1 to 15 are widely distributed memory cells.

[0096] The first verification result includes the number of storage units in the current programming state. In addition, the first verification result may also include a first type of indication information indicating whether each storage unit has been successfully programmed, and a second type of indication information indicating whether each storage unit has failed to be programmed.

[0097] In this process, the step size of the programming pulses in the first programming verification operation is larger than that in the second programming verification operation. Therefore, the first programming verification operation can be understood as coarse programming, and the second programming verification operation as fine programming. Both coarse and fine programming can employ incremental steppulse programming (ISPP), with the step size of coarse programming being larger than that of fine programming. The memory first performs coarse programming to quickly reach different programming states, improving programming speed, and then performs fine programming to achieve better programming quality and shorten programming time.

[0098] The first programming verification operation may include a first programming operation and a first verification operation. The first programming operation can be understood as applying a first programming pulse to the memory cell, and the first verification operation can be understood as applying a first verification voltage to the memory cell. Based on the first verification voltage of the current programming state, the number of memory cells that have reached the current programming state can be obtained.

[0099] S602. The memory performs a second programming verification operation on the memory cell of the nth programming state to obtain the second verification result of the memory cell of the nth programming state, where n is a positive integer. Specifically, n should be a positive integer less than i.

[0100] For example, the second programming verification operation may include a second programming operation and a second verification operation. The second programming operation can be understood as applying a second programming pulse to the memory cell, and the second verification operation can be understood as applying a second verification voltage to the memory cell. The number of memory cells that have reached the current programming state can be obtained based on the second verification voltage of the current programming state.

[0101] Specifically, the memory applies a second programming pulse to the memory cell in the nth programming state, and obtains a second verification result for the memory cell that has reached the nth programming state based on the second verification voltage of the nth programming state. The second verification result is the number of successful bits programmed into the nth programming state. In addition, the second verification result may also include a first type of indication information indicating whether each verified memory cell has been successfully programmed, and a second type of indication information indicating whether each verified memory cell has failed to be programmed.

[0102] S603. If the second verification result of the storage unit in the nth programming state is greater than or equal to the second preset value, the memory performs a second programming verification operation on the storage unit in the (n+1)th programming state. The second preset value is different from the first preset value.

[0103] For example, if the second verification result is greater than or equal to the second preset value, it indicates that a large number of memory cells have reached the nth programming state. Therefore, it can be predicted that after applying the next programming pulse, there will be memory cells with a target programming state of n+1 that can reach the n+1th programming state. Thus, after applying the next programming pulse, a second programming verification operation needs to be performed on the n+1th programming state. This reduces the occurrence of overprogramming and improves programming quality.

[0104] For example, compared to coarse programming and fine programming using the same preset values, the first preset value and the second preset value in the memory operation method provided in this application embodiment are different. Therefore, the influence of the number of successful memory cells that already exist after coarse programming can be eliminated in fine programming, reducing the number of verifications in fine programming.

[0105] Optionally, the memory operation method further includes: if the second verification result of the storage cell in the nth programming state is less than the second preset value, the memory performs a second programming verification operation on the storage cell in the nth programming state.

[0106] For example, if the second verification result is less than the second preset value, it indicates that no memory cells or only a small number of memory cells have reached the nth programming state. Therefore, it can be predicted that after applying the next programming pulse, almost no memory cells with the target programming state being the (n+1)th programming state will be able to reach the (n+1)th programming state; that is, the (n+1)th programming state will not be successfully programmed. Thus, after applying the next encoding pulse, there is no need to perform a second programming verification operation on the (n+1)th programming state. This reduces the number of programming states that need to be verified in the next second programming verification operation, which helps to shorten the programming verification time, reduce the number of verification results to be processed, and improve programming efficiency.

[0107] In another implementation, the second verification result can also be the number of failed bits in programming the nth programming state. If the second verification result is less than a third preset value, it is determined that a second programming verification operation will be performed on the memory cell of the (n+1)th programming state. If the second verification result is greater than or equal to the third preset value, it is determined that a second programming verification operation will be performed on the memory cell of the nth programming state.

[0108] For example, binary encoding can be used to indicate whether a memory cell has been successfully programmed. For instance, 0 can represent successful programming and 1 can represent unsuccessful programming. Alternatively, 0 can represent unsuccessful programming and 1 can represent successful programming. In implementation, those skilled in the art can choose an appropriate method to represent whether a memory cell has been successfully programmed based on the actual situation, and this disclosure does not limit this approach.

[0109] Understandably, when the number of failure bits during programming the nth programming state is less than the third preset value, the programming of the nth programming state can be considered successful. Therefore, in the next second programming verification operation, it is not necessary to verify the programming of the nth programming state again. This shortens the programming verification time compared to verifying the nth programming state every time. When the number of failure bits during programming the nth programming state is greater than or equal to the third preset value, the programming of the nth programming state can be considered unsuccessful. Therefore, in the next second programming verification operation, it is necessary to continue verifying the programming of the nth programming state.

[0110] Optionally, before step S602, the operation method of the memory may further include: the memory obtaining the pre-verification result of the memory cell in the nth programming state based on the verification voltage of the second programming verification operation.

[0111] For example, pre-verification results are obtained after coarse programming is completed and before fine programming begins. The pre-verification result represents the number of memory units that have reached the nth programming state after coarse programming. The pre-verification result can be understood as the impact of coarse programming on fine programming. To improve the accuracy of fine programming, the impact of the pre-verification result should be eliminated during fine programming.

[0112] Specifically, after the first fine-tuning is completed, a second verification result can be obtained based on the verification voltage of the fine-tuning. At this point, if the second verification result includes the number of memory cells in the nth programming state, the second preset value is greater than the first preset value. For example... Figure 7 As shown, Figure 7 This application provides a threshold voltage distribution diagram for the nth programmed state, as illustrated in an embodiment. Figure 7 The diagram shows the threshold voltage distribution for the final coarse programming in the nth programming state, the threshold voltage distribution for the final fine programming in the nth programming state, and the threshold voltage distribution for the first fine programming. Pre-verification results can be obtained based on the verification voltage of the fine programming. At this point, the second verification result includes the pre-verification result, that is, the second verification result includes the number of memory cells that have been programmed in the coarse programming. To reduce the risk of overprogramming, the second preset value should be set greater than the first preset value; that is, the preset value for fine programming is greater than the preset value for coarse programming.

[0113] Furthermore, if the second verification result includes the number of memory cells in the nth programming state, excluding the number of memory cells corresponding to the pre-verification result, the second preset value is less than the first preset value. For example... Figure 8 As shown, Figure 8 This is another threshold voltage distribution diagram for the nth programming state provided in an embodiment of this application. Wherein, Figure 8 The diagram shows the threshold voltage distribution for the final coarse programming of the nth programming state, the threshold voltage distribution for the final fine programming of the nth programming state, and the threshold voltage distribution for the first fine programming. A pre-verification result can be obtained based on the verification voltage of the fine programming. At this point, the second verification result includes the number of memory cells in the nth programming state, excluding the number of memory cells corresponding to the pre-verification result; that is, the second verification result does not include the pre-verification result. To reduce the risk of overprogramming, the second preset value should be set lower than the first preset value; that is, the preset value for fine programming is lower than the preset value for coarse programming.

[0114] Optionally, S601 may include S6011 to S6014, such as Figure 9 As shown, Figure 9 This is a flowchart illustrating a rough programming of a memory according to an embodiment of this application.

[0115] S6011. The memory performs a first programming verification operation on the storage unit of the m-th programming state to obtain the first verification result of the storage unit of the m-th programming state, where m is a positive integer.

[0116] For example, the first programming verification operation may include a first programming operation and a first verification operation. The first programming operation is to apply a programming pulse to the memory cell of the m-th programming state, and the first verification result can be obtained based on the first verification voltage of the first verification operation. The first verification result is the number of successfully programmed bits in the m-th programming state.

[0117] S6012. If the first verification result of the storage unit in the m-th programming state is greater than or equal to the first preset value, the memory performs the first programming verification operation on the storage unit in the (m+1)-th programming state.

[0118] For example, if the first verification result is greater than or equal to a first preset value, it indicates that a large number of memory cells have reached the m-th programming state. Therefore, it can be predicted that after applying the next programming pulse, memory cells storing the target programming state as the (m+1)-th programming state will also reach the (m+1)-th programming state. Thus, after applying the next programming pulse, a first programming verification operation needs to be performed on the (m+1)-th programming state. This reduces the occurrence of overprogramming and improves programming quality.

[0119] S6013. If the first verification result of the storage unit in the m-th programming state is less than the first preset value, the memory performs the first programming verification operation on the storage unit in the m-th programming state.

[0120] For example, if the first verification result is less than the second preset value, it indicates that no memory cells or only a small number of memory cells have reached the m-th programming state. Therefore, it can be predicted that after applying the next programming pulse, almost no memory cells with the target programming state being the (m+1)-th programming state will be able to reach it, meaning the (m+1)-th programming state will not be successfully programmed. Thus, after applying the next encoding pulse, there is no need to perform the first programming verification operation on the (m+1)-th programming state. This reduces the number of programming states that need to be verified in the next first programming verification operation, which helps to shorten the programming verification time, reduce the number of verification results to be processed, and improve programming efficiency.

[0121] In another implementation, the first verification result can also be the number of failed bits in programming the m-th programming state. If the first verification result is less than a fourth preset value, it is determined that the first programming verification operation will be performed on the memory cell of the (m+1)-th programming state. If the first verification result is greater than or equal to the fourth preset value, it is determined that the first programming verification operation will be performed on the memory cell of the m-th programming state.

[0122] Understandably, when the number of failure bits during programming the m-th programming state is less than the fourth preset value, the programming of the m-th programming state can be considered successful. Therefore, in the next first programming verification operation, it is not necessary to verify the m-th programming state again. This shortens the programming verification time and increases programming speed compared to verifying the m-th programming state every time. When the number of failure bits during programming the m-th programming state is greater than or equal to the fourth preset value, the programming of the m-th programming state can be considered unsuccessful. Therefore, in the next first programming verification operation, it is necessary to continue verifying the m-th programming state.

[0123] S6014. If the first verification result obtained by performing the first programming verification operation on the storage unit of the highest programming state is greater than or equal to the first preset value, multiple storage units from the first programming state to the i-th programming state are obtained.

[0124] For example, if the first verification result includes the number of storage units that have reached the highest programming state, and the first verification result is greater than or equal to the first preset value, then it indicates that a larger number of storage units have reached the highest programming state, that is, the coarse programming process has been completed.

[0125] Optionally, the memory operation method further includes: the memory acquiring a first number of times the first programming verification operation is performed, and determining a first preset value based on the first number; the memory acquiring a second number of times the second programming verification operation is performed, and determining a second preset value based on the second number.

[0126] For example, both the first and second counts can be understood as the number of cycles. One erase operation and one write operation for the memory constitute one cycle. As the number of cycles increases, the programming performance of the memory may change, leading to variations in programming speed. It is understood that a cycle is defined by the smallest unit of programming. For example, when encoding in blocks, the number of cycles for each memory cell within that block is essentially the same. Furthermore, when the memory is programmed in different smallest units, the obtained cycle count represents the number of cycles for that smallest unit of programming.

[0127] Compared to fixed first and second preset values, this embodiment of the application obtains the number of programming verification operations and determines the preset value based on the number of operations. Therefore, the programming characteristics that change with the number of iterations can be tracked during the programming verification operations, allowing for flexible adjustment of the preset value's range. This reduces slow programming speeds caused by improperly determined preset values, thus improving programming speed and ensuring programming quality.

[0128] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0129] Electronic devices may include the memory system described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0130] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for operating a memory, characterized in that, The method includes: Multiple first programming verification operations are performed on multiple storage cells of the memory to obtain multiple storage cells from the first programming state to the i-th programming state, where i is a positive integer. In the first programming verification operation, it is determined whether to perform the first programming verification operation of the next programming state based on whether the first verification result reaches the first preset value. The first verification result includes the number of storage cells in the current programming state. The pre-verification result of the memory cell in the nth programming state is obtained based on the verification voltage of the second programming verification operation; Perform a second programming verification operation on the memory cell of the nth programming state to obtain the second verification result of the memory cell of the nth programming state, where n is a positive integer; If the second verification result of the storage unit in the nth programming state is greater than or equal to the second preset value, the second programming verification operation is performed on the storage unit in the (n+1)th programming state, where the second preset value is different from the first preset value.

2. The operating method according to claim 1, characterized in that, The second verification result includes the number of storage units in the nth programming state, and the second preset value is greater than the first preset value.

3. The operating method according to claim 1, characterized in that, The second verification result includes the number of storage units in the nth programming state, excluding the number of storage units corresponding to the pre-verification result, and the second preset value is less than the first preset value.

4. The operating method according to claim 1, characterized in that, The step of performing multiple first programming verification operations on multiple memory cells of the memory to obtain multiple memory cells from the first programming state to the i-th programming state includes: Perform the first programming verification operation on the storage unit of the m-th programming state to obtain the first verification result of the storage unit of the m-th programming state, where m is a positive integer; If the first verification result of the storage unit in the m-th programming state is greater than or equal to the first preset value, the first programming verification operation is performed on the storage unit in the (m+1)-th programming state. If the first verification result of the storage unit in the m-th programming state is less than the first preset value, the first programming verification operation is performed on the storage unit in the m-th programming state. If the first verification result obtained by performing the first programming verification operation on the storage cell of the highest programming state is greater than or equal to the first preset value, multiple storage cells from the first programming state to the i-th programming state are obtained.

5. The operating method according to claim 1, characterized in that, The step size of the multiple programming pulses in the first programming verification operation is greater than the step size of the multiple programming pulses in the second programming verification operation.

6. The operating method according to claim 1, characterized in that, The method further includes: If the second verification result of the storage unit in the nth programming state is less than the second preset value, the second programming verification operation is performed on the storage unit in the nth programming state.

7. The operating method according to claim 1, characterized in that, The method further includes: Obtain the first number of times the first programming verification operation is performed, and determine the first preset value based on the first number of times; Obtain the second number of times the second programming verification operation is performed, and determine the second preset value based on the second number of times.

8. A memory, characterized in that, The memory includes: A storage cell array, wherein the storage cell array comprises a plurality of storage cells; Peripheral circuitry, coupled to the memory cell array, is configured as follows: Multiple first programming verification operations are performed on multiple storage cells of the memory to obtain multiple storage cells from the first programming state to the i-th programming state, where i is a positive integer. In the first programming verification operation, it is determined whether to perform the first programming verification operation of the next programming state based on whether the first verification result reaches the first preset value. The first verification result includes the number of storage cells in the current programming state. The pre-verification result of the memory cell in the nth programming state is obtained based on the verification voltage of the second programming verification operation; Perform a second programming verification operation on the memory cell of the nth programming state to obtain the second verification result of the memory cell of the nth programming state, where n is a positive integer; If the second verification result of the storage unit in the nth programming state is greater than or equal to the second preset value, the second programming verification operation is performed on the storage unit in the (n+1)th programming state, where the second preset value is different from the first preset value.

9. The memory according to claim 8, characterized in that, The second verification result includes the number of storage units in the nth programming state, and the second preset value is greater than the first preset value.

10. The memory according to claim 8, characterized in that, The second verification result includes the number of storage units in the nth programming state, excluding the number of storage units corresponding to the pre-verification result, and the second preset value is less than the first preset value.

11. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: Perform the first programming verification operation on the storage unit of the m-th programming state to obtain the first verification result of the storage unit of the m-th programming state, where m is a positive integer; If the first verification result of the storage unit in the m-th programming state is greater than or equal to the first preset value, the first programming verification operation is performed on the storage unit in the (m+1)-th programming state. If the first verification result of the storage unit in the m-th programming state is less than the first preset value, the first programming verification operation is performed on the storage unit in the m-th programming state. If the first verification result obtained by performing the first programming verification operation on the storage cell of the highest programming state is greater than or equal to the first preset value, multiple storage cells from the first programming state to the i-th programming state are obtained.

12. The memory according to claim 8, characterized in that, The step size of the multiple programming pulses in the first programming verification operation is greater than the step size of the multiple programming pulses in the second programming verification operation.

13. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: If the second verification result of the storage unit in the nth programming state is less than the second preset value, the second programming verification operation is performed on the storage unit in the nth programming state.

14. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: Obtain the first number of times the first programming verification operation is performed, and determine the first preset value based on the first number of times; Obtain the second number of times the second programming verification operation is performed, and determine the second preset value based on the second number of times.

15. A memory system, characterized in that, The memory system includes: One or more memories as described in any one of claims 8 to 14; A memory controller coupled to the memory and configured to control the memory.

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