Apparatus for controlling trapped ions

Abstract

The invention relates to a device for controlling trapped ions. An apparatus for controlling trapped ions includes a semiconductor substrate. The semiconductor substrate includes a first main surface and a second main surface opposite the first main surface. The substrate includes a doped region adjacent to the first major surface. An electrode of the ion trap is disposed over the doped region. An insulating layer is disposed between the electrode and the doped region. The substrate includes a contact region configured to be biased by an external potential, the contact region being electrically connected to the doped region and having a higher doping concentration than a doping concentration of the doped region.

Description

Technical Field

[0001] The present disclosure relates generally to the field of ion traps, and in particular to ion traps for quantum computing. Background Art

[0002] Trapped ions are one of the most promising candidates for use as qubits (quantum bits) in quantum computers because they can be trapped in scalable arrays with long lifetimes using electromagnetic fields.

[0003] Ions can be trapped in an alternating electromagnetic field generated by RF (radio frequency) voltages applied to surface electrodes of a micromachined ion trap.The more ions to be trapped in a micromachined ion trap device, the smaller the structural width of the electrodes and, for example, feed lines to the electrodes can be.

[0004] Ions can be addressed by lasers for cooling, state preparation, and other purposes. Photoionization can generate charges in and / or on the substrate, which can cause uncontrolled stray fields and electrical noise. Stray fields can push trapped ions beyond the potential minimum of the RF field, increasing the micromotion of the ions and thus heating the ions. This heating makes it difficult to use ions for low-error rate quantum operations. Summary of the invention

[0005] According to one aspect of the present disclosure, a device for controlling trapped ions includes a semiconductor substrate. The semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The substrate includes a doped region adjacent to the first main surface. An electrode of the ion trap is disposed on the doped region. An insulating layer is disposed between the electrode and the doped region. The substrate includes a contact region, the contact region being configured to be biased by an external potential, the contact region being electrically connected to the doped region and having a doping concentration higher than the doping concentration of the doped region.

[0006] According to another aspect of the present disclosure, a device for controlling trapped ions includes a semiconductor substrate. The semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate includes a drift region adjacent to the first main surface. An RF electrode of the ion trap is disposed above the drift region. An insulating layer is disposed between the RF electrode and the drift region. The semiconductor substrate includes a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential, the drift region being disposed between the first contact region and the second contact region and being electrically connected to the first contact region and the second contact region.

[0007] According to another aspect of the present disclosure, a method for manufacturing an apparatus for controlling trapped ions includes: providing a semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate is doped to produce a doped region adjacent to the first main surface. An insulating layer is produced above the doped region. A contact region configured to be biased by an external potential is produced in the semiconductor substrate. The contact region is electrically connected to the doped region and has a doping concentration higher than the doping concentration of the doped region. An electrode of an ion trap is produced that is placed above the doped region.

[0008] According to another aspect of the present disclosure, a method for manufacturing an apparatus for controlling trapped ions includes: providing a semiconductor substrate including a first main surface and a second main surface opposite to the first main surface. Producing an insulating layer above the first main surface of the semiconductor substrate. Producing a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential, wherein a drift region of the semiconductor substrate is disposed between and electrically connected to the first contact region and the second contact region. Producing an RF electrode of an ion trap disposed above the drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The elements of the drawings are not necessarily drawn to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated examples can be combined unless they exclude each other, and / or can be selectively omitted if not described as necessarily required. Examples are depicted in the drawings and are exemplarily detailed in the following description.

[0010] Figure 1 is a schematic cross-sectional view of an exemplary apparatus for controlling trapped ions.

[0011] Figure 2 yes Figure 1 Top view of an exemplary apparatus for controlling trapped ions shown in FIG.

[0012] Figure 3 is a schematic cross-sectional view of an exemplary apparatus for controlling trapped ions, the apparatus having a doped region adjacent to an upper surface of a substrate of the apparatus.

[0013] Figure 4 is a schematic cross-sectional view of an exemplary apparatus for controlling trapped ions having a drift zone adjacent to an upper surface of a substrate of the apparatus and an RF electrode of an ion trap disposed above the drift zone.

[0014] Figure 5is a schematic cross-sectional view of an exemplary apparatus for controlling trapped ions having a drift zone adjacent to an upper surface of a substrate of the apparatus and an RF electrode of an ion trap disposed above the drift zone.

[0015] Figure 6 yes Figure 5 Schematic cross-sectional view of an exemplary device in which the drift zone includes a doped zone located below a ground electrode.

[0016] Figure 7 is a schematic cross-sectional view of an exemplary device for controlling trapped ions, wherein a contact region is adjacent to a back surface of a substrate of the device.

[0017] Figure 8 is a schematic cross-sectional view of an exemplary apparatus for controlling trapped ions, the apparatus having multiple metal layers disposed over an upper surface of a substrate of the apparatus.

[0018] Fig. 9 is a schematic cross-sectional view of an exemplary apparatus for controlling trapped ions having another substrate disposed above and spaced apart from the substrate.

[0019] Fig.10 is a flow chart illustrating exemplary stages in a method of making an apparatus for controlling trapped ions.

[0020] Fig.11 is a flow chart illustrating exemplary stages in a method of making an apparatus for controlling trapped ions. DETAILED DESCRIPTION

[0021] As used in this specification, the terms "electrically connected" or "electrically coupled" or similar terms are not intended to mean that elements are directly in contact together; intervening elements may be provided between the elements that are "electrically connected" or "electrically coupled", respectively. However, according to the present disclosure, the above and similar terms may optionally also have the following specific meanings: the elements are directly in contact together, that is, no intervening elements are provided between the elements that are "electrically connected" or "electrically coupled", respectively.

[0022] In addition, the words “on” or “below” with respect to a part, element, or material layer formed or located or arranged “on a surface” or “below a surface” may be used herein to mean that the part, element, or material layer is “directly” located (e.g., placed, formed, arranged, deposited, etc.) “on the implied surface” or “directly” located (e.g., placed, formed, arranged, deposited, etc.) “below the implied surface”, such as directly contacting the implied surface. However, the words “on” or “below” with respect to a part, element, or material layer formed or located or arranged “on a surface” or “below a surface” may be used herein to mean that the part, element, or material layer is “indirectly” located (e.g., placed, formed, arranged, deposited, etc.) “on the implied surface” or “indirectly” located (e.g., placed, formed, arranged, deposited, etc.) “below the implied surface”, with one or more additional parts, elements, or layers arranged between the implied surface and the part, element, or material layer.

[0023] Reference Figure 1 The device 100 for controlling trapped ions comprises: a semiconductor substrate 120; and one or more electrodes 125 disposed on the semiconductor substrate 120. The (one or more) electrodes 125 may be, for example, formed of a structured electrode layer M. el form.

[0024] The device 100 includes at least one ion trap. The electrode 125 is part of such an ion trap and is configured to trap one or more ions 180 (for ease of illustration, only one ion 180 is shown in FIG. 1 ). Figure 1 middle).

[0025] Through micro-machining technology, the structured electrode layer M of the ion trap device 100 is el (and therefore, the electrode 125) can be processed. The semiconductor substrate 120 can be substantially planar. The Z direction can represent the height dimension of the ion trap device 100. The X direction and the Y direction are perpendicular to each other and define a plane in the width and length direction of the ion trap device 100, which is orthogonal to the Z direction.

[0026] In the examples disclosed herein, the structured electrode layer M el RF electrodes 125 for RF trapping and DC electrodes 125 for electrostatic field trapping may be included.The ion trap disclosed herein is capable of trapping a number of ions 180 that are individually addressable and movable by appropriately controlling the potentials of the electrodes 125 of the ion trap.

[0027] By applying to the structured electrode layer M elThe location of ions 180 can be controlled by applying voltages to the electrode(s) 125. For example, by separately coupling RF and DC voltages to specific electrodes 125, ions 180 can be directed in one or more lateral directions (e.g., in the Y direction (see Figure 2 ) or generally in any direction in a plane orthogonal to the Z direction), ions 180 are able to move in space.

[0028] Structured electrode layer M el A feed line connected to the electrode 125 may also be included. el This feed line may also be indicated by reference numeral 125, like any other structure of the apparatus.

[0029] Structured electrode layer M el is a conductive layer. For example, it may include a metal layer, or a metal layer. That is, the structured electrode layer M el (and therefore, the electrode 125) may include or may have an electrically conductive material, such as, for example, Al, Cu, Au, or an AlSiCu alloy or an AlCu alloy.

[0030] The semiconductor substrate 120 may be, for example, a semiconductor wafer or a portion sliced ​​from a semiconductor wafer such as a chip. For example, the semiconductor substrate 120 may be, for example, a silicon (Si) substrate or a silicon carbide (SiC) substrate.

[0031] The ion trap device 100 further comprises an electrically insulating layer 130 disposed on the first main surface 120A of the semiconductor substrate 120 and disposed on the structured electrode layer M. el The semiconductor substrate 120 includes a second main surface 120B opposite to the first main surface 120A.

[0032] exist Figure 1 In the embodiment, the ion trap of the ion trap device 100 is illustrated as being designed as a so-called "surface electrode" ion trap. In a surface electrode ion trap, all electrodes (i.e., DC electrode 125 and RF electrode 125) are contained in a single plane. This two-dimensional (2D) ion trap geometry provides high scalability. As will be further described below, in other examples, the ion trap device 100 may use a three-dimensional (3D) ion trap geometry ( Fig. 9 ).

[0033] Figure 2 is a structured electrode layer M formed in the ion trap device 100 elSchematic top view of an exemplary simplified electrode structure in . For example, some of the electrodes 125 may be formed as stripe electrodes, while other electrodes 125 may be formed as island electrodes with small lateral dimensions. Many different electrode layouts are known in the art and can be used in the exemplary ion trap device 100 disclosed herein.

[0034] The ion trap device 100 may also be referred to as a micro-machined ion trap or an ion trap chip. The ion trap device 100 may have one or more trapping sites, ie, may be configured to trap, for example, one ion or a chain of ions, for example, oriented in the Y direction.

[0035] Figure 2 Also shown is the structured electrode layer M el Optional terminal land 125t can be used to electrically connect the micromachined electrode 125 to an external circuit (not shown) via a connector (not shown), such as a wire bond. Other designs of electrical connections of the electrical interconnect are also possible. In other examples, the electrode 125 may not be connected to the terminal land 125t exposed at the insulator 130, but instead, for example, to a via, which can, for example, be directly connected to the electrical interconnect (e.g., Figure 8 ) and / or connected to an integrated circuit (not shown) in the semiconductor substrate 120.

[0036] In the following, without loss of generality, the semiconductor substrate 120 is exemplified by a silicon substrate 120 (eg, by a silicon chip).

[0037] Reference Figure 3 In the exemplary ion trap device 300 of FIG. 1 , the semiconductor substrate 120 includes a doped region 120_1 adjacent to a (upper) first main surface 120A of the semiconductor substrate 120 . The doped region 120_1 may increase the conductivity of the semiconductor substrate 120 near an interface between the semiconductor substrate 120 and the insulating layer 130 .

[0038] In addition, the semiconductor substrate 120 includes a contact region 120_2. The contact region 120_2 is electrically connected to the doping region 120_1 and has a higher doping concentration than that of the doping region 120_1.

[0039] The contact region 120_2 is configured to be electrically connected to the external potential V bias For example, via the bias voltage terminal 127, the external bias potential V bias For example, the bias voltage terminal 127 may be formed by the electrode layer M el The structured part is formed.

[0040] The bias voltage terminal 127 is electrically coupled to the contact region 120_2 of the semiconductor substrate 120 and allows a defined potential (relative to V bias The doping region 120_1 is applied with a corresponding charge (corresponding to the charge) to the doping region 120_1. This allows the influence of stray charges on the trapped ions 180 to be eliminated, thereby reducing micro-motion and ion heating of the ions 180. In other words, uncontrolled stray fields and electrical noise caused by charges generated by photoionization in or on the semiconductor substrate, for example, can be reduced or eliminated.

[0041] The doping concentration of the doping region 120_1 is higher than the doping concentration of the body region 120_3 of the semiconductor substrate 120. The doping concentration of the doping region 120_1 may be, for example, equal to or greater than 2.0×10 17 or 1.0×10 18 or 1.0×10 19 cm -3 The doping concentration of the doping region 120_1 may be high enough to significantly increase the conductivity of the doping region 120_1 at cryogenic temperatures (e.g., at temperatures equal to or lower than 50K, 40K, 30K, 20K) compared to when the doping region 120_1 would not exist. The doping concentration of the doping region 120_1 may be high enough to form degenerate doped silicon in the doping region 120_1 (at room temperature or even at cryogenic temperatures as described above). The high conductivity of the doping region 120_1 may ensure that interfering stray charges cannot remain in or on the semiconductor substrate 120 because they are removed by the biased doping region 120_1.

[0042] The doped region 120_1 is also referred to as a well in the art. Assume that the semiconductor substrate is a P-type substrate 120 (having a doping area of ​​approximately 1.0×10 15 cm -3 or 1.0×10 16 cm -3 The doped region 120_1 (having a substantially higher doping concentration than the body region 120_3 as described above) may be referred to as a P-well of the substrate 120. Similarly, using an N-type semiconductor substrate, the doped region 120_1 may be referred to as an N-well.

[0043] Because the substrate 120 of the ion trap device 100 is a semiconductor substrate, electronic devices (such as, for example, a digital-to-analog converter (DAC) or a switch) can be directly integrated in the semiconductor substrate 120 and thus integrated in the ion trap device 100. In this case, the doped region 120_1 can also be used to effectively shield the ion trap region above the substrate 120 from the electronic devices integrated in the substrate 120.

[0044] The doped region 120_1 may extend across a large area of ​​the semiconductor substrate 120. The larger the lateral area over which the doped region 120_1 extends, the more effectively stray charges can be eliminated in the ion trap device 100. In other examples, the doped region 120_1 may also cover only a specific lateral area of ​​the semiconductor substrate 120. For example, the doped region 120_1 may extend over at least the entire area of ​​the semiconductor substrate 120 where the electrodes 125 are located. For example, the doped region 120_1 may overlap with a plurality of electrodes 125 of the ion trap device 100 in a vertical projection. Since stray charges preferentially accumulate under the RF electrodes, the doped region 120_1 may, for example, at least partially or completely overlap with some or all of the RF electrodes 125 in a vertical projection.

[0045] In some examples, doped region 120_1 may extend continuously across most or all of the lateral extent of ion trap device 100. For example, bias voltage terminal 127 may be placed adjacent to a corner of semiconductor substrate 120 ( Figure 2 ). Optionally, a plurality of bias voltage terminals 127 may be provided. For example, the bias voltage terminal 127 may be placed adjacent to each corner of the semiconductor substrate 120.

[0046] The insulating layer 130 may be, for example, an inorganic dielectric layer such as, for example, a hard passivation layer comprising or having silicon oxide, silicon nitride or silicon oxynitride. The insulating layer 130 may be, for example, a thermal silicon oxide layer. In other examples, the insulating layer 130 may include or have deposited silicon oxide.

[0047] The insulating layer 130 may also extend across a large area of ​​the semiconductor substrate 120. In particular, the insulating layer 130 may extend substantially over the entire first main surface 120A of the semiconductor substrate 120.

[0048] The insulating layer 130 may be directly adjacent to the first main surface 120A of the substrate 120. In this manner, when the conductive doped region 120_1 is connected to V via the contact region 120_2, bias When the conductive doping region 120_1 is used, any stray charges on the lower surface of the insulating layer 130 are effectively removed.

[0049] The contact region 120_2 may be heavily doped to provide a conductive metal-semiconductor contact. More specifically, an ohmic contact or a Schottky contact may be implemented.

[0050] In order to create a low resistance contact, the band gap of the contact region 120_2 should be narrow enough to allow tunneling of charge carriers. The width of the band gap is inversely proportional to the root of the doping concentration. Therefore, the doping concentration of the contact region 120_2 can be selected to be high enough to create an ohmic contact.

[0051] In a degenerately doped semiconductor, the Fermi level moves very close to or into the conduction band (or valence band). This enables the conductivity of the semiconductor material (e.g., silicon) to be similar to that of a metal (even at cryogenic temperatures). For example, the doping concentration of the contact region 120_2 may be equal to or greater than 2.0×10 18 or 1.0×10 19 or 1.0×10 20 cm -3 .

[0052] The contact region 120_2 may be adjacent to the first main surface 120A of the semiconductor substrate 120 ( Figure 3 ) to provide a front side contact of the doped region 120_1. In other examples, as will be described in further detail below, the contact region 120_2 may be adjacent to the second main surface 120B of the substrate 120 to provide a back side contact of the semiconductor substrate 120 ( Figure 7 ).

[0053] Reference Figure 4 The ion trap device 400 includes the semiconductor substrate 120, as described above. In the ion trap device 400, the semiconductor substrate 120 includes a drift region 420 adjacent to the first main surface 120A of the semiconductor substrate 120. The drift region 420 is separated from the electrode 125 by the insulating layer 130, as described above.

[0054] The drift region 420 may be located below the RF electrode 125_1. More particularly, the lateral extension of the drift region 420 (indicated by the arrows) may be selected to completely overlap the RF electrode 125_1 in a vertical projection. In other words, the drift region 420 may exclude any (conductive) doped region 120_1 from the area located below the RF electrode 125_1 in the vertical direction.

[0055] like Figure 4 As shown in , the drift region 420 may be formed by regions of the body region 120_3 of the semiconductor substrate 120 having a low doping concentration. In a lateral direction, the drift region 420 may be delimited by regions having a higher doping concentration than the drift region 420. These regions, between which the drift region 420 extends, may be represented by the doped region 120_1, as described above.

[0056] The semiconductor substrate 120 may further include a first contact region 120_2N and a second contact region 120_2P. The first contact region 120_N is configured to be biased by a first external potential, and the second contact region 120_2P is configured to be biased by a second external potential, wherein there is a potential difference between the first external potential and the second external potential. For example, the first contact region 120_N may be configured to be biased by a negative potential -V, and the second contact region 120_2P may be configured to be biased by a positive potential +V, so that both electrons and holes can drift. The drift region 420 is disposed between the first contact region 120_2N and the second contact region 120_2P, and is electrically connected to the first contact region 120_2N and the second contact region 120_2P. As Figure 4 As shown in FIG. 4 , for example, the drift region 420 may be electrically connected to the first contact region 120_2N and the second contact region 120_2P via the doped region 120_1 (P-well).

[0057] In the ion trap device 400, stray charges under the RF electrode 125_1 (and optionally, under all electrodes 125, 125_1, 125_2) are removed by the electric field generated in the drift region 420, rather than as Figure 3 By applying a positive potential (+V) and a negative potential (-V) to the substrate 120 through two contact regions 120_2P, 120_2N, an electric field is generated between, for example, the doped region 120_1 (P well), through which charge carriers generated, for example, by stray light can flow away.

[0058] Providing a drift region 420 below the RF electrode 125_1 significantly reduces the capacitance of the ion trap device 400 between the RF voltage and the ground (GND). More specifically, the drift region 420 can be used to replace the originally necessary ground shielding layer below the RF electrode 125_1. Such a drift region 420 can be particularly effective for silicon as a semiconductor material because silicon has a very low loss tangent.

[0059] The drift region 420 may optionally also extend in vertical projection under a portion or the entire extension of some or all of the DC electrodes 125_2. However, because the voltage applied to the DC electrodes 125_2 is not alternating and is substantially smaller than the (alternating) voltage applied to the RF electrodes 125_1, the effect in reducing the overall device capacitance is less significant for the DC electrodes 125_2 than for the RF electrodes 125_1.

[0060] Combination Figure 3 (highly conductive doped region 120_1) and Figure 4The concepts described in (drift region 420) can be combined in a single ion trap device. That is, in the drift region concept ( Figure 4 ) is used, for example, mainly or only under the RF electrode 125_1 , while the doping region 120_1 concept can be used in the remaining areas of the semiconductor substrate 120 .

[0061] For example, refer to Figure 2 , the doped region 120_1 may extend across most of the semiconductor substrate 120. However, near the RF electrode 125_2, the doped region 120_1 may be structured to provide a "local" drift region(s) 420 and a separate (island-shaped) doped region 120_1 (P-well) to define the drift region(s) 420 below the RF electrode(s) 125_2. The separate (island-shaped) doped region 120_1 (P-well) may be connected to at least two different potentials -V and +V, as described above.

[0062] As the following combination Fig. 9 As will be further described, in a three-dimensional (3D) ion trap device, one substrate may carry only the DC electrodes, while another substrate may carry only the RF electrodes. In other words, the DC electrodes and the RF electrodes may be applied separately to different substrates. That is, returning to Figure 3 , if the substrate 120 is used in a 3D ion trap device, the substrate 120 may carry the DC electrode 125_2 and not the RF electrode 125_1, carry the RF electrode 125_1 and not the DC electrode 125_2, or, as shown in the figure, carry both the DC electrode 125_2 and the RF electrode 125_1. Similarly, if Figure 4 If the substrate 120 shown in FIG. 1 is used in a 3D ion trap device, the substrate 120 may carry the DC electrode 125_2 but not the RF electrode 125_1, carry the RF electrode 125_1 but not the DC electrode 125_2, or, as shown in the figure, carry both the DC electrode 125_2 and the RF electrode 125_1.

[0063] Reference Figure 5 , the ion trap device 500 includes, for example, a (center) ground electrode 125_3 (GND) disposed between two RF electrodes 125_1. The ground electrode 125_3 may be maintained at a potential of 0 V. The DC electrodes 125_2 may be disposed on both outer sides of the RF electrode 125_1.

[0064] In this example, the drift region 420 may extend below the RF electrode 125_1 and below the ground electrode 125_3. Additionally, as described above, the drift region 420 may extend below the DC electrode(s) 125_2 in a vertical projection, or may not extend below the DC electrode(s) 125_2, or may extend partially below the DC electrode(s) 125_2 (if the DC electrode 125_2 is present, see the comments above). Given Figure 5 Any other features of the ion trap device 500 are referred to in conjunction with Figure 4 description to avoid duplication.

[0065] Figure 6 An exemplary ion trap device 600 is shown. The ion trap device 600 may be used with Figure 5 ion trap device 500 is the same as ion trap device 500, except that drift region 420 includes doped band 620 located below ground electrode 125_3. Doped band 620 may, for example, have the same (relatively high) doping concentration as doped region 120_1. Doped band 620 does not increase the overall capacitance of ion trap device 600 because it is located below ground electrode 125_3. However, removal of stray charges (charge carriers) in the central region of ion trap device 600 may be improved. Figure 6 As shown in , a ground electrode 125_3 may be provided, for example, below the trapping site of ion 180 in a vertical direction, so that the doped zone 620 may be located near (or closest to) the trapping site of ion 180 in the substrate region.

[0066] like Figure 6 As shown in , the doped strip 620 may be electrically floating, for example. In other examples, the doped strip 620 may be electrically connected to the ground electrode 125_3 or another external potential. This may be achieved by a further contact region (not shown) located adjacent to the doped strip 620 and, for example, below the ground electrode 125_3 (GND). The further contact region (not shown) may, for example, have the same (high) doping concentration as the contact region 120_2 (or 120_2N, 120_2P).

[0067] For example, if the doped strip 620 is to be connected to the ground electrode 125_3 (GND), the metal of the ground electrode 125_3 (GND) may pass through the insulating layer 130 and contact this other contact area (not shown), which contacts the doped strip 620 and keeps the doped strip 620 at the ground potential. If the doped strip 620 is to be connected to another external potential different from the ground potential (GND), the other contact area (not shown) may be connected to a metal wiring (not shown), and this external potential can be applied to the metal wiring.

[0068] If, as described above, another external potential is to be applied to the doped zone 620 via another contact region, the other external potential may have a sign opposite to the potential (or potentials) to which the outer doped region 120_1 is connected. For example, the doped zone 620 may be applied to a positive potential +V, and the outer doped region 120_1 may be applied to a negative potential -V. Then, for the two undoped regions of the drift region 420, the charge carrier drift will be towards the central doped zone 620. That is, arrows (indicating electron drift) will then point to the doped zone 620 from both sides in the center direction.

[0069] Figure 7 The diagram shows that the doped regions 120_1 (eg, P-well) are electrically connected to the external potential V bias Or another possibility of negative voltage -V or positive voltage +V (voltage V bias , -V and +V are DC voltages which are substantially smaller than the RF voltage applied to the RF electrode 125_1). Figure 7 In the example shown in , the contact region 120_2 is located adjacent to and below the doped region 120_1. In this way, a backside contact to the semiconductor substrate 120 may be realized.

[0070] To this end, a back metal layer 727 may be disposed on the (lower) second main surface 120B of the substrate 120. The back metal layer 727 may be electrically connected to the contact region 120_2 of the semiconductor substrate 120. As described above, an ohmic contact or a Schottky contact may be implemented to connect the back metal layer 727 to the doped region 120_1 (P well) of the semiconductor substrate. In this manner, any potential (e.g., V bias , +V, −V) may be applied to the contact region 120_2.

[0071] The concept of providing electrical contacts on the back side ( Figure 7 ) can be used with Figures 3 to 6 In particular, if the doped region 120_1 can be structured to form one or more drift regions 420, the backside contacts can provide a high degree of design variability (because the contacts and electrodes are located on opposite sides of the semiconductor substrate 120).

[0072] Figure 8 and 9 Ion trap devices 800 and 900 using the above-mentioned concepts or features are shown. Figure 8 A two-dimensional (2D) ion trap device 800 is shown, which is similar to the ion trap device 100 ( Figure 1), except that the electrode 125 is electrically coupled to an electrical interconnect that is structured in a lower metal layer 135 (also referred to as M1). The dielectric layer 140 may be disposed above the electrode layer M1. el and between the lower metal layer 135 (M1).

[0073] The lower metal layer 135 (M1) may be, for example, a structured metal layer. The structured lower metal layer 135 (M1) may form a metal interconnect (wiring) configured to electrically connect the structured electrode layer M1 to the structured electrode layer. el The electrode 125 is connected to an external circuit. Figure 8 As shown in FIG. 1 , the structured lower metal layer 135 (M1) can be electrically connected to the structured electrode layer M1 through vias extending through the dielectric layer 140. el (separate) electrodes 125.

[0074] In other words, the structured lower metal layer 135 (M1) can be structured as an electrical redistribution layer, for example. This allows the structured electrode layer M el Complex electrode structures and island electrodes 125 are formed in the ion trap device 800. In addition, the multi-layer architecture of the ion trap device 800 promotes the scalability of the device 800.

[0075] Fig. 9 An ion trap device 900 that implements a 3D ion trap is shown. Compared to a 2D trap geometry, a 3D ion trap geometry (such as, for example, a linear Paul trap) can allow substantially higher potential depths and higher trap frequencies. In the exemplary ion trap device 900, ions 180 are trapped between a semiconductor substrate 120 and another substrate 150 that is disposed above and spaced apart from the semiconductor substrate 120. One or more separator members 160 can be disposed between the semiconductor substrate 120 and the other substrate 150.

[0076] The spacer member 160 defines a space between the semiconductor substrate 120 and the other substrate 150. The spacer member 160 may be bonded to the semiconductor substrate 120 and / or to the other substrate 150 by a wafer bonding technique. For example, a glass bonding technique or a eutectic bonding technique or an anodic bonding technique or a thermal compression bonding technique may be used.

[0077] Structured top electrode layer M el ' can be placed on the structured electrode layer M el The main side of the other substrate 150 is opposite. The structured top electrode layer M el 'Electrode 155 of the 3D ion trap device 900 is formed. The 3D ion trap device 900 is configured to have a structured electrode layer M el and structured top electrode layer Mel (One or more) ions 180 are trapped in the space between ′.

[0078] Similar to the electrode layer M el , through micromachining technology, the top electrode layer M el ' may also be formed and structured. In addition, the further substrate 150, the electrode 155 and the intermediate layer (not shown) may be optionally designed as described in conjunction with the semiconductor substrate 120, the electrode 125 and the intermediate layer (particularly, the insulating layer 130). For the sake of brevity, reference is made to the above description.

[0079] In particular, as described above, the 3D design allows the RF electrodes and the DC electrodes to be separated into different substrates 120, 150. In this case, and also in other cases, the semiconductor substrate 120 and the further (semiconductor) substrate 150 can be combined using the above Figure 3 (doped region 120_1) and Figures 4 to 6 (Drift region 420) Different concepts described. In addition, any type of contactor implementation, such as front side contacts (eg, bias voltage terminal 127) or back side contacts at back side metal layer 727, may be feasible.

[0080] Fig.10 is a flow chart illustrating exemplary stages in a method of making an apparatus for controlling trapped ions.

[0081] At S1 , a semiconductor substrate is provided, the semiconductor substrate including a first main surface and a second main surface opposite to the first main surface.

[0082] At S2, the semiconductor substrate is doped to produce a doped region adjacent to the first main surface. The doped region may be a continuous region extending across the entire region or a major region of the semiconductor substrate, or may be patterned into a plurality of doped regions. For example, boron (B) may be used for substrate doping to produce doped region 120_1 (P well). In some examples, approximately 1×10 16 cm -2 An implantation dose of about 100 keV and an implantation energy of about 70 keV may be used. In this manner, degenerately doped silicon may be formed in the doping region 120_1.

[0083] In S3, an insulating layer is produced over the doped regions of the semiconductor substrate. For example, the insulating layer may be produced, for example, by thermal oxidation of the silicon semiconductor substrate. Due to the high temperature, this process may be used simultaneously as an annealing for the doping process in S2. In other examples, the insulating layer may be produced by a deposition process rather than a growth process. In this case, a separate annealing process may follow for annealing of the doped regions produced in S2.

[0084] At S4, a contact region in the semiconductor substrate may be generated. The contact region is configured to be biased by an external potential. The contact region is generated to be electrically connected to the doping region and has a doping concentration higher than that of the doping region.

[0085] For example, S4 is performed by first patterning an insulating layer, such as by photolithography and etching. The patterned insulating layer can then be used as a hard mask for a high dose implantation at the contact region of S4.

[0086] S4 may be followed by a process of annealing the contact region.

[0087] At S5, electrodes of the ion trap are produced and placed on the insulating layer. Electrode production can be performed by deposition and patterning of a continuous electrode layer or by producing a patterned electrode layer according to the desired electrode layout.

[0088] Reference Fig.11 , a method for manufacturing an ion trap device may include: at S1, providing a semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface opposite to the first main surface.

[0089] Optionally, the semiconductor substrate is doped to produce doped regions adjacent to the first main surface (compare S2).Since the drift region remains undoped, the doping process comprises lithography to provide a pattern of doped regions.

[0090] At S3', an insulating layer is produced over the first main surface of the semiconductor substrate. Refer to the description of S3.

[0091] At S4', a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential are generated. A drift region of the semiconductor substrate is disposed between the first contact region and the second contact region and is electrically connected to the first contact region and the second contact region.

[0092] As mentioned above, the electrical connection between the contact region and the drift region may be provided by a (patterned) doped region.

[0093] At S5', an RF electrode is produced above the drift region. In this way, a low capacitance between the RF electrode and ground (GND) can be obtained.

[0094] In order to verify the doping and electrical contact of the semiconductor substrate 120, four-point conductance measurement was performed. 16 cm -3 The doping concentration of the silicon substrate was measured by 1×10 16 cm -2The substrate doping (P-well doping) for producing the doped region 120_1 is performed by boron (B) implantation with a dose of 1×10 16 cm -2 The contact region doping is carried out using BF2 with a dose of 1000 keV and an implantation energy of 20 keV. The contact manufactured in this way is an ohmic contact with a resistance of less than 60 Ω. For the flow from one edge of the silicon substrate to the other edge through the doped region (see Figure 2 , the current of the bias voltage terminal 127) can achieve a resistance of less than 2kΩ, and after optimizing the doping concentration, a resistance of less than 1.1kΩ can be achieved.

[0095] Example

[0096] The following examples relate to further aspects of the present disclosure:

[0097] Example 1 is a device for controlling trapped ions. The device includes a semiconductor substrate. The semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The substrate includes a doped region adjacent to the first main surface. An electrode of the ion trap is disposed on the doped region. An insulating layer is disposed between the electrode and the doped region. The substrate includes a contact region, the contact region being configured to be biased by an external potential, the contact region being electrically connected to the doped region and having a doping concentration higher than the doping concentration of the doped region.

[0098] In Example 2, the subject matter of Example 1 can optionally include, wherein the ion trap comprises a plurality of electrodes, and the doped region overlaps the plurality of electrodes in a vertical projection.

[0099] In Example 3, the subject matter of Example 1 or 2 can optionally include, wherein the insulating layer is directly adjacent to the first major surface of the semiconductor substrate.

[0100] In Example 4, the subject matter of any of the preceding examples can optionally include, wherein the doping concentration of the doping region is equal to or greater than 2.0×10 17 or 1.0×10 18 or 1.0×10 19 cm -3 .

[0101] In Example 5, the subject matter of any of the preceding examples can optionally include, wherein the doping concentration of the contact region is equal to or greater than 2.0×10 18 or 1.0×10 19 or 1.0×10 20 cm -3 .

[0102] In Example 6, the subject matter of any preceding example can optionally include, wherein the contact region is adjacent to the first major surface.

[0103] In Example 7, the subject matter of one of Examples 1 to 5 can optionally include that the contact region is adjacent to the second major surface.

[0104] Example 8 is a device for controlling trapped ions. The device includes a semiconductor substrate. The semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate includes a drift region adjacent to the first main surface. An RF electrode of the ion trap is disposed above the drift region. An insulating layer is disposed between the RF electrode and the drift region. The semiconductor substrate includes a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential, the drift region being disposed between the first contact region and the second contact region and being electrically connected to the first contact region and the second contact region.

[0105] In Example 9, the subject matter of Example 8 can optionally include, wherein the ion trap comprises a plurality of DC electrodes and a plurality of RF electrodes, and wherein the drift region overlaps the plurality of RF electrodes in a vertical projection.

[0106] In Example 10, the subject matter of Example 9 can optionally include, wherein the ion trap further comprises a ground electrode, wherein the drift region comprises a doped band located below the ground electrode.

[0107] In Example 11, the subject matter of any one of Examples 8 to 10 can optionally include, wherein the insulating layer is directly adjacent to the first major surface of the semiconductor substrate.

[0108] In Example 12, the subject matter of any one of Examples 8 to 11 can optionally include, wherein the drift region comprises 1.0×10 15 and 1.0×10 17 cm -3 The doping concentration in the range between, and particularly including, 4.0×10 15 and 5.0×10 16 cm -3 The doping concentration is in the range between .

[0109] In Example 13, the subject matter of any one of Examples 8 to 12 can optionally include, wherein the first contact region and the second contact region are adjacent to the first major surface, or wherein the first contact region and the second contact region are adjacent to the second major surface.

[0110] Example 14 A method for manufacturing a device for controlling trapped ions. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate is doped to produce a doped region adjacent to the first main surface. An insulating layer is produced above the doped region. A contact region configured to be biased by an external potential is produced in the semiconductor substrate. The contact region is electrically connected to the doped region and has a doping concentration higher than the doping concentration of the doped region. An electrode for an ion trap is produced that is placed above the doped region.

[0111] Example 15 is a method of manufacturing an apparatus for controlling trapped ions. The method includes: providing a semiconductor substrate, the semiconductor substrate including a first main surface and a second main surface opposite to the first main surface. Producing an insulating layer above the first main surface of the semiconductor substrate. Producing a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential, wherein a drift region of the semiconductor substrate is disposed between the first contact region and the second contact region and electrically connected to the first contact region and the second contact region. Producing an RF electrode of an ion trap disposed above the drift region.

[0112] Although specific examples have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific examples discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A device for controlling trapped ions, the device comprising: A semiconductor substrate comprising a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate comprising a doped region adjacent to the first main surface; An electrode of the ion trap is placed on the doped region; and an insulating layer disposed between the electrode and the doped region; in The semiconductor substrate includes a contact region configured to be biased by an external potential, the contact region being electrically connected to the doping region and having a doping concentration higher than a doping concentration of the doping region. 2 . The apparatus of claim 1 , wherein the ion trap comprises a plurality of electrodes, and the doped region overlaps the plurality of electrodes in vertical projection.

3. The device of claim 1 or 2, wherein the insulating layer is directly adjacent to the first major surface of the semiconductor substrate.

4. The device according to any one of the preceding claims, wherein the doping concentration of the doped region is equal to or greater than 2.0×10 17 or 1.0×10 18 or 1.0×10 19 cm -3 .

5. The device according to any one of the preceding claims, wherein the doping concentration of the contact region is equal to or greater than 2.0×10 18 or 1.0×10 19 or 1.0×10 20 cm -3 .

6. A device as claimed in any preceding claim, wherein the contact area is adjacent to the first major surface.

7. The device of any one of claims 1 to 5, wherein the contact region is adjacent to the second major surface.

8. A device for controlling trapped ions, the device comprising: a semiconductor substrate comprising a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate comprising a drift region adjacent to the first main surface; an RF electrode of the ion trap, disposed above the drift region; and an insulating layer disposed between the RF electrode and the drift region; in The semiconductor substrate includes a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential, and the drift region is disposed between and electrically connected to the first contact region and the second contact region.

9. The apparatus of claim 8, wherein the ion trap comprises a plurality of DC electrodes and a plurality of RF electrodes, and wherein the drift region overlaps the plurality of RF electrodes in a vertical projection.

10. The apparatus of claim 9, wherein the ion trap further comprises a ground electrode, wherein the drift region comprises a doped zone located below the ground electrode.

11. The device of any one of claims 8 to 10, wherein the insulating layer is directly adjacent to the first major surface of the semiconductor substrate.

12. The device of any one of claims 8 to 11, wherein the drift region comprises 1.0×10 15 and 1.0×10 17 cm -3 The doping concentration in the range between, and particularly including, 4.0×10 15 and 5.0×10 16 cm -3 The doping concentration is in the range between .

13. The device of any one of claims 8 to 12, wherein the first contact area and the second contact area are adjacent to the first major surface, or wherein the first contact area and the second contact area are adjacent to the second major surface.

14. A method of manufacturing an apparatus for controlling trapped ions, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first main surface and a second main surface opposite to the first main surface; doping the semiconductor substrate to produce a doped region adjacent to the first major surface; producing an insulating layer over the doped region; creating a contact region in the semiconductor substrate configured to be biased by an external potential, the contact region being electrically connected to the doped region and having a doping concentration higher than that of the doped region; and Electrodes are created to create an ion trap disposed above the insulating layer.

15. A method of making an apparatus for controlling trapped ions, the method comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first main surface and a second main surface opposite to the first main surface; producing an insulating layer over the first major surface of the semiconductor substrate; generating a first contact region configured to be biased by a first external potential and a second contact region configured to be biased by a second external potential, wherein a drift region of the semiconductor substrate is disposed between and electrically connected to the first contact region and the second contact region; and An RF electrode is generated which produces an ion trap placed above the drift region.

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