Semiconductor package and manufacturing method thereof

Abstract

A semiconductor package is provided. The semiconductor package includes: a redistribution substrate; a first semiconductor chip disposed on a right side portion of the redistribution substrate in the first direction; a through pillar disposed on the redistribution substrate in a region adjacent to a left side of the first semiconductor chip in the first direction; a heat dissipation chip disposed on the first semiconductor chip; and a second semiconductor device disposed adjacent to the heat dissipation chip on the through pillar. The metal pad and the adhesive layer are disposed between the heat dissipation chip and the first semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0084527 filed in the Korean Intellectual Property Office on June 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a redistribution substrate located under a semiconductor chip and a method for manufacturing the same. Background Art

[0004] According to the rapid development of the electronics industry and the needs of users, electronic devices have become more compact and lightweight. As electronic devices become smaller and lighter, semiconductor packages used therein are also smaller and lighter. In addition, high reliability as well as high performance and large capacity of semiconductor packages are required. As performance and capacity increase, the power consumption of semiconductor packages also increases. Therefore, the importance of heat dissipation characteristics of semiconductor packages corresponding to the size / performance of semiconductor packages is increasing. Summary of the invention

[0005] One or more example embodiments provide a semiconductor package which minimizes the overall thickness of the semiconductor package and maximizes heat dissipation characteristics, and a method of manufacturing the same.

[0006] Furthermore, the objects of the present inventive concept are not limited to the aforementioned objects, but other objects not described herein will be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of an example embodiment, a semiconductor package includes: a redistribution substrate; a first semiconductor chip disposed on a right portion of the redistribution substrate in a first direction; a through-pillar disposed on the redistribution substrate in a region adjacent to a left side of the first semiconductor chip in the first direction; a heat dissipation chip disposed on the first semiconductor chip; and a second semiconductor device disposed adjacent to the heat dissipation chip on the through-pillar. A metal pad and an adhesive layer are disposed between the heat dissipation chip and the first semiconductor chip.

[0008] According to another aspect of the example embodiment, a semiconductor package includes: a redistribution substrate including a plurality of wiring lines in a plurality of layers; a first semiconductor chip disposed on a right portion of the redistribution substrate in a first direction via a first bump; a through-pillar disposed on the redistribution substrate in an area adjacent to a left side of the first semiconductor chip in the first direction; a sealing material disposed on the redistribution substrate, surrounding the first semiconductor chip and the through-pillar, and exposing an upper surface of the first semiconductor chip and the through-pillar; a heat dissipation chip disposed on the first semiconductor chip, wherein a metal pad and an adhesive layer are disposed between the heat dissipation chip and the first semiconductor chip; and a second semiconductor chip disposed adjacent to the heat dissipation chip on the through-pillar, wherein a second bump is disposed between the through-pillar and the second semiconductor chip.

[0009] According to another aspect of the example embodiment, a semiconductor package includes: a redistribution substrate having a lower surface provided with external connection terminals and including multiple wiring lines in multiple layers; a first semiconductor chip arranged on the right portion of the redistribution substrate in a first direction through a first bump; a plurality of through-pillars arranged on the redistribution substrate in a region adjacent to the left side of the first semiconductor chip in the first direction and in a region on the opposite side of the first semiconductor chip in a second direction perpendicular to the first direction; a sealing material arranged on the redistribution substrate, covering side surfaces of the first semiconductor chip and the plurality of through-pillars, and exposing upper surfaces of the first semiconductor chip and the plurality of through-pillars; a heat dissipation chip arranged on the first semiconductor chip through a metal pad and an adhesive layer; and a second semiconductor chip arranged on the plurality of through-pillars through a second bump, adjacent to the heat dissipation chip.

[0010] According to another aspect of the example embodiment, a method for manufacturing a semiconductor package includes: forming an alignment metal pad and a plurality of through-pillars on a first carrier substrate; stacking a first semiconductor chip on the alignment metal pad so that an active surface of the first semiconductor chip faces the first carrier substrate; forming a sealing material around the plurality of through-pillars and the first semiconductor chip; bonding a second carrier substrate to the plurality of through-pillars and a non-active surface of the first semiconductor chip, and removing the first carrier substrate; grinding the sealing material to expose a first surface of the plurality of through-pillars and a first bump of the first semiconductor chip; forming a redistribution substrate on the first surface of the plurality of through-pillars and the first bump of the first semiconductor chip; bonding the redistribution substrate to a membrane ring mount, and removing the second carrier substrate; stacking a second semiconductor chip on a second surface of the plurality of through-pillars opposite to the first surface; and, in an area adjacent to the second semiconductor chip, stacking a heat dissipation chip on the non-active surface of the first semiconductor chip via a metal pad and an adhesive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features will become more apparent from the following description of example embodiments given in conjunction with the accompanying drawings, in which:

[0012] Figure 1A , Figure 1B and Figure 1C are a plan view and a cross-sectional view of a semiconductor package according to example embodiments;

[0013] Figure 2 is a cross-sectional view of a semiconductor package according to an example embodiment;

[0014] Figure 3 is a cross-sectional view of a semiconductor package according to an example embodiment;

[0015] Figure 4A and Figure 4B is a cross-sectional view of a semiconductor package according to an example embodiment;

[0016] Figure 5 is a cross-sectional view of a semiconductor package according to an example embodiment;

[0017] Figure 6 is a cross-sectional view of a semiconductor package according to an example embodiment;

[0018] Figure 7 is a cross-sectional view of a semiconductor package according to an example embodiment;

[0019] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Fig.8F , Figure 8G , Figure 8H , Fig.8I , Figure 8J and Figure 8K is a schematic diagram showing a method of manufacturing a Figure 1B A cross-sectional view of a process of a semiconductor packaging method;

[0020] Fig. 9 yes Fig.8D floor plan during operation; and

[0021] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E , Fig.10F , Figure 10G and Fig. 10H is shown in more detail Fig. 8A sectional view of the operation. DETAILED DESCRIPTION

[0022] Hereinafter, the example embodiments are described in detail with reference to the accompanying drawings. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and can be implemented in various other forms. Each example embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as "on", "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer, directly connected to or coupled to the other element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. As used herein, the term "and / or" includes any and all combinations of one or more items listed in association. Statements such as "at least one of..." modify the entire element list when it is after the element list, rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It should also be understood that even if a particular step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation. In the accompanying drawings, the same reference numerals are given to the same elements, and their repeated descriptions are omitted.

[0023] Figures 1A to 1C are a plan view and a cross-sectional view of a semiconductor package 100 according to example embodiments. Figure 1B is a cross-sectional view of the semiconductor package 100 taken along line II′, and Figure 1C yes Figure 1B An enlarged cross-sectional view of region A.

[0024] refer to Figures 1A to 1C , a semiconductor package 100 according to example embodiments may include a redistribution substrate 110 , a first semiconductor chip 120 , a through-pillar 130 , a second semiconductor chip 140 , a heat dissipation chip 150 , a heat dissipation connector 160 , and a sealing material 170 .

[0025] The redistribution substrate 110 may be located under the first semiconductor chip 120, the through pillars 130, and the sealing material 170. The redistribution substrate 110 may redistribute the connection of the chip pads of the first semiconductor chip 120 to the outer region of the first semiconductor chip 120. The redistribution substrate 110 may include a body insulating layer 112, redistribution lines 114, and vias 116.

[0026] The body insulating layer 112 may include an insulating material (e.g., a photoimageable dielectric (PID) or a photoimageable polyimide (PIP) resin), and may also include an inorganic filler. However, the material of the body insulating layer 112 is not limited to the above materials. For example, the body insulating layer 112 may include polyimide isoindolequinolinedione (PIQ), polyimide (PI), polybenzoxazole (PBO), etc.

[0027] The body insulating layer 112 may have a multi-layer structure according to the multi-layer structure of the redistribution line 114. However, for convenience, the body insulating layer 112 is Figure 1B In addition, when the body insulating layer 112 has a multi-layer structure, all layers of the body insulating layer 112 may include the same material, or at least one layer of the body insulating layer 112 may include different materials.

[0028] The redistribution line 114 may include a layer disposed inside the body insulating layer 112. The redistribution lines 114 on different layers may be connected to each other through vias 116. The redistribution line 114 and the via 116 may include, for example, copper (Cu). However, the material of the redistribution line 114 and the via 116 is not limited to Cu.

[0029] The external connection terminal 115 may be disposed on the lower surface of the body insulating layer 112. The external connection terminal 115 may be disposed on an external connection pad formed on the lower surface of the body insulating layer 112. The external connection pad may be included as a part of the redistribution line 114. However, in some example embodiments, the external connection pad may be regarded as a component separate from the redistribution line 114.

[0030] The external connection terminal 115 may be electrically connected to the redistribution line 114 through the external connection pad. Therefore, the external connection terminal 115 may be electrically connected to the first semiconductor chip 120 through the redistribution line 114 of the redistribution substrate 110 and the first bump 125. In addition, the external connection terminal 115 may connect the semiconductor package 100 to the package substrate of the external system, or the mainboard of an electronic device such as a mobile device. The external connection terminal 115 may include a conductive material, for example, at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). However, the material of the external connection terminal 115 is not limited to the above materials.

[0031] The external connection terminals 115 may be arranged on a first lower surface of the redistribution substrate 110 corresponding to the lower surface of the first semiconductor chip 120, and a second lower surface of the redistribution substrate 110 extending outwardly along the x direction from the first lower surface of the redistribution substrate 110. As described above, a package structure in which the external connection terminals 115 are arranged in a region wider than the lower surface of the first semiconductor chip 120 is referred to as a fan-out (FO) package structure. On the other hand, a package structure in which the external connection terminals 115 are arranged only in a region corresponding to the lower surface of the first semiconductor chip 120 is referred to as a fan-in (FI) package structure.

[0032] The first semiconductor chip 120 may be mounted on the redistribution substrate 110 through the first bump 125. The first bump 125 may include a metal column. In some example embodiments, the first bump 125 may include a metal column and solder. Here, the metal column may include, for example, Cu. However, the material of the metal column is not limited to Cu.

[0033] The first semiconductor chip 120 may be disposed on the redistribution substrate 110 while being offset (ie, shifted from the center) to one side in the x-direction. Figure 1B As shown, the first semiconductor chip 120 can be disposed on the redistribution substrate 110 while being biased to the right in the x-direction. In addition, since the first semiconductor chip 120 is biased to the right in the x-direction, the heat dissipation chip 150 above the first semiconductor chip 120 can also be biased to the right. This arrangement structure can allow the heat generated from the first semiconductor chip 120 to be effectively dissipated.

[0034] The first semiconductor chip 120 may include an analog chip. The first semiconductor chip 120 may include a plurality of logic elements therein. Here, the logic element may refer to an element that performs various signal processing, and may include, for example, an AND gate, an OR gate, a NOT gate, and a trigger. The logic element may also include an element for supporting communication. In the semiconductor package 100, the first semiconductor chip 120 may include, for example, an application processor (AP) chip. Depending on the function, the first semiconductor chip 120 may also be referred to as a control chip, a processing chip, a central processing unit (CPU) chip, etc. In addition, in terms of integrated functions, the first semiconductor chip 120 is also referred to as a system on chip (SoC). In addition, according to example embodiments, the elements for supporting communication may be separately provided as another chip (for example, a modem chip), and may be provided on the redistribution substrate 110 in the form of a structure coupled to the first semiconductor chip 120. The following is a description of the structure of the first semiconductor chip 120. Figure 4A and Figure 4B Example embodiments of a semiconductor package having such a structure are described in more detail in the description of FIG.

[0035] The first semiconductor chip 120 may include a substrate and a multi-wiring layer. In addition, an integrated circuit layer may be formed on the active surface of the substrate. The integrated circuit layer may include a plurality of logic elements. The multi-wiring layer may be provided on the lower surface of the substrate and include multi-layer wiring. In the first semiconductor chip 120, its lower surface may be a front surface as an active surface, and its upper surface may be a rear surface as a non-active surface. In this regard, the lower surface of the substrate provided with the multi-wiring layer may correspond to the front surface of the first semiconductor chip 120, and the upper surface of the substrate may correspond to the rear surface of the first semiconductor chip 120.

[0036] The through-pillar 130 may be located between the redistribution substrate 110 and the second semiconductor chip 140. In addition, the sealing material 170 may be located between the redistribution substrate 110 and the second semiconductor chip 140. Therefore, the through-pillar 130 may have a structure extending through the sealing material 170. The through-pillar 130 may electrically connect the redistribution substrate 110 and the second semiconductor chip 140 to each other. For example, the lower surface of the through-pillar 130 may be connected to the redistribution line 114 of the redistribution substrate 110, and the upper surface of the through-pillar 130 may be connected to the second semiconductor chip 140 through the second bump 145.

[0037] The through-pillar 130 may include, for example, Cu. Therefore, the through-pillar 130 may be referred to as a Cu pillar. However, the material of the through-pillar 130 is not limited to Cu. The through-pillar 130 may be formed by an electroplating process using a seed metal. The seed metal may include, for example, various metal materials (e.g., Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN)). In the semiconductor package 100, the seed metal may be included as a part of the through-pillar 130. For example, the seed metal may include Cu, and the through-pillar 130 may also include Cu. Therefore, Figure 1B The seed metal is not shown separately.

[0038] The second semiconductor chip 140 may be disposed adjacent to the heat dissipation chip 150 and mounted on the through pillar 130. The second semiconductor chip 140 may include a memory chip. Therefore, the second semiconductor chip 140 may include a plurality of storage elements therein. The second semiconductor chip 140 may include, for example, a volatile storage element (e.g., a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile storage element (e.g., a flash memory). In the semiconductor package 100, the second semiconductor chip 140 may include, for example, a DRAM element.

[0039] Furthermore, in some example embodiments, instead of the second semiconductor chip 140, a memory element having a package structure in which a plurality of memory chips are stacked may be stacked on the through pillar 130. As described above, when the memory element of the package structure is stacked on the through pillar 130, the entire semiconductor package may correspond to a package-on-package (POP) structure. Figure 3 A semiconductor package having a POP structure is described in more detail in the description of .

[0040] The second semiconductor chip 140 may be mounted on the through-pillar 130 by the second bump 145 in a flip chip bonding structure. For example, the second bump 145 may be located between the chip pad of the second semiconductor chip 140 and the upper surface of the corresponding through-pillar 130, respectively. According to example embodiments, the column pad may be formed on the through-pillar 130, and the second bump 145 may be located between the chip pad and the corresponding column pad. In addition, the bottom filler 147 may fill the space between the second semiconductor chip 140 and the sealing material 170, and the space between the second bumps 145. According to example embodiments, the bottom filler 147 may be omitted.

[0041] The heat dissipation chip 150 may be disposed adjacent to the second semiconductor chip 140 and stacked on the first semiconductor chip 120. The heat dissipation chip 150 may be stacked on the first semiconductor chip 120 through the heat dissipation connector 160. The heat dissipation chip 150 may include, for example, a silicon (Si) chip. Elements or wiring may not be formed inside the heat dissipation chip 150. Typically, the thermal conductivity of Si may be higher than the thermal conductivity of the resin (e.g., epoxy molding compound (EMC)) constituting the sealing material 170. Therefore, the heat dissipation chip 150 may help to effectively dissipate the heat generated from the first semiconductor chip 120.

[0042] The heat dissipation connector 160 may include a metal pad 162 and an adhesive layer 164. Each metal pad 162 may be disposed on the lower surface of the heat dissipation chip 150 and may have a metal with high thermal conductivity. For example, the metal pad 162 may include copper (Cu), nickel (Ni), aluminum (Al), tin (Sn), gold (Au), silver (Ag), etc. However, the material of the metal pad 162 is not limited to the above-mentioned metals. In addition, according to example embodiments, a passivation layer may be disposed on the lower surface of the heat dissipation chip 150, and the metal pad 162 may be disposed on the lower surface of the heat dissipation chip 150 in the form of passing through the passivation layer. The passivation layer may include, for example, a silicon oxide material or a silicon nitride material.

[0043] The adhesive layer 164 may adhere and fix the heat dissipation chip 150 on the first semiconductor chip 120. Figure 1BAs shown, the adhesive layer 164 may cover the metal pad 162 on the lower surface of the heat dissipation chip 150 and slightly protrude from the side surface of the heat dissipation chip 150. In addition, the adhesive layer 164 may include a material with high thermal conductivity to effectively transfer heat from the first semiconductor chip 120 to the metal pad 162 and the heat dissipation chip 150. For example, the adhesive layer 164 may include a thermal interface material (TIM), a thermally conductive resin, a thermally conductive polymer, or silicon oxide or silicon nitride (e.g., SiO 2 Here, the TIM may include a material with high thermal conductivity (ie, a material with low thermal resistance), for example, grease, tape, an elastomer-filled pad, a phase change material, etc.

[0044] like Figure 1C As shown, a gap G may be maintained between the first semiconductor chip 120 and the metal pad 162. That is, the gap G may exist between the lower surface of the metal pad 162 and the upper surface of the first semiconductor chip 120, and the adhesive layer 164 may be disposed in the gap G. In the semiconductor package 100, the gap G may be, for example, 1 μm or less. As described above, the gap G is maintained between the metal pad 162 and the first semiconductor chip 120, and the adhesive layer 164 is disposed in the gap G. Therefore, warping may be prevented by alleviating the stress caused by the difference in thermal expansion coefficient between the metal pad 162 and the first semiconductor chip 120. In addition, according to example embodiments, when warping is not a critical consideration, the lower surface of the metal pad 162 may be in contact with the upper surface of the first semiconductor chip 120.

[0045] For reference, in the case of a related semiconductor package, a sealing material surrounds the upper surface and side surface of the first semiconductor chip, and a redistribution substrate is located above the first semiconductor chip. In addition, the related semiconductor package may have a structure in which an upper package is arranged above the first semiconductor chip through an inter-substrate connection terminal. In the case of such a structure, since the first semiconductor chip is covered with a sealing material having low thermal conductivity, the heat dissipation efficiency may be seriously deteriorated. However, in the semiconductor package 100 according to an embodiment, the upper surface of the first semiconductor chip 120 is exposed, and a heat dissipation chip 150 having Si is stacked on the first semiconductor chip 120 through a heat dissipation connector 160. Therefore, the heat dissipation efficiency can be significantly improved.

[0046] The sealing material 170 may be located between the redistribution substrate 110 and the second semiconductor chip 140, and between the redistribution substrate 110 and the heat dissipation chip 150. The sealing material 170 may cover the side surface of the first semiconductor chip 120 and seal the side surface. In addition, the sealing material 170 may cover the side surface of the through pillar 130. In addition, as Figure 1BAs shown, the sealing material 170 may fill the space between the redistribution substrate 110 and the first semiconductor chip 120, and the space between the first bumps 125 on the lower surface of the first semiconductor chip 120. However, in some example embodiments, an underfill may fill the space between the first bumps 125 on the lower surface of the first semiconductor chip 120, and the sealing material 170 may cover the side surfaces of the first semiconductor chip 120 and the underfill.

[0047] The sealing material 170 may include an insulating material, for example, a thermosetting resin (e.g., epoxy resin), a thermoplastic resin (e.g., polyimide), or a resin formed by providing a reinforcing material (e.g., an inorganic filler) to a thermosetting or thermoplastic resin. For example, the sealing material 170 may include an Ajinomoto laminated film (ABF), FR-4, or a bismaleimide triazine (BT) resin. In addition, the sealing material 170 may include a molding material such as EMC or a photosensitive material such as a photoimageable encapsulant (PIE). However, the material of the sealing material 170 is not limited to the above materials.

[0048] like Figure 1B As shown, the sealing material 170 can seal the first semiconductor chip 120 by exposing the structure of the upper surface of the first semiconductor chip 120. As described above, because the sealing material 170 has a structure that exposes the upper surface of the first semiconductor chip 120, the thickness of the sealing material 170 can be minimized. For example, the sealing material 170 has a first thickness H1, and the first thickness H1 can be 100 μm or less. However, the thickness of the sealing material 170 is not limited to the aforementioned numerical range. As described above, the sealing material 170 has a small thickness of 100 μm or less, and therefore, the warpage can be easily controlled. For example, since the sealing material 170 becomes thinner, the stress caused by the difference in thermal expansion coefficient between the sealing material 170 and the first semiconductor chip 120 can be reduced. Therefore, the warpage can be reduced. In addition, since the sealing material 170 has a smaller thickness, the total thickness of the semiconductor package 100 can be reduced by the reduced thickness amount of the sealing material 170.

[0049] refer to Figure 1A, with respect to the planar size and positional relationship between the redistribution substrate 110 and the first semiconductor chip 120, the second semiconductor chip 140, and the heat dissipation chip 150, the redistribution substrate 110 may have substantially the same size as the sealing material 170 in a plan view. Therefore, in a plan view, the first semiconductor chip 120 and the through-pillar 130 may be arranged within the redistribution substrate 110. In addition, in a plan view, the second semiconductor chip 140 and the heat dissipation chip 150, which are respectively disposed above the first semiconductor chip 120 and the through-pillar 130, may also be arranged within the redistribution substrate 110. In addition, most of the first semiconductor chip 120 may overlap with the heat dissipation chip 150, and only a portion of the first semiconductor chip 120 may overlap with the second semiconductor chip 140. For example, the portion of the first semiconductor chip 120 overlapping with the second semiconductor chip 140 may be smaller than the portion of the first semiconductor chip 120 that does not overlap with the second semiconductor chip 140.

[0050] In the semiconductor package 100, the heat dissipation chip 150 is arranged on the upper surface of the first semiconductor chip 120 including the SoC through the heat dissipation connector 160, and therefore, the heat dissipation effect of the first semiconductor chip 120 can be maximized. In addition, in the semiconductor package 100, the sealing material 170 has a small thickness of 100 μm or less, and therefore, the warpage can be easily controlled and the total thickness of the semiconductor package can be reduced. Here, the signal exchange between the first semiconductor chip 120 and the second semiconductor chip 140 can be performed through the second bump 145, the through column 130, the redistribution line 114 of the redistribution substrate 110, and the first bump 125. In the semiconductor package 100, the thickness of the sealing material 170 is reduced, and therefore, the length of the through column 130 can also be reduced. Therefore, the signal exchange path between the first semiconductor chip 120 and the second semiconductor chip 140 can be shortened.

[0051] In the semiconductor package 100, the first semiconductor chip 120 can be self-aligned and disposed on the redistribution substrate 110. Therefore, the redistribution lines 114 in the redistribution substrate 110 can be designed to have fine lines and spaces (L / S). For example, among the redistribution lines 114 of the redistribution substrate 110 in the semiconductor package 100, the uppermost redistribution line 114 connected to the first bump 125 of the first semiconductor chip 120 can have a line width and space of about 2 / 2 μm. In addition, the redistribution lines 114 below the uppermost redistribution lines 114 can have a line width and space of, for example, about 7 / 8 μm. 8A to 10H The self-aligned arrangement of the first semiconductor chip 120 is described in more detail in the description of the semiconductor package manufacturing method.

[0052] Figure 2is a cross-sectional view of a semiconductor package 100a according to an example embodiment. Figures 1A to 1C Description given.

[0053] refer to Figure 2 The semiconductor package 100a can be similar to the heat dissipation chip 150a in terms of structure. Figure 1B The semiconductor package 100 of FIG. 100 is different. Specifically, in the semiconductor package 100a, a plurality of metal wires 155 may be arranged inside the heat dissipation chip 150a. The metal wires 155 may include, for example, through holes that pass through the heat dissipation chip 150a in a vertical direction. Each metal wire 155 may include a metal with high thermal conductivity. For example, the metal wire 155 may include Cu, Ni, Al, Sn, Au, Ag, etc. However, the material of the metal wire 155 is not limited to the above-mentioned metals.

[0054] The metal wires 155 have a higher thermal conductivity than Si of the heat dissipation chip 150a, and thus can help to more effectively dissipate heat from the first semiconductor chip 120. The metal wires 155 can be connected to the metal pads 162 located under the heat dissipation chip 150a. However, at least some of the metal wires 155 may not be connected to the metal pads 162.

[0055] Figure 3 is a cross-sectional view of a semiconductor package 100b according to an example embodiment. Figure 1A to Figure 2 Description given.

[0056] refer to Figure 3 The semiconductor package 100b can be compared with Figure 1B The semiconductor package 100 of FIG. 1 is different from that of FIG. 1 : a memory element 140 a having a package structure is stacked on the through pillar 130 instead of the second semiconductor chip. In the semiconductor package 100 b, the memory element 140 a may include a high bandwidth memory (HBM) package. More specifically, the memory element 140 a including the HBM package may include a substrate chip 142 and a plurality of core chips 144 on the substrate chip 142.

[0057] The substrate chip 142 and the core chip 144 may include through electrodes 148 inside the substrate chip 142 and the core chip 144. Here, the through electrodes 148 may include through silicon vias (TSVs). Figure 3 As shown, the uppermost core chip 144-4 among the core chips 144 may not include the through-electrode 148. Here, fine bumps and adhesive layers may be arranged between the substrate chip 142 and the core chip 144, and between adjacent core chips 144. In addition, the fine bumps may be connected to the through-electrode 148.

[0058] The substrate chip 142 may include logic elements. Therefore, the substrate chip 142 may include a logic chip. The substrate chip 142 may be located below the core chip 144 to integrate and send the signals of the core chip 144 to the outside (i.e., to an external component or device), and to send signals and power from the outside to the core chip 144. Therefore, the substrate chip 142 may be referred to as a buffer chip or a control chip. In addition, each core chip 144 may include a memory chip. For example, each core chip 144 may include a DRAM chip. Here, the core chip 144 may be stacked on the substrate chip 142 or the lower core chip 144 by pad-to-pad bonding, hybrid bonding (HB), bonding using a bonding member, or bonding using an anisotropic conductive film (ACF), etc. In Figure 3 In the embodiment, four core chips 144 are stacked on the substrate chip 142 , but the number of core chips 144 is not limited to four. For example, three or less core chips 144 , or five or more core chips 144 may be stacked on the substrate chip 142 .

[0059] The memory element 140a may be mounted on the through pillar 130 by a second bump 145. More specifically, the second bump 145 may be disposed between the lower surface of the substrate chip 142 and the through pillar 130. A chip pad may be disposed on the lower surface of the substrate chip 142, and the second bump 145 may be disposed on the chip pad. In addition, according to example embodiments, a pillar pad may be formed on the through pillar 130, and the second bump 145 may be located between the chip pad and the corresponding pillar pad.

[0060] The core chip 144 on the substrate chip 142 may be sealed by the internal sealing material 146. For example, the side surface of the core chip 144 may be covered by the internal sealing material 146. The upper surface of the uppermost core chip 144-4 among the core chips 144 may not be covered by the internal sealing material 146. However, in some example embodiments, the upper surface of the uppermost core chip 144-4 may be covered by the internal sealing material 146.

[0061] In semiconductor package 100b, storage element 140a is not limited to HBM packaging. For example, storage element 140a may have a general packaging structure. For example, storage element 140a may include an upper package substrate and a plurality of memory chips stacked on the upper package substrate. The upper package substrate may be stacked on through-pillar 130 by second bump 145. In addition, the memory chip may be stacked on the upper package substrate by bonding wires, or may be stacked on the upper package substrate by bumps and TSVs.

[0062] The semiconductor package 100b may have a POP structure. Specifically, the redistribution substrate 110, the first semiconductor chip 120, the through-pillar 130 and the sealing material 170 may constitute a first package PKG1, and the storage element 140a may constitute a second package PKG2. Therefore, the semiconductor package 100b may have a POP structure, wherein the second package PKG2 is stacked on the first package PKG1 through the second bump 145.

[0063] Figure 4A and Figure 4B is a cross-sectional view of a semiconductor package 100c according to an example embodiment, and Figure 4B is shown in more detail Figure 4A A cross-sectional view of a third semiconductor chip 120a in a semiconductor package 100c is briefly given or omitted. Figures 1A to 3 Description given.

[0064] refer to Figure 4A and Figure 4B The semiconductor package 100c according to example embodiments may be similar to Figure 1B The semiconductor package 100c is different from the semiconductor package 100 of FIG. 100a: the semiconductor package 100c also includes a third semiconductor chip 120a located below the first semiconductor chip 120. For example, the third semiconductor chip 120a may include a modem chip for supporting communication of the first semiconductor chip 120. However, the type of the third semiconductor chip 120a is not limited to the modem chip. For example, the third semiconductor chip 120a may include various types of integrated components for supporting the operation of the first semiconductor chip 120. The third semiconductor chip 120a may include a multi-channel I / O interface for exchanging storage signals with the second semiconductor chip 140.

[0065] like Figure 4B As shown, the third semiconductor chip 120a may include a substrate 121, a lower multi-wiring layer 123, an upper wiring layer 127, and a through electrode 129. The substrate 121 constitutes the body of the third semiconductor chip 120a and may be formed based on Si. An integrated circuit layer may be formed on an active surface of the substrate 121. The integrated circuit layer may include a plurality of logic elements. The lower multi-wiring layer 123 may be disposed on the lower surface of the substrate 121 and include multi-layer wiring. In addition, a chip pad may be arranged on the lower surface of the lower multi-wiring layer 123, and a first bump 125 may be arranged on the chip pad.

[0066] The upper wiring layer 127 may be disposed above the substrate 121. The wiring may be located in the upper wiring layer 127, and the wiring may be arranged in the form of a single layer or multiple layers (i.e., multiple layers). In the case of multi-layer wiring, the wirings on different layers may be connected to each other through vias. The upper pad connected to the wiring may be arranged on the upper surface of the upper wiring layer 127. According to example embodiments, the upper wiring layer 127 may be omitted. When the upper wiring layer 127 is omitted, the upper surface of the through electrode 129 may be exposed through the substrate 121, or the electrode pad on the upper surface of the through electrode 129 may be exposed through the substrate 121.

[0067] The through-electrode 129 may pass through the substrate 121 and connect the wiring of the upper wiring layer 127 and the wiring of the lower multi-wiring layer 123 to each other. Because each through-electrode 129 has a structure passing through silicon constituting the substrate 121, the through-electrode 129 may be referred to as a TSV. For reference, the through-electrode 129 may be classified into: a first via structure formed before forming an integrated circuit layer on the substrate 121; an intermediate via structure formed after forming the integrated circuit layer and before forming the multi-wiring layer; and a later via structure formed after forming the multi-wiring layer. Figure 4B In the embodiment, the through-electrode 129 may correspond to, for example, a middle via structure.

[0068] In the third semiconductor chip 120a, its lower surface may be a front surface as an active surface, and its upper surface may be a rear surface as an inactive surface. In this regard, the lower surface of the lower multi-wiring layer 123 may correspond to the front surface of the third semiconductor chip 120a, and the upper surface of the upper wiring layer 127 may correspond to the rear surface of the third semiconductor chip 120a. A chip pad is formed on the front surface of the third semiconductor chip 120a as an active surface, and the third semiconductor chip 120a may be mounted on the redistribution substrate 110 through the first bump 125 in a flip-chip structure.

[0069] In addition, the first semiconductor chip 120 may be stacked on the third semiconductor chip 120a by bonding using bumps, bonding using ACF, HB, etc. For reference, HB may refer to bonding that combines pad-to-pad bonding and insulator-to-insulator bonding. ACF may refer to an anisotropic conductive film that conducts electricity only in one direction, and may also refer to a conductive film made into a film state by mixing fine conductive particles with an adhesive resin.

[0070] Figure 5 is a cross-sectional view of a semiconductor package 100d according to an example embodiment. Figures 1A to 4B Description given.

[0071] refer to Figure 5The semiconductor package 100d can be compared with Figure 1B The semiconductor package 100d is different from the semiconductor package 100: the semiconductor package 100d also includes a passive element 180. Specifically, in the semiconductor package 100d, the passive element 180 may be located on the lower surface of the redistribution substrate 110. However, according to example embodiments, the passive element 180 may be disposed on the upper surface of the redistribution substrate 110 or located inside the redistribution substrate 110. The passive element 180 may include a two-terminal element, such as a resistor, an inductor, or a capacitor. For example, the passive element 180 may include a multilayer ceramic capacitor (MLCC) 182 and a Si capacitor 184.

[0072] Figure 6 is a cross-sectional view of a semiconductor package 100e according to an example embodiment. Figures 1A to 5 Description given.

[0073] refer to Figure 6 The semiconductor package 100e may further include an upper sealing material 175 disposed above the first semiconductor chip 120, the through pillar 130 and the sealing material 170 to seal the second semiconductor chip 140 and the heat dissipation chip 150. The upper sealing material 175 has a Figure 1B The same material and characteristics as the sealing material 170 of the semiconductor package 100. Figure 6 As shown, the upper sealing material 175 may cover the side surfaces of the second semiconductor chip 140 and the bottom filler 147, and the side surfaces of the heat dissipation chip 150 and the heat dissipation connector 160. In some example embodiments, the bottom filler 147 may be omitted, and the upper sealing material 175 may fill the space between the second semiconductor chip 140 and the sealing material 170, and the space between the second bumps 145.

[0074] In addition, the upper sealing material 175 may not cover the upper surfaces of the second semiconductor chip 140 and the heat dissipation chip 150. However, according to example embodiments, the upper sealing material 175 may cover the upper surface of the second semiconductor chip 140. In this structure, the upper surface of the second semiconductor chip 140 may be lower than the upper surface of the heat dissipation chip 150.

[0075] Figure 7 is a cross-sectional view of a semiconductor package 100f according to an example embodiment. Figures 1A to 6 Description given.

[0076] refer to Figure 7 , the semiconductor package 100f can be compared with Figure 6The semiconductor package 100e is different from the semiconductor package 100f: the semiconductor package 100f further includes a heat dissipation structure 190 on the second semiconductor chip 140 and the heat dissipation chip 150. In addition, the heat dissipation structure 190 of the semiconductor package 100f is not limited to Figure 6 The semiconductor package 100e, and the heat dissipation structure 190 can be arranged at Figure 1B and Figures 2 to 5 On each of the semiconductor packages 100, 100a to 100d.

[0077] The heat dissipation structure 190 may include, for example, a heat sink or a heat sink. The heat dissipation structure 190 may be bonded to the second semiconductor chip 140 and the heat dissipation chip 150 through an upper adhesive layer 195 and stacked on the second semiconductor chip 140 and the heat dissipation chip 150. The upper adhesive layer 195 may include a material having high thermal conductivity (e.g., TIM or thermally conductive resin).

[0078] FIG. 8A to FIG. 8K is a schematic diagram showing a method of manufacturing a Figure 1B A cross-sectional view of a process of a method of semiconductor packaging 100, and Fig. 9 yes Fig.8D The floor plan during operation. Figure 1B A description is given and references to Figures 1A to 7 Description given.

[0079] refer to Fig. 8A In the semiconductor package manufacturing method, an alignment metal pad 310 and an initial through-pillar 130a are formed on a first carrier substrate 200. The alignment metal pad 310 and the initial through-pillar 130a may be formed on a first adhesive layer 210 of the first carrier substrate 200. The first adhesive layer 210 may include, for example, a glue coating. However, the material of the first adhesive layer 210 is not limited to glue. The alignment metal pad 310 and the initial through-pillar 130a may be formed by a plating process. FIG. 10A to FIG. 10H The process of fabricating the alignment metal pad 310 and the initial through-pillar 130a is described in more detail in the description of FIG.

[0080] The alignment metal pad 310 may include, for example, Cu or Ti / Cu. However, the material of the alignment metal pad 310 is not limited thereto. The alignment metal pad 310 may have a fine width and spacing. In addition, the alignment metal pad 310 may allow the first semiconductor chip 120 to be self-aligned and stacked on the redistribution substrate 110. In addition, since the alignment metal pad 310 has a fine width and spacing, the width and spacing of the redistribution line formed on the redistribution substrate 110 (e.g., the width and spacing of the uppermost redistribution line) may be made very fine.

[0081] The initial through-pillars 130a may also include Cu or Ti / Cu. However, the material of the initial through-pillars 130a is not limited thereto. The initial through-pillars 130a may have a relatively larger width and interval than the alignment metal pads 310. The initial through-pillars 130a may be arranged in a two-dimensional array structure on at least one side of the region where the alignment metal pads 310 are arranged.

[0082] refer to Figure 8B , stacking the first semiconductor chip 120 on the alignment metal pad 310. In detail, the first semiconductor chip 120 may include an initial bump 125a formed on the lower surface of the first semiconductor chip 120. Each initial bump 125a may include a metal column 125-1 and a solder 125-2. The metal column 125-1 may include, for example, Cu. However, the material of the metal column 125-1 is not limited to Cu. The first semiconductor chip 120 may be stacked on the alignment metal pad 310 in a manner that the initial bump 125a is coupled to the corresponding alignment metal pad 310.

[0083] refer to Figure 8C , an initial sealing material 170a covering the initial through-pillars 130a and the first semiconductor chip 120 is formed on the first adhesive layer 210. Figure 8C As shown, the initial sealing material 170a may cover the side surfaces and the upper surface of the initial through pillars 130a and the first semiconductor chip 120. In addition, the initial sealing material 170a may fill the space between the first semiconductor chip 120 and the first adhesive layer 210, and the space between the initial bumps 125a. The initial sealing material 170a has a Figure 1B The sealing material 170 of the semiconductor package 100 has the same material and characteristics.

[0084] refer to Fig.8D and Fig. 9 As shown by the arrow, the upper portion of the initial sealing material 170a is partially removed by the first grinding process, thereby forming an initial sealing material 170b thinner than the initial sealing material 170a. Through the first grinding process, the initial through-pillar 130a and the upper surface of the first semiconductor chip 120 may be exposed through the initial sealing material 170b.

[0085] In addition, if Fig. 9 As shown, the initial through-pillars 130a may be arranged in a two-dimensional array structure on at least one side of the first semiconductor chip 120 (e.g., in a region on the left side of the first semiconductor chip 120 in the x-direction). In addition, some of the initial through-pillars 130a may be arranged in a partial region on the opposite side of the first semiconductor chip 120 in the y-direction.

[0086] refer to Fig. 8E, after forming the initial sealing material 170b, the second carrier substrate 400 is coupled to the upper surface of the first semiconductor chip 120, the initial through-pillar 130a, and the initial sealing material 170b. The second carrier substrate 400 may be bonded and fixed to the upper surface of the first semiconductor chip 120, the initial through-pillar 130a, and the initial sealing material 170b by the second adhesive layer 410. After coupling the second carrier substrate 400 to the upper surface of the first semiconductor chip 120, the initial through-pillar 130a, and the initial sealing material 170b, the first carrier substrate 200 is removed from the alignment metal pad 310, the initial through-pillar 130a, and the initial sealing material 170b. The first adhesive layer 210 may be removed together with the first carrier substrate 200. However, in some example embodiments, only the first carrier substrate 200 may be removed while the first adhesive layer 210 remains.

[0087] refer to Fig.8F After removing the first carrier substrate 200, the entire structure is flipped over so that the second carrier substrate 400 is located on the lower side and the alignment metal pad 310 is located on the upper side. Subsequently, as indicated by the arrow, the alignment metal pad 310 and the initial bump 125a are partially removed by a second grinding process. For example, since the solder 125-2 of the initial bump 125a is removed by the second grinding process, the first bump 125 can be formed on the first semiconductor chip 120. In addition, since the initial through-pillar 130a and the initial sealing material 170b are thinned by the second grinding process, the through-pillar 130 and the sealing material 170 can be formed together. The sealing material 170 and Figure 1B The sealing material 170 of the semiconductor package 100 is substantially the same and thus may have a first thickness H1.

[0088] refer to Figure 8G , a redistribution substrate 110 is formed on the first semiconductor chip 120, the through pillars 130 and the sealing material 170. The redistribution substrate 110 may include a body insulating layer 112, redistribution lines 114 and vias 116. As described above, the first bumps 125 of the first semiconductor chip 120 may be self-aligned using the alignment metal pads 310, and thus formed very finely. Accordingly, the redistribution lines 114 of the redistribution substrate 110 may also have very fine widths and spacings. For example, among the redistribution lines 114 of the redistribution substrate 110, the redistribution lines 114 coupled to the first bumps 125 of the first semiconductor chip 120 have a line width and spacing of approximately 2 / 2 μm.

[0089] refer to Figure 8H After forming the redistribution substrate 110, an external connection terminal 115 is formed on the redistribution substrate 110. The external connection terminal 115 has Figure 1BThe features of the external connection terminals 115 of the semiconductor package 100 are the same as the features of the external connection terminals 115 of the semiconductor package 100 .

[0090] refer to Fig.8I , and then the external connection terminal 115 is attached to the adhesive film 520 of the film frame mount 500. The film frame mount 500 may include a support ring 510 having a circular ring shape, and an adhesive film 520 covering an opening portion of the support ring 510. Therefore, the film frame mount 500 is also called a ring frame mount.

[0091] After attaching the external connection terminals 115 of the redistribution substrate 110 to the film frame mount 500, the second carrier substrate 400 is removed from the first semiconductor chip 120, the through-pillars 130, and the sealing material 170. The second adhesive layer 410 may be removed together with the second carrier substrate 400.

[0092] refer to Figure 8J , after removing the second carrier substrate 400, the entire structure is flipped again, and the second semiconductor chip 140 is stacked on the through pillar 130. The second semiconductor chip 140 may be stacked by the second bumps 145. Subsequently, the space between the second semiconductor chip 140 and the sealing material 170, and the space between the second bumps 145 may be filled with an underfill 147. However, in some example embodiments, the underfill 147 may be omitted.

[0093] refer to Figure 8K , and then stacking a heat dissipation chip 150 on the first semiconductor chip 120 in a region adjacent to the second semiconductor chip 140. The heat dissipation chip 150 may be stacked using a heat dissipation connector 160. The heat dissipation connector 160 may include a metal pad 162 and an adhesive layer 164. The heat dissipation chip 150 may be stacked on the first semiconductor chip 120. Figure 1B A semiconductor package 100 is provided.

[0094] FIG. 10A to FIG. 10H is a more detailed illustration of the formation Fig. 8A The cross-sectional view of the structure shown below. Figure 1B A description is given and references to Figures 1A to 8K Description given.

[0095] refer to Fig. 10A In the process of manufacturing the alignment metal pad 310 and the initial through-pillar 130a, a first adhesive layer 210 is first formed on the first carrier substrate 200. The first adhesive layer 210 may include, for example, a glue coating. However, the material of the first adhesive layer 210 is not limited to glue.

[0096] refer to Fig. 10BAfter forming the first adhesive layer 210, a metal seed layer 301 is formed on the first adhesive layer 210. The metal seed layer 301 may include, for example, a Cu single layer or a Ti / Cu multilayer. However, the material and layer structure of the metal seed layer 301 are not limited to the above materials and layer structures. Here, in the case of a Ti / Cu multilayer, the lower portion may include a Ti layer, and the upper portion may include a Cu layer.

[0097] refer to Fig. 10C , after forming the metal seed layer 301, a first PR pattern PH1 is formed on the metal seed layer 301. More specifically, a first PR layer 610 having a small thickness may be first formed on the entire surface of the metal seed layer 301. Subsequently, a photolithography process may be performed on the first PR layer 610 so that the first PR pattern PH1 is formed at a region where the first semiconductor chip 120 will be located. Here, the first PR pattern PH1 may have a very fine width and interval in consideration of the size and interval of the alignment metal pad 310 to be formed later. Here, the first PR pattern PH1 may expose the metal seed layer 301 at the bottom surface of the first PR pattern PH1.

[0098] refer to Fig. 10D After forming the first PR pattern PH1, a plating process is performed on the metal seed layer 301 exposed by the first PR pattern PH1, thereby forming an initial alignment metal pad 310a. The plating process may include, for example, a Cu plating process. However, the plating process is not limited to the Cu plating process.

[0099] refer to Fig.10E After forming the initial alignment metal pad 310a, the first PR layer 610 and the first PR pattern PH1 are removed. The first PR layer 610 and the first PR pattern PH1 may be removed by a PR stripping and / or ashing process. The metal seed layer 301 and the initial alignment metal pad 310a may be exposed by removing the first PR layer 610 and the first PR pattern PH1.

[0100] refer to Fig.10F , and then a second PR pattern PH2 is formed in a region adjacent to the initial alignment metal pad 310a. More specifically, the second PR layer 620 covering the entire surface of the metal seed layer 301 and the initial alignment metal pad 310a may be formed to a relatively large thickness. Subsequently, a photolithography process may be performed on the second PR layer 620 so that the second PR pattern PH2 is formed at a region where the through pillar 130 is to be arranged. Here, the second PR pattern PH2 may expose the metal seed layer 301 at the bottom surface of the second PR pattern PH2.

[0101] refer to Figure 10GAfter forming the second PR pattern PH2, a plating process is performed on the metal seed layer 301 exposed by the second PR pattern PH2, thereby forming the initial through-pillar 130b. The plating process may include, for example, a Cu plating process. However, the plating process is not limited to the Cu plating process.

[0102] refer to Fig. 10H , after forming the initial through-pillar 130b, the second PR layer 620 and the second PR pattern PH2 are removed. The second PR layer 620 and the second PR pattern PH2 may be removed by a PR stripping and / or ashing process. By removing the second PR layer 620 and the second PR pattern PH2, the metal seed layer 301 may be exposed between the initial through-pillars 130b, between the initial alignment metal pads 310a, and outside of the region where the initial through-pillars 130b and the initial alignment metal pads 310a are arranged. Subsequently, the exposed metal seed layer 301 is removed by an etching process, and thus, the initial through-pillar 130a and the alignment metal pads 310 may be formed.

[0103] While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Redistribution substrate; a first semiconductor chip disposed on a right portion of the redistribution substrate in a first direction; a through-pillar disposed on the redistribution substrate in a region adjacent to a left side of the first semiconductor chip in the first direction; a heat dissipation chip, disposed on the first semiconductor chip; and A second semiconductor device is disposed on the through column adjacent to the heat dissipation chip, Wherein, the metal pad and the adhesive layer are arranged between the heat dissipation chip and the first semiconductor chip.

2. The semiconductor package according to claim 1, further comprising: a sealing material on the redistribution substrate and surrounding the first semiconductor chip and the through-pillar, Wherein, upper surfaces of the first semiconductor chip and the through-pillar are exposed through the sealing material.

3. The semiconductor package according to claim 1, wherein: The adhesive layer includes thermal interface material TIM, polymer or oxide.

4. The semiconductor package according to claim 1, wherein: A gap between a lower surface of the metal pad and an upper surface of the first semiconductor chip is 1 μm or less, and Wherein, the adhesive layer extends into the gap.

5. The semiconductor package according to claim 1, wherein The first semiconductor chip includes a logic circuit, and Wherein, the second semiconductor device includes a memory circuit.

6. The semiconductor package according to claim 1, wherein The heat dissipation chip includes a metal wire inside the heat dissipation chip.

7. The semiconductor package according to claim 1, wherein: The redistribution substrate includes a plurality of wiring lines arranged in a plurality of layers of the redistribution substrate, and A pitch of first wiring lines on an uppermost layer among the multiple layers and coupled to the first semiconductor chip is smaller than a pitch of wiring lines on the remaining layers among the multiple layers located below the first wiring lines.

8. The semiconductor package according to claim 7, wherein: The line width of the first wiring line is 2 μm, and Wherein, the line spacing of the first wiring line is 2 μm.

9. A semiconductor package, comprising: a redistribution substrate including a plurality of routing lines in a plurality of layers; A first semiconductor chip is disposed on a right portion of the redistribution substrate in a first direction through a first bump; a through-pillar disposed on the redistribution substrate in a region adjacent to a left side of the first semiconductor chip in the first direction; a sealing material disposed on the redistribution substrate, surrounding the first semiconductor chip and the through-pillar, and exposing upper surfaces of the first semiconductor chip and the through-pillar; a heat dissipation chip disposed on the first semiconductor chip, wherein a metal pad and an adhesive layer are disposed between the heat dissipation chip and the first semiconductor chip; and A second semiconductor chip is disposed on the through-pillar adjacent to the heat dissipation chip, wherein a second bump is disposed between the through-pillar and the second semiconductor chip.

10. The semiconductor package according to claim 9, wherein The through-pillar extends through the sealing material to connect the redistribution substrate and the second semiconductor chip to each other.

11. The semiconductor package according to claim 9, wherein: The through-pillar includes a plurality of through-pillars, wherein the first semiconductor chip is disposed between two through-pillars of the plurality of through-pillars in a second direction perpendicular to the first direction.

12. The semiconductor package according to claim 9, wherein: A left portion of the first semiconductor chip overlaps the second semiconductor chip in a direction perpendicular to an upper surface of the redistribution substrate.

13. The semiconductor package according to claim 9, wherein: A pitch of a first wiring line on an uppermost layer among the plurality of layers and coupled to the first semiconductor chip is smaller than a pitch of wiring lines on remaining layers among the plurality of layers located below the first wiring line.

14. The semiconductor package according to claim 9, wherein: The second semiconductor chip is electrically connected to the first semiconductor chip through the second bumps, the through-pillars, the plurality of wiring lines of the redistribution substrate, and the first bumps.

15. A semiconductor package, comprising: a redistribution substrate having a lower surface provided with external connection terminals and including a plurality of wiring lines in a plurality of layers; A first semiconductor chip is disposed on a right portion of the redistribution substrate in a first direction through a first bump; a plurality of through-pillars disposed on the redistribution substrate in a region adjacent to a left side of the first semiconductor chip in the first direction and in a region on an opposite side of the first semiconductor chip in a second direction perpendicular to the first direction; a sealing material disposed on the redistribution substrate, covering side surfaces of the first semiconductor chip and the plurality of through-pillars, and exposing upper surfaces of the first semiconductor chip and the plurality of through-pillars; a heat dissipation chip, disposed on the first semiconductor chip via a metal pad and an adhesive layer; and The second semiconductor chip is disposed on the plurality of through pillars through second bumps and is adjacent to the heat dissipation chip.

16. The semiconductor package according to claim 15, wherein: The second semiconductor chip is electrically connected to the first semiconductor chip through the second bumps, the plurality of through-pillars, the plurality of wiring lines of the redistribution substrate, and the first bumps.

17. A method for manufacturing a semiconductor package, the method comprising: forming an alignment metal pad and a plurality of through-pillars on a first carrier substrate; stacking a first semiconductor chip on the alignment metal pad such that an active surface of the first semiconductor chip faces the first carrier substrate; forming a sealing material surrounding the plurality of through-pillars and the first semiconductor chip; bonding a second carrier substrate to the plurality of through-pillars and the inactive surface of the first semiconductor chip, and removing the first carrier substrate; grinding the sealing material to expose the first surfaces of the plurality of through-pillars and the first bumps of the first semiconductor chip; forming a redistribution substrate on the first surfaces of the plurality of through-pillars and the first bumps of the first semiconductor chip; bonding the redistribution substrate to a membrane ring mount and removing the second carrier substrate; stacking a second semiconductor chip on a second surface of the plurality of through-pillars opposite to the first surface; as well as In a region adjacent to the second semiconductor chip, a heat dissipation chip is stacked on the inactive surface of the first semiconductor chip through a metal pad and an adhesive layer.

18. The method according to claim 17, wherein: Forming the alignment metal pad and the plurality of through-pillars comprises: forming a glue coating on the first carrier substrate; forming a metal seed layer on the glue coating; forming the alignment metal pad on a right portion of the metal seed layer in the first direction; forming the plurality of through-pillars on a left portion of the metal seed layer in the first direction; and The metal seed layer exposed between the alignment metal pads, between the plurality of through-pillars, and outside the plurality of through-pillars and the alignment metal pads is removed.

19. The method according to claim 18, wherein: Forming the alignment metal pad includes: forming a first photoresist PR layer on the metal seed layer; patterning the first PR layer to form a first PR pattern on the right portion of the metal seed layer; and performing a first plating process to grow the alignment metal pad on the metal seed layer exposed by the first PR pattern, and Wherein, forming the plurality of through-pillars comprises: forming a second PR layer on the metal seed layer and the alignment metal pad; patterning the second PR layer to form a second PR pattern on the left portion of the metal seed layer; and A second plating process is performed to grow the plurality of through-pillars on the metal seed layer exposed by the second PR pattern.

20. The method according to claim 17, wherein: During the exposure of the first surfaces of the plurality of through-pillars and the first bumps of the first semiconductor chip, the sealing material has a thickness of 100 μm or less.

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